DC-DC converters

Abstract

The control circuit has a first intermittent control mode in which the pulses of the drive signal are shortened according to the input current; a hybrid control mode in which a pulse width control mode for controlling the width of the pulses of the drive signal and an intermittent control mode for shortening the pulses of the drive signal are combined; and a second intermittent control mode in which the pulses of the drive signal are shortened according to the output voltage. When the duty cycle of the drive signal is below a predetermined threshold, the control circuit selects the second intermittent control mode. When the duty cycle of the drive signal exceeds the predetermined threshold and the input voltage is above a predetermined value, the control circuit selects the hybrid control mode. When the duty cycle of the drive signal exceeds the predetermined threshold and the input voltage is below a predetermined value, the control circuit selects the first intermittent control mode.

Description

Technical Field

[0001] The present invention relates to a power supply device, and in particular to a direct current-to-direct current (DC-DC) converter. Background Art

[0002] A DC-DC converter is a conversion circuit that converts a certain DC (direct current) input voltage into a required fixed DC output voltage. Patent Document 1 describes intermittent operation of a switching element when the DC-DC converter is in a low-load state.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2016-063621 Summary of the Invention

[0006] Problems to be solved by the invention

[0007] In a low-load state, the pulse width of the drive signal supplied to the gate of the switching element is very narrow. Therefore, a high-precision integrated circuit (IC) is required to accurately detect the output current used to determine whether the device is in a low-load state. Therefore, it is desirable to detect the low-load state cheaply without using an expensive IC. In addition, in a DC-DC converter used in a power supply device such as an engine-driven generator, the no-load state sometimes lasts for a long time. Therefore, it is also desirable to improve the efficiency of the DC-DC converter in the no-load state. Therefore, an object of the present invention is to provide a DC-DC converter that can cheaply improve the power conversion efficiency in a low-load state.

[0008] Solutions for solving problems

[0009] According to the present invention, for example, a DC-DC converter is provided, which has:

[0010] a conversion circuit that converts a DC input voltage supplied from a DC power supply into a DC output voltage;

[0011] a current detection circuit for detecting an input current supplied from the DC power supply to the conversion circuit;

[0012] an input voltage detection circuit, which detects the input voltage;

[0013] an output voltage detection circuit, which detects the output voltage; and

[0014] a control circuit that controls the output voltage by supplying a pulsed drive signal to the conversion circuit;

[0015] The control circuit has:

[0016] A first intermittent control mode is a mode in which the pulses of the driving signal are reduced in intervals according to the input current;

[0017] A hybrid control mode, which is a combination of pulse width control for controlling the width of the pulses of the drive signal and intermittent control for reducing the intervals between the pulses of the drive signal; and

[0018] The second intermittent control mode is a mode in which the pulses of the driving signal are reduced in intervals according to the output voltage.

[0019] The control circuit is composed of:

[0020] When the duty cycle of the driving signal is below a predetermined threshold, the second intermittent control mode is selected.

[0021] When the duty cycle of the drive signal exceeds the predetermined threshold and the input voltage is equal to or greater than a predetermined value, the hybrid control mode is selected.

[0022] The first intermittent control mode is selected when the duty ratio of the drive signal exceeds the predetermined threshold value and when the input voltage is less than the predetermined specified value.

[0023] Effects of the Invention

[0024] According to the present invention, a DC-DC converter capable of improving power conversion efficiency in a low-load state at low cost is provided.

[0025] Other features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included in the specification and constitute a part of the specification. They illustrate embodiments of the present invention and, together with the description of the embodiments, explain the principles of the present invention.

[0027] Figure 1 is a block diagram showing a power supply device.

[0028] Figure 2 It is a block diagram showing the functions of the CPU.

[0029] Figure 3 It is a block diagram showing the functions of the CPU.

[0030] Figure 4 is a flowchart illustrating a method for controlling a DC-DC converter.

[0031] Figure 5 is a block diagram showing a conversion circuit. DETAILED DESCRIPTION

[0032] The following embodiments are described in detail with reference to the accompanying drawings. The following embodiments are not intended to limit the scope of the claims, and the present invention does not require the combination of all features described in the embodiments. Any combination of two or more of the multiple features described in the embodiments is also possible. Identical or similar structures are denoted by the same reference numerals, and repeated descriptions are omitted.

[0033] <Power Supply Unit>

[0034] Figure 1 A power supply device 1 is shown. The power supply device 1 includes a DC power supply 10, a DC-DC converter 20, and an inverter 30. The DC power supply 10 is a battery, an engine-driven generator, or the like. Here, a battery-type DC power supply 10 is assumed. The DC-DC converter 20 converts a DC input voltage Vin supplied from the DC power supply 10 into a DC output voltage Vout, which is then output to the inverter 30. The inverter 30 converts the output voltage Vout supplied from the DC-DC converter 20 into an AC output voltage Vac, which is then supplied to a load 40.

[0035] In the DC-DC converter 20, the current detection circuit 23 detects the input current Iin from the DC power supply 10 and outputs the detection result to the AD interface of the CPU 28. The AD interface includes an AD converter that converts analog signals into digital signals. The current detection circuit 23 includes, for example, a shunt resistor (a resistor for detecting current). The voltage detection circuit 22a detects the input voltage Vin from the DC power supply 10 and outputs the detection result to the CPU 28. The voltage detection circuit 22a includes, for example, a plurality of voltage-dividing resistors that convert the input voltage Vin into a detection voltage proportional to the input voltage Vin.

[0036] The conversion circuit 25 is a circuit that converts the input voltage Vin into the output voltage Vout. The conversion circuit 25 can also be a switching converter including a switching circuit (for example, a full-bridge circuit formed by four field-effect transistors), a transformer, a rectifier circuit (for example, a bridge diode), and a smoothing circuit (for example, an electrolytic capacitor). The CPU 28 controls the output voltage Vout toward the target voltage Vtar by controlling the drive signal input to the conversion circuit 25. The drive signal is, for example, a pulse signal (a signal that has undergone pulse width modulation (PWM)). Such a drive signal is individually supplied to each of the four switching elements that constitute the switching circuit provided inside the conversion circuit 25. The conversion circuit 25 includes a transformer. The winding ratio n of the transformer is determined as follows: the DC-DC converter 20 outputs a predetermined maximum output voltage (for example, 200V) relative to a predetermined minimum input voltage (for example, 40V).

[0037] CPU 28 executes various processes according to the control program stored in memory 29. For example, CPU 28 can calculate the power consumption Pin of DC-DC converter 20 based on the detection results of input current Iin and input voltage Vin, and determine the load status based on the power consumption Pin. In this way, input current Iin and power consumption Pin can be used as indicators for determining the load 40. Power consumption Pin can also be referred to as input power.

[0038] [CPU Function]

[0039] Figure 2 The following table shows functions related to controlling the output voltage Vout. The CPU 28 implements the functions described below by executing a control program. Some or all of the functions described below can be implemented using hardware circuits such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). Alternatively, the CPU 28 can be comprised of one or more processor circuits. Thus, each function can be implemented by either logic circuits or program modules.

[0040] The input current monitoring unit 201 monitors the input current Iin detected by the current detection circuit 23. When the conditions for obtaining the input current Iin are met, the input current monitoring unit 201 obtains the detection result of the input current Iin from the current detection circuit 23. The input current monitoring unit 201 may be an analog-to-digital conversion circuit. The input voltage monitoring unit 202 monitors the input voltage Vin detected by the voltage detection circuit 22a. When the conditions for obtaining the input voltage Vin are met, the input voltage monitoring unit 202 obtains the detection result of the input voltage Vin from the current detection circuit 23. The input voltage monitoring unit 202 may be an analog-to-digital conversion circuit. The load calculation unit 203 calculates the load status (e.g., Pin = Iin × Vin) based on the input current Iin and the input voltage Vin. Alternatively, the load calculation unit 203 may calculate the load status using only the input current Iin. The mathematical formula used to calculate the load status based on the input current Iin may be stored in the ROM area of ​​the memory 29. The load determination unit 204 determines whether the load status is low load or normal load. For example, if the power consumption Pin associated with the load state is less than a threshold value Pth, the load determination unit 204 may determine that the load state is a low load. Alternatively, if the power consumption Pin associated with the load state is greater than or equal to the threshold value Pth, the load determination unit 204 may determine that the load state is a normal load.

[0041] When the load state is low, the low-load control unit 205 controls the conversion circuit 25. When the load state is normal, the normal-load control unit 206 controls the conversion circuit 25. The normal-load control unit 206 controls the pulse width of the drive signal (pulse width control) so that the output voltage Vout reaches the target voltage Vtar. Thus, the load determination unit 204 selects either the low-load control unit 205 or the normal-load control unit 206, or sets it to active (enabled), depending on the load state.

[0042] Figure 3 Detailed information about the low-load control unit 205 is shown. The pulse width monitoring unit 301 acquires and monitors the pulse width D of the drive signal. For example, the pulse width monitoring unit 301 can read the pulse width D determined by the CPU 28 and stored in the RAM area of ​​the memory 29. The pulse width determination unit 302 determines whether the pulse width D exceeds a threshold value Dth. The threshold value Dth can be predetermined and stored in the ROM area of ​​the memory 29.

[0043] Typically, when the output voltage Vout exceeds the target voltage Vtar, the pulse width D is reduced. On the other hand, when the output voltage Vout does not exceed the target voltage Vtar, the pulse width D increases. In the steady-state state, where the output voltage Vout is maintained at the target voltage Vtar, the pulse width D increases when the input voltage Vin decreases. Similarly, in the steady-state state, when the input voltage Vin increases, the pulse width D is reduced. Furthermore, as the load increases, more current is required, and therefore the pulse width D increases. Furthermore, as the load decreases, the pulse width D is also reduced. When the load 40 becomes light, the pulse width D sometimes becomes extremely short. Specifically, the duty cycle of the drive signal sometimes drops below 0.1 (=10%). For example, the pulse width sometimes becomes several nanoseconds. Under such low-load conditions, it is difficult to detect the required current value. Typically, integrated circuits (current sensing ICs) used for current detection can only detect signals up to 1 MHz when converted to a frequency. Therefore, when the pulse width D exceeds the threshold Dth, intermittent control based on the input current Iin is performed to improve the conversion efficiency of the DC-DC converter 20. On the other hand, when pulse width D is below threshold Dth, the detection accuracy of input current Iin decreases. Therefore, intermittent control corresponding to output voltage Vout is implemented. Here, intermittent control refers to the interval reduction of the pulses of the drive signal.

[0044] Here, the duty ratio can be replaced with a pulse width D. Therefore, the pulse width D may refer to the duty ratio or the duration of the pulse (on-time).

[0045] ●When the pulse width D exceeds the threshold Dth

[0046] Input voltage determination unit 303 determines whether input voltage Vin is less than threshold value Vth1. As the charge level of the battery in DC power supply 10 decreases, input voltage Vin decreases. Therefore, when input voltage Vin is less than threshold value Vth1, first intermittent control unit 304 performs intermittent control of the drive signal based on input current Iin. First intermittent control unit 304 appropriately reduces the pulse width of the drive signal based on input current Iin, thereby maintaining output voltage Vout at target voltage Vtar.

[0047] On the other hand, when the input voltage Vin is above the threshold value Vth1, the hybrid control unit 305 executes the drive signal. The hybrid control unit 305 performs a control that combines pulse width control and partial intermittent control. For example, the hybrid control unit 305 adjusts the pulse width D within a range in which the pulse width D does not fall below the threshold value Dth, and reduces the intervals of the pulses of the drive signal as needed, thereby maintaining the output voltage Vout at the target voltage Vtar. For example, the hybrid control unit 305 sets the pulse width D (duty cycle) to an upper limit value (e.g., 90%) and reduces the intervals of the pulses, thereby maintaining the output voltage Vout at the target voltage Vtar. Assuming that even if the pulse interval is reduced, the output voltage Vout cannot be reduced to the target voltage Vtar, the hybrid control unit 305 reduces the pulse width D.

[0048] The output voltage monitoring unit 306 obtains or monitors the detection result of the output voltage Vout outputted from the voltage detection circuit 22b. The output voltage determination unit 307 determines whether the output voltage Vout exceeds the threshold value Vth2. The DC-DC converter 20 has a rated voltage (specification). For example, the rated voltage is set to 165±10V. In this example, the threshold value Vht2 is set to 155V as the lower limit. When the pulse width D is extremely shortened, the detection accuracy of the input current Iin decreases. Therefore, the second intermittent control unit 308 performs intermittent control of the drive signal based on the output voltage Vout. In other words, if the pulse width D is extremely shortened and the output voltage Vout exceeds the threshold value Vth2, the pulse width D cannot be reduced. Therefore, the pulse interval of the drive signal is reduced according to the output voltage Vout. On the other hand, when the pulse width D is extremely short, the output voltage Vout may not exceed the threshold value Vth2. In this case, the pulse width setting unit 309 increases the pulse width D of the drive signal to maintain the output voltage Vout at the target voltage Vtar.

[0049] Furthermore, first intermittent control unit 304, mixing control unit 305, and second intermittent control unit 308 sometimes reduce the intervals of the drive signal pulses. For example, if the drive signal frequency is 100 kHz and the pulse intervals are reduced during three of four consecutive cycles, the drive signal frequency may partially reach 25 kHz. If the frequency drops further, the drive signal generates audible sound (sound waves below 20 kHz) from the transformer, which can be heard by humans. This may result in noise. Therefore, when reducing the intervals of the pulses, CPU 28 sets the pulse interval reduction rate (interval reduction period) so that the drive signal frequency exceeds the frequency of the audible sound.

[0050] <Flowchart>

[0051] Figure 4 1 and 2 show a series of processes executed according to the control program by the CPU 28. In the following, the pulse period of the drive signal is basically fixed.

[0052] In step S401, the CPU 28 (input current monitoring unit 201 and load calculation unit 203) detects the load 40 based on the input current Iin. For example, if the load 40 is represented by the power consumption Pin, the CPU 28 (input current monitoring unit 201 and input voltage monitoring unit 202) detects the input current Iin and the input voltage Vin. The load calculation unit 203 calculates the power consumption Pin, a parameter representing the load state, based on the input current Iin and the input voltage Vin.

[0053] In step S402, the CPU 28 (load judgment unit 204) determines whether the load 40 is a low load. For example, if the power consumption Pin is less than the load threshold value Pth, the load judgment unit 204 determines that the load 40 is a low load. If the power consumption Pin is above the load threshold value Pth, the load judgment unit 204 determines that the load 40 is a normal load. If the load state is not a low load, the CPU 28 proceeds to step S441. In step S441, the CPU 28 (normal load control unit 206) performs pulse width control. Normally, the load control unit 206 adjusts the pulse width D of the drive signal so that the output voltage Vout is maintained at a preset target voltage Vtar. If the load state is a low load, the CPU 28 proceeds to step S403.

[0054] In step S403, the CPU 28 (low-load control unit 205 and pulse width monitoring unit 301) obtains the pulse width D of the drive signal. As described above, the current pulse width D is stored in the RAM area of ​​the memory 29, so the CPU 28 obtains the pulse width D from the memory. Alternatively, the pulse width D can be calculated based on the input voltage Vin, the output voltage Vout, and the transformer winding ratio n (D = Vout / (n × Vin)). The transformer winding ratio n is stored in the ROM area of ​​the memory 29.

[0055] In step S404, the CPU 28 (pulse width determination unit 302) determines whether the pulse width D exceeds a predetermined threshold value Dth. If the pulse width D exceeds the predetermined threshold value Dth, the CPU 28 proceeds to step S405. Here, if the pulse width D represents the duty cycle, the threshold value Dth may be set to, for example, 0.1 (i.e., 10%).

[0056] In step S405, the CPU 28 (input voltage determination unit 303) determines whether the input voltage Vin is less than a predetermined threshold value Vth1. If the input voltage Vin is less than the predetermined threshold value Vth1, the CPU 28 proceeds to step S406. The threshold value Vth1 is set to 60V, for example.

[0057] In step S406, the CPU 28 (first intermittent control unit 304) performs intermittent control based on the input current Iin. That is, the first intermittent control unit 304 reduces the pulse intervals of the drive signal based on the input current Iin so that the output voltage Vout is maintained at the target voltage Vtar. The CPU 28 reduces the pulse intervals within a range that does not produce audible sound. The pulse period of the drive signal is fixed. Here, the pulse width D increases until the output voltage Vout reaches the target voltage Vtar. When the output voltage Vout reaches the target voltage Vtar, the pulse width D is fixed. Thereafter, when the output voltage Vout exceeds the target voltage Vtar, the pulse intervals of the drive signal are reduced. Thus, the output voltage Vout is maintained at the target voltage Vtar. Alternatively, a control table storing the relationship between the input current Iin and the amount of reduction in pulse intervals may be stored in the ROM area of ​​the memory 29. The CPU 28 can refer to this table to determine the amount of reduction in pulse intervals based on the input current Iin.

[0058] In step S405, when it is determined that the input voltage Vin is above the predetermined threshold value Vth1, step S411 is executed. In step S411, the CPU 28 (hybrid control unit 305) executes a hybrid control that combines pulse width control and partial intermittent control. The hybrid control unit 305 sets the initial value of the pulse width D (duty cycle) to 90%. The hybrid control unit 305 reduces the pulse intervals of the drive signal so that the output voltage Vout is maintained at the target voltage Vtar. In this case, the hybrid control unit 305 gradually increases the pulse interval reduction period (reduces the interval reduction frequency) within a range where the output voltage Vout does not fluctuate and does not produce audible sound. When the interval reduction frequency reaches 20kHz, most people can recognize the sound. Therefore, the lower limit of the interval reduction frequency can be set to 25kHz, for example. Even if the interval reduction frequency is reduced to the lower limit, the output voltage Vout sometimes does not reach the target voltage Vtar. In this case, the hybrid control unit 305 gradually reduces the pulse width D from the initial value. The pulse period of the drive signal is fixed.

[0059] Furthermore, the ROM area of ​​the memory 29 may store a control table for determining the pulse width. For example, the control table may store the relationship between the input voltage Vin and the amount of pulse interval reduction. Alternatively, the control table may store the relationship between the input power (input voltage Vin x input current Iin) and the amount of pulse interval reduction. The CPU 28 can obtain the amount of pulse interval reduction from the control table by referring to it based on the input voltage Vin.

[0060] In step S404, when the pulse width D is equal to or smaller than the threshold value Dth (for example, when there is no load), the CPU 28 proceeds to step S421. In step S421, the CPU 28 (output voltage monitoring unit 306) detects the output voltage Vout.

[0061] In step S422, the CPU 28 (output voltage determination unit 307) determines whether the output voltage Vout exceeds a predetermined threshold value Vth2. If the output voltage Vout exceeds the predetermined threshold value Vth2, the CPU 28 proceeds to step S423. The threshold value Vth2 is set to 155V, for example.

[0062] In step S423, the CPU 28 (second intermittent control unit 308) performs intermittent control based on the output voltage Vout. The second intermittent control unit 308 reduces the pulse intervals of the drive signal based on the output voltage Vout, maintaining the output voltage Vout at the target voltage Vtar. In other words, the frequency of pulse interval reduction is determined based on the output voltage Vout. The pulse period of the drive signal is fixed. Furthermore, a control table storing the relationship between the output voltage Vout and the amount of pulse interval reduction is stored in the ROM area of ​​the memory 29. The CPU 28 can refer to this table to determine the amount of pulse interval reduction based on the output voltage Vout.

[0063] In step S422, if the output voltage Vout is equal to or lower than the predetermined threshold value Vth2, the CPU 28 proceeds to step S431. In step S431, the CPU 28 (pulse width setting unit 309) increases the pulse width D. As a result, the output voltage Vout exceeds the threshold value Vth2 and approaches the target voltage Vtar.

[0064] Summary

[0065] [Viewpoint 1]

[0066] like Figure 1As shown, the conversion circuit 25 converts the DC input voltage Vin supplied from the DC power supply 10 into a DC output voltage Vout. The current detection circuit 23 detects the input current Iin supplied from the DC power supply 10 to the conversion circuit 25. The voltage detection circuit 22a functions as an input voltage detection circuit for detecting the input voltage Vin. The voltage detection circuit 22b functions as an output voltage detection circuit for detecting the output voltage Vout. The CPU 28 functions as a control circuit, controlling the output voltage Vout by supplying a pulsed drive signal to the conversion circuit 25. The control circuit can have multiple control modes. As described in connection with S406, the first intermittent control mode is a control mode in which the pulses of the drive signal are shortened according to the input current Iin. As described in connection with S411, the hybrid control mode is a control mode that combines pulse width control, which controls the width of the pulses of the drive signal, with intermittent control, which shortens the pulses of the drive signal. As described in connection with S423, the second intermittent control mode is a control mode in which the pulses of the drive signal are shortened according to the output voltage Vout. When the duty cycle of the drive signal (e.g., pulse width D) is below a predetermined threshold (e.g., Dth), the control circuit selects the second intermittent control mode. When the duty cycle of the drive signal exceeds the predetermined threshold and the input voltage Vin is above a predetermined value (e.g., Vth1), the control circuit selects the hybrid control mode. The control circuit is configured to select the first intermittent control mode when the duty cycle of the drive signal exceeds the predetermined threshold and the input voltage Vin is below a predetermined value. This allows intermittent control (the second intermittent control mode) to be performed under very low load conditions (e.g., no load), using the output voltage instead of the input current detection result. Therefore, an expensive and highly accurate current sensing IC is not required. Furthermore, under low load conditions (not nearly no load), current detection accuracy can be low. In other words, intermittent control (the first intermittent control mode) is performed based on the input current detected by a current sensing IC with low detection accuracy. When the input voltage Vin is above a predetermined value (e.g., Vth1), the hybrid control mode is selected. In hybrid control mode, the pulse interval is reduced while maintaining a certain pulse width. In conventional pulse width control, when the input voltage increases, the pulse width is reduced to maintain the output voltage Vout at the target voltage Vtar. In this case, under low load conditions, the duty cycle is less than 10%, and the pulse width becomes several nanoseconds, which may reduce power conversion efficiency. Therefore, in the present invention, the pulse interval is reduced while maintaining a certain pulse width. As a result, it is believed that power conversion efficiency is improved. Thus, according to the present invention, a DC-DC converter 20 is provided that can inexpensively improve power conversion efficiency under low load conditions.

[0067] In a normal load state, when the input voltage Vin exceeds the threshold value Vth1, the hybrid control mode may be applied, thereby improving the power conversion efficiency.

[0068] In the second intermittent control mode, the pulse interval is reduced based on the output voltage, so the ripple is less likely to increase. This can also reduce the capacitance of the electrolytic capacitor used to suppress the ripple.

[0069] [Viewpoints 2-4]

[0070] The first intermittent control mode and the second intermittent control mode temporarily stop the output of the drive signal, thereby reducing the pulse interval for each predetermined period that is longer than the pulse period of the drive signal. The predetermined period for reducing the pulse interval is a period shorter than the period of audible sound. For example, when the frequency (switching frequency) of the drive signal is 100kHz, one to three pulses out of four consecutive pulses in the drive signal are reduced. For example, when three pulses are reduced, the reduction frequency becomes 25kHz, which exceeds the frequency of audible sound, i.e., 20kHz. As a result, even if the pulse interval is reduced, the user is less likely to perceive noise. In this way, the frequency of audible sound is 20kHz. The control circuit determines the predetermined period for reducing the pulse interval in a manner that satisfies the constraints established to prevent the generation of audible sound below 20kHz. In addition, audible sound may be generated in the windings of the transformer provided in the conversion circuit 25. This is sometimes also referred to as ringing.

[0071] [Viewpoint 5]

[0072] Figure 5 An example of a conversion circuit 25 is shown. The switching circuit 501 is a circuit that switches the input voltage Vin supplied from the DC power supply 10. The switching circuit 501 includes switching elements Q1, Q2, Q3, and Q4 such as MOSFETs. The transformer T1 is connected to the switching circuit 501. The rectifier and smoothing circuit 502 is connected to the secondary side of the transformer T1 to generate the output voltage Vout. The rectifier and smoothing circuit 502 includes a diode bridge (rectifier circuit) composed of diodes D1, D2, D3, and D4. The rectifier and smoothing circuit 502 includes an electrolytic capacitor C1. The electrolytic capacitor C1 is a smoothing circuit that smoothes the pulsating current output from the diode bridge and generates a direct current. The switching circuit 501 can be any of a full-bridge circuit and a half-bridge circuit.

[0073] The present invention is not limited to the above-described embodiment, and various modifications and changes can be made within the scope of the gist of the invention.

Claims

1. A DC-DC converter comprising: a conversion circuit that converts a DC input voltage supplied from a DC power supply into a DC output voltage; a current detection circuit for detecting an input current supplied from the DC power supply to the conversion circuit; an input voltage detection circuit, which detects the input voltage; an output voltage detection circuit, which detects the output voltage; as well as a control circuit that controls the output voltage by supplying a pulsed drive signal to the conversion circuit; The control circuit has: A first intermittent control mode is a mode in which the pulses of the driving signal are reduced in intervals according to the input current; A hybrid control mode, which is a combination of pulse width control for controlling the width of the pulses of the drive signal and intermittent control for reducing the intervals between the pulses of the drive signal; and The second intermittent control mode is a mode in which the pulses of the driving signal are reduced in intervals according to the output voltage. The control circuit is configured to select the following corresponding control mode when the load state is low load: When the duty cycle of the drive signal is below a predetermined threshold and the output voltage exceeds a predetermined second specified value, the second intermittent control mode is selected. When the duty cycle of the drive signal exceeds the predetermined threshold and the input voltage is equal to or greater than a predetermined first value, the hybrid control mode is selected. The first intermittent control mode is selected when the duty ratio of the drive signal exceeds the predetermined threshold value and when the input voltage is less than the predetermined first specified value.

2. The DC-DC converter according to claim 1, wherein: The first intermittent control mode and the second intermittent control mode include temporarily stopping the output of the drive signal to thereby reduce the interval between pulses at every predetermined period longer than the period of the pulses of the drive signal.

3. The DC-DC converter according to claim 2, wherein: The predetermined period for reducing the intervals of the pulses is a period shorter than a period of audible sound.

4. The DC-DC converter according to claim 3, wherein: The frequency of the audible sound is 20 kHz, and the control circuit determines the predetermined period for reducing the intervals between the pulses so as to satisfy a constraint condition determined so as not to emit audible sounds below 20 kHz.

5. The DC-DC converter according to any one of claims 1 to 4, characterized in that: The conversion circuit comprises: a switching circuit for switching the input voltage supplied from the DC power supply; a transformer connected to the switching circuit; and The rectifying and smoothing circuit is connected to the secondary side of the transformer and generates the output voltage.

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