Amplifier

Abstract

This application relates to an amplifier that can selectively operate in a first mode or a second mode. The first mode is a BTL mode, in which both a first output driver and a second output driver (103p, 103n) are active to generate corresponding drive signals that vary with the input signal. The second mode is an SE mode, in which the first output driver (103p) is active to generate the drive signal, and the output of the second driver (103n) remains constant. A controller (201) selectively controls the mode based on an indication of the output signal amplitude. In the first mode, the ratio of the magnitudes of the two drive signals varies with the indication of the output signal amplitude, i.e., the magnitudes of the two drive signals can vary so that they are not equal.

Description

Technical Field

[0001] The field of representative embodiments of this disclosure relates to amplifiers, particularly amplifiers for driving loads such as transducers, or methods, apparatus and / or implementations related to amplifiers. Background Technology

[0002] Many electronic devices include amplifier circuits for generating drive signals for driving transducers (e.g., for driving audio signals into audio output transducers such as loudspeakers).

[0003] In some applications, amplifier circuits can be configured to drive transducers in a bridged load (BTL) configuration. In a BTL configuration, the two sides of the load are driven by complementary drive signals to apply an associated drive voltage to the load.

[0004] Figure 1 An example of an amplifier circuit 100 for driving transducer 101 (in this example, a loudspeaker) in a BTL configuration is shown. Figure 1 The amplifier circuit shown has an amplifier stage 102, which in this example includes a corresponding positive driver 103p and a negative driver 103n, which are used to drive corresponding positive output terminals 104p and negative output terminals 104n coupled to opposite sides of transducer 101 with complementary drive signals Vp and Vn based on the input signal Sin, so as to apply an output signal Vout to the load 101.

[0005] exist Figure 1 In the example, amplifier stage 102 receives differential inputs Sinp and Sinn and amplifies these differential inputs to provide differential drive signals Vp and Vn. In some implementations, amplifier circuit 100 may receive the input signal Sin and derive the differential signals Sinp and Sinn from it, for example, as shown in the example below. Figure 1 As shown, the input signal Sin is used as the positive signal component, and an inverter 105 is provided to invert the input signal Sin to provide the negative signal component Sinn. However, it should be understood that other arrangements are possible, or the amplifier circuit 100 may accept differential inputs.

[0006] Each of the positive driver 103p and the negative driver 103n can be an amplifier that receives supply voltages VH and VL, such as a supply voltage and ground, or a positive supply voltage and a negative supply voltage. In some applications, drivers 103p and 103n can be implemented as Class D amplifiers, which, as those skilled in the art will understand, can switch between the two supply voltages by duty cycle based on the corresponding input Sinp or Sinn.

[0007] Therefore, the BTL arrangement of amplifier circuit 100 utilizes a drive voltage that varies with the input signal Sin to drive both sides of the load (e.g., transducer 101). This offers an advantage in terms of maximum power output compared to an alternative single-ended configuration, in which the variable drive voltage is applied only to one side of the load transducer, and the other side of the transducer is connected to a reference voltage, which, for audio transducers, is the midpoint voltage.

[0008] In a BTL configuration, one side of the load can be driven close to VH (inappropriate margin), while the other side can be driven close to VL. Therefore, the maximum value of the output voltage may be close to the supply voltage, i.e., VH-VL. In a single-ended configuration, one side of the load is held at the midpoint voltage, and therefore the maximum value of the output voltage is equal to half the supply voltage (less margin).

[0009] In at least some applications, it may be desirable for amplifier circuitry to be operable to drive the transducer with a relatively high power drive voltage, and thus enable a BTL configuration.

[0010] However, power efficiency is also desirable in at least some applications, particularly for portable devices and / or battery-powered devices, where power consumption is an important consideration for lifespan. Summary of the Invention

[0011] Embodiments of this disclosure relate to improved amplifier arrangements and amplification methods. Specifically, embodiments may relate to an amplifier arrangement that can operate in a BTL configuration but provides power efficiency advantages.

[0012] According to one aspect of this disclosure, an amplifier circuit is provided for generating an output signal between a first output node and a second output node based on a received input signal, the amplifier circuit comprising:

[0013] First output driver and second output driver; and

[0014] A controller, configured to selectively control the amplifier circuit in a first mode or a second mode based on an indication of the output signal amplitude; wherein:

[0015] In the first mode, both the first output driver and the second output driver are active to generate corresponding first and second drive signals, which vary according to the input signals at the first and second output nodes, respectively.

[0016] In the second mode, the first output driver is activated to generate a first drive signal at the first output node that varies with the input signal, and the second output node is maintained at a constant voltage;

[0017] Furthermore, in the first mode, the ratio of the magnitude of the second drive signal to the magnitude of the first drive signal varies with the indication of the output signal amplitude.

[0018] In some examples, the controller is configured such that, when operating in the first mode, the ratio of the magnitude of the second drive signal to the magnitude of the first drive signal varies from zero to one and increases as the output signal amplitude increases. The controller may be configured to minimize the ratio of the magnitude of the second drive signal to the magnitude of the first drive signal in the first mode.

[0019] In some examples, the first output driver is located in a first signal path and the second output driver is located in a second signal path, and the controller is configured to control the ratio of the magnitude of the second drive signal to the magnitude of the first drive signal by controlling the gain applied in the first signal path and the second signal path.

[0020] In some examples, the indication of the output signal amplitude includes a gain setting that indicates the gain to be applied by the amplifier circuitry.

[0021] Alternatively or concurrently, in some examples, the indication of the output signal amplitude includes an indication of the amplitude of the input signal. In this case, the controller may include an envelope detector configured to receive a version of the input signal and determine the amplitude of the input signal. The amplifier circuit may include at least one element having a propagation delay, the at least one element being located upstream of the signal path of at least one of the first output driver and the second output driver, and the envelope detector may receive the version of the input signal upstream of the delay element.

[0022] In some examples, the controller may be further configured to selectively control the bias applied to at least the first output driver based on the indication of the amplitude of the output signal. The controller may be configured such that a lower bias current is applied to the first output driver in the second mode compared to the first mode. The controller may be configured such that the bias current applied to the first output driver in the first mode increases with increasing output signal amplitude.

[0023] In some examples, the amplifier circuit may include a voltage regulator that activates in the second mode to regulate the voltage at the second output node. The voltage regulator may include at least one of the following: a DC-DC converter and a charge pump.

[0024] In some examples, the controller may be configured to disable the second output driver when operating in the second mode.

[0025] In some examples, the first output driver and the second output driver each include a corresponding Class D amplifier.

[0026] In use, the amplifier circuit may further include a load transducer coupled between the first output node and the second output node. In some examples, the load transducer may include a loudspeaker.

[0027] The invention also relates to an electronic device comprising an amplifier circuit of any of the embodiments described herein.

[0028] On the other hand, an amplifier circuit is provided for generating an output signal between a first output node and a second output node based on a received input signal, the amplifier circuit comprising:

[0029] First output driver and second output driver;

[0030] The amplifier circuit can operate in a first mode, in which both the first output driver and the second output driver are active to generate corresponding first and second drive signals, the first and second drive signals varying with the input signals at the first and second output nodes, respectively; and wherein in the first mode, the ratio of the magnitude of the second drive signal to the magnitude of the first drive signal varies with the indication of the output signal amplitude.

[0031] In another aspect, an amplifier circuit is provided, comprising:

[0032] A first signal path, the first signal path including a first amplifier;

[0033] A second signal path, the second signal path including a second amplifier; and

[0034] A controller, the controller being configured to selectively operate the circuit as follows:

[0035] A first mode, wherein both the first amplifier and the second amplifier are active to drive a first output node and a second output node using corresponding first and second drive signals, the first and second drive signals respectively varying with the input signal; and

[0036] In the second mode, the first amplifier is activated to drive the first output node using the first drive signal, the first drive signal varying with the input signal, and the second output node is maintained at a constant voltage.

[0037] When the output signal amplitude is within a first range, the controller operates in the first mode, and the controller controls the gain of the second signal path to decrease as the output signal amplitude decreases within the first range, while maintaining or increasing the gain of the first signal path.

[0038] In another aspect, an amplifier circuit is provided, comprising:

[0039] A first signal path, the first signal path including a first amplifier;

[0040] A second signal path, the second signal path including a second amplifier; and

[0041] A controller, the controller being configured to selectively operate the circuit as follows:

[0042] A first mode, wherein both the first amplifier and the second amplifier are active to drive a first output node and a second output node using corresponding first and second drive signals, the first and second drive signals respectively varying with the input signal; and

[0043] In the second mode, the first amplifier is activated to drive the first output node using the first drive signal, the first drive signal varying with the input signal, and the second output node remains at a constant voltage; and

[0044] In the first mode, the gain of the first signal path is controlled to be constant at a first value, and the gain of the second signal path is selectively variable within a range of gain values ​​up to the first value, based on a gain control signal; and

[0045] In the second mode, the gain of the first signal path is selectively variable within a range of gain values ​​up to the first value, based on a gain control signal.

[0046] Unless otherwise expressly indicated, any of the various features of the various implementations discussed herein may be implemented in any and all suitable combinations together with any one or more of the other described features. Attached Figure Description

[0047] To better understand the examples of this disclosure and to more clearly illustrate how these examples can be implemented, reference will now be made to the accompanying drawings by way of example only, in which:

[0048] Figure 1 An example of an amplifier circuit for driving a load in a bridged load configuration is shown;

[0049] Figure 2 An example of an amplifier circuit according to one embodiment is shown;

[0050] Figure 3 Another example of an amplifier circuit according to one embodiment is shown;

[0051] Figure 4 An example illustrating how to control the gain of the positive and negative paths of an amplifier circuit;

[0052] Figure 5 This provides another example of how to control the gain of the positive and negative paths of an amplifier circuit; and

[0053] Figure 6 An example of a suitable voltage regulator is shown. Detailed Implementation

[0054] The following description illustrates exemplary embodiments according to this disclosure. Further exemplary embodiments and implementations will be apparent to those skilled in the art. Furthermore, those skilled in the art will recognize that various equivalent techniques may be applied in place of or in combination with the embodiments discussed below, and all such equivalents should be considered to be covered by this disclosure.

[0055] As referenced above Figure 1The bridged load (BTL) configuration discussed can be used to drive loads, such as transducers, in several applications. In a BTL configuration, both sides of the load transducer are driven by a drive signal. Therefore, with two drivers 103p and 103n receiving supply voltages VH and VL, one side of the transducer can be driven close to VH, while the other side is driven close to VL (with a smaller amplifier margin), thus applying almost the full voltage value |VH-VL| as the output signal Vout across the load transducer. For a single-ended drive configuration, one side of the transducer remains at the midpoint voltage Vmid (equal to (VH-VL) / 2), and therefore the maximum voltage of the output signal that can be applied is close to half the full voltage value of the difference between the supply voltages (again, a smaller margin). Therefore, for a given voltage supply, the BTL configuration is advantageous for driving loads with a higher power drive signal than the single-ended configuration.

[0056] However, while a BTL configuration may be advantageous for providing output drive signals with amplitudes significantly proportional to the supply voltage, it can be relatively inefficient in terms of power efficiency at lower output signal levels. Generally, as those skilled in the art will understand, the efficiency of a linear amplifier can be characterized as being proportional to Vsig / Vdd, where Vsig is the amplitude of the amplifier output and Vdd is a magnitude of the supply voltage (i.e., VH-VL). Therefore, in general, any amplifier with an output amplitude significantly lower than the supply voltage operates inefficiently, but for a BTL configuration, this is because each output driver 103p and 103n generates a drive signal Vp or Vp with an amplitude of half the total drive signal.

[0057] Alternatively, the BTL amplifier circuit can also be implemented using a Class D amplifier for the drivers 103p and 103n. Class D amplifiers operate by switching between supply voltages, with the duty cycle controlled based on the input signal. Switching losses mean that Class D amplifiers are relatively inefficient at low power signal levels.

[0058] This disclosure relates to an amplifier circuit and its operation method, wherein the amplifier circuit includes an output stage that can be BTL configured to operate to drive a load, but can also operate in a single-ended operation mode, and is configured to dynamically switch between operating modes during use. The operating mode can be controlled based on an indication of the output signal amplitude.

[0059] If the output signal amplitude indication indicates a relatively low desired output signal amplitude, and this amplitude is within the output range of only one of the drivers, the amplifier circuit can operate in single-ended mode. In this mode, one of the drivers in the output stage provides a drive signal that provides a full voltage offset for the desired output signal relative to a defined quiescent voltage level (typically the midpoint voltage Vmid). The other driver can then be disabled, and the voltage at the relevant output can be maintained at the midpoint voltage. Therefore, disabling one driver and using the other to provide the full voltage offset improves the efficiency of the amplifier circuit and, in the case of a Class D amplifier, avoids the switching losses associated with one of the drivers.

[0060] However, if the output signal amplitude indication suggests that the required output signal may exceed the output range of only one of the drivers, the amplifier circuit can be configured to operate in BTL mode and apply a time-varying drive signal to both sides of the load based on the input signal.

[0061] Figure 2 An example of an amplifier circuit 200 according to one embodiment is shown, wherein the same reference numerals are used to identify and reference it. Figure 1 The similar components discussed.

[0062] Figure 2 The amplifier circuit 200 includes an amplifier stage 202. The amplifier stage 202 has outputs 104p and 104n, which are used to connect to both sides of a load 101, such as an audio output transducer like a loudspeaker. The amplifier stage 202 includes drivers 103p and 103n, which are operable to generate corresponding drive signals Vp and Vn at the respective output nodes 104p and 104n. Drivers 103p and 103n may each include a Class D amplifier or driver.

[0063] According to one embodiment, the amplifier circuit 200 also includes a controller 201 for controlling the operating mode of circuitry such as amplifier stage 202. The controller 201 is operable to selectively control circuitry 200 in a first mode, which may be referred to as BTL (Bridged Load) mode. In the first mode, both drivers 103p and 103n are operable to generate corresponding drive signals based on the input signal Sin. Therefore, in the first or BTL operating mode, the voltages Vp and Vn at the two output nodes 104p and 104n can vary with the input signal Sin. The voltages Vp and Vn can vary opposite to each other relative to the midpoint voltage, but, as will be described below, can vary asymmetrically or unequally.

[0064] The controller 201 is also operable to selectively control the circuit in a second mode, which may be referred to as SE (single-ended) mode. In the second mode, the drive signal based on the input signal Sin is generated only at one of the output nodes, and the other output node remains substantially constant, generally at a voltage corresponding to the static level of the drive signal, such as the midpoint voltage Vmid.

[0065] exist Figure 2 In the example, driver 103n can be deactivated or disabled in the second (SE) operating mode, and the voltage at output node 104n is maintained at the midpoint voltage Vmid, for example, by the start-up voltage regulator 203, which will be discussed in more detail below. In this mode, the voltage Vp at output node 104p can therefore vary with the input signal Vin, but the voltage Vn at output node 104n can remain substantially constant.

[0066] Controller 201 may generate one or more control signals Scn for controlling whether driver 103n is enabled and whether voltage regulator 202 is active. When active in BTL mode, the one or more control signals Scn may also control one or more parameters of the negative signal path of amplifier stage 102, particularly the gain applied to the negative signal path. Controller may also generate at least one control signal Scp to control one or more parameters of the positive signal path, particularly the gain applied to the positive signal path. In some embodiments, controller 201 may also control at least the bias level applied to driver 103p.

[0067] The controller 201 is configured to selectively control the operating mode, i.e., BTL or SE mode, based on an indication of the amplitude of the output signal Vout. If the indication of the amplitude of the output signal Vout indicates that the voltage offset required to generate the output signal Vout can be generated using only the driver 103p, the controller 201 can be configured to operate in SE mode.

[0068] For example, consider that each of drivers 103p and 103n is operable to generate a drive signal Vp or Vn within an output range of 0V to +1.0V. It should be understood, of course, that this output range is chosen merely as an illustrative example. In BTL operating mode, the output signal Vout can vary between +1.0V (where Vp = +1.0V, Vn = 0V) and -1.0V (Vp = 0V, Vn = +1.0V). The static signal level Vout = 0V corresponds in this example to Vp = Vn = Vmid = 0.5V.

[0069] In SE mode, the voltage Vn will remain at Vmid = 0.5V. In this mode, the output signal Vout can vary between +0.5V (Vp = +1.0V) and -0.5V (Vp = 0V).

[0070] Therefore, if the output signal amplitude indicator suggests, in this example, that the output signal amplitude will be below 0.5V, the controller can be configured to control the circuit in SE operating mode, where the voltage Vn at output node 104n is kept substantially constant, for example, by regulator 203. This allows driver 103n to be disabled or paused.

[0071] However, if the output signal amplitude indicator indicates that the output signal amplitude is higher than or can be higher than 0.5V, the circuit can operate in BTL operation mode and the driver 103n can be enabled, so that the voltage Vn at the output node 104n also varies with the input signal Sin to provide the required output signal Vout.

[0072] In some examples, the indication of the output signal amplitude may be an indication of the total gain (e.g., the system or user-controlled volume setting VOL) ​​applied between the input signal Sin and the output signal Sout by the amplifier circuitry.

[0073] The volume setting defines the maximum voltage offset, or maximum amplitude, of the output signal Vout from a full-scale input signal. For example, considering that amplifier circuit 200 has a controllable volume range of 0 to 1, this controllable volume defines the ratio between the input signal (normalized within the available input signal range) and the output signal (normalized within the available output signal range). If the volume setting is set to 1, a full-scale input signal can produce a full-scale output signal, which requires BTL operation. However, at volume settings below 0.5, even a full-scale input signal may utilize less than half of the available output range. This volume setting can therefore be used to control the operating mode, and as... Figure 2 As shown, the controller can receive a volume signal VOL indicating the volume setting. Note that in this case, for a full-scale input signal, the volume setting is effectively used as an indication of the output signal amplitude.

[0074] However, in some examples, the amplitude indication of the output signal can be an indication of the amplitude of the input signal. In some examples, the controller can determine this amplitude indication from the input signal. The output signal Vout is generated based on the input signal Sin, and therefore the level of the input signal, along with the total gain of the amplifier circuitry, defines the level of the output signal.

[0075] The controller 201 can therefore be configured to receive a version of the input signal Sin and to determine the amplitude or envelope value of the input signal.

[0076] Figure 3 An example of an amplifier circuit 300 according to one embodiment is shown, illustrating a version of the input signal Sin received by a controller 201. In this example, the controller 201 includes an envelope detector 301 that generates an indication of the envelope, or amplitude, of the input signal Sin.

[0077] In some examples, envelope detector 301 may include a peak detector that determines the absolute value of a peak as the input signal varies over defined time frames. The indication of the absolute peak value can be used directly as an indication of the signal amplitude or envelope; however, in some implementations, envelope detector 301 may include an envelope tracker configured to track the envelope or amplitude value of the input signal. The envelope tracker may have a fast start-up time constant to respond quickly to any increase in signal amplitude, but may have a slow decay time constant to avoid rapid changes in the envelope level.

[0078] It should be understood that envelope trackers and the like are used in other applications to determine the amplitude of an input signal, such as for controlling the supply voltage in a Class G amplifier, or for gain control for dynamic range extension of ADCs and DACs. Any of the signal monitoring techniques or devices used in such other applications may be used in embodiments of this disclosure to monitor the input signal and its amplitude.

[0079] An indication of the amplitude of the input signal Sin can be supplied to the processor 302 of the controller 201, which is configured to determine the operating mode of the amplifier circuit based on the amplitude level. For example, if the amplitude of the input signal is below a threshold, meaning the output signal is within the output range of the driver 103p, the processor 302 can operate the circuit in SE mode, where the driver 103n is disabled and the regulator 203 is activated to maintain the voltage Vn at the output node at the midpoint. However, if the amplitude of the input signal increases above this threshold, the processor 302 can operate the circuit in BTL mode and activate the driver 103n and deactivate the voltage regulator 203.

[0080] In some implementations, if any variable gain, such as a user- or system-controlled volume VOL, is applied downstream of the location where the input signal Sin is monitored, the processor 302 may take this gain or volume into account when determining the operating mode.

[0081] To allow controller 201 time to determine the amplitude level of the input signal and the desired operating mode, and sufficient time to activate driver 103n when switching from SE operating mode to BTL operating mode, or to activate regulator 203 when switching from BTL mode to SE mode, controller 201 can be implemented as part of a look-ahead arrangement. Controller 201 can therefore be configured to monitor the input signal Sin preceding some element in a downstream signal path with signal path propagation delay or lag, such that controller 201 has time to react to changes in signal amplitude before any changes have propagated to drivers 103p and 103n. Figure 3 The amplifier stage 202 is shown to include at least one DAC (digital-to-analog converter), and... Figure 3 In the example, corresponding DACs 303p and 303n exist in each of the positive and negative signal paths of amplifier stage 202 to provide corresponding analog input signals to drivers 103p and 103n. Some processing delays or latency will exist associated with DACs 303p and 303n, such as due to interpolation, sampling rate conversion, etc. By monitoring the input signals preceding DACs 303p and 303n, controller 201 can utilize some inherent delays in the main signal path to provide at least a portion of look-ahead, and allow controller 201 to monitor the input signal Sin in the digital domain. However, the DAC is only one example of an element with signal path propagation delay, and additional and / or alternative delay elements may exist in the signal path, including at least one dedicated delay element 304, which exists only to provide a suitable propagation delay.

[0082] To change the operating mode, controller 201 can enable or disable driver 103n, while also disabling or starting regulator 203. For Class D amplifiers, the driver can be disabled by stopping the switching of the Class D amplifier's output stage. In some examples, when driver 103n is disabled, individual sections of the Class D amplifier can be de-energized, although some sections of the Class D amplifier can remain energized to allow the amplifier to be enabled more quickly when needed.

[0083] Furthermore, controller 201 can control the switching gain of the positive and / or negative signal paths of amplifier stage 202. Advantageously, the controller can be operable such that, when operating in BTL mode, different gains can be applied to the positive and negative signal paths of the amplifier stage according to the indication of the output signal amplitude. In other words, when operating in BTL mode, the magnitudes of the positive and negative drive signals can differ from each other according to the indication of the signal amplitude. This differs from conventional BTL operation, in which the positive and negative drive signals are equal and opposite to each other. Changing the gain applied to the positive and negative signal paths of amplifier stage 202, and thus changing the relative magnitudes of voltages Vp and Vn, and thus their relative contribution to the output signal Vout, can be advantageous in transitions between operating modes.

[0084] Consider amplifier circuit 300 operating in BTL mode with an input signal Sin having a specific signal level, such as S1. In BTL mode, the voltage Vp depends on the input signal Sin, therefore the drive voltage Vp equals Gp*S1, where Gp is ​​the gain of the positive signal path. Similarly, in BTL mode, the voltage Vn depends on the input signal Sin, therefore the drive voltage Vn equals -Gn*S1, where Gn is the gain of the negative signal path. The output signal Vout equals Vp - Vn = (Gp + Gn)*S1.

[0085] Conventionally, in BTL operation, the positive drive voltage and the negative drive voltage are equal and opposite, i.e., Vp = Vn, and therefore the positive signal path and the negative signal path have the same gain, i.e., Gp = Gn.

[0086] However, in SE mode, the voltage Vn at output node 104n remains constant at Vmid. Therefore, the gain Gn of the negative path is effectively zero. In this mode, driver 103p must generate a drive signal Vp to provide all the required voltage offset for the output signal Vout, instead of just half the voltage offset in regular BTL operation. If the controller were to switch between SE operation mode (where drive signal Vp provides all the required voltage offset) and regular BTL mode (where drive signals Vp and Vn are equal and opposite), this would require a step change in gain in both the positive and negative signal paths upon mode change, which could lead to undesirable artifacts, etc.

[0087] In embodiments of this disclosure, controller 201 can control amplifier stage 202 in BTL mode such that, for at least some indications of the output signal amplitude, the contributions from the positive and negative signal paths to the output signal are unequal. Specifically, controller 201 can operate in BTL mode to reduce the relative contribution of the voltage Vn at output node 104n (i.e., a voltage that would remain constant in SE mode) to the output signal for lower output signal amplitudes. Essentially, as the indication of the output signal amplitude decreases, the relative contribution from voltage Vn to the output signal can decrease compared to voltage Vp. This means that as the indication of the output signal amplitude decreases, the voltage offset of Vn around Vmid will decrease (potentially increasing the voltage offset of Vp to maintain the desired output signal Vout). If the indication of the output amplitude then decreases to a level where the amplifier circuit can operate in SE mode, the contribution of voltage Vn to the output signal Vout will therefore be small and most of the output signal will be attributed to Vp.

[0088] Therefore, the amplifier circuit can operate in SE mode for a first range of output signal amplitude and in BTL mode for a second and higher range of signal amplitude. Controller 201 can control the contributions from the positive and negative signal paths such that when the indication of the output signal amplitude approaches the bottom of the second range, the contribution from one of the signal paths approaches zero. This facilitates the transition between modes.

[0089] Therefore, controller 201 can be configured such that, when operating in BTL mode, the control circuitry causes the ratio of the magnitude of the negative drive signal to the magnitude of the positive drive signal to vary with the indication of the output signal amplitude. That is, the ratio |Vn-Vmid| / |Vp-Vmid| varies with the indication of the signal amplitude.

[0090] Figure 4 An example illustrating how to control the contributions from the positive and negative signal paths, for example, based on volume settings, to achieve the desired overall effective gain. Figure 4 The top diagram shows how to control the gains Gp and Gn of the positive and negative signal paths based on the volume setting, and the bottom diagram shows the effective gain of the amplifier circuit. Figure 4 The normalized values ​​are shown, with gains Gp and Gn normalized in the range of 0 to 1, where gain 1 corresponds to the full-scale input signal that results in a full-scale drive signal from the associated driver 103p or 103n. The effective gain of the amplifier circuit is equal to Gp + Gn, and is therefore shown in the range of 0 to 2. The amplitude indication is also normalized in the range of 0 to 1, where 1 corresponds to the maximum value.

[0091] If the volume is set to its maximum value of 1, a full-scale input signal may result in a full-scale output signal. Therefore, in this case, both gains Gp and Gn are at their maximum values. In this operating state, the circuit operates in normal BTL mode, and the voltage changes of Vp and Vn from the midpoint voltage will be opposite and equal, i.e., the ratio |Vn-Vmid| / |Vp-Vmid| will equal 1.

[0092] However, if the volume setting is reduced, the gain Gn decreases while keeping the gain Gp at its maximum value as much as possible. Therefore, as the volume setting decreases, the gain Gn decreases accordingly within the range of 1 to 0.5. The contribution of the voltage Vn to the output signal Vout also decreases. Consequently, the ratio of |Vn-Vmid| / |Vp-Vmid| drops below 1.

[0093] When the volume is set to 0.5, the gain Gn decreases to zero. At this point, the output change caused by the full-scale input signal can be provided solely by driver 103p. The circuit can therefore switch to SE operation mode, disabling driver 103n. It should be noted that driver 103p now provides the entire voltage change for the output signal Vout, and therefore there is no need to change the gain of the positive signal path.

[0094] To further reduce the volume setting, you can decrease the gain Gp to provide the desired volume control.

[0095] Figure 5 Alternatively, the gain of the positive and negative signal paths is shown to vary based on an indication of the desired output signal amplitude, and how it varies with the desired signal amplitude to maintain a constant effective gain over the range of signal amplitude. In this case, the amplitude can be considered as the input signal amplitude (assuming any volume control gain has been applied).

[0096] If the input signal amplitude is less than 0.5, the desired output signal can be generated solely by the positive driver 103p, and the circuit can operate in SE mode. Therefore, the gain Gn of the negative signal path is 0. For a normalized range of input signal amplitude from 0 to 0.5, the gain of the positive signal path can be fixed at a level that means an input signal amplitude of 0.5 corresponds to the level of the full-scale output from driver 103p. For illustrative purposes, Figure 5 The gain Gp in this case is therefore expressed as 2.0 within this range.

[0097] If the input signal amplitude is greater than 0.5, the driver 103p cannot generate the corresponding output signal on its own, and therefore the amplifier circuit switches to BTL mode. The gain Gp of the positive signal path decreases to avoid clipping, but it is not simply set to be equal; the gain Gp is ​​only reduced to the extent necessary to avoid clipping, and the gain Gn increases by a corresponding amount to keep the total gain constant. If the signal amplitude increases further, the gain Gp decreases further, followed by an increase in the gain Gn, until the signal amplitude is 1.0, at which point the gains Gp and Gn are equal and the circuit operates in normal BTL mode.

[0098] This means that in BTL mode, as the signal amplitude decreases, the relative contribution of voltage Vn to the output signal becomes smaller and smaller compared to Vp, until it reaches the point where the negative signal path makes no contribution, and the circuit can enter SE mode.

[0099] Therefore, for example, consider the example above, where the output range of each driver 103p and 103n is from 0V to 1V. If an output signal with an amplitude of 0.6V is required, for example, varying between +0.6V and -0.6V, then conventionally in BTL operation, drivers 103p and 103n would generate inverse drive signals, each with an amplitude of 0.3V. However, in the embodiments of this disclosure, in order to generate an output signal value of 0.6V, driver 103p can be driven to provide an output signal with a value of 0.5V, i.e., full-scale output, while driver 103n generates a drive signal that varies in the opposite direction to the value of 0.1V.

[0100] Therefore, operating in this way allows for relatively easy switching between modes, as if the signal amplitude were to change only relatively gradually, and the required gain change when switching between BTL and SE operating modes may be relatively low.

[0101] There are multiple ways in which the controller 201 can control the gain of the positive and negative signal paths. In some examples, the controller can control the dialogue gain of drivers 103p and 103n. Alternatively, at least some gain control can be applied by one or more gain elements 305p and 305n in the respective signal paths. The gain elements can be conveniently located in the digital portion of the relevant signal path.

[0102] In SE mode, driver 103n can be disabled and the overall change in the output signal Vout is driven by driver 103p. This improves the efficiency of the amplifier circuit and avoids any power consumption associated with driver 103n, such as the switching losses associated with a Class D amplifier.

[0103] Furthermore, in SE mode, as the overall output signal Vout changes, it is driven by driver 103p, and the overall load resistance RL is seen by driver 103p. This contrasts with BTL mode, where both drivers 103p and 103n provide drive signals that vary with the input signal, and each driver only sees a portion of the load resistance.

[0104] A higher effective load resistance for the 103pF driver may be beneficial, as various performance requirements can be relaxed for higher load impedance.

[0105] Therefore, for lower output signal amplitudes, operation in SE mode may be advantageous, as this alleviates some design considerations of the driver 103p. Alternatively, the operating parameters of the driver 103p may be varied during use.

[0106] Specifically, in some implementations, the bias supplied to driver 103p can vary during use, for example, the amount of bias current. When operating in SE mode with driver 103p subjected to full load resistance, a lower bias current can be supplied than when operating in BTL mode to achieve the desired performance.

[0107] Re-reference Figure 3 The controller 201 can therefore also be configured to control the bias source 306 to control the bias applied to at least the driver 103p. Specifically, a lower bias current can be used in SE mode, which provides additional power savings.

[0108] When operating in BTL mode, it may be necessary to increase the bias to achieve the desired performance. However, as discussed above, the relative contributions from the positive and negative signal paths to the output signal Vout may not be equal, unless operating at the highest output amplitude.

[0109] In at least some applications, it is desirable that a relatively high amplitude output signal is required only relatively infrequently, and therefore it is desirable that for most of the time during normal use, the required output signal can have a relatively low amplitude. Therefore, embodiments of this disclosure effectively optimize the amplifier circuitry for generating such low amplitude output signals, while still allowing operation to provide a relatively high amplitude output signal when needed.

[0110] As discussed above, in SE mode, the voltage at the output node or terminal 104p is maintained by regulator 203 at a defined midpoint voltage Vmid.

[0111] In some implementations, the midpoint voltage can be ground. For example, if the supply voltages VH and VL are positive and negative voltages of the same magnitude, the midpoint voltage will be grounded. In this case, the voltage regulator 203 can simply be a switch for selectively coupling the output node 104n to ground, or some other type of ground clamping circuit that can be started and stopped as needed.

[0112] However, in some cases, the midpoint voltage Vmid can be a voltage level other than ground. For example, the supply voltages VH and VL could be the voltage Vdd and the ground voltage, respectively. In this case, the midpoint voltage might be Vdd / 2, and the voltage regulator must maintain the defined voltage. The voltage regulator should advantageously be relatively efficient.

[0113] In some examples, voltage regulator 203 may include a DC-DC converter such as a charge pump. Figure 6 An example is shown with a supply voltage of Vdd and ground. In this example, the voltage regulator includes a charge pump that receives the supply voltage Vdd and is operable to generate an output voltage of Vdd / 2. As those skilled in the art will understand, various types of such buck charge pumps exist that can effectively generate a midpoint voltage when needed. The charge pump can be started and stopped by a control signal Scn from controller 201. In some embodiments, the switching frequency of the charge pump can also be variable in use and can be reduced when the indication of the output signal amplitude decreases in order to save power.

[0114] Therefore, embodiments of this disclosure relate to amplifier circuits that can selectively operate in BTL mode to drive both ends of a load with a voltage varying according to the input signal, or in SE operating mode, in which only one side of the load is driven with a varying drive voltage, while the other side of the load remains at a substantially constant voltage. The amplifier circuit can operate in SE mode when possible and can switch to BTL mode when a higher amplitude output signal is required. When operating in BTL mode, the drive voltages on either side of the load may be asymmetrical or unequal with respect to at least some amplitudes of the output signal. Specifically, the circuit can be operable such that when operating in BTL mode, the relative contribution of the drive voltage from one side of the load to the output signal is reduced at lower signal amplitudes, which may be advantageous for switching between modes.

[0115] The discussion above has described how the voltage at the negative output node 104n remains constant in SE mode and the contribution at the positive output node 104p is maximized in BTL mode. It should be understood, of course, that the reverse can be achieved. It should also be understood that the terms positive and negative are used only as labels to distinguish differential signal components and should not be construed as implying anything about the level or polarity of any voltage produced.

[0116] The description also focuses on driving audio output transducers. This may include transducers such as loudspeakers for generating audible sound, but may also include ultrasonic or other similar transducers and / or tactile transducers. Embodiments also relate to amplifier circuitry for driving other types of transducers.

[0117] The implementation scheme can be advantageously implemented as part of an audio processing circuit, such as an audio amplifier for providing audio drive signals to audio output transducers such as loudspeakers, which may be transducers of a host device and / or transducers of accessory devices that can be removably connected to the host device during use.

[0118] The implementation scheme can be arranged as part of audio processing circuitry and / or signal processing circuitry, such as audio circuitry like a codec that may be provided in a host device. The circuitry according to the embodiments of the invention can be implemented as an integrated circuit.

[0119] The implementation scheme can be incorporated into a host electronic device, which may be, for example, a portable device and / or a device that can be operated by battery power. The host device may be a device having one or more speakers provided as part of the host device and / or a connector for wired connection to a removable accessory device, which is removably connected to the host device during use. The host device may include a wireless communication module for receiving input data. The host device may be a communication device such as a mobile phone or smartphone, a computing device such as a laptop, notebook computer, or tablet computing device, or a wearable device such as a smartwatch. Alternatively, the host device may be an accessory device for use with any such communication, computing, or wearable device. For example, the host device may be headphones or earbuds.

[0120] Those skilled in the art will recognize that some aspects of the aforementioned apparatus and methods can be embodied as processor control code on, for example, non-volatile media (such as disks, CD-ROMs, or DVD-ROMs), programmable memory (such as read-only memory (firmware)), or data carriers (such as optical or electrical signal carriers). For many applications, implementations will be carried out on DSPs (Digital Signal Processors), ASICs (Application-Specific Integrated Circuits), or FPGAs (Field-Programmable Gate Arrays). Therefore, the code can include conventional program code or microcode, or, for example, code for setting up or controlling an ASIC or FPGA. The code can also include code for dynamically configuring reconfigurable devices such as reprogrammable logic gate arrays. Similarly, the code can include code for use with hardware description languages ​​(such as Verilog). TM Or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language) code. As those skilled in the art should understand, the code can be distributed among multiple coupled components that communicate with each other. Where appropriate, implementations can also be implemented using code that runs on a field-programmable analog array or similar device to configure the analog hardware.

[0121] It should be noted that the above embodiments are illustrative and not limiting of the invention, and those skilled in the art will be able to devise many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in the claims, "an" or "a" does not exclude a plurality, and a single feature or other unit may perform the function of several units recited in the claims. Any reference numerals in the claims should not be construed as limiting the scope of the claims.

Claims

1. An amplifier circuit for generating an output signal between a first output node and a second output node based on a received input signal, the amplifier circuit comprising: a first output driver and a second output driver; and a controller to selectively control the amplifier circuit in a first mode or a second mode based on an indication of output signal amplitude; wherein: in the first mode, both the first output driver and the second output driver are active to generate respective first and second drive signals that each vary with an input signal at the first and second output nodes; and in the second mode, the first output driver is active to generate a first drive signal at the first output node that varies with the input signal, and the second output node is held at a constant voltage; and wherein in the first mode, a ratio of a magnitude of the second drive signal to a magnitude of the first drive signal varies with the indication of output signal amplitude.

2. The amplifier circuit of claim 1, wherein the controller is configured so that when operating in the first mode, the ratio of a magnitude of the second drive signal to a magnitude of the first drive signal varies in a range from zero to one and increases with an increase in an indication of output signal amplitude.

3. The amplifier circuit of claim 2, wherein the controller is configured to minimize the ratio of the magnitude of the second drive signal to the magnitude of the first drive signal in the first mode.

4. The amplifier circuit of any of claims 1-3, wherein the first output driver is in a first signal path and the second output driver is in a second signal path, and wherein the controller is configured to control the ratio of a magnitude of the second drive signal to a magnitude of the first drive signal by controlling gains applied in the first and second signal paths.

5. The amplifier circuit of any of claims 1-3, wherein the indication of output signal amplitude comprises a gain setting that indicates a gain to be applied by the amplifier circuit.

6. The amplifier circuit of any of claims 1-3, wherein the indication of output signal amplitude comprises an indication of an amplitude of the input signal.

7. The amplifier circuit of claim 6, wherein the controller comprises an envelope detector configured to receive a version of the input signal and determine the amplitude of the input signal.

8. The amplifier circuit of claim 7, wherein the amplifier circuit comprises at least one element having a propagation delay upstream of a signal path of at least one of the first and second output drivers, and wherein the envelope detector receives the version of the input signal upstream of the at least one element having a propagation delay.

9. The amplifier circuit of any of claims 1-3, wherein the controller is further configured to selectively control bias applied to at least the first output driver based on the indication of output signal amplitude.

10. The amplifier circuit of claim 9, wherein the controller is configured such that a lower bias current is applied to the first output driver in the second mode as compared to the first mode.

11. The amplifier circuit of claim 9, wherein the controller is configured such that the bias current applied to the first output driver increases with increasing output signal amplitude in the first mode.

12. The amplifier circuit of any one of claims 1 to 3, comprising: a voltage regulator enabled to regulate voltage at the second output node in the second mode.

13. The amplifier circuit of claim 12, wherein the voltage regulator comprises at least one of: a DC-DC converter and a charge pump.

14. The amplifier circuit of any of claims 1-3, wherein the controller is configured to disable the second output driver when operating in the second mode.

15. The amplifier circuit of any of claims 1-3, wherein the first output driver and the second output driver each comprise a respective class-D amplifier.

16. The amplifier circuit of any one of claims 1 to 3, further comprising: a load transducer coupled between the first output node and the second output node.

17. The amplifier circuit of claim 16, wherein the load transducer comprises a loudspeaker.

18. An electronic device comprising: the amplifier circuit of any of claims 1-16.

19. An amplifier circuit for generating an output signal between a first output node and a second output node based on a received input signal, the amplifier circuit comprising: a first output driver and a second output driver; the amplifier circuit is operable in a first mode in which both the first output driver and the second output driver are active to generate respective first and second drive signals that each varies with the input signal at the first and second output nodes; and wherein in the first mode, a ratio of a magnitude of the second drive signal to a magnitude of the first drive signal varies with an indication of output signal amplitude.

20. An amplifier circuit comprising: a first signal path comprising a first amplifier; a second signal path comprising a second amplifier; and a controller to selectively operate the circuit: in a first mode in which both the first amplifier and the second amplifier are active to drive first and second output nodes with respective first and second drive signals that each varies with an input signal; and in a second mode in which the first amplifier is active to drive the first output node with the first drive signal that varies with the input signal and the second output node is held at a constant voltage. ​ wherein the controller operates in the first mode when an indication of the output signal amplitude is in a first range, and wherein the controller controls a gain of the second signal path to decrease as the indication of the output signal amplitude decreases in the first range, while maintaining or increasing a gain of the first signal path.

21. An amplifier circuit comprising: a first signal path comprising a first amplifier; a second signal path comprising a second amplifier; and a controller for selectively operating the circuit: in a first mode in which both the first amplifier and the second amplifier are active to drive first and second output nodes with respective first and second drive signals that each vary with an input signal; and in a second mode in which the first amplifier is active to drive the first output node with the first drive signal that varies with the input signal, and the second output node is held at a constant voltage; and wherein in the first mode, a gain of the first signal path is controlled to be constant at a first value, and a gain of the second signal path is selectively variable within a range of gain values up to the first value based on a gain control signal; and in the second mode, the gain of the first signal path is selectively variable within the range of gain values up to the first value based on a gain control signal. ​

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