Transparent packet splitting and reassembly

Abstract

A transmitting device generates multiple small packets for a large packet and transmits them to a receiving device. A routing device forwards the multiple small packets to the receiving device. Each of the smaller packets, except the last packet, is provided with a sequence indicator. Thus, the receiving device is able to determine that each of the smaller packets is part of a larger packet and buffer the smaller packets or their payloads. When the last packet is received, the larger packet is complete and can be processed by the receiving device. The routing device delays requests from other transmitting devices to transmit data to the receiving device until the last packet is sent to the receiving device. The routing device can continue to route traffic to the receiving device on all virtual channels except the virtual channel being used for the large packet.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Application No. 17 / 007,492, filed August 31, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure generally relate to network protocols, and more specifically, to networking using methods for transparently transmitting large packets over a network using smaller packets. Background Technology

[0004] Packets are sent over the network and individually routed to their destinations. If multiple packets are related, the receiving device processes them as needed. The network does not process data structures larger than a single packet.

[0005] Chiplets are an emerging technology for integrating various processing functionalities. Typically, a chiplet system consists of discrete chips (e.g., integrated circuits (ICs) on different substrates or dies) integrated and packaged together on an interposer. This arrangement differs from a single chip (e.g., an IC) containing different device blocks (e.g., intellectual property blocks) on a single substrate (e.g., a single die), such as a system-on-a-chip (SoC) or a discrete packaged device integrated on a board. Generally, chiplets offer better performance (e.g., lower power consumption, reduced latency, etc.) than discrete packaged devices, and offer greater manufacturing benefits than single-die chips. These manufacturing benefits can include higher yields or reduced development costs and time.

[0006] Chiplet systems generally consist of one or more application chiplets and support chiplets. Here, the distinction between application and support chiplets is merely a reference to possible design scenarios for chiplet systems. Thus, for example, a synthetic vision chiplet system might include an application chiplet for generating synthetic vision output, as well as support chiplets such as memory controller chiplets, sensor interface chiplets, or communication chiplets. In typical use cases, synthetic vision designers may design the application chiplet and obtain the support chiplet from other sources. Therefore, design expenditures (e.g., in terms of time or complexity) are reduced by avoiding the design and manufacturing of the functionality contained in the support chiplet. Chiplets also support tight integration of intellectual property blocks that might otherwise be difficult to achieve, such as those using different feature sizes. Therefore, for example, devices designed during previous-generation manufacturing with larger feature sizes, or those where feature sizes are optimized for power, speed, or heat (which can occur for sensors), can be integrated with devices of different feature sizes more easily than attempting to do so on a single die. Furthermore, by reducing the overall die size, chiplet yields tend to be higher than those of more complex single-die devices. Attached Figure Description

[0007] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings, which describe various embodiments of the present disclosure. However, the drawings should not be construed as limiting the disclosure to the specific embodiments, but are for explanation and understanding only.

[0008] Figure 1A and 1B An example of a chiplet system according to an embodiment is described.

[0009] Figure 2 This describes the components of an example of a memory controller chiplet according to an embodiment.

[0010] Figure 3 This describes an example of routing between chiplets using a chiplet protocol interface (CPI) network according to an embodiment.

[0011] Figure 4 This is a block diagram of a data packet comprising multiple micro-pieces according to some embodiments of the present disclosure.

[0012] Figure 5 This is a flowchart illustrating the operation of a method performed by a circuit during transparent packet splitting according to some embodiments of the present disclosure.

[0013] Figure 6 This is a flowchart illustrating the operation of a method performed by a circuit when transparently routing via packet splitting, according to some embodiments of the present disclosure.

[0014] Figure 7This is a flowchart illustrating the operation of a method performed by circuitry during the transparent reassembly of split packets according to some embodiments of the present disclosure.

[0015] Figure 8 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0016] Embodiments of this disclosure relate to systems and methods for transparently splitting large packets into multiple smaller packets for transmission over a network. A transmitting device determines that a large packet intended for a receiving device will be split into multiple smaller packets. For example, the large packet may exceed the maximum size of a network protocol. The transmitting device generates multiple smaller packets for the large packet and transmits them to the receiving device. Zero or more routing devices forward the multiple smaller packets along a path from the transmitting device to the receiving device, whereby the receiving device reassembles the smaller packets.

[0017] Each of the smaller packets, except the last one, has a sequence indicator set. The sequence indicator is cleared in the last packet. Therefore, the routing and receiving devices can determine that each of the smaller packets is part of the larger packet and buffer the smaller packets or their payloads. When the last packet is received, the larger packet is complete and ready for processing by the receiving device.

[0018] Routing devices along the path from the transmitting device to the destination device recognize that a large packet transmission is in progress. Therefore, requests from other transmitting devices to transmit data to the receiving device are delayed until the last packet with a cleared sequence indicator is sent to the receiving device. In this way, the receiving device will not receive irrelevant packets while buffering the large packet. In some example embodiments, sequence indicator processing is based on each virtual channel of each receiving device, rather than solely on each receiving device. In these embodiments, the routing device continues to route traffic to the receiving device on all virtual channels except the one currently being used for the large packet.

[0019] One benefit of the embodiments of this disclosure is that large packets of the first network protocol can be transparently transmitted over a network using a second network protocol with smaller packets without increasing the buffer memory of the receiving device. Compared to solutions that allow data transmission to the receiving device while it is buffering large packets (or solutions that allow data transmission using the receiving device's virtual channel while it is buffering large packets received using the virtual channel), this reduces buffer memory, manufacturing costs, increases manufacturing yield, reduces the physical size of the receiving component, or any suitable combination thereof. The processing cycles consumed in transmitting, receiving, and processing data packets are reduced. Additionally, the power consumed in performing processing is reduced. The performance of the system, including the communication device, is also improved due to reduced networking overhead. Other benefits will be apparent to those skilled in the art who will receive the benefits of this disclosure.

[0020] Such efficiency in reducing these processing loops can have specific benefits in chiplet systems that include memory controllers, thus providing the system with the modularity to be configured in some embodiments for implementing relatively high-performance memory operations, as may be required, for example, for systems performing large and / or relatively high-complexity computations. Allowing the memory controller to receive large packets over a network using protocols with smaller maximum packet sizes enables other devices already configured to use large packets to benefit from using the memory controller without reconfiguration.

[0021] For example, various forms of navigation and guidance systems may require coordinating data from multiple sensors substantially simultaneously to perform navigation functions. An example application of such chiplet systems for implementing memory systems comprising memory controllers with one or more forms of memory would be autonomous vehicles, where data from various ranging sensors (e.g., radar, LiDAR, and / or ultrasonic sensors) can be correlated with data from multiple optical sensors (potentially requiring image processing and pattern recognition), gyroscopes, slip sensors, and so on.

[0022] Figure 1A and 1B An example of a chiplet system 110 according to an embodiment is described. Figure 1A This illustration illustrates a chiplet system 110 mounted on a peripheral board 105, which can be connected to a wider range of computer systems, for example, via peripheral component interconnect (PCIe). The chiplet system 110 includes a package substrate 115, an interposer 120, and four chips: an application chiplet 125, a host interface chiplet 135, a memory controller chiplet 140, and a memory device chiplet 150. Other systems may include numerous additional chipsets to provide additional functionality, as will be apparent from the following discussion. The package of the chiplet system 110 is illustrated as having a cover or shield 165, but other packaging techniques and structures for the chiplet system 110 may be used. Figure 1B This is a block diagram of the components in the chiplet system 110 for clarity.

[0023] Application chip 125 is described as including a network on chip (NOC) 130 to support a chip network 155 for inter-chip communication. In an example embodiment, NOC 130 may be included on application chip 125. In an example, NOC 130 may be defined in response to the selected supporting chips (e.g., chips 135, 140, and 150), allowing the designer to select an appropriate number of chip network connections or switches for NOC 130. In an example, NOC 130 may reside on a single chip or even within interposer 120. In the example discussed herein, NOC 130 implements a CPI network.

[0024] CPI is a packet-based network that supports virtual channels to enable flexible and high-speed interaction between chiplets. CPI bridges the chiplet-internal network to chiplet network 155. For example, the Advanced Extensible Interface (AXI) is a widely used specification for designing intra-chip communication. However, the AXI specification covers a large number of physical design options, such as the number of physical channels, signal timing, and power. Within a single chip, these options are generally selected to meet design goals, such as power consumption and speed. However, to achieve the flexibility of the chiplet system 110, adapters such as CPI are used to intersect between various AXI design options that can be implemented in various chiplets. By implementing a mapping from physical channels to virtual channels and encapsulating time-based signaling using packetization protocols, CPI bridges the intra-chiplet network 155.

[0025] CPI can use a variety of different physical layers to transmit packets. A physical layer may contain simple conductive connections or drivers to increase voltage, or otherwise facilitate signal transmission over longer distances. An example of such a physical layer may contain an Advanced Interface Bus (AIB), which in various instances may be implemented in intermediate layer 120. The AIB uses source-synchronous data transfer with a forwarding clock to transmit and receive data. Packets are transmitted across the AIB at Single Data Rate (SDR) or Double Data Rate (DDR) relative to the transmitted clock. The AIB supports various channel widths. When operating in SDR mode, the AIB channel width is a multiple of 20 bits (20, 40, 60, ...), and for DDR mode, the AIB channel width is a multiple of 40 bits (40, 80, 120, ...). The AIB channel width includes both transmit (TX) and receive (RX) signals. Channels can be configured to have a symmetrical number of TX and RX inputs / outputs (I / O), or an asymmetrical number of transmitters and receivers (e.g., all transmitters or all receivers). The chiplet providing the master clock is the master chiplet; the other chipslets are secondary chipslets. In this scenario, the master chiplet can be independent of the other chipslets and can have management authority over more than one or more secondary chipslets. This relationship is analogous to the relationship between devices described using the sometimes derogatory and outdated terminology of master and slave. The AIB I / O unit supports three clock modes: asynchronous (i.e., non-timed), SDR, and DDR. Other physical layers can support any or all of these clock modes, or additional clock modes. In various instances, the non-timed mode is used for the clock and some control signals. SDR mode can use dedicated SDR-only I / O units or dual-purpose SDR / DDR I / O units.

[0026] In this example, the CPI packet protocol (e.g., point-to-point or routable) can use symmetrical receive and transmit I / O units within an AIB channel. The CPI streaming protocol allows for more flexible use of AIB I / O units. In this example, the streaming mode AIB channel can be configured with I / O units as all TX, all RX, or half TX and half RX. The CPI packet protocol can use AIB channels in SDR or DDR operating modes. In this example, the AIB channel is configured in increments of 80 I / O units (i.e., 40 TX and 40 RX) for SDR mode and in increments of 40 I / O units for DDR mode. The CPI streaming protocol can use AIB channels in either SDR or DDR operating modes. Here, in this example, the AIB channel is configured in increments of 40 I / O units for both SDR and DDR modes. In this example, a unique interface identifier is assigned to each AIB channel. This identifier is used during CPI reset and initialization to determine paired AIB channels across adjacent chiplets. In this example, the interface identifier is a 20-bit value comprising a seven-bit chiplet identifier, a seven-bit column identifier, and a six-bit link identifier. The AIB physical layer uses an AIB out-of-band shift register to transmit the interface identifier. Bits 32-51 of the shift register are used to transmit the 20-bit interface identifier in both directions across the AIB interface.

[0027] AIB defines a stacked group of AIB channels as an AIB channel column. An AIB channel column has a certain number of AIB channels, plus an auxiliary (AUX) channel. The AUX channel contains signals used for AIB initialization. All AIB channels within a column (except for the AUX channel) have the same configuration (e.g., all TX, all RX, or half TX and half RX, and the same number of data I / O signals). In this example, AIB channels are numbered in consecutive ascending order, starting with the AIB channel adjacent to the AUX channel. The AIB channel adjacent to the AUX channel is defined as AIB channel zero.

[0028] Typically, the CPI interface on an individual chiplet may include serialization-deserialization (SERDES) hardware. SERDES interconnects are well-suited for scenarios requiring high-speed signaling and low signal counts. However, SERDES can introduce additional power consumption and longer latency for multiplexing and demultiplexing, error detection or correction (e.g., using block-level cyclic redundancy check (CRC)), link-level retries, or forward error correction. However, when low latency or power consumption is a primary concern for ultra-short-distance chiplet-to-chiplet interconnects, parallel interfaces that allow data transmission with minimal latency can be utilized. CPIs contain elements designed to reduce latency and power consumption in these ultra-short-distance chiplet interconnects.

[0029] For flow control, CPI employs a credit-based technique. For example, the receiving side of application chip 125, or the sender side of memory controller chip 140, provides credits indicating available buffers. In this example, the CPI receiver contains buffers for each virtual channel for a given transmission time unit. Therefore, if the CPI receiver supports five messages and a single virtual channel in time, the receiver has five buffers arranged in five rows (e.g., one row per unit time). If four virtual channels are supported, the receiver has twenty buffers arranged in five rows. Each buffer holds the payload of one CPI packet.

[0030] When a sender transmits data to a receiver, the sender decrements its available credits based on the transmission. Once the receiver has exhausted all its credits, the sender stops sending packets to the receiver. This ensures that the receiver always has an available buffer to store transmissions.

[0031] When the receiver processes the received packet and releases the buffer, it sends the available buffer space back to the sender. The sender can then use this credit return to allow the transmission of additional information.

[0032] The paper also describes a chiplet mesh network 160 that uses direct chiplet-to-chiplet technology without requiring a NOC130. The chiplet mesh network 160 can be implemented in a CPI or another chiplet-to-chiplet protocol. The chiplet mesh network 160 typically implements a chiplet pipeline, where one chiplet acts as an interface to the pipeline, while other chipslets in the pipeline interface only interface with themselves.

[0033] Alternatively, dedicated device interfaces can be used to interconnect chiplets, such as one or more industry-standard memory interfaces 145 (e.g., synchronous memory interfaces, such as DDR5, DDR6). Connections from a chiplet system or individual chiplets to external devices (e.g., larger systems) can be made via the desired interface (e.g., a PCIe interface). In an example, such an external interface can be implemented via a host interface chiplet 135, which, in the depicted example, provides a PCIe interface external to the chiplet system 110. Such interfaces are typically used when industry practice or standards have converged on them. The illustrated example of a DDR interface for connecting a memory controller chiplet 140 to a dynamic random access memory (DRAM) memory device chiplet 150 is such an industry practice.

[0034] Among the various possible supporting chiplets, the memory controller chiplet 140 may be present in the chiplet system 110 due to the ubiquitous use of storage for computer processing and the complexity of existing technologies for memory devices. Therefore, using the memory device chiplet 150 and memory controller chiplet 140, both designed by other designers, allows chiplet system designers to obtain robust products manufactured by established companies. Typically, the memory controller chiplet 140 provides a memory device-specific interface for reading, writing, or erasing data. Typically, the memory controller chiplet 140 can provide additional features such as error detection, error correction, maintenance operations, or atomic operation execution. For some types of memory, maintenance operations are often specific to the memory device chiplet 150, such as garbage collection in NAND flash or memory-class memory and temperature regulation (e.g., cross-temperature management) in NAND flash memory. In instances, maintenance operations may involve logic-to-physical (L2P) mapping or management to provide an indirection hierarchy between the physical and logical representations of data. In other types of memory, such as DRAM, some memory operations, such as refresh, may be controlled at certain times by the host processor or memory controller, and at other times by the DRAM memory device or logic associated with one or more DRAM devices, such as an interface chip (in this example, a buffer).

[0035] Atomic operations are data manipulations that can be performed, for example, by the memory controller chiplet 140. In other chiplet systems, atomic operations can be performed by other chipsets. For example, an atomic operation can be specified as an "increment" in a command by the application chiplet 125, the command containing a memory address and possibly an increment value. Upon receiving the command, the memory controller chiplet 140 retrieves a number from the specified memory address, increments the number by the amount specified in the command, and stores the result. Upon successful completion, the memory controller chiplet 140 provides the application chiplet 125 with an indication that the command was successful. Atomic operations avoid transferring data across the chiplet mesh network 160, thereby reducing latency in executing such commands.

[0036] Atomic operations can be classified as built-in atoms or programmable (e.g., custom) atoms. Built-in atoms are a limited set of operations that are implemented immutably in the hardware. Programmable atoms are small programs that can run on programmable atomic units (PAUs) (e.g., custom atomic units (CAUs)) of the memory controller chiplet 140. Figure 1A and 1B This section describes an example of a memory controller chiplet including a PAU.

[0037] Memory device chip 150 may be or include any combination of volatile memory devices or non-volatile memory. Examples of volatile memory devices include, but are not limited to, random access memory (RAM) (e.g., DRAM), synchronous DRAM (SDRAM), graphics dual data rate type 6 SDRAM (GDDR6 SDRAM), and so on. Examples of non-volatile memory devices include, but are not limited to, NAND flash memory, memory-class memory (e.g., phase-change memory or memristor-based technology), and ferroelectric RAM (FeRAM), and so on. The illustrated examples include memory devices as memory device chip 150; however, the memory devices may reside elsewhere, such as in different packages on board 105. For many applications, multiple memory device chips may be provided. In examples, these memory device chips may each implement one or more memory technologies. In examples, the memory chip may include multiple stacked memory dies of different technologies (e.g., one or more SRAM devices stacked or otherwise communicating with one or more DRAM devices). The memory controller chiplet 140 can also be used to coordinate the operation between multiple memory chipsets in the chiplet system 110 (e.g., utilizing one or more memory chipsets in one or more tiers of cache memory and using one or more additional memory chipsets as main memory). The chiplet system 110 may also include multiple memory controller chipsets 140, which can be used to provide memory control functionality for individual processors, sensors, networks, etc. For example, chiplet architectures such as the chiplet system 110 offer the benefit of allowing adaptation to different memory storage technologies and different memory interfaces through updated chiplet configurations without requiring redesign of the rest of the system architecture.

[0038] Figure 2The components of an example of a memory controller chiplet 205 according to an embodiment are described below. The memory controller chiplet 205 includes a cache 210, a cache controller 215, an off-die memory controller 220 (e.g., for communicating with off-die memory 275), a network communication interface 225 (e.g., for interfacing with chiplet network 285 and communicating with other chiplets), and a set of atomic and merge operation units 250. This set of components may include, for example, a write merge unit 255, a memory danger clearance unit 260, a built-in atomic operation unit 265, or a PAU 270. The various components are described logically and they may not necessarily be implemented. For example, the built-in atomic operation unit 265 may include different means along the path to off-die memory 275 and / or 280. For example, the built-in atomic operation unit 265 may be in an interface means / buffer on the memory chiplet, as discussed above. In contrast, the PAU 270 may be implemented in a separate processor on the memory controller chiplet 205 (but in various instances, it may be implemented in other locations, such as on the memory chiplet).

[0039] The off-die memory controller 220 is directly coupled to off-die memory 275 (e.g., via a bus or other communication connection) to provide write and read operations to and from the one or more off-die memories, such as off-die memory 275 and off-die memory 280. In the depicted example, the off-die memory controller 220 is also coupled to the output of the atom and merge operation unit 250 and to the input of the cache controller 215 (e.g., a memory-side cache controller).

[0040] In the instance configuration, the cache controller 215 is directly coupled to the cache 210 and can be coupled to the network communication interface 225 for input (e.g., incoming read or write requests) and coupled to the off-die memory controller 220.

[0041] Network communication interface 225 includes packet decoder 230, network input queue 235, packet encoder 240, and network output queue 245 to support packet-based chiplet network 285, such as CPI. Chiplet network 285 can provide packet routing between processors, memory controllers, mixed-thread processors, configurable processing circuitry, or communication interfaces. In such packet-based communication systems, each packet typically contains destination and source addressing, as well as any data payload or instructions. In some instances, depending on the configuration, chiplet network 285 may be implemented as a collection of crossbar switches with a folded Clos configuration, or as a mesh network providing additional connectivity.

[0042] In various instances, the chiplet network 285 may be part of an asynchronous switching structure. Here, data packets can be routed along any of various paths, such that any selected data packet can arrive at the addressed destination at any time among multiple different times, depending on the routing. Furthermore, the chiplet network 285 may be implemented at least partially as a synchronous communication network, such as a synchronous mesh communication network. Both configurations of the communication network are intended for use in embodiments according to this disclosure.

[0043] The memory controller chip 205 can receive packets having, for example, a source address, a read request, and a physical address. In response, the off-die memory controller 220 or the cache controller 215 reads data from the specified physical address (which may be in off-die memory 275 or cache 210) and assembles a response packet into a source address containing the requested data. Similarly, the memory controller chip 205 can receive packets having a source address, a write request, and a physical address. In response, the memory controller chip 205 writes data to the specified physical address (which may be in cache 210 or in off-die memory 275 or 280) and assembles a response packet into a source address containing confirmation that data has been stored in memory.

[0044] Therefore, where possible, the memory controller chiplet 205 can receive read and write requests via chiplet network 285 and process the requests using cache controller 215, which interfaces with cache 210. If cache controller 215 cannot process the request, then off-die memory controller 220 processes the request by communicating with off-die memory 275 or 280, atom and merge operation unit 250, or both. As described above, one or more levels of cache can also be implemented in off-die memory 275 or 280, and in some such instances, can be directly accessed by cache controller 215. Data read by off-die memory controller 220 can be cached in cache 210 by cache controller 215 for later use.

[0045] The atomic and merge operation unit 250 is coupled to receive (as input) the output of the off-die memory controller 220 and provides the output to cache 210, network communication interface 225, or directly to chiplet network 285. The memory danger clear (reset) unit 260, write merge unit 255, and built-in (e.g., predetermined) atomic operation unit 265 can each be implemented as a state machine with other combinational logic circuitry (such as adders, shifters, comparators, AND gates, OR gates, XOR gates, or any suitable combination thereof) or other logic circuitry. These components may also include one or more registers or buffers to store operands or other data. The PAU 270 can be implemented as one or more processor cores or control circuitry, and various state machines with other combinational logic circuitry or other logic circuitry, and may also include one or more registers, buffers, or memories to store addresses, executable instructions, operands, and other data, or may be implemented as a processor.

[0046] Write merging unit 255 receives read data and request data, and merges the request data and read data to produce a single unit having the read data and a source address to be used in the response or return data packet. Write merging unit 255 provides the merged data to the write port of cache 210 (or equivalently, to cache controller 215 for writing to cache 210). Optionally, write merging unit 255 provides the merged data to network communication interface 225 to encode and prepare response or return data packets for transmission on chiplet network 285.

[0047] When requested data is used for a built-in atomic operation, the built-in atomic operation unit 265 receives the request and reads the data from the write merging unit 255 or directly from the off-chip memory controller 220. The atomic operation is performed, and using the write merging unit 255, the resulting data is written to the cache 210 or provided to the network communication interface 225 to encode and prepare response or return packets for transmission on the chiplet network 285.

[0048] Built-in atomic operation unit 265 handles predefined atomic operations, such as fetch and increment or compare and swap. In examples, these operations perform simple read-modify-write operations on a single memory location of 32 bytes or less. An atomic memory operation is initiated from a request packet transmitted via chiplet network 285. The request packet has a physical address, atomic operator type, operand size, and optionally up to 32 bytes of data. The atomic operation performs a read-modify-write operation on a cache line of cache 210, thereby filling the cache memory as needed. The atomic operator response can be a simple complete response or a response with up to 32 bytes of data. Example atomic memory operators include fetch and AND, fetch and OR, fetch and XOR, fetch and add, fetch and subtract, fetch and increment, fetch and decrement, fetch and minimum, fetch and maximum, fetch and swap, and compare and swap. In various example embodiments, 32-bit and 64-bit operations and operations on 16 or 32 bytes of data are supported. The methods disclosed in this paper are also compatible with hardware that supports larger or smaller operations and more or less data.

[0049] Built-in atomic operations may also involve requests for "standard" atomic operations on the requested data, such as relatively simple single-loop integer atoms, such as fetch and increment or compare and swap, whose throughput will be the same as regular memory read or write operations that do not involve atomic operations. For these operations, cache controller 215 can typically preserve cache lines in cache 210 by setting a danger bit (in hardware) so that the cache line cannot be read by another process during translation. Data is obtained from off-chip memory 275 or cache 210 and provided to built-in atomic operation unit 265 to perform the requested atomic operation. After the atomic operation, in addition to providing the obtained data to packet encoder 240 to encode outgoing packets for transmission on chiplet network 285, built-in atomic operation unit 265 also provides the obtained data to write merging unit 255, which writes the obtained data back to cache 210. After the obtained data is written to cache 210, memory danger clearing unit 260 clears any corresponding danger bits that were set.

[0050] The PAU 270 implements high-performance (high throughput and low latency) programmable atomic operations (also known as "custom atomic operations"), comparable to the performance of built-in atomic operations. Instead of performing multiple memory accesses, in response to an atomic operation request specifying a programmable atomic operation and a memory address, the circuitry in the memory controller chiplet 205 transmits the atomic operation request to the PAU 270 and sets a danger bit stored in a memory danger register corresponding to the memory address of the memory row used in the atomic operation. This ensures that no other operation (read, write, or atomic operation) is performed on the memory row, and the danger bit is then cleared after the atomic operation is completed. The additional direct data path provided to the PAU 270 for performing programmable atomic operations allows for additional write operations without being limited by the bandwidth of the communication network and without increasing any congestion on the communication network.

[0051] The PAU 270 includes a multi-threaded processor, such as a RISC-VIS-based multi-threaded processor, with one or more processor cores and further featuring an extended instruction set for performing programmable atomic operations. When equipped with the extended instruction set for performing programmable atomic operations, the PAU 270 can be embodied as one or more hybrid-threaded processors. In some example implementations, the PAU 270 provides bucket-style polling instantaneous thread switching to maintain a high instruction-per-clock rate.

[0052] Programmable atomic operations can be executed by PAU 270, which involve requesting programmable atomic operations on requested data. Users can prepare programming code to provide such programmable atomic operations. For example, programmable atomic operations can be relatively simple multi-loop operations, such as floating-point addition, or relatively complex multi-instruction operations, such as Bloom filter insert. Programmable atomic operations can be the same as or different from predetermined atomic operations, as long as they are defined by the user and not the system vendor. For these operations, cache controller 215 can preserve cache lines in cache 210 by setting a danger bit (in hardware), preventing the cache lines from being read by another process during transitions. Data is obtained from cache 210 or off-chip memory 275 or 280 and provided to PAU 270 to execute the requested programmable atomic operation. After the atomic operation, PAU 270 provides the obtained data to network communication interface 225 to directly encode outgoing data packets containing the obtained data for transmission on chiplet network 285. Additionally, PAU 270 provides the obtained data to cache controller 215, which then writes the obtained data to cache 210. After writing the obtained data to cache 210, cache controller 215 clears any corresponding dangerous bits that were set.

[0053] In the selected example, the approach taken for programmable atomic operations is to provide multiple custom atomic request types that can be sent from an originating source, such as a processor or other system component, to the memory controller chiplet 205 via chiplet network 285. Cache controller 215 or off-die memory controller 220 recognizes the request as a custom atom and forwards the request to PAU 270. In a representative embodiment, PAU 270: (1) is a programmable processing element capable of efficiently performing user-defined atomic operations; (2) can perform load and store operations on memory, arithmetic and logical operations, and control flow decisions; and (3) utilizes a RISC-V ISA with a new set of dedicated instructions to facilitate interaction with such controllers 215, 220, thereby performing user-defined operations atomically. In desirable examples, the RISC-V ISA contains a complete instruction set supporting high-level language operators and data types. PAU 270 may utilize the RISC-V ISA, but typically supports a more limited instruction set and a limited register file size to reduce the die size of the unit when contained within the memory controller chiplet 205.

[0054] As mentioned above, before writing read data to cache 210, the memory danger clearing unit 260 clears the set danger bits of the reserved cache lines. Therefore, when the write merging unit 255 receives a request and read data, the memory danger clearing unit 260 can transmit a reset or clear signal to cache 210 to reset the set memory danger bits of the reserved cache lines. Furthermore, resetting this danger bit releases pending read or write requests involving the specified (or reserved) cache line, thereby providing the pending read or write requests to the inbound request multiplexer for selection and processing.

[0055] Figure 3 This describes an example of routing between chiplets in a chiplet layout 300 using a CPI network according to an embodiment. The chiplet layout 300 includes chiplets 310A, 310B, 310C, 310D, 310E, 310F, 310G, and 310H. Chipslets 310A-310H are interconnected by a network including nodes 330A, 330B, 330C, 330D, 330E, 330F, 330G, and 330H. Each of chiplets 310A-310H includes hardware transceivers labeled 320A-320H. Network nodes 330A-330H also include one or more hardware transceivers, thereby allowing the reception and transmission of chips over the network. In some example embodiments, network nodes 330A-330H are implemented as chiplets that can provide additional functionality.

[0056] AIBs can be used to transmit CPI packets between chiplets 310. AIBs provide physical layer functionality. The physical layer uses source-synchronous data transfer with a forwarding clock to transmit and receive data. Packets are transmitted across the AIB relative to the transmitted clock in SDR or DDR. AIBs support various channel widths. When operating in SDR mode, AIB channel widths are multiples of 20 bits (20, 40, 60, ...), and for DDR mode, AIB channel widths are multiples of 40 bits (40, 80, 120, ...). The AIB channel width includes TX and RX signals. Channels can be configured to have a symmetrical number of TX and RX I / Os, or an asymmetrical number of transmitters and receivers (e.g., all transmitters or all receivers). A channel can act as an AIB master or slave depending on which chiplet provides the master clock.

[0057] The AIB adapter provides interfaces to the AIB link layer and to the AIB physical layer (PHY). The AIB adapter provides a data hierarchy register, a power-on reset sequencer, and a control signal shift register.

[0058] The AIB physical layer consists of AIB I / O units. AIB I / O units (implemented in some embodiments by hardware transceiver 320) can be input-only, output-only, or bidirectional. An AIB channel consists of a set of AIB I / O units, and the number of units depends on the AIB channel configuration. A receive signal on a chiplet is connected to a transmit signal on a pair of chipslets. In some embodiments, each column includes an AUX channel and data channels numbered 0 to N.

[0059] AIB channels are typically configured as half TX data and half RX data, all TX data, or all RX data plus associated clock and promiscuous control. In some example implementations, the number of TX data signals relative to the number of RX data signals is determined at design time and cannot be configured as part of system initialization.

[0060] The CPI packet protocol (point-to-point and routable) uses symmetrical receive and transmit I / O units within the AIB channel. The CPI streaming protocol allows for more flexible use of AIB I / O units. In some example implementations, the AIB channel for streaming mode can be configured with all TX, all RX, or half TX and half RX.

[0061] Data packets are routed between chiplets 310 via network nodes 330. Node 330 can determine the next node 330 to forward a received data packet to based on one or more data fields of the data packet. For example, source or destination address, source or destination port, virtual channel, or any suitable combination thereof can be hashed to select consecutive network nodes or available network paths. Path selection in this manner can be used to balance network traffic.

[0062] Therefore, in Figure 3 The diagram illustrates the data path from chiplet 310A to chiplet 310D. Data packets are sent from hardware transceiver 320A to network node 330A; forwarded by network node 330A to network node 330C; forwarded by network node 330C to network node 330D; and delivered by network node 330D to hardware transceiver 320D of chiplet 310D.

[0063] Figure 3 The diagram also illustrates a second data path from chiplet 310A to chiplet 310G. Data packets are sent from hardware transceiver 320A to network node 330A; forwarded by network node 330A to network node 330B; forwarded by network node 330B to network node 330D; forwarded by network node 330D to network node 330C; forwarded by network node 330C to network node 330E; forwarded by network node 330E to network node 330F; forwarded by network node 330F to network node 330H; forwarded by network node 330H to network node 330G; and delivered by network node 330G to hardware transceiver 320G of chiplet 310G. (The last sentence appears to be a fragment and doesn't translate directly.) Figure 3 As can be clearly seen, multiple paths traversing the network can be used for data transfer between any two chiplets.

[0064] The AIB I / O unit supports three clock modes: asynchronous (i.e., non-timed), SDR, and DDR. Non-timed mode is used for clocking and some control signals. SDR mode can use a dedicated SDR-only I / O unit or a dual-purpose SDR / DDR I / O unit.

[0065] The CPI packet protocol (point-to-point and routable) can use the AIB channel in either SDR or DDR operating mode. In some example implementations, the AIB channel increments by 80 I / O units (i.e., 40 TX and 40 RX) for SDR mode and by 40 I / O units for DDR mode.

[0066] The CPI streaming protocol can use AIB channels in either SDR or DDR operating modes. In some example implementations, the AIB channels are incremented by 40 I / O units for both modes (SDR and DDR).

[0067] A unique interface identifier is assigned to each AIB channel. This identifier is used during CPI reset and initialization to determine the paired AIB channels spanning adjacent chiplets. In some example embodiments, the interface identifier is a 20-bit value comprising a seven-bit chiplet identifier, a seven-bit column identifier, and a six-bit link identifier. The AIB physical layer uses an AIB out-of-band shift register to transmit the interface identifier. Bits 32-51 of the shift register are used to transmit the 20-bit interface identifier in both directions across the AIB interface.

[0068] In some implementations, AIB channels are numbered in ascending order, starting with the AIB channel adjacent to the AUX channel. The AIB channel adjacent to the AUX channel is defined as AIB channel zero.

[0069] Figure 3 An example is provided to illustrate eight chiplets 310 connected by a network comprising eight nodes 330. More or fewer chiplets 310 and more or fewer nodes 330 can be included in the chiplet network, thus allowing the creation of networks of chiplets of any size.

[0070] Figure 4 This is a block diagram of a data packet 400 comprising multiple micro-pieces according to some embodiments of the present disclosure. The data packet 400 is divided into flow control units (micro-pieces), each comprising 36 bits. A first micro-piece of the data packet 400 includes a control path field 405, a path field 410, a destination identifier (DID) field 415, a sequence continuation (SC) field 420, a length field 425, and a command field 430. A second micro-piece 435 and a last micro-piece 440 contain packet-related data. The data packet 400 contains micro-pieces indicating the total number of destinations as indicated by the length field 425, and therefore may not include one or both of the second micro-piece 435 and the last micro-piece 440 (e.g., if the packet contains only one or two micro-pieces) or may include one or more additional micro-pieces between the second micro-piece 435 and the last micro-piece 440.

[0071] The control path field 405 is a two-bit field that indicates whether the path field 410 should be used to control packet ordering. In some implementations, a value of 0 indicates that the path field 410 should be ignored, a value of 1 or 3 indicates that the path field 410 is used to determine the path for packet 400, and a value of 2 indicates that a single path ordering will be used. In some implementations, a one-bit field is used.

[0072] The path field 410 is an eight-bit field. When the control path field 405 indicates that the path field 410 is used to determine the path for packet 400, all packets with the same value for the path field 410 are guaranteed to take the same path across the network. Therefore, the order of the packets will remain unchanged between the sender and receiver. If the control path field 405 indicates that a single path ordering will be used, then the path for each packet is determined as if the path field 410 were set to zero. Therefore, all packets take the same path and the order will remain unchanged, regardless of the actual value of the path field 410 for each packet. If the control path field 405 indicates that the path field 410 will be ignored, then packets are routed without considering the value of the path field 410, and packets can be received by the receiver in an order different from the order in which they were sent by the sender. However, this avoids network congestion and allows for higher throughput in the device.

[0073] The DID field 415 stores a twelve-bit DID. The DID uniquely identifies the destination (e.g., a destination chip) within the network. The length field 425 is a five-bit field indicating the number of chips comprising packet 400. The interpretation of the length field 425 can be non-linear. For example, a value of 0-22 can be interpreted as 0-22 chips in packet 400, and a value of 23-27 can be interpreted as 33-37 chips in packet 400 (i.e., 10 more than the indicated value). Other values ​​for the length field 425 can be vendor-defined, rather than protocol-defined.

[0074] The system ensures that all packets with the SC field 420 set are delivered in sequence. Additionally, when the routing device detects that the SC field 420 is set in a packet on the virtual channel from source to destination, the routing device will not route packets from other sources on the virtual channel to the destination. Once packets with the SC field 420 cleared on the virtual channel from source to destination have been sent to the destination, the routing device resumes routing packets from other sources on the virtual channel to the destination. Routes to other destinations and routes on other virtual channels of the destination are unaffected.

[0075] Commands for data packet 400 are stored in command field 430, which is an eight-bit field. Commands can be write commands, read commands, predefined atomic operation commands, custom atomic operation commands, read responses, acknowledgment responses, or vendor-specific commands. Additionally, commands can indicate the virtual channel of data packet 400. For example, different commands can be used for different virtual channels, or bits 1, 2, 3, or 4 of the eight-bit command field 430 can be used to indicate the virtual channel, with the remaining bits used to indicate the command. The following table illustrates protocol- and command-based virtual channels according to some example embodiments.

[0076] Virtual Channel CPI Agreement AXI Protocol 0 Read / Write Requests Write request 1 Read / Write Response Write response 2 Unused Read request 3 Unused Read response 4 Priority read / write requests Priority write requests 5 Priority read / write response Priority write response 6 Unused Priority read request 7 Unused Priority read response

[0077] The address used for the command can be indicated in the path field 410. The memory access command can identify the number of bytes to be written or accessed, the memory space to be accessed (e.g., off-die memory 275 or instruction memory for custom atomic operations), or any suitable combination thereof. In some example embodiments, the command can instruct additional bits of a later microchip to identify the command. For example, the multi-byte command can be sent using a vendor-specific command in the eight-bit command field 430 and using a portion or all of the storage multi-byte command in the second microchip 435. Therefore, for certain values ​​of the command field 430, the packet 400 contains only one header microchip (e.g., ...). Figure 4 The first header micro-piece shown in the document contains fields 405-430. For other values ​​of command field 430, package 400 contains a predetermined additional number of header micro-pieces or a predetermined total number of header micro-pieces.

[0078] Figure 5 This is a flowchart illustrating the operation of method 500 performed by circuitry during transparent packet splitting according to some embodiments of the present disclosure. Method 500 includes operations 510, 520, 530, and 540. By way of example and not limitation, method 500 is described as using... Figure 4 The data packets are from Figure 1A-3 The device performs the operation.

[0079] In operation 510, the first small chip (e.g., Figure 3 The small chip 310A, its implementation Figure 2 The memory controller chip 205 is based on a predetermined threshold (e.g., Figure 2 The size of the network packet (the maximum packet size supported by the network) and the size of the data packet determine the segmentation of the data packet. In some example embodiments, the data packet has a protocol different from the network protocol (e.g., having a protocol with a different protocol than the network protocol). Figure 2 The network's CPI protocol has a maximum payload of AXI packets. Therefore, the chiplet 310A or hardware transceiver 320A can act as a bridge between a first network with a first maximum packet size and a second network with a second maximum packet size.

[0080] In operation 520, the first chip generates multiple smaller packets from the data packet, each comprising fewer bits than the data packet. For example, the data packet may include a header and a payload. The header indicates the packet size, the packet's source, and the packet's destination. Each of the multiple smaller packets may also include a header and a payload. The header of each of the multiple smaller packets indicates the smaller packet's size, the packet's source, and the packet's destination, wherein the source and destination of each of the smaller packets are the same as the source and destination of the larger packet. Each of the smaller packets contains an indication of the same virtual channel (e.g., the virtual channel indicated by command field 430) for all the smaller packets. The total payload size of all the smaller packets is equal to or greater than the data packet's payload size, but each smaller packet is smaller than the data packet.

[0081] In operation 530, the first chip transmits the first of a plurality of smaller packets that have set a first sequence indicator (e.g., SC field 420 of the first packet). In operation 540, the first chip also transmits the second of a plurality of smaller packets that have cleared a second sequence indicator (e.g., SC field 420 of the second packet). Regarding operations 530 and 540, the terms "first packet" and "second packet" are distinguished only between two packets and do not imply that the first and second packets are sequential first and second packets of the plurality of smaller packets. For example, "first packet" could be the first packet sent, and "second packet" could be the last packet sent. As another example, "first packet" could be the penultimate packet sent (out of more than two packets), and "second packet" could be the last packet sent. Therefore, the first chip may send additional packets of multiple smaller packets between operations 530 and 540, before operation 530, or both. In some example embodiments, operation 520 is performed entirely before any of the smaller packets are sent. In other example embodiments, operations 520, 530, and 540 are interleaved such that each smaller packet is sent when each smaller packet is generated.

[0082] By using method 500, the first chiplet is able to transmit the entire payload of a data packet using a network protocol with a payload size smaller than the maximum payload size of the data packet. (The following section discusses...) Figure 6 and 7 The methods 600 and 700 described enable the receiving device to reconstruct data packets without modifying the circuitry or software instructions designed for them. This reduces circuit complexity, thereby improving component reusability and manufacturing efficiency, and lowering costs. Furthermore, it reduces processing cycles, memory consumption, and the power used to transmit and receive data packets.

[0083] Figure 6This is a flowchart illustrating the operation of method 600, performed by a circuit during transparent routing of split packets, according to some embodiments of the present disclosure. Method 600 includes operations 610, 620, 630, 640, 650, 660, and 670. By way of example and not limitation, method 600 is described as using... Figure 4 The data packets are from Figure 1A-3 The device performs the operation.

[0084] In operation 610, the routing device (e.g., Figure 3 Network node 330C receives a first packet addressed to a second chiplet (e.g., chiplet 310D) from a first chiplet (e.g., chiplet 310A performing method 500), the first packet setting a first sequence indicator. As discussed above with respect to method 500, the SC field 420 indicates that subsequent packets to the same destination (or the same virtual channel to the same destination) are part of a larger packet.

[0085] In operation 620, based on the addressing of the first packet to the second chiplet, the routing device routes the first packet to the receiving device. Therefore, the first packet is typically routed to the second chiplet. In some example embodiments, the routing device's register file or other data structures are updated to record the identifier of the transmitting device, the identifier of the receiving device, the identifier of the virtual channel, or any suitable combination thereof.

[0086] In operation 630, the routing device receives a third packet addressed to the second chip from the third chip. For example, chip 310C can also send packets routed through network node 330C to chip 310D.

[0087] In operation 640, based on the set first sequence identifier, the routing device delays the transmission of the third packet to the second chiplet. By referring to the data structure updated in operation 620, the routing device determines that a packet with the set sequence identifier has already been sent to the second chiplet, and that the sending device of the packet is different from the sending device of the third packet. Therefore, transmitting the third packet to the second chiplet would cause the second chiplet to interrupt the reception of a larger packet that includes the first packet. To avoid this, the routing device either rejects the packet, requests the third chiplet to attempt to retransmit the packet, or caches the packet in its local memory for later transmission.

[0088] In operation 650, the routing device receives a second packet addressed to a second chip from the first chip, the second packet having its second sequence indicator cleared. In the simplest case of splitting a larger packet into two smaller packets, the "second packet" in operation 650 is the second packet of the larger packet. However, if the larger packet is split into more than two packets, then any number of intermediate packets, each with a sequence indicator set, can be received between the first and last packets. Therefore, the "first packet" in operation 610 can be any of the smaller packets except the last one, and the "second packet" in operation 650 is the last smaller packet of the larger packet.

[0089] In operation 660, based on the second packet being addressed to the second chiplet, the routing device routes the second packet to the second chiplet. In some example embodiments, the routing device's register file or other data structures are updated to clear the relationship between the transmitting and receiving devices recorded in operation 620. Therefore, when subsequent packets are received from other transmitting devices, those packets will be routed to the receiving device.

[0090] In operation 670, after routing the second packet to the second chiplet, the routing device routes the third packet to the second chiplet based on the fact that the second sequence indicator has been cleared. For example, if the third packet was cached at the routing device in operation 640, then the third packet is now sent to the second chiplet. As another example, if the routing device rejected the third packet in operation 640, then the third chiplet resends the third packet to the routing device and routes the third packet to the second chiplet.

[0091] By using method 600, the routing device can route multiple packets from the first chiplet to the second chiplet without allowing intermediate packets to be transmitted from other chiplets to the second chiplet and without interrupting other services. For example, in a virtual channel-based system, services to other chiplets and other virtual channel services to the second chiplet continue without interruption. In this way, circuit complexity is reduced, thereby improving component reusability and manufacturing efficiency and reducing costs. In addition, processing loops, memory consumption, and power used to transmit and receive large packets of data are reduced.

[0092] Figure 7 A flowchart illustrating the operation of method 700, performed by circuitry during the transparent reassembly of split packets, according to some embodiments of this disclosure. Method 700 includes operations 710, 720, 730, and 740. By way of example and not limitation, method 700 is described as using... Figure 4 The data packets are from Figure 1A-3 The device performs the operation.

[0093] In operation 710, the receiving device (e.g., Figure 3The small chip 310D receives a first set of packets, each of which is configured with a sequence indicator. For example, the transmitting device performing method 500 may split a large packet into multiple smaller packets, each of which, except for the last packet, is configured with a sequence indicator. The receiving device receives these packets.

[0094] In operation 720, the receiving device buffers the first set of packets based on the sequence indicator set for each packet in the first set of packets. For example, when each packet in the first set of packets is received, the receiving device may check the sequence indicator of the received packet, and if the sequence indicator is set, then the received packet is added to the buffer. The receiving device may have multiple buffers, one buffer for each virtual channel. In these example embodiments, the buffer may be based on the virtual channel of the packet (e.g., as provided by...). Figure 4 The buffer selected for the received packet is indicated by the command field 430 of packet 400 or by the dedicated virtual channel field in the packet header.

[0095] In operation 730, the receiving device receives a second packet with the sequence indicator cleared. Continuing with an example of the transmitting device in method 500, the last small packet resulting from splitting the larger packet is transmitted with the sequence indicator cleared. Therefore, the "second packet" in operation 730 can be the last small packet in a split larger packet transmitted by the transmitting device.

[0096] In operation 740, based on the second packet's cleared sequence indicator, the receiving device combines the first group of packets with the second packet to recreate the payload of the larger data packet. For example, when a packet with a cleared sequence indicator is received, the contents of the buffer can be checked. If the buffer is empty, the received packet is treated as a single packet of the network protocol (e.g., a CPI packet). If the buffer contains one or more previously received packets with set sequence indicators, the previously received packets are combined with the last received packet with a cleared sequence indicator to recreate the original large packet. In some implementations, the header of the original large packet is also recreated. In other implementations, the payload is recreated simply by discarding the headers of smaller packets. The reconstructed packet is then provided to the receiving device's processor or memory storage.

[0097] Therefore, by using method 700, the receiving device is able to receive packets larger than the maximum packet size of the network and deliver the packets through the network. In embodiments where the hardware transceiver reconstructs large packets, no modifications to other circuitry are required. Thus, existing devices that wish to transmit large packets using the first network protocol can communicate using the second network protocol without modification.

[0098] Figure 8This illustrates a block diagram of an example machine 800, which may be used, in, or through which any or more of the techniques (e.g., methods) discussed herein be implemented. As described herein, an example may contain logic or several components or mechanisms in, or be operable by, machine 800. A circuit system (e.g., a processing circuit system) is a collection of circuits (e.g., simple circuits, gates, logic, etc.) implemented in a tangible entity containing hardware of machine 800. The membership of a circuit system can be flexible over time. A circuit system contains components that can perform a specified operation individually or in combination during operation. In an example, the hardware of a circuit system may be designed invariably to perform a specific operation (e.g., hardwired). In an example, the hardware of a circuit system may contain variablely connected physical components (e.g., execution units, transistors, simple circuits, etc.) and machine-readable media that are physically modified (e.g., invariant magnetism of concentrated particles, electrically movable placement, etc.) to encode instructions for a specific operation. When connecting physical components, the underlying electrical properties of the hardware configuration change, for example, from an insulator to a conductor, or vice versa. Instructions enable embedded hardware (e.g., an execution unit or a loading mechanism) to create components of a circuit system within the hardware via variable connections, portions of which perform specific operations during operation. Thus, in an example, a machine-readable media element is part of the circuit system or another component communicatively coupled to the circuit system during device operation. In an example, any of the physical components can be used in more than one component within more than one circuit system. For instance, during operation, an execution unit may be used at one point in time in a first circuit of a first circuit system and reused at different times by a second circuit in the first circuit system, or by a third circuit in the second circuit system. Further examples of these components of machine 800 are given below.

[0099] In alternative embodiments, machine 800 may be used as a standalone device or connected (e.g., networked) to other machines. In a networked deployment, machine 800 may operate within the capacity of server machines, client machines, or both in a server-client network environment. In an example, machine 800 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 800 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network appliance, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) instructions specifying actions to be taken by said machine. Furthermore, while only a single machine is described, the term "machine" will also be considered as any collection of machines that individually or collectively execute a set (or more) of instructions to perform any one or more of the methods discussed herein (e.g., cloud computing, Software as a Service (SaaS), other computer cluster configurations).

[0100] Machine (e.g., computer system) 800 may include a hardware processor 802 (e.g., a central processing unit (CPU), graphics processing unit (GPU), hardware processor core, or any combination thereof), main memory 804, static memory 806 (e.g., memory or storage device for firmware, microcode, basic input / output (BIOS), unified extensible firmware interface (UEFI), etc.), and mass storage device 808 (e.g., hard disk drive, tape drive, flash memory, or other block device), some or all of which may communicate with each other via interconnect (e.g., bus) 830. Machine 800 may further include a display device 810, an alphanumeric input device 812 (e.g., keyboard), and a user interface (UI) navigation device 814 (e.g., mouse). In an example, the display device 810, input device 812, and UI navigation device 814 may be a touchscreen display. Machine 800 may additionally include a signal generating device 818 (e.g., a speaker), a network interface device 820, and one or more sensors 816, such as a Global Positioning System (GPS) sensor, a compass, an accelerometer, or other sensors. Machine 800 may include an output controller 828, for example, serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection, to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0101] The registers of processor 802, main memory 804, static memory 806, or mass storage device 808 may be or contain machine-readable media 822, on which one or more sets of data structures or instructions 824 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. Instructions 824 may also reside wholly or at least partially in any of the registers of processor 802, main memory 804, static memory 806, or mass storage device 808 during execution by machine 800. In an example, one or any combination of hardware processor 802, main memory 804, static memory 806, or mass storage device 808 may constitute machine-readable media 822. While machine-readable media 822 is described as a single medium, the term "machine-readable media" may include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store the one or more instructions 824.

[0102] The term "machine-readable media" can include any medium capable of storing, encoding, or carrying instructions executable by machine 800 and causing machine 800 to perform any one or more of the technologies disclosed herein, or any medium capable of storing, encoding, or carrying data structures used by or associated with such instructions. Examples of non-limiting machine-readable media can include solid-state memory, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon-based signals, sound signals, etc.). In examples, non-transitory machine-readable media includes machine-readable media having a plurality of particles having constant (e.g., rest) mass and therefore being composed of matter. Thus, non-transitory machine-readable media is machine-readable media that does not contain transiently propagating signals. Specific examples of non-transitory machine-readable media can include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and compact optical disc read-only memory (CD-ROM) and digital versatile optical disc read-only memory (DVD-ROM).

[0103] In this example, information stored or otherwise set on machine-readable medium 822 may represent instructions 824, such as instructions 824 themselves or a format from which instructions 824 may be derived. This format from which instructions 824 may be derived may include source code, encoded instructions (e.g., in compressed or encrypted form), encapsulated instructions (e.g., split into multiple encapsulations), etc. The information representing instructions 824 in machine-readable medium 822 may be processed by a processing circuitry system into instructions to perform any of the operations discussed herein. For example, deriving instructions 824 from information (e.g., processed by a processing circuitry system) may include: compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, decrypting, encapsulating, decapsulating, or otherwise manipulating information into instructions 824.

[0104] In an example, the derivation of instruction 824 may involve assembling, compiling, or decompiling information (e.g., by a processing circuitry) to create instruction 824 from some intermediate or preprocessed format provided by machine-readable media 822. When information is provided in multiple parts, the information may be combined, decapsulated, and modified to create instruction 824. For example, information may be contained in multiple compressed source code packages (or object code, or binary executable code, etc.) on one or more remote servers. The source code packages may be encrypted during transmission over a network and, if necessary, decrypted, decompressed, assembled (e.g., linked), and compiled or decompiled at the local machine (e.g., into a stand-alone executable library, etc.) and executed by the local machine.

[0105] Instruction 824 may further utilize any of several transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.) to transmit or receive over the communication network 826 via the network interface device 820 using a transport medium. Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone (POTS) networks, and wireless data networks (e.g., the IEEE 802.11 series of standards known as Wi-Fi®, the IEEE 802.16 series of standards known as WiMax®), the IEEE 802.15.4 series of standards, peer-to-peer (P2P) networks, etc. In examples, network interface device 820 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to the communication network 826. In an example, network interface device 820 may include multiple antennas to communicate wirelessly using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered as any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 800, and containing digital or analog communication signals or other intangible media for facilitating communication of such software. The transmission medium is a machine-readable medium.

[0106] In the foregoing description, some exemplary embodiments of this disclosure have been described. It will be apparent that various modifications can be made to this disclosure without departing from the broader scope set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive. The following is a non-exhaustive list of exemplary embodiments of this disclosure.

[0107] Example 1 is a system comprising: a transmitter at a first chiplet; a router coupled to the transmitter via a chiplet network; and a receiver at a second chiplet coupled to the router via the chiplet network, wherein: the first chiplet is configured to perform operations including: determining to split the data packet based on a predetermined threshold and the size of a data packet addressed to the second chiplet; generating from the data packet a plurality of smaller packets, each comprising fewer bits than the data packet; transmitting a first packet of the plurality of smaller packets having a first sequence indicator set, the first packet being addressed to the second chiplet; and transmitting a second packet of the plurality of smaller packets having a second sequence indicator cleared, the second packet being addressed to the second chiplet.

[0108] In Example 2, the subject matter according to Example 1 is included, wherein the router is configured to perform operations including: receiving a first packet; routing the first packet to a second chiplet based on the first packet being addressed to the second chiplet; receiving a third packet from a third chiplet coupled to the router via the chiplet network, the third packet being addressed to the second chiplet; delaying the transmission of the third packet to the second chiplet based on the first packet being addressed to the second chiplet and the first sequence indicator being set; receiving a second packet; routing the second packet to the second chiplet based on the second packet being addressed to the second chiplet; and after routing the second packet to the second chiplet, routing the third packet to the second chiplet based on the second packet having cleared the second sequence indicator.

[0109] In Example 3, the subject matter according to Example 2 is included, wherein the delay of the transmission of the third packet to the second chiplet is further based on the same virtual channel of the first packet and the same virtual channel of the third packet.

[0110] In Example 4, the subject matter according to Examples 2 to 3 is included, wherein: the routing of the third packet to the second chiplet after routing the second packet to the second chiplet is further based on the virtual channel of the second packet being the same as the virtual channel of the third packet.

[0111] In Example 5, the subject matter according to Examples 2 through 4 is included, wherein the router is further configured to perform operations including: receiving a fourth packet from a fourth chip connected to the router via the chip network, the fourth packet being addressed to a second chip; and routing the fourth packet to the second chip based on the fact that the virtual channel of the first packet is different from the virtual channel of the fourth packet.

[0112] In Example 6, the subject matter according to Examples 1 to 5 is included, wherein the second chip is configured to perform operations including: receiving the plurality of smaller packets; setting the first sequence indicator based on the first packet; buffering the first packet; and combining the plurality of smaller packets to recreate the payload of the data packet based on the second packet having cleared the second sequence indicator.

[0113] In Example 7, the subject matter according to Examples 1 to 6 is included, wherein: the transmission of the first packet with the first sequence indicator set is part of: determining that each packet in a set of packets of the plurality of smaller packets is not the last packet of the plurality of smaller packets; and the transmission of each packet in the set of packets with the sequence indicator set; and the transmission of the second packet with the second sequence indicator cleared is based on determining that the second packet is the last packet of the plurality of smaller packets.

[0114] In Example 8, the subject matter described in Examples 1 to 7 is included, wherein the second chiplet is a memory controller chiplet.

[0115] In Example 9, the subject matter according to Example 8 is included, wherein the memory controller chip communicates with at least one memory device chip via a memory interface.

[0116] Example 10 is a method comprising: determining, by a first chiplet coupled to a router via a chiplet network, to split a large packet based on a predetermined threshold and the size of a data packet addressed to a second chiplet coupled to the router via the chiplet network; generating, by the first chiplet, a plurality of smaller packets from the data packet, each comprising fewer bits than the data packet; transmitting, by the first chiplet, a first packet of the plurality of smaller packets set with a first sequence indicator on the chiplet network, the first packet being addressed to the second chiplet; and transmitting, by the first chiplet, a second packet of the plurality of smaller packets with a second sequence indicator cleared on the network, the second packet being addressed to the second chiplet.

[0117] In Example 11, the subject matter according to Example 10 includes: receiving a first packet by the router; routing the first packet to the second chiplet based on the first packet being addressed to the second chiplet; receiving a third packet by the router from a third chiplet coupled to the router via the chiplet network, the third packet being addressed to the second chiplet; delaying the transmission of the third packet to the second chiplet based on the first packet being addressed to the second chiplet and the first sequence indicator being set; receiving a second packet by the router; routing the second packet to the second chiplet based on the second packet being addressed to the second chiplet; and after routing the second packet to the second chiplet, routing the third packet to the second chiplet based on the second packet having cleared the second sequence indicator.

[0118] In Example 12, the subject matter according to Example 11 is included, wherein the delay of the transmission of the third packet to the second chiplet is further based on the same virtual channel of the first packet and the same virtual channel of the third packet.

[0119] In Example 13, the subject matter described in Examples 11 to 12 is included, wherein: the routing of the third packet to the second chiplet after routing the second packet to the second chiplet is further based on the same virtual channel as the second packet.

[0120] In Example 14, the subject matter according to Examples 11 to 13 includes: the router receiving a fourth packet from a fourth chip connected to the router via the chip network, the fourth packet being addressed to a second chip; and routing the fourth packet to the second chip based on the fact that the virtual channel of the first packet is different from the virtual channel of the fourth packet.

[0121] In Example 15, the subject matter according to Examples 10 to 14 includes: receiving the plurality of smaller packets by the second chip; setting the first sequence indicator based on the first packet; buffering the first packet; and combining the plurality of smaller packets to recreate the payload of the data packet based on the second packet having cleared the second sequence indicator.

[0122] In Example 16, the subject matter according to Examples 10 to 15 is included, wherein: the transmission of the first packet with the first sequence indicator set is part of: determining that each packet in a set of packets of the plurality of smaller packets is not the last packet of the plurality of smaller packets; and the transmission of each packet in the set of packets with the sequence indicator set; and the transmission of the second packet with the second sequence indicator cleared is based on determining that the second packet is the last packet of the plurality of smaller packets.

[0123] Example 17 is a non-transitory machine-readable medium storing instructions that, when executed by a first chiplet coupled to a router via a chiplet network, cause the first chiplet to perform the following operations: determining to split a large packet based on a predetermined threshold and the size of a data packet of a second chiplet coupled to the router via the chiplet network; generating from the large packet a plurality of smaller packets, each comprising fewer bits than the data packet; transmitting on the chiplet network a first packet of the plurality of smaller packets with a first sequence indicator set, the first packet being addressed to the second chiplet; and transmitting on the chiplet network a second packet of the plurality of smaller packets with a second sequence indicator cleared, the second packet being addressed to the second chiplet.

[0124] In Example 18, the subject matter according to Example 17 is included, wherein: the transmission of the first packet with the first sequence indicator set is part of: determining that each packet in a set of packets of the plurality of smaller packets is not the last packet of the plurality of smaller packets; and the transmission of each packet in the set of packets with the sequence indicator set; and the transmission of the second packet with the second sequence indicator cleared is based on determining that the second packet is the last packet of the plurality of smaller packets.

[0125] In Example 19, the subject matter described in Examples 17 and 18 is included, wherein the second chiplet is a memory controller chiplet.

[0126] In Example 20, the subject matter according to Example 19 is included, wherein the memory controller chip communicates with at least one memory device chip via a memory interface.

[0127] Example 21 is at least one machine-readable medium containing instructions that, when executed by a processing circuitry system, cause the processing circuitry system to perform operations to implement any of Examples 1-20.

[0128] Example 22 is an apparatus that includes components for implementing any of Examples 1 to 20.

[0129] Example 23 is a system for implementing any of Examples 1 to 20.

[0130] Example 24 is a method for implementing any of Examples 1 through 20.

Claims

1. A system for transparent packet splitting and reassembly, the system comprising: The transmitter is located at the first small chip; A router, which is coupled to the transmitter via a chip network; as well as The receiver, located at a second chip coupled to the router via the chip network, wherein: The first chip is configured to perform operations including the following: The data packet is split based on a predetermined threshold and the size of the data packet addressed to the second chip. Generate multiple smaller packets, each comprising fewer bits than the data packet, from the data packet; The first packet of the plurality of smaller packets, which is configured with a first sequence indicator, is transmitted and addressed to the second chiplet; and Transmit the second packet, one of the plurality of smaller packets whose second sequence indicator has been cleared, the second packet being addressed to the second chiplet; and The router is configured to perform operations including the following: The system receives the first packet, the second packet, and the third packet, wherein the third packet is received from the third chip via the chip network and is addressed to the second chip; Based on the fact that the first packet is addressed to the second chip and the first sequence indicator is set, the transmission of the third packet to the second chip is delayed; and After routing the second packet to the second chiplet, the third packet is routed to the second chiplet.

2. The system of claim 1, wherein the router is configured to perform operations including: Based on the fact that the first packet is addressed to the second chip, the first packet is routed to the second chip; as well as Based on the fact that the second packet is addressed to the second chip, the second packet is routed to the second chip; The third packet is routed to the second chiplet after the second packet is routed to the second chiplet based on the fact that the second sequence indicator has been cleared by the second packet.

3. The system according to claim 1, wherein: The delay in the transmission of the third packet to the second chip is further based on the fact that the virtual channel of the first packet is the same as the virtual channel of the third packet.

4. The system according to claim 2, wherein: The routing of the third packet to the second chiplet after routing the second packet to the second chiplet is further based on the fact that the virtual channel of the second packet is the same as the virtual channel of the third packet.

5. The system of claim 1, wherein the router is further configured to perform operations including: A fourth packet is received from a fourth chip coupled to the router via the chip network, the fourth packet being addressed to the second chip; and Based on the fact that the virtual channel of the first packet is different from the virtual channel of the fourth packet, the fourth packet is routed to the second chip.

6. The system of claim 1, wherein the second chip is configured to perform operations including: Receive the plurality of smaller packets; Based on the first packet, the first sequence indicator is set, and the first packet is buffered; and Based on the fact that the second sequence indicator has been cleared from the second packet, the plurality of smaller packets are combined to recreate the payload of the data packet.

7. The system according to claim 1, wherein: The first packet that transmits the first sequence indicator is a subset of the following: Determine that each of the multiple smaller packages in a set of packages is not the last of the multiple smaller packages; as well as Each packet in the set of packets is transmitted with a sequence indicator set; as well as The transmission of the second packet with the second sequence indicator cleared is based on determining that the second packet is the last of the plurality of smaller packets.

8. The system according to claim 1, wherein: The second small chip is a memory controller chip.

9. The system according to claim 8, wherein: The memory controller chip communicates with at least one memory device chip via a memory interface.

10. A method for transparent packet splitting and reassembly, the method comprising: The packet is split based on a predetermined threshold and the size of the packet addressed to a second chip connected to the router via the chip network. The first chip generates multiple smaller packets from the data packet, each comprising fewer bits than the data packet. The first chip transmits a first packet of the plurality of smaller packets, which are set with a first sequence indicator, on the chip network, and the first packet is addressed to the second chip. The first chip transmits a second packet from the plurality of smaller packets on the chip network that has had its second sequence indicator cleared, and the second packet is addressed to the second chip. The router receives the first packet, the second packet, and a third packet from a third chip coupled to the router via the chip network, the third packet being addressed to the second chip; Based on the fact that the first packet is addressed to the second chip and the first sequence indicator is set, the transmission of the third packet to the second chip is delayed; as well as After routing the second packet to the second chiplet, the third packet is routed to the second chiplet.

11. The method of claim 10, further comprising: Based on the fact that the first packet is addressed to the second chip, the first packet is routed to the second chip; as well as Based on the fact that the second packet is addressed to the second chip, the second packet is routed to the second chip; The third packet is routed to the second chiplet after the second packet is routed to the second chiplet based on the fact that the second sequence indicator has been cleared by the second packet.

12. The method according to claim 10, wherein: The delay in the transmission of the third packet to the second chip is further based on the fact that the virtual channel of the first packet is the same as the virtual channel of the third packet.

13. The method according to claim 11, wherein: The routing of the third packet to the second chiplet after routing the second packet to the second chiplet is further based on the fact that the virtual channel of the second packet is the same as the virtual channel of the third packet.

14. The method of claim 10, further comprising: The router receives a fourth packet from a fourth chip coupled to the router via the chip network, and the fourth packet is addressed to the second chip; as well as Based on the fact that the virtual channel of the first packet is different from the virtual channel of the fourth packet, the fourth packet is routed to the second chip.

15. The method of claim 10, further comprising: The second small chip receives the plurality of smaller packets; The first sequence indicator is set based on the first packet, and the first packet is buffered; as well as Based on the fact that the second sequence indicator has been cleared from the second packet, the plurality of smaller packets are combined to recreate the payload of the data packet.

16. The method of claim 10, wherein: The first packet that transmits the first sequence indicator is a subset of the following: Determine that each of the multiple smaller packages in a set of packages is not the last of the multiple smaller packages; as well as Each packet in the set of packets is transmitted with a sequence indicator set; as well as The transmission of the second packet with the second sequence indicator cleared is based on determining that the second packet is the last of the plurality of smaller packets.

17. A non-transitory machine-readable medium storing instructions, which, when executed by a router coupled to a first chiplet, a second chiplet, and a third chiplet via a chiplet network, cause the router to perform operations including: The first packet is received from the first chip, and the first packet is addressed to the second chip. Based on the fact that the first packet is addressed to the second chip, the first packet is routed to the second chip; A third packet is received from the third chip, and the third packet is addressed to the second chip. Based on the fact that the first packet is addressed to the second chip and a first sequence indicator is set, the transmission of the third packet to the second chip is delayed; The second packet is received from the first chip, the second packet is addressed to the second chip, and the second packet has cleared the second sequence indicator; Based on the fact that the second packet is addressed to the second chip, the second packet is routed to the second chip; as well as After routing the second packet to the second chiplet, the third packet is routed to the second chiplet based on the fact that the second sequence indicator has been cleared from the second packet.

18. The non-transitory machine-readable medium according to claim 17, wherein: The second small chip is a memory controller chip.

19. The non-transitory machine-readable medium according to claim 18, wherein: The memory controller chip communicates with at least one memory device chip via a memory interface.

20. The non-transitory machine-readable medium of claim 17, wherein: The delay in the transmission of the third packet to the second chip is further based on the fact that the virtual channel of the first packet is the same as the virtual channel of the third packet.

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