A method for preparing a low-density-defect epitaxial layer on a high-L-Pit silicon single crystal substrate

Abstract

The application discloses a method for preparing a low-density defect epitaxial layer on a high L-Pits silicon single crystal substrate, and belongs to the technical field of silicon epitaxial wafer growth. The method comprises the following steps: (1) placing the high L-Pits silicon single crystal substrate in an epitaxial furnace, heating to 1200-1250 DEG C, and introducing HCl gas to remove the L-Pits aggregates near the surface of the silicon single crystal substrate; (2) cooling to 800-1100 DEG C, continuously introducing HCl gas to clean the surface of the silicon single crystal substrate, and obtaining a pretreated substrate; and (3) adjusting the temperature to the epitaxial growth process temperature to grow an epitaxial layer, and obtaining a low-density defect epitaxial wafer. According to the method, the surface of the high L-Pits silicon single crystal substrate is pretreated at high and low temperatures, and the L-Pits defects on the surface of the silicon substrate are reduced or eliminated. The silicon epitaxial wafer obtained by the method has low-density surface microdefects, and the surface particles are extremely few, so that the quality of the silicon epitaxial wafer is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of silicon epitaxial wafer growth, in particular to a method for preparing an epitaxial layer with low defect density on a high L-Pits silicon single crystal substrate. BACKGROUND

[0002] The epitaxial growth process of a silicon wafer is an important process in the manufacturing process of semiconductor chips. The process refers to the process of growing a single crystal silicon thin film with the same crystal orientation on a polished silicon wafer under certain conditions, i.e. an epitaxial layer, so as to obtain an epitaxial silicon wafer. The epitaxial silicon wafer is widely used in the production and manufacturing of high-performance semiconductor devices due to its good crystal structure, low defect density and excellent electrical conductivity.

[0003] In order to reduce the series resistance and prepare energy-efficient advanced devices, super-doped substrates (such as super-doped phosphorus substrates with a resistivity of less than 0.001 ohm.cm) are developed for the production and processing of silicon epitaxial wafers, and the surface quality of the silicon single crystal polishing wafer as the substrate is crucial to obtaining a high-quality epitaxial layer.

[0004] Most of the silicon single crystal substrate wafers currently used in the industry are obtained by using the Czochralski method (CZ). However, some trace impurities are inevitably introduced during the growth of single crystal silicon, and due to the particularity of single crystal growth, primary microdefects are generated. For example, when super-doped single crystals are grown, the concentration of interstitial atoms is dominant, and the concentration of vacancies is unsaturated. During the cooling process of the single crystal, the supersaturated interstitial atoms will aggregate to form A / B helix type defects (L-Pits), which will extend into the epitaxial layer when the polished substrate wafer is epitaxially grown, and will appear as LPDN (Non-cleanable Light Point Defect) particles on the surface of the epitaxial wafer. In order to more easily prepare super-doped substrates, the pulling speed needs to be reduced in the Czochralski method growth process, which results in the dominance of L-Pits defects.

[0005] In the semiconductor industry, the presence of impurities and defects in single crystal silicon can seriously affect the electrical properties of devices. For super-doped B / P / As substrates and interstitial-rich defect substrates, when epitaxial growth is performed by conventional processes, the surface of the epitaxial wafer exhibits LPDN abnormality caused by high L-Pits of the silicon single crystal substrate, resulting in high-density epitaxial layer defects and abnormal distribution of particles on the surface of the epitaxial wafer, which adversely affects the performance of advanced devices such as leakage, and can cause large quantities of silicon wafers to be scrapped, resulting in a great waste of production costs and reducing production efficiency. In order to solve the above problems, new growth process technology needs to be developed.

[0006] Considering the preparation cost and production efficiency and other factors, it is a problem to be solved by those skilled in the art to develop an efficient, simple and low-cost method for preparing a low-density defect epitaxial layer on a high-L-Pits silicon single crystal substrate. SUMMARY

[0007] The purpose of the present application is to provide a method for preparing a low-density defect epitaxial layer on a high-L-Pits silicon single crystal substrate, realizing the distribution of low-density surface microdefects and surface few particles, ensuring the stable and reliable quality of silicon epitaxial wafers, and meeting the processing requirements of high-performance devices.

[0008] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0009] The present application provides a method for preparing a low-density defect epitaxial layer on a high-L-Pits silicon single crystal substrate, comprising the following steps:

[0010] (1) placing the high-L-Pits silicon single crystal substrate in an epitaxial furnace, heating to 1200-1250℃, and introducing HCl (hydrogen chloride) gas to remove the L-Pits aggregates near the surface of the silicon single crystal substrate;

[0011] (2) cooling to 800-1100℃ at a cooling rate of 15-50℃ / s, continuing to introduce HCl gas to clean the surface of the silicon single crystal substrate, and obtaining a pretreated substrate;

[0012] (3) adjusting the temperature to the epitaxial growth process temperature, growing an epitaxial layer on the pretreated substrate, and obtaining a low-density defect epitaxial wafer.

[0013] The present application improves the cleanliness of the surface of the silicon wafer by two-step gas phase polishing pretreatment of the surface of the silicon substrate at high and low temperatures, reduces or eliminates the number of L-Pits defects existing on the surface of the silicon substrate, and prepares for stable and uniform crystal growth of the subsequent epitaxial layer.

[0014] In steps (1) and (2), HCl gas phase polishing is continuously carried out at a high temperature of 1200-1250℃ and a rapid cooling to 800-1100℃, which utilizes the characteristics that silicon substrate surface self-interstitials diffuse to the surface faster than vacancies under high temperature conditions, combined with rapid cooling, the internal vacancies of the silicon wafer do not have time to diffuse outward, forming self-interstitials diffusing to the surface, and the internal is a supersaturated distribution of vacancies. After self-interstitials diffuse to the surface layer, they react with HCl to generate chlorine-containing gas which is carried away, so that the high-density defect layer is polished and removed, forming a low-defect-density interface layer on the substrate surface, preparing for the subsequent high-quality epitaxial layer growth.

[0015] The protective atmosphere of the epitaxial furnace is hydrogen.

[0016] As preferred, in step (1), the heating rate is 15-50℃ / s, the HCl gas flow is 0.5-1 slm, and the treatment time is 30-60s.

[0017] More preferably, the heating rate is 20℃ / s, and the temperature is raised to 1220℃.

[0018] As preferred, in step (2), the cooling rate is 15-50℃ / s, the HCl gas flow is 0.5-1 slm, and the treatment time is 30-60s.

[0019] More preferably, the cooling rate is 20℃ / s, and the temperature is lowered to 1090℃.

[0020] As preferred, before step (3) is performed, the temperature is raised to 1160-1200℃, and the silicon source gas SiHCl3 and H2 are introduced to grow a buffer layer on the pretreated substrate surface. To reduce the influence of the buffer layer on the thickness and doping concentration of the target epitaxial layer, the thickness is generally controlled to be 0.1-0.5μm.

[0021] The present application improves the surface cleanliness of the silicon wafer by high and low temperature pretreatment, and grows a defect-free thin buffer layer on this basis. The thin buffer layer can provide a single crystal seed for the growth of an epitaxial layer with low density defects, and reduce the influence on the electrical properties of the target epitaxial layer on the basis of thickness control.

[0022] As preferred, the heating rate is 5-15℃ / s.

[0023] As preferred, 1-5 slm of the silicon source gas SiHCl3 and 50-80 slm of H2 are introduced to perform the reaction. The present application reduces the proportion of the silicon source gas SiHCl3 in the mixed gas, and slows down the growth reaction rate, which is helpful to generate a buffer layer with low density defects.

[0024] In step (3), a conventional epitaxial growth process is used to prepare the epitaxial layer. The epitaxial growth process temperature is 1100-1160℃, the silicon source gas SiHCl3, H2 and a specific concentration of doping gas (such as AsH3, PH3 or B2H6) are introduced to perform epitaxial growth, and the growth rate is controlled to be 3-4μm / min.

[0025] As preferred, after the epitaxial growth, post-treatment is performed, the post-treatment adopts high-temperature vapor polishing or high-temperature baking, the high-temperature vapor polishing comprises: heating to 1200-1250℃, polishing by inputting HCl gas, the flow rate of HCl gas is 0.5-1 slm, and the processing time is 30-60s; the high-temperature baking comprises: heating to 1200-1250℃, and the baking time is 30-60s. After the epitaxial growth, the surface of the epitaxial layer is polished by high-temperature HCl in-situ etching or high-temperature baking, and the surface quality of the epitaxial layer is improved. More preferably, the temperature of the high-temperature post-treatment is 1220℃.

[0026] After the post-treatment is completed, the whole growth process is completed by decreasing the temperature at a rate of 5-15℃ / s.

[0027] The present application has the beneficial effects of:

[0028] The present application forms self-interstitial diffusion to the surface by high-low temperature pretreatment of the high-L-Pits silicon single crystal substrate surface, and the distribution of the internal is vacancy supersaturation, in combination with vapor polishing to remove the high-density defect layer on the surface, so that the L-Pits defects on the silicon substrate surface are reduced or eliminated, and the stable and uniform crystal growth of the subsequent epitaxial layer is prepared. The silicon epitaxial wafer obtained by the preparation method of the present application has low-density surface microdefects and few surface particles, and the purpose of improving the quality of the silicon epitaxial wafer is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 It is the process flow chart of Example 1.

[0030] Figure 2 It is the process temperature change schematic diagram of Example 1, wherein ① is heating, ② is high-temperature vapor polishing treatment, ③ is low-temperature vapor polishing treatment, ④ is buffer layer growth, ⑤ is conventional epitaxial process, and ⑥ is high-temperature vapor polishing post-treatment.

[0031] Figure 3 It is the process temperature change schematic diagram of Comparative Example 1, wherein ① is heating, and ⑤ is conventional epitaxial process.

[0032] Figure 4 It is the process temperature change schematic diagram of Comparative Example 2, wherein ① is heating, ④ is buffer layer growth, and ⑤ is conventional epitaxial process.

[0033] Figure 5 It is the process temperature change schematic diagram of Comparative Example 3, wherein ① is heating, ② is vapor polishing treatment, and ⑤ is conventional epitaxial process.

[0034] Figure 6 It is the schematic diagram of high-L-Pits defect density of the substrate surface without treatment, and the left drawing is a partial enlarged view of the right drawing.

[0035] Figure 7 Figure 8 is a schematic diagram of the internal distribution of self-interstitial atoms and vacancies in a high L-Pits substrate before being treated.

[0036] Figure 8 Figure 9 is a schematic diagram of the internal distribution of self-interstitial atoms and vacancies in a high L-Pits substrate after being treated according to the present application.

[0037] Figure 9 Figure 10 is a LPDN particle distribution map of an epitaxial wafer prepared according to the process conditions of Comparative Example 1, obtained by SP1 scanning.

[0038] Figure 10 Figure 11 is a LPDN particle distribution map of an epitaxial wafer prepared according to the process conditions of Example 1, obtained by SP1 scanning.

[0039] Figure 11 Figure 12 is a comparison of surface LPDN data of epitaxial wafers prepared according to the old process and the new process, obtained after SP1 testing and analysis.

[0040] Figure 12 Figure 13 is a comparison of surface LPDN data of epitaxial wafers prepared according to different examples, obtained after SP1 testing and analysis. DETAILED DESCRIPTION

[0041] The application will be further described below with reference to the specific examples. It should be understood that these examples are only used to illustrate the application and not intended to limit the scope of the application. Furthermore, it should be understood that those skilled in the art can make various modifications or changes to the application after reading the content of the present application, and these equivalent forms also fall within the scope of the appended claims.

[0042] The test methods used in the following examples are conventional methods unless otherwise specified; the materials, reagents, etc. used are commercially available reagents and materials unless otherwise specified.

[0043] The high L-Pits silicon single crystal substrates (super-doped substrates) used in the following examples and comparative examples are from the same batch of products.

[0044] Example 1

[0045] This example provides a method for preparing a low-density defect epitaxial layer on a high L-Pits silicon single crystal substrate, as shown in Figure 1 The method comprises the following specific steps:

[0046] S1: Place the high L-Pits silicon single crystal substrate in an epitaxial furnace, start the epitaxial equipment, and perform rapid heating operation under a hydrogen atmosphere, with a heating rate of 20°C / s, and heat to 1220°C;

[0047] S2: Pretreatment of the outer surface of the silicon wafer under a hydrogen atmosphere, high-temperature gas-phase polishing pretreatment of the high-L-Pit substrate under a high-temperature condition of 1220℃ by passing in HCl to remove near-surface L-Pit aggregates, treatment time 60s, HCl flow rate 0.5slm;

[0048] S3: Rapid cooling to 1090℃ at a cooling rate of 20℃ / s, continuing to pass in HCl for surface cleaning treatment, treatment time 60s, HCl flow rate 0.5slm;

[0049] S4: Reheating to 1180℃ for buffer layer growth, passing in a silicon source gas SiHCl3 at a flow rate of 2slm and H2 at a flow rate of 70slm to grow a buffer layer on the pretreated substrate surface, thickness controlled at 0.3μm;

[0050] S5: Then cooling to a growth temperature of 1130℃, passing in a silicon source gas SiHCl3, H2 and a doping gas for epitaxial growth, growth rate 3.5μm / min;

[0051] S6: Reheating to 1220℃ for high-temperature gas-phase polishing post-treatment, treatment time 60s, HCl flow rate 0.5slm;

[0052] S7: Final cooling to complete the entire growth process, cooling rate 15℃ / s.

[0053] The temperature change schematic diagram in the above process is shown in Figure 2 .

[0054] Example 2

[0055] The present example provides a method for preparing a low-density defect epitaxial layer on a high-L-Pit silicon single crystal substrate, comprising the following specific steps:

[0056] S1: Start the epitaxial device, perform rapid heating operation, heating rate 15℃ / s, heat to 1200℃;

[0057] S2: Pretreatment of the outer surface of the silicon wafer under a hydrogen atmosphere, high-temperature gas-phase polishing pretreatment of the high-L-Pit substrate under a high-temperature condition of 1220℃ by passing in HCl to remove near-surface L-Pit aggregates, treatment time 60s, HCl flow rate 0.5slm;

[0058] S3: Rapid cooling to 1090℃ at a cooling rate of 20℃ / s, continuing to pass in HCl for surface cleaning treatment, treatment time 60s, HCl flow rate 0.5slm;

[0059] S4: Reheat to 1160℃, grow buffer layer, flow rate 1 slm of silicon source gas SiHCl3 and flow rate 80 slm of H2, react to grow buffer layer on pretreated substrate surface, thickness controlled at 0.1 μm;

[0060] S5: Then grow at temperature 1160℃, pass in silicon source gas SiHCl3, H2 and doping gas to epitaxially grow, growth rate 3.5 μm / min;

[0061] S6: Reheat to 1220℃ to perform high-temperature vapor polishing post-processing, processing time 60 s, HCl flow rate 0.5 slm;

[0062] S7: Finally, complete the entire growth process by cooling at a rate of 15℃ / s.

[0063] Example 3

[0064] The embodiment provides a method for preparing an epitaxial layer with low density of defects on a high L-Pits silicon single crystal substrate, comprising the following specific steps:

[0065] S1: Start the epitaxial device and perform rapid heating operation, heating rate 50℃ / s, heat to 1250℃;

[0066] S2: Pretreat the outer surface of the silicon wafer, pass in HCl at 1250℃ high temperature to perform high-temperature vapor polishing pretreatment on the high L-Pits substrate to remove near-surface L-Pit aggregates, processing time 30 s, HCl flow rate 1 slm;

[0067] S3: Rapidly cool to 800℃ at a rate of 50℃ / s, continue to pass in HCl to perform surface cleaning treatment, processing time 60 s, HCl flow rate 0.5 slm;

[0068] S4: Reheat to 1200℃ to grow buffer layer, flow rate 5 slm of silicon source gas SiHCl3 and flow rate 80 slm of H2, react to grow buffer layer on pretreated substrate surface, thickness controlled at 0.5 μm;

[0069] S5: Then cool to growth temperature 1130℃, pass in silicon source gas SiHCl3, H2 and doping gas to epitaxially grow, growth rate 3.5 μm / min;

[0070] S6: Reheat to 1250℃ to perform high-temperature vapor polishing post-processing, processing time 30 s, HCl flow rate 1 slm;

[0071] S7: Finally, complete the entire growth process by cooling at a rate of 15℃ / s.

[0072] Example 4

[0073] The high and low temperature pretreatment is performed on the high L-Pits silicon single crystal substrate, and then the epitaxial layer is grown by using the conventional epitaxial process and high temperature baking post-processing, and the method is as follows:

[0074] S1: start the epitaxial equipment, perform rapid heating operation, the heating rate is 20℃ / s, and the temperature is raised to 1220℃;

[0075] S2: the outer surface of the silicon wafer is pretreated, HCl is introduced under the high temperature condition of 1220℃ to perform high temperature gas phase polishing pretreatment on the high L-Pits substrate to remove the near-surface L-Pit aggregate, the processing time is 30s, and the HCl flow is 1 slm;

[0076] S3: rapidly cool to 1090℃ at a cooling rate of 20℃ / s, continue to introduce HCl for surface cleaning treatment, the processing time is 60s, and the HCl flow is 1 slm;

[0077] S4: the temperature is raised to the growth temperature of 1130℃, the silicon source gas SiHCl3, H2 and the doping gas are introduced for epitaxial growth, and the growth rate is 3.5μm / min;

[0078] S5: the temperature is raised to 1220℃ again for high temperature baking treatment, and the processing time is 60s;

[0079] S6: finally, the cooling rate is 15℃ / s to complete the whole growth process.

[0080] Example 5

[0081] The high and low temperature pretreatment is performed on the high L-Pits silicon single crystal substrate, and then the epitaxial layer is grown by using the conventional epitaxial process, and the method is as follows:

[0082] S1: start the epitaxial equipment, perform rapid heating operation, the heating rate is 20℃ / s, and the temperature is raised to 1220℃;

[0083] S2: the outer surface of the silicon wafer is pretreated, HCl is introduced under the high temperature condition of 1220℃ to perform high temperature gas phase polishing pretreatment on the high L-Pits substrate to remove the near-surface L-Pit aggregate, the processing time is 30s, and the HCl flow is 1 slm;

[0084] S3: rapidly cool to 1090℃ at a cooling rate of 20℃ / s, continue to introduce HCl for surface cleaning treatment, the processing time is 60s, and the HCl flow is 1 slm;

[0085] S4: the temperature is raised to the growth temperature of 1130℃, the silicon source gas SiHCl3, H2 and the doping gas are introduced for epitaxial growth, and the growth rate is 3.5μm / min;

[0086] S5: The last cooling completes the whole growth process, and the cooling rate is 15 °C / s.

[0087] Comparative Example 1

[0088] The present comparative example (old process) directly grows an epitaxial layer on a high L-Pits silicon single crystal substrate under conventional epitaxial process conditions, in the following manner:

[0089] S1: Start the epitaxial equipment, and perform a warming operation at a warming rate of 10 °C / s;

[0090] S2: Warm to 1130 °C, and introduce a silicon source gas SiHCl3, H2, and a doping gas to perform epitaxial growth, with a growth rate of 3.5 μm / min;

[0091] S3: The last cooling completes the whole growth process, and the cooling rate is 10 °C / s.

[0092] The temperature change schematic diagram in the above process is shown in Figure 3 .

[0093] Comparative Example 2

[0094] The present comparative example (buffer layer process) does not use high and low temperature pretreatment, and grows a buffer layer and an epitaxial layer on a high L-Pits silicon single crystal substrate, in the following manner:

[0095] S1: Start the epitaxial equipment, and perform a rapid warming operation at a warming rate of 20 °C / s;

[0096] S2: Warm to 1180 °C, and grow a buffer layer, with a flow rate of 2 slm of a silicon source gas SiHCl3 and a flow rate of 70 slm of H2, to grow a buffer layer directly on the surface of the unpretreated substrate, with a thickness of 0.3 μm;

[0097] S3: Cool to a growth temperature of 1130 °C, and introduce a silicon source gas SiHCl3, H2, and a doping gas to perform epitaxial growth, with a growth rate of 3.5 μm / min;

[0098] S4: The last cooling completes the whole growth process, and the cooling rate is 15 °C / s.

[0099] The temperature change schematic diagram in the above process is shown in Figure 4 .

[0100] Comparative Example 3

[0101] The present comparative example (single-step vapor polishing process) grows an epitaxial layer on a high L-Pits silicon single crystal substrate after single-step vapor polishing pretreatment under conventional epitaxial process conditions, in the following manner:

[0102] S1: start the epitaxial equipment, perform rapid heating operation, heating rate 10°C / s, heat to 1180°C;

[0103] S2: pretreat the outer surface of the silicon wafer, under high temperature condition of 1180°C, introduce HCl to perform high temperature gas phase polishing pretreatment on the high L-Pit substrate to remove near-surface L-Pit aggregates, treatment time 60s, HCl flow rate 0.5 slm;

[0104] S3: cool to growth temperature 1130°C, introduce silicon source gas SiHCl3, H2 and doping gas to perform epitaxial growth, growth rate 3.5 μm / min;

[0105] S4: finally cool to complete the whole growth process, cooling rate 15°C / s.

[0106] The temperature change schematic diagram in the above process is shown in Figure 5 .

[0107] Test Example

[0108] 1. After surface preferential etching of the high L-Pit single crystal substrate, the silicon wafer strip area is scanned by the detection equipment NSX330 produced by Onto Company, and the L-Pit defect diagram is obtained, as shown in Figure 6 .

[0109] Figure 7 and Figure 8 are the schematic diagrams of generation and elimination of surface microdefects of high L-Pit silicon single crystal substrate before and after high temperature treatment, respectively. L-Pit defects are microdefects formed by agglomeration and growth of silicon and impurity interstitial atoms during crystal cooling process.

[0110] 2. After cleaning the silicon wafer produced by the above process, SP1 test is performed, the Surfscan SP1 laser particle size scanner produced by KLA-Tencor Company is selected for test, DCN (Dark composite normal) mode is adopted to scan and analyze particles with particle size not less than 0.13 μm on the surface of the epitaxial wafer, and the silicon wafer surface particle LPDN distribution diagram is obtained.

[0111] As shown in Figure 9 and Figure 11 , when there are high density L-Pit microdefects in the near-surface region of the silicon single crystal substrate and they are not removed by high temperature pretreatment, under the epitaxial process condition, growth into the epitaxial layer (Comparative Example 1) produces high density of surface LPDN defects.

[0112] Although room-temperature vapor phase polishing in Comparative Example 3 removed surface layer defects, a low-defect epitaxial growth interface was not formed after the defect layer was removed because a vacancy supersaturation distribution was not established internally. Therefore, the surface LPDN defect level remained high after epitaxial growth. Figure 11 Data corresponding to the single-step polishing process.

[0113] like Figure 10 As shown, the number of LPDNs in the epitaxial wafers grown after high and low temperature pretreatment of the substrate is significantly reduced, combined with Figure 7 and Figure 8 The schematic diagram suggests that high- and low-temperature vapor phase polishing pretreatment is beneficial for removing L-Pits defects on the substrate surface layer, resulting in an epitaxial growth interface layer with low defect density. Simultaneously, buffer layer growth serves as a single-crystal seed for preparing low-density defects under high-temperature conditions; this thin single-crystal seed layer facilitates the growth of the low-density defect epitaxial layer. The combination of the aforementioned high- and low-temperature vapor phase polishing pretreatment and high-temperature single-crystal seed layer growth provides sufficient conditions for obtaining a low-density defect epitaxial layer. Figure 11 Data shows that surface LPDN defects in epitaxial wafers prepared under the optimized process conditions of Example 1 can be eliminated.

[0114] according to Figure 12 The data comparison clearly suggests that after high and low temperature pretreatment of the substrate surface, HCl reacts with the rapidly diffused, enriched interstitial Si clusters near the surface, generating Si halide gas which is carried out of the cavity by a large flow of hydrogen. This forms a defect-free epitaxial interface layer on the silicon substrate surface, preparing it for subsequent growth of a low-density defect epitaxial layer. Based on this, a high-quality epitaxial layer can be fabricated. After high-temperature vapor phase polishing or high-temperature baking, the surface LPDN data can be further improved. Specific LPDN data for the epitaxial wafer surface are shown below. Figure 12 As shown.

[0115] The present invention provides a detailed description of a method for preparing a low-density defect epitaxial layer on a high-L-Pits silicon single crystal substrate. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method of preparing a low-density-defect epitaxial layer on a high L-Pit silicon single crystal substrate, characterized by, The method comprises the following steps: (1) placing a high L-Pit silicon single crystal substrate in an epitaxial furnace, heating to 1200-1250 DEG C, and introducing HCl gas to remove L-Pit clusters near the surface of the silicon single crystal substrate; (2) cooling to 800-1100 DEG C at a cooling rate of 15-50 DEG C / s, and continuously introducing HCl gas to clean the surface of the silicon single crystal substrate, thereby obtaining a pretreated substrate; (3) adjusting the temperature to an epitaxial growth process temperature, growing an epitaxial layer on the pretreated substrate, and obtaining a low-density defect epitaxial wafer; In steps (1) and (2), the HCl gas flow rate is 0.5-1 slm, and the treatment time is 30-60 s.

2. The method of claim 1, wherein the high L-Pit silicon single crystal substrate is a silicon single crystal substrate having a density of L-Pits of 1 x 105 / cm2 or more. In step (1), the heating rate is 15-50 DEG C / s.

3. The method of claim 2, wherein the high L-Pit silicon single crystal substrate is a silicon single crystal substrate having a density of L-Pits of 1 x 105 / cm2 or more. In step (1), the heating rate is 20 DEG C / s, and the temperature is raised to 1220 DEG C; in step (2), the cooling rate is 20 DEG C / s, and the temperature is cooled to 1090 DEG C.

4. The method of claim 1, wherein the high L-Pit silicon single crystal substrate is a silicon single crystal substrate having a density of L-Pits of 1 x 105 / cm2 or more. Before step (3) is performed, the temperature is raised to 1160-1200 DEG C, and a silicon source gas SiHCl3 and H2 are introduced to react and grow a buffer layer on the surface of the pretreated substrate, with a thickness controlled to be 0.1-0.5 μm.

5. The method of claim 4, wherein the high L-Pit silicon single crystal substrate is a silicon single crystal substrate having a density of L-Pits of 1 x 105 / cm2 or more. The silicon source gas SiHCl3 is introduced at a flow rate of 1-5 slm, and the H2 is introduced at a flow rate of 50-80 slm.

6. The method of claim 4, wherein the high L-Pit silicon single crystal substrate is a silicon single crystal substrate having a density of L-Pits of 1 x 105 / cm2 or more. Before step (3) is performed, the temperature is raised to 1160-1200 DEG C at a rate of 5-15 DEG C / s.

7. The method of claim 1, wherein the high L-Pit silicon single crystal substrate is a silicon single crystal substrate having a density of L-Pits of 1 x 105 / cm2 or more. In step (3), the epitaxial growth process temperature is 1100-1160 DEG C, and the growth rate is controlled to be 3-4 μm / min.

8. The method of claim 1, wherein the high L-Pit silicon single crystal substrate is a silicon single crystal substrate having a density of L-Pits of 1 x 105 / cm2 or more. In step (3), after the epitaxial growth is completed, post-treatment is performed, and the post-treatment is high-temperature vapor polishing or high-temperature baking; the high-temperature vapor polishing comprises: heating to 1200-1250 DEG C, introducing HCl gas to polish, the HCl gas flow rate is 0.5-1 slm, and the treatment time is 30-60 s; the high-temperature baking comprises: heating to 1200-1250 DEG C, and baking for 30-60 s.

9. The method of claim 8, wherein the high L-Pit silicon single crystal substrate is a silicon single crystal substrate having a density of L-Pits of 1 x 105 / cm2 or more. After the post-treatment is completed, the temperature is cooled at a rate of 5-15 DEG C / s.

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