Over-temperature protection circuit and method

Abstract

The present application discloses an over-temperature protection circuit and method, which includes a reference current module, a temperature detection module, and a current comparison module; the output end of the reference current module is connected to the input end of the current comparison module; the output end of the temperature detection module is connected to the other input end of the current comparison module. The present application uses the current comparison module to compare the received positive temperature coefficient current and the reference current to obtain a comparison result, and adjusts the output voltage VOUT of the over-temperature protection circuit according to the comparison result. There is no need to perform temperature detection through the base-emitter voltage of the transistor. Therefore, the over-temperature protection circuit does not have the inherent disadvantages of temperature detection (that is, the detection accuracy will be affected by the manufacturing process deviation), thereby improving the detection accuracy of the over-temperature protection circuit.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to an over-temperature protection circuit and method. Background Art

[0002] With the rapid development of the microelectronics industry, the industry's requirements for integrated circuit reliability are becoming increasingly stringent. Temperature is often one of the most important factors affecting the quality of various performance indicators. To ensure the performance of integrated circuits, high-performance over-temperature protection circuits are required. When the chip temperature rises to a certain value, the output signal shuts down the integrated circuit, keeping the integrated circuit within the appropriate temperature range.

[0003] Currently, overtemperature protection circuits primarily use the base-emitter voltage of a transistor for temperature detection. This voltage is compared with a set reference voltage or a positive temperature coefficient voltage to generate an overtemperature shutdown signal. When the temperature exceeds the preset value, the output signal of the overtemperature protection circuit flips from a high level to a low level, thus achieving protection. However, the inherent disadvantage of using the base-emitter voltage of a transistor for temperature detection is that detection accuracy is affected by manufacturing process variations, resulting in low detection accuracy for overtemperature protection circuits.

[0004] Therefore, how to improve the detection accuracy of the over-temperature protection circuit has become an urgent problem to be solved in this field. Summary of the Invention

[0005] The present application provides an over-temperature protection circuit and method, the purpose of which is to improve the detection accuracy of the over-temperature protection circuit.

[0006] In order to achieve the above objectives, this application provides the following technical solutions:

[0007] An over-temperature protection circuit includes: a reference current module, a temperature detection module, and a current comparison module;

[0008] The output end of the reference current module is connected to the input end of the current comparison module;

[0009] The output end of the temperature detection module is connected to the other input end of the current comparison module.

[0010] Optionally, the reference protection circuit includes a startup circuit, a first circuit, and a second circuit;

[0011] The output end of the startup circuit is connected to the input end of the first circuit;

[0012] The output end of the first circuit is connected to the input end of the second circuit.

[0013] Optionally, the startup circuit includes a third PMOS transistor, a fourth PMOS transistor, and a sixth resistor;

[0014] The drain of the third PMOS tube and one end of the sixth resistor are connected to the gate of the fourth PMOS tube; the source of the third NMOS tube and the source of the fourth NMOS tube are grounded; and the other end of the sixth resistor is connected to the power supply voltage port.

[0015] Optionally, the first circuit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a first NMOS transistor, and a second NMOS transistor;

[0016] The first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the first NMOS transistor and the second NMOS transistor form a self-bias structure;

[0017] The fifth PMOS transistor and the seventh PMOS transistor form a cascode current mirror;

[0018] The sixth PMOS transistor and the eighth PMOS transistor form a cascode current mirror;

[0019] The ninth PMOS transistor and the eleventh PMOS transistor form a cascode current mirror;

[0020] The tenth PMOS transistor and the twelfth PMOS transistor form a cascode current mirror;

[0021] The thirteenth PMOS transistor and the fourteenth PMOS transistor form a cascode current mirror;

[0022] The source of the fifth PMOS tube, the source of the sixth PMOS tube, the source of the first PMOS tube, the source of the second PMOS tube, the source of the ninth PMOS tube, the source of the tenth PMOS tube, and the source of the thirteenth PMOS tube are connected to the power supply voltage port.

[0023] Optionally, the second circuit includes a first triode, a second triode, a third triode, a fourth triode, a fifth triode, a sixth triode, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor;

[0024] The emitter of the first transistor is connected to one end of the fourth resistor, the base of the first transistor and the base of the second transistor are connected to the emitter of the third transistor, and the emitter of the second transistor and the other end of the fourth resistor are connected to one end of the second resistor;

[0025] The emitter of the fifth transistor is connected to one end of the fifth resistor, the base of the fifth transistor and the base of the fourth transistor are connected to the emitter of the sixth transistor, the emitter of the fourth transistor is connected to one end of the first resistor, and the other end of the first resistor and one end of the third resistor are connected to the other end of the fifth resistor;

[0026] The collector of the first transistor, the collector and base of the third transistor, the collector of the second transistor, the other end of the second resistor, the other end of the third resistor, the collector of the fourth transistor, the collector and base of the sixth transistor, and the collector of the fifth transistor are grounded.

[0027] Optionally, the temperature detection module includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a seventh triode, an eighth triode, a ninth triode, a tenth triode, a seventh resistor, an eighth resistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, and a twenty-first PMOS transistor;

[0028] The fifteenth PMOS transistor, the sixteenth PMOS transistor, the seventeenth PMOS transistor, the eighteenth PMOS transistor, the seventh transistor, and the eighth transistor form a self-biased structure; the source of the fifteenth PMOS transistor and the source of the sixteenth PMOS transistor are connected to a power supply voltage port;

[0029] The 20th PMOS transistor and the 21st PMOS transistor form a cascode current mirror; the source of the 20th PMOS transistor is connected to the power supply voltage port;

[0030] The drain of the fifth NMOS transistor is connected to the gate of the eighteenth PMOS transistor, the gate of the sixteenth PMOS transistor, and the gate of the nineteenth PMOS transistor; the gate of the fifth NMOS transistor and one end of the eighth resistor are connected to the drain of the seventh NMOS transistor; the source of the fifth NMOS transistor is grounded;

[0031] The source of the nineteenth PMOS tube and the other end of the eighth resistor are connected to a power supply voltage port;

[0032] The gate of the seventh NMOS transistor is connected to the gate and drain of the sixth NMOS transistor; the source of the seventh NMOS transistor and the source of the sixth NMOS transistor are grounded;

[0033] The base of the ninth transistor is connected to the collector of the tenth transistor, and the collector of the ninth transistor is connected to the base of the tenth transistor; the emitter of the tenth transistor is connected to one end of the seventh resistor; the other end of the seventh resistor and the emitter of the ninth transistor are grounded.

[0034] Optionally, the current comparison module includes: an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a twenty-fifth PMOS transistor, a twenty-sixth PMOS transistor, and a twenty-seventh PMOS transistor;

[0035] The twenty-second PMOS transistor, the twenty-third PMOS transistor, the twenty-fourth PMOS transistor, and the twenty-fifth PMOS transistor form a cascode current mirror; the source of the twenty-second PMOS transistor and the source of the twenty-third PMOS transistor are connected to the power supply voltage port;

[0036] The fourteenth NMOS transistor, the twenty-sixth PMOS transistor, the fifteenth NMOS transistor, and the twenty-seventh PMOS transistor form a bipolar inverter structure; the source of the twenty-sixth PMOS transistor and the source of the twenty-seventh PMOS transistor are connected to the power supply voltage port; the drain of the twenty-seventh PMOS transistor and the drain of the fifteenth NMOS transistor are connected to the output voltage VOUT;

[0037] The drain of the eighth NMOS transistor is connected to the drain and gate of the twenty-fourth PMOS transistor, and the gate of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor; the source of the eighth NMOS transistor is grounded;

[0038] The gate of the ninth NMOS transistor is connected to the gate of the tenth NMOS transistor, and the gate and drain of the ninth NMOS transistor are connected to the drain of the eleventh NMOS transistor; the source of the ninth NMOS transistor is grounded;

[0039] The drain of the tenth NMOS transistor is connected to the drain of the twelfth transistor, and the source of the tenth NMOS transistor is grounded;

[0040] The gate of the eleventh NMOS transistor is connected to the gate and drain of the twelfth NMOS transistor, and the source of the eleventh NMOS transistor is grounded;

[0041] The drain of the twelfth NMOS tube is connected to the gate of the thirteenth NMOS tube, and the source of the twelfth NMOS tube is grounded;

[0042] The drain of the thirteenth NMOS tube and the drain of the twenty-fifth PMOS tube are connected to the gate of the fourteenth NMOS tube and the gate of the twenty-sixth NMOS tube, and the source of the thirteenth NMOS tube is grounded.

[0043] An over-temperature protection method, applicable to the over-temperature protection circuit, comprising:

[0044] The current comparison module in the over-temperature protection circuit, when receiving the reference current sent by the reference current module and the positive temperature coefficient current sent by the temperature detection module, compares the reference current with the positive temperature coefficient current to obtain a comparison result;

[0045] The output voltage VOUT of the over-temperature protection circuit is adjusted according to the comparison result.

[0046] Optionally, the comparing the reference current with the positive temperature coefficient current to obtain a comparison result includes:

[0047] Determining whether the positive temperature coefficient current is less than the reference current;

[0048] If the positive temperature coefficient current is less than the reference current, determining that the over-temperature protection circuit is in a low-temperature state;

[0049] If the positive temperature coefficient current is not less than the reference current, it is determined that the over-temperature protection circuit is in a high temperature state.

[0050] Optionally, adjusting the output voltage VOUT of the over-temperature protection circuit according to the comparison result includes:

[0051] When the comparison result indicates that the over-temperature protection circuit is in a high-temperature state, the voltage value of the output voltage VOUT is reduced to reduce the temperature of the over-temperature protection circuit.

[0052] The technical solution provided by the present application is that the over-temperature protection circuit includes a reference current module, a temperature detection module, and a current comparison module; the output end of the reference current module is connected to the input end of the current comparison module; the output end of the temperature detection module is connected to the other input end of the current comparison module. The present application uses the current comparison module to compare the received positive temperature coefficient current and the reference current to obtain a comparison result, and adjusts the output voltage VOUT of the over-temperature protection circuit according to the comparison result. There is no need to perform temperature detection through the base-emitter voltage of the transistor. Therefore, the over-temperature protection circuit does not have the inherent disadvantages of temperature detection (that is, the detection accuracy will be affected by the manufacturing process deviation), thereby improving the detection accuracy of the over-temperature protection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0054] Figure 1 A schematic diagram of the architecture of an over-temperature protection circuit provided in an embodiment of the present application;

[0055] Figure 2 A schematic diagram of the architecture of a reference current module provided in an embodiment of the present application;

[0056] Figure 3 A schematic diagram of the architecture of a temperature detection module provided in an embodiment of the present application;

[0057] Figure 4 A schematic diagram of the architecture of a current comparison module provided in an embodiment of the present application;

[0058] Figure 5 A flow chart of an over-temperature protection method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0060] like Figure 1 , which is a schematic diagram of the architecture of an over-temperature protection circuit provided in an embodiment of the present application, wherein the over-temperature protection circuit includes a reference current module 101 , a temperature detection module 102 , and a current comparison module 103 .

[0061] An output terminal of the reference current module 101 is connected to an input terminal of the current comparison module 103 .

[0062] The output end of the reference current module 101 sends the reference current to the input end of the circuit comparison module.

[0063] It should be noted that the reference current module 101 includes a startup circuit, a first circuit, and a second circuit; the output end of the startup circuit is connected to the input end of the first circuit; and the output end of the first circuit is connected to the input end of the second circuit.

[0064] An output terminal of the temperature detection module 102 is connected to another input terminal of the current comparison module 103 .

[0065] Among them, the output end of the temperature detection module 102 sends the positive temperature coefficient current to the other input end of the current comparison module 103. The current comparison module compares the received positive temperature coefficient current with the reference current to obtain a comparison result, and adjusts the output voltage VOUT of the over-temperature protection circuit according to the comparison result.

[0066] To sum up, the current comparison module compares the received positive temperature coefficient current and the reference current to obtain a comparison result, and adjusts the output voltage VOUT of the over-temperature protection circuit according to the comparison result. Compared with the existing technology, it is not necessary to perform temperature detection through the base-emitter voltage of the transistor. Therefore, the over-temperature protection circuit does not have the inherent disadvantages of temperature detection (that is, the detection accuracy will be affected by the manufacturing process deviation), thereby improving the detection accuracy of the over-temperature protection circuit.

[0067] Optional, combined Figure 1 , see Figure 2 , is a schematic diagram of the architecture of a reference current module provided in an embodiment of the present application, wherein the reference current module 101 includes a startup circuit, a first circuit, and a second circuit.

[0068] The startup circuit includes a third PMOS transistor, a fourth PMOS transistor, and a sixth resistor.

[0069] The drain of the third PMOS tube and one end of the sixth resistor are connected to the gate of the fourth PMOS tube; the source of the third NMOS tube and the source of the fourth NMOS tube are grounded; the other end of the sixth resistor is connected to the power supply voltage port.

[0070] It should be noted that the circuit may not be in normal working state after the power is turned on. The corresponding current in the transistor may be zero or small. At this time, the emitter junction of the transistor cannot be forward-conducted. Therefore, a startup circuit is required to pull the circuit back to normal state from the abnormal working state, and after the startup is completed, it should not affect the operation of the main circuit.

[0071] Specifically, the gate of the third NMOS tube is used to detect the emitter voltage of the second transistor (about 1.2V in a normal state). When the second transistor is not conducting, the emitter voltage of the second transistor is lower than 0.6V. At this time, the third NMOS tube is not conducting, and its equivalent impedance is very large. Then, the gate of the fourth NMOS tube is a high voltage, and the fourth NMOS tube is turned on, which lowers the gate voltages of the first PMOS tube and the second PMOS tube, changes the conduction state of the PMOS tube, and thus injects a large current into the circuit. The circuit starts, and after the startup is completed, the third NMOS tube is turned on and the fourth NMOS tube is turned off, thereby cutting off the startup circuit from the main circuit and will not affect the normal operation of the main circuit.

[0072] Among them, the first circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a first NMOS transistor, and a second NMOS transistor.

[0073] The first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the first NMOS transistor and the second NMOS transistor form a self-bias structure.

[0074] The fifth PMOS transistor and the seventh PMOS transistor form a cascode current mirror.

[0075] The sixth PMOS transistor and the eighth PMOS transistor form a cascode current mirror.

[0076] The ninth PMOS transistor and the eleventh PMOS transistor form a cascode current mirror.

[0077] The tenth PMOS transistor and the twelfth PMOS transistor form a cascode current mirror.

[0078] The thirteenth PMOS transistor and the fourteenth PMOS transistor form a cascode current mirror.

[0079] The source of the fifth PMOS transistor, the source of the sixth PMOS transistor, the source of the first PMOS transistor, the source of the second PMOS transistor, the source of the ninth PMOS transistor, the source of the tenth PMOS transistor, and the source of the thirteenth PMOS transistor are connected to the power supply voltage port.

[0080] The second circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor.

[0081] The emitter of the first transistor is connected to one end of the fourth resistor, the base of the first transistor and the base of the second transistor are connected to the emitter of the third transistor, and the emitter of the second transistor and the other end of the fourth resistor are connected to one end of the second resistor.

[0082] The emitter of the fifth transistor is connected to one end of the fifth resistor, the base of the fifth transistor and the base of the fourth transistor are connected to the emitter of the sixth transistor, the emitter of the fourth transistor is connected to one end of the first resistor, and the other end of the first resistor and one end of the third resistor are connected to the other end of the fifth resistor.

[0083] The collector of the first transistor, the collector and base of the third transistor, the collector of the second transistor, the other end of the second resistor, the other end of the third resistor, the collector of the fourth transistor, the collector and base of the sixth transistor and the collector of the fifth transistor are grounded.

[0084] It should be noted that the reference current can be calculated by the reference current module, and the calculation process of the reference current is:

[0085] The size ratio of the first PMOS transistor: the second PMOS transistor, the third PMOS transistor: the fourth PMOS transistor, and the first NMOS transistor: the second NMOS transistor is 1:1, so that the currents of the first NMOS transistor and the second NMOS transistor are equal and have nothing to do with the power supply. Therefore, the voltages of the first NMOS transistor and the second NMOS transistor are approximately equal. The voltage difference across the first resistor is the voltage difference between the second and third triodes and the fourth and sixth triodes. Therefore, the emitter-base voltage of the triode can be expressed as formula (1).

[0086]

[0087] In formula (1), V EB is the emitter-base voltage, V T is the thermal voltage, and V T =kT / q, k is the Boltzmann constant, T is the absolute temperature, q is the charge of a single electron, I C is the collector current of the transistor, I S is the reverse saturation current of the transistor.

[0088] Since the emitter area of the fourth and sixth transistors is n times that of the second and third transistors, the current density of the fourth and sixth transistors is 1 / n times that of the second and third transistors. Therefore, the current flowing through the first resistor is as shown in formula (2).

[0089]

[0090] In formula (2), I R1is the current of the first resistor, V EB3 is the emitter-base voltage of the third transistor, V EB2 is the emitter-base voltage of the second transistor, V EB4 is the emitter-base voltage of the fourth transistor, V EB6 is the emitter-base voltage of the sixth transistor, and R1 is the first resistor.

[0091] The current flowing through the third resistor is shown in formula (3).

[0092]

[0093] In formula (3), I R3 is the current flowing through the third resistor, and R3 is the third resistor.

[0094] Since V T is a voltage with a positive temperature coefficient, and V EB It is a voltage with a negative temperature coefficient. Theoretically, by adjusting the size of the first resistor and the third resistor, the positive temperature coefficient and the negative temperature coefficient can be equal, so that a current with a zero temperature coefficient can be obtained. However, in reality, the emitter-base voltage V EB It does not change linearly with temperature. There is a high-order nonlinear term, which is related to TlnT. Therefore, the change of the emitter-base voltage of the transistor with temperature is shown in formula (4).

[0095]

[0096] In formula (4), is the band gap voltage estimated at 0K, is the emitter voltage when the temperature is the reference temperature, T is the absolute temperature, T0 is the reference temperature, η is a constant related to the process and has nothing to do with temperature, and the value of α is related to the temperature characteristic of the collector current.

[0097] Optionally, when the collector current is a positive temperature coefficient current, the value of α is 1, and when the collector current is a zero temperature coefficient current, the value of α is 0; therefore, the voltage difference of the transistor emitter junction under the action of collector currents with different temperature coefficients can be used to perform high-order temperature compensation of the bandgap reference, thereby obtaining a reference voltage or reference current with smaller temperature drift.

[0098] It should be noted that, since the cascode structures of the fifth and seventh PMOS tubes, the sixth and eighth PMOS tubes, the ninth and eleventh PMOS tubes, and the tenth and twelfth PMOS tubes are consistent in size with the cascode structures of the second and fourth PMOS tubes, the current with an approximately zero temperature coefficient flowing through the second NMOS tube can be replicated and supplied to other transistors. The use of the cascode structure can improve the accuracy of current replication.

[0099] The current flowing through the fourth resistor is shown in formula (5).

[0100]

[0101] In formula (5), I R4 is the current flowing through the fourth resistor, V EB1 is the emitter-base voltage of the first transistor, and R4 is the fourth resistor.

[0102] The current flowing through the fifth resistor is shown in formula (6).

[0103]

[0104] In formula (6), I R5 is the current flowing through the fifth resistor, and R5 is the fifth resistor.

[0105] It should be emphasized that the current flowing through the first transistor and the fifth transistor is accurately replicated by the common-source common-gate current mirror of the fifth PMOS transistor, the seventh PMOS transistor, the tenth PMOS transistor, and the twelfth PMOS transistor, and can be approximately regarded as a zero temperature coefficient current, while the collector current flowing through the second transistor and the fourth transistor is a current with a positive temperature coefficient. Therefore, the variation of the emitter-base voltage of the first transistor with temperature is shown in formula (7), the variation of the emitter-base voltage of the second transistor with temperature is shown in formula (8), and the difference between the emitter-base voltage of the first transistor and the emitter-base voltage of the second transistor is shown in formula (9).

[0106]

[0107]

[0108]

[0109] In formula (9), the difference between the emitter-base voltage of the first transistor and the emitter-base voltage of the second transistor can generate a nonlinear current on the fourth resistor to compensate for the nonlinear term of the emitter voltage. Similarly, the fifth resistor will also generate a nonlinear current for temperature compensation, so that the obtained reference current has a smaller temperature drift, and the simulation can reach about 16ppm / ℃. Finally, the high-precision reference current obtained is copied through the common-source and common-gate current mirrors of the thirteenth PMOS transistor and the fourteenth PMOS transistor and sent to the current comparison module. The obtained reference current can be shown in formula (10).

[0110]

[0111] In formula (10), IREF is the reference voltage.

[0112] Optionally, in an actual production process, due to the influence of process mismatch, the source terminal voltages of the second NMOS transistor and the second NMOS transistor are not completely equal, but there is an offset voltage. When a single-machine triode structure is adopted, the influence of the offset voltage on the reference voltage is shown in formula (11).

[0113]

[0114] In formula (11), V OS is the offset voltage.

[0115] Optionally, when a two-electrode triode series structure is used, the effect of the offset voltage on the reference current is shown in formula (12).

[0116]

[0117] It should be noted that the offset voltage V OS The proportion is smaller than that of IREF1, so the use of two transistors in series can reduce the impact of the offset voltage introduced by the process mismatch and obtain better accuracy.

[0118] To sum up, the current comparison module compares the received positive temperature coefficient current and the reference current to obtain a comparison result, and adjusts the output voltage VOUT of the over-temperature protection circuit according to the comparison result. Compared with the existing technology, it is not necessary to perform temperature detection through the base-emitter voltage of the transistor. Therefore, the over-temperature protection circuit does not have the inherent disadvantages of temperature detection (that is, the detection accuracy will be affected by the manufacturing process deviation), thereby improving the detection accuracy of the over-temperature protection circuit.

[0119] Optional, combined Figure 1 , see Figure 3, is a schematic diagram of the architecture of a temperature detection module provided in an embodiment of the present application, wherein the temperature detection module includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a seventh triode, an eighth triode, a ninth triode, a tenth triode, a seventh resistor, an eighth resistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, and a twenty-first PMOS transistor.

[0120] The fifteenth PMOS transistor, the sixteenth PMOS transistor, the seventeenth PMOS transistor, the eighteenth PMOS transistor, the seventh transistor and the eighth transistor form a self-bias structure; the source of the fifteenth PMOS transistor and the source of the sixteenth PMOS transistor are connected to the power supply voltage port.

[0121] The fifteenth PMOS tube and the sixteenth PMOS tube have the same size, and the seventeenth PMOS tube and the eighteenth PMOS tube have the same size.

[0122] It should be noted that the self-bias structure can generate a current that is independent of the power supply voltage and only related to the temperature, and the current increases with the increase of the current temperature.

[0123] The twentieth PMOS transistor and the twenty-first PMOS transistor form a cascode current mirror; the source of the twentieth PMOS transistor is connected to the power supply voltage port.

[0124] The drain of the fifth NMOS tube is connected to the gates of the eighteenth PMOS tube, the sixteenth PMOS tube, and the nineteenth PMOS tube. The gate of the fifth NMOS tube and one end of the eighth resistor are connected to the drain of the seventh NMOS tube. The source of the fifth NMOS tube is grounded.

[0125] The source of the nineteenth PMOS tube and the other end of the eighth resistor are connected to the power supply voltage port.

[0126] The gate of the seventh NMOS tube is connected to the gate and drain of the sixth NMOS tube; the source of the seventh NMOS tube and the source of the sixth NMOS tube are grounded.

[0127] The base of the ninth transistor is connected to the collector of the tenth transistor, and the collector of the ninth transistor is connected to the base of the tenth transistor; the emitter of the tenth transistor is connected to one end of the seventh resistor; the other end of the seventh resistor and the emitter of the ninth transistor are grounded.

[0128] It should be noted that the base of the ninth transistor is connected to the collector of the tenth transistor, and the collector of the ninth transistor is connected to the base of the tenth transistor; the emitter of the tenth transistor is connected to one end of the seventh resistor; this cross-coupling method can reduce the precision error caused by process mismatch, and the use of two transistors in series can also reduce the impact of process mismatch.

[0129] It should be noted that the positive temperature coefficient current can be calculated by the temperature detection module, wherein the calculation process of the positive temperature coefficient current is:

[0130] Among them, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are used to detect temperature, and the emitter area ratio of the seventh transistor and the eighth transistor is n:1; the fifteenth PMOS transistor, the sixteenth PMOS transistor, the seventeenth PMOS transistor, the eighteenth PMOS transistor, the seventh transistor and the eighth transistor form a self-bias structure. The positive temperature coefficient current generated by the self-bias structure is copied by the cascode structure composed of the twentieth PMOS transistor and the twenty-first PMOS transistor, and is supplied to the current comparison module. The specific expression of the positive temperature coefficient current is shown in formula (13).

[0131]

[0132] In formula (13), IPTAT is the positive temperature coefficient current, and R7 is the seventh resistor.

[0133] Optionally, when there is a process mismatch, when the collector currents of the seventh transistor and the eighth transistor are not equal, the current magnitude can be expressed as I c1 and I c2 , then the derivation process of the positive temperature coefficient current is shown in formula (14).

[0134]

[0135] In formula (14), V BE7 is the base-emitter voltage of the seventh transistor, V BE8 is the base-emitter voltage of the eighth transistor, V BE9 is the base-emitter voltage of the ninth transistor, V BE10 is the base-emitter voltage of the thirteenth transistor.

[0136] It should be noted that the use of a transistor cross-coupling structure can also reduce the impact of process mismatch and improve detection accuracy.

[0137] It should be emphasized that the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the nineteenth PMOS transistor and the eighth resistor constitute the startup circuit of the temperature detection module. Since the self-bias structure has more than one working state, the working process of the startup circuit is as follows: the nineteenth PMOS transistor detects whether there is current in the circuit passing through the common-source common-gate current mirror structure composed of the sixth NMOS transistor and the seventh NMOS transistor, generating a voltage drop on the eighth resistor. When the circuit is not started normally, there is no current in the circuit, the seventh NMOS transistor is turned off, and the fifth NMOS transistor is turned on, reducing the gate voltage of the PMOS transistor, thereby starting the circuit. Once the circuit is started, there is zero current in the circuit, causing the seventh NMOS transistor to turn on, the gate voltage of the fifth NMOS transistor to be pulled down, and the fifth NMOS transistor to be turned off, thereby closing the startup circuit.

[0138] To sum up, the current comparison module compares the received positive temperature coefficient current and the reference current to obtain a comparison result, and adjusts the output voltage VOUT of the over-temperature protection circuit according to the comparison result. Compared with the existing technology, it is not necessary to perform temperature detection through the base-emitter voltage of the transistor. Therefore, the over-temperature protection circuit does not have the inherent disadvantages of temperature detection (that is, the detection accuracy will be affected by the manufacturing process deviation), thereby improving the detection accuracy of the over-temperature protection circuit.

[0139] Optional, combined Figure 1 , see Figure 4 , is a schematic diagram of the architecture of a current comparison module provided in an embodiment of the present application, wherein the current comparison module includes an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a twenty-fifth PMOS transistor, a twenty-sixth PMOS transistor, and a twenty-seventh PMOS transistor.

[0140] The twenty-second PMOS transistor, the twenty-third PMOS transistor, the twenty-fourth PMOS transistor and the twenty-fifth PMOS transistor form a cascode current mirror; the source of the twenty-second PMOS transistor and the source of the twenty-third PMOS transistor are connected to the power supply voltage port.

[0141] The cascode current mirror formed by the twenty-second PMOS transistor, the twenty-third PMOS transistor, the twenty-fourth PMOS transistor, and the twenty-fifth PMOS transistor serves as a load of the current comparison module to improve amplification capability. The width-to-length ratios of the twenty-second PMOS transistor, the twenty-third PMOS transistor, the twenty-fourth PMOS transistor, and the twenty-fifth PMOS transistor are as follows: the twenty-second PMOS transistor: the twenty-third PMOS transistor = 1:1, and the twenty-fourth PMOS transistor: the twenty-fifth PMOS transistor = 1:1.

[0142] The fourteenth NMOS transistor, the twenty-sixth PMOS transistor, the fifteenth NMOS transistor, and the twenty-seventh PMOS transistor form a bipolar inverter structure; the source of the twenty-sixth PMOS transistor and the source of the twenty-seventh PMOS transistor are connected to the power supply voltage port; the drain of the twenty-seventh PMOS transistor and the drain of the fifteenth NMOS transistor are connected to the output voltage VOUT.

[0143] It should be noted that the fourteenth NMOS transistor, the twenty-sixth PMOS transistor, the fifteenth NMOS transistor, and the twenty-seventh PMOS transistor form a bipolar inverter structure for performing signal shaping and improving signal driving capability.

[0144] The drain of the eighth NMOS tube is connected to the drain and gate of the twenty-fourth PMOS tube, the gate of the eighth NMOS tube is connected to the drain of the ninth NMOS tube; and the source of the eighth NMOS tube is grounded.

[0145] The width-to-length ratio of the eighth NMOS transistor and the ninth NMOS transistor is B:1.

[0146] It should be noted that the width-to-length ratio of the eighth NMOS transistor and the ninth NMOS transistor is B:1, so that the current comparison module has a certain current amplification capability, thereby improving the comparison accuracy.

[0147] The gate of the ninth NMOS tube is connected to the gate of the tenth NMOS tube, the gate and drain of the ninth NMOS tube are connected to the drain of the eleventh NMOS tube; and the source of the ninth NMOS tube is grounded.

[0148] It should be noted that the width-to-length ratio of the tenth NMOS tube and the tenth NMOS tube is greater than the width-to-length ratio of the ninth NMOS tube and the twelfth NMOS tube, and the ratio is K. Positive feedback can be introduced inside the current comparison module. Compared with traditional external loop feedback, at least two gate delays can be saved, thereby improving the comparison speed. This structure can also produce a hysteresis characteristic for over-temperature protection to prevent oscillation.

[0149] The drain of the tenth NMOS tube is connected to the drain of the twelfth NMOS tube, and the source of the tenth NMOS tube is grounded.

[0150] The gate of the eleventh NMOS transistor is connected to the gate and drain of the twelfth NMOS transistor, and the source of the eleventh NMOS transistor is grounded.

[0151] The drain of the twelfth NMOS tube is connected to the gate of the thirteenth NMOS tube, and the source of the twelfth NMOS tube is grounded.

[0152] The drain of the thirteenth NMOS tube and the drain of the twenty-fifth PMOS tube are connected to the gate of the fourteenth NMOS tube and the gate of the twenty-sixth NMOS tube, and the source of the thirteenth NMOS tube is grounded.

[0153] The width-to-length ratios of the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, and the thirteenth NMOS transistor are B:1:K:K:1:B.

[0154] It should be noted that the process of the current comparison module comparing the reference current with the positive temperature system current is as follows: when the temperature is in a low temperature state, the positive temperature coefficient current is less than the reference current. At this time, the reference current flows entirely through the ninth NMOS tube, and the current is multiplied by the common source and common gate current structure formed by the ninth NMOS tube and the tenth NMOS tube. The width-to-length ratio of the tenth NMOS tube is K times that of the ninth NMOS tube. Therefore, theoretically, the current that can flow through the tenth NMOS tube is K·IREF, which is much larger than the IPTAT at this time. Therefore, IREF will all flow through the tenth NMOS tube, and almost no current will flow through the twelfth NMOS tube. Similarly, the width-to-length ratio of the eleventh NMOS tube is K times that of the twelfth NMOS tube. Therefore, the current in the eleventh NMOS tube is K·I MN12 , but it can be ignored at this time, and IREF flows entirely through the ninth NMOS tube. And because the voltage of the gate node of the thirteenth NMOS tube is affected by IPTAT and I MN10 Therefore, the gate voltage of the thirteenth NMOS tube is kept at a low level, and the thirteenth NMOS tube is turned off; the gate voltage of the eighth NMOS tube is controlled by IREF and I MN11 Regulation, since IREF is much larger than I MN11 , so the gate voltage of the eighth NMOS tube is high voltage, the eighth NMOS tube is turned on, and the eighth NMOS tube and the ninth NMOS tube also form a common source and common gate current mirror structure. The current flowing through the eighth NMOS tube is K·I MN9 The current is copied through the cascode current mirror formed by the 22nd PMOS tube, the 23rd PMOS tube, the 24th PMOS tube and the 25th PMOS tube, and compared with the current in the 13th NMOS tube, I MN8 Much greater than I MN13 , so that the gate voltage of the inverter composed of the fourteenth NMOS tube and the sixteenth PMOS tube is high level, and after passing through the two-pole inverter, VOUT maintains a high level.

[0155] As the temperature continues to rise, the IPTAT current continues to increase. When the IPTAT current just exceeds K·IREF, the current flowing through the twelfth NMOS tube increases, and the thirteenth NMOS tube is turned on. The current flowing through the thirteenth NMOS tube is B·I MN12 ; At the same time I MN11 The current in is K·I MN12 , which reduces the current IREF flowing through the ninth NMOS tube, so the current in the tenth NMOS tube also reduces, IMN12 Rapidly increases, forming a positive feedback, accelerating the opening of the thirteenth NMOS tube, and the current in the eighth and ninth NMOS tubes also decreases rapidly, I MN8 After being copied by the cascode current mirror and I MN13 By comparison, the gate voltage of the inverter composed of the fourteenth NMOS tube and the sixteenth PMOS tube is regulated. When I MN8 Less than I MN13 , VOUT is quickly pulled down, and the temperature at this time is the shutdown threshold in time. Similarly, when the temperature drops from high, K·IPTAT is compared with IREF. When K·IPTAT is lower than IREF, VOUT is quickly pulled high through positive feedback. The temperature at this time is the recovery threshold of the over-temperature protection.

[0156] To sum up, the current comparison module compares the received positive temperature coefficient current and the reference current to obtain a comparison result, and adjusts the output voltage VOUT of the over-temperature protection circuit according to the comparison result. Compared with the existing technology, it is not necessary to perform temperature detection through the base-emitter voltage of the transistor. Therefore, the over-temperature protection circuit does not have the inherent disadvantages of temperature detection (that is, the detection accuracy will be affected by the manufacturing process deviation), thereby improving the detection accuracy of the over-temperature protection circuit.

[0157] Corresponding to the over-temperature protection circuit provided in the above embodiment of the present application, see Figure 5 , a flow chart of an over-temperature protection method provided in an embodiment of the present application, which is applicable to the over-temperature protection circuit mentioned in the above embodiment of the present application, includes:

[0158] S501: The current comparison module in the over-temperature protection circuit receives the reference current sent by the reference current module and the positive temperature coefficient current sent by the temperature detection module.

[0159] S502: Determine whether the positive temperature coefficient current is less than the reference current.

[0160] If the positive temperature coefficient current is less than the reference current, execute S503 ; otherwise, execute S504 .

[0161] S503: Determine that the over-temperature protection circuit is in a low-temperature state.

[0162] S504: Determine that the over-temperature protection circuit is in a high-temperature state.

[0163] After executing S504, continue to execute S505.

[0164] S505: reducing the voltage value of the output voltage VOUT to reduce the temperature of the over-temperature protection circuit.

[0165] To sum up, the current comparison module compares the received positive temperature coefficient current and the reference current to obtain a comparison result, and adjusts the output voltage VOUT of the over-temperature protection circuit according to the comparison result. Compared with the existing technology, it is not necessary to perform temperature detection through the base-emitter voltage of the transistor. Therefore, the over-temperature protection circuit does not have the inherent disadvantages of temperature detection (that is, the detection accuracy will be affected by the manufacturing process deviation), thereby improving the detection accuracy of the over-temperature protection circuit.

[0166] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0167] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An over-temperature protection circuit, characterized in that: include: Reference current module, temperature detection module, current comparison module; The output end of the reference current module is connected to the input end of the current comparison module; The output end of the temperature detection module is connected to the other input end of the current comparison module; The current comparison module, when receiving the reference current sent by the reference current module and the positive temperature coefficient current sent by the temperature detection module, compares the reference current with the positive temperature coefficient current to obtain a comparison result; and adjusts the output voltage VOUT according to the comparison result; The temperature detection module includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a seventh triode, an eighth triode, a ninth triode, a tenth triode, a seventh resistor, an eighth resistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, a twentieth PMOS transistor, and a twenty-first PMOS transistor; The fifteenth PMOS transistor, the sixteenth PMOS transistor, the seventeenth PMOS transistor, the eighteenth PMOS transistor, the seventh transistor, and the eighth transistor form a self-biased structure; the source of the fifteenth PMOS transistor and the source of the sixteenth PMOS transistor are connected to a power supply voltage port; The 20th PMOS transistor and the 21st PMOS transistor form a cascode current mirror; the source of the 20th PMOS transistor is connected to the power supply voltage port; The drain of the fifth NMOS transistor is connected to the gate of the eighteenth PMOS transistor, the gate of the sixteenth PMOS transistor, and the gate of the nineteenth PMOS transistor; the gate of the fifth NMOS transistor and one end of the eighth resistor are connected to the drain of the seventh NMOS transistor; the source of the fifth NMOS transistor is grounded; The source of the nineteenth PMOS tube and the other end of the eighth resistor are connected to a power supply voltage port; The gate of the seventh NMOS transistor is connected to the gate and drain of the sixth NMOS transistor; the source of the seventh NMOS transistor and the source of the sixth NMOS transistor are grounded; The base of the ninth transistor is connected to the collector of the tenth transistor, and the collector of the ninth transistor is connected to the base of the tenth transistor; the emitter of the tenth transistor is connected to one end of the seventh resistor; the other end of the seventh resistor and the emitter of the ninth transistor are grounded.

2. The over-temperature protection circuit according to claim 1, characterized in that: The reference current module includes a startup circuit, a first circuit, and a second circuit; The output end of the startup circuit is connected to the input end of the first circuit; The output end of the first circuit is connected to the input end of the second circuit.

3. The over-temperature protection circuit according to claim 2, characterized in that: The startup circuit includes a third NMOS transistor, a fourth NMOS transistor, and a sixth resistor; The drain of the third NMOS tube and one end of the sixth resistor are connected to the gate of the fourth NMOS tube; the source of the third NMOS tube and the source of the fourth NMOS tube are grounded; and the other end of the sixth resistor is connected to the power supply voltage port.

4. The over-temperature protection circuit according to claim 2, characterized in that: The first circuit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the first NMOS transistor and the second NMOS transistor form a self-bias structure; The fifth PMOS transistor and the seventh PMOS transistor form a cascode current mirror; The sixth PMOS transistor and the eighth PMOS transistor form a cascode current mirror; The ninth PMOS transistor and the eleventh PMOS transistor form a cascode current mirror; The tenth PMOS transistor and the twelfth PMOS transistor form a cascode current mirror; The thirteenth PMOS transistor and the fourteenth PMOS transistor form a cascode current mirror; The source of the fifth PMOS tube, the source of the sixth PMOS tube, the source of the first PMOS tube, the source of the second PMOS tube, the source of the ninth PMOS tube, the source of the tenth PMOS tube, and the source of the thirteenth PMOS tube are connected to the power supply voltage port.

5. The over-temperature protection circuit according to claim 2, characterized in that: The second circuit includes a first triode, a second triode, a third triode, a fourth triode, a fifth triode, a sixth triode, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; The emitter of the first transistor is connected to one end of the fourth resistor, the base of the first transistor and the base of the second transistor are connected to the emitter of the third transistor, and the emitter of the second transistor and the other end of the fourth resistor are connected to one end of the second resistor; The emitter of the fifth transistor is connected to one end of the fifth resistor, the base of the fifth transistor and the base of the fourth transistor are connected to the emitter of the sixth transistor, the emitter of the fourth transistor is connected to one end of the first resistor, and the other end of the first resistor and one end of the third resistor are connected to the other end of the fifth resistor; The collector of the first transistor, the collector and base of the third transistor, the collector of the second transistor, the other end of the second resistor, the other end of the third resistor, the collector of the fourth transistor, the collector and base of the sixth transistor, and the collector of the fifth transistor are grounded.

6. The over-temperature protection circuit according to claim 1, characterized in that: The current comparison module includes: an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a twenty-fifth PMOS transistor, a twenty-sixth PMOS transistor, and a twenty-seventh PMOS transistor; The twenty-second PMOS transistor, the twenty-third PMOS transistor, the twenty-fourth PMOS transistor, and the twenty-fifth PMOS transistor form a cascode current mirror; the source of the twenty-second PMOS transistor and the source of the twenty-third PMOS transistor are connected to the power supply voltage port; The fourteenth NMOS transistor, the twenty-sixth PMOS transistor, the fifteenth NMOS transistor, and the twenty-seventh PMOS transistor form a bipolar inverter structure; the source of the twenty-sixth PMOS transistor and the source of the twenty-seventh PMOS transistor are connected to the power supply voltage port; the drain of the twenty-seventh PMOS transistor and the drain of the fifteenth NMOS transistor are connected to the output voltage VOUT; The drain of the eighth NMOS transistor and the drain of the twenty-fourth PMOS transistor are connected via a gate, and the gate of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor; the source of the eighth NMOS transistor is grounded; The gate of the ninth NMOS transistor is connected to the gate of the tenth NMOS transistor, and the gate and drain of the ninth NMOS transistor are connected to the drain of the eleventh NMOS transistor; the source of the ninth NMOS transistor is grounded; The drain of the tenth NMOS tube is connected to the drain of the twelfth NMOS tube, and the source of the tenth NMOS tube is grounded; The gate of the eleventh NMOS transistor is connected to the gate and drain of the twelfth NMOS transistor, and the source of the eleventh NMOS transistor is grounded; The drain of the twelfth NMOS tube is connected to the gate of the thirteenth NMOS tube, and the source of the twelfth NMOS tube is grounded; The drain of the thirteenth NMOS tube and the drain of the twenty-fifth PMOS tube are connected to the gate of the fourteenth NMOS tube and the gate of the twenty-sixth PMOS tube, and the source of the thirteenth NMOS tube is grounded.

7. The over-temperature protection circuit according to claim 1, characterized in that: The current comparison module that compares the reference current with the positive temperature coefficient current to obtain a comparison result is specifically used to: Determining whether the positive temperature coefficient current is less than the reference current; If the positive temperature coefficient current is less than the reference current, determining that the over-temperature protection circuit is in a low-temperature state; If the positive temperature coefficient current is not less than the reference current, it is determined that the over-temperature protection circuit is in a high temperature state.

8. The over-temperature protection circuit according to claim 1, characterized in that: The current comparison module for adjusting the output voltage VOUT according to the comparison result is specifically configured to: When the comparison result indicates that the over-temperature protection circuit is in a high-temperature state, the voltage value of the output voltage VOUT is reduced to reduce the temperature of the over-temperature protection circuit.

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