An input bias current cancellation circuit

Abstract

The present application discloses an input bias current cancellation circuit, comprising: a main input module, which includes an operational amplifier based on main input transistors Q1 and Q2; an input common-mode following module realizes the input common-mode following of the main input module based on Q3 and Q4 respectively connected to the positive and negative inputs of the operational amplifier, and a common-mode acquisition transistor Q5, so that the working state of Q5 is the same as that of the main input transistors Q1 and Q2; an adjustment module adjusts the collector current of Q5; a feedback module collects the base current Ib1 of Q5 to a current mirror module; the current mirror module mirrors and outputs Ib1 to the positive and negative inputs of the operational amplifier according to a ratio k, canceling the input bias current of the main input module. The present invention can cancel the new input bias current generated due to the change of the input common mode.

Description

Technical Field

[0001] The present invention belongs to the technical field of base current elimination of transistors and relates to an input bias current elimination circuit. Background Art

[0002] A bipolar transistor is a current amplification device, and the ratio of the collector current to the base current is the current amplification factor β of the bipolar transistor. Since the current amplification factor β of an actual transistor is limited, generally about 100 times, an input current inevitably exists in the bipolar transistor. Generally, it is desirable to minimize the input current provided by an external node to the base of the bipolar transistor. Accordingly, related base current elimination circuits have emerged.

[0003] The working principle of the base current elimination circuit of a bipolar transistor is to connect an appropriate current source to the base of the bipolar transistor to eliminate or reduce the current flowing into the base of the bipolar transistor from an external node.

[0004] Figure 1 The existing solution is that two fixed current sources I1 and I2 are respectively connected to the negative and positive inputs IN- and IN+ of an operational amplifier. Among them, since the current source I1 is generated by a fixed bias, it does not change with the state change of the transistor Q1. For example, when the input common-mode voltages of the two input transistors Q1 and Q2 change, the current amplification factors β of these two transistors will change slightly, which means that with I1 remaining unchanged, the base currents flowing into Q1 and Q2 will change, while the base current Ib1 of the transistor Q1 remains unchanged, thus generating a new uneliminated base current.

[0005] In addition, in practical applications, the output impedance of I1 is not infinite, which means that I1 will change with the change of the input common-mode voltages of Q1 and Q2, causing the emitter currents of Q1 and Q2 to change. Even if the current amplification factor β of the transistor does not change at this time, the base currents Ib of these two transistors will also change. With Ib1 remaining unchanged, new uneliminated currents will still be generated. Summary of the Invention

[0006] To solve the deficiencies in the prior art, the present application provides an input bias current elimination circuit.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] An input bias current elimination circuit includes a main input module, an input common-mode following module, a feedback module, a current mirror module, and an adjustment module;

[0009] The main input module includes an operational amplifier based on the main input transistors bipolar transistors Q1 and Q2;

[0010] The input common-mode following module is used to achieve the input common-mode following of the main input module based on bipolar transistors Q3 and Q4 respectively connected to the positive and negative inputs of the operational amplifier, and a common-mode acquisition bipolar transistor Q5, so that the working state of Q5 is the same as that of the main input transistors Q1 and Q2;

[0011] The adjustment module is used to adjust the collector current of Q5;

[0012] The feedback module is used to collect the base current Ib1 of Q5 to the current mirror module;

[0013] The current mirror module is used to mirror and output Ib1 to the positive and negative inputs of the operational amplifier according to the ratio k to eliminate the input bias current of the main input module.

[0014] The present invention further includes the following preferred solutions:

[0015] Preferably, the main input module includes main input transistors bipolar transistors Q1 and Q2 and their corresponding cascode devices Mn1 and Mn2, and a current source I1;

[0016] The drains of Mn1 and Mn2 are connected to the load circuit, the gates are connected to the power supply vb, and the sources are respectively connected to the collectors of Q1 and Q2;

[0017] The bases of Q2 and Q1 are respectively the positive and negative inputs of the operational amplifier, the emitters are connected to the current source I1, and the current source I1 is grounded.

[0018] Preferably, the input common-mode following module includes bipolar transistors Q3, Q4, a common-mode acquisition bipolar transistor Q5 and their corresponding cascode devices Mn3, Mn4, Mn5, and a current source I2;

[0019] The emitters of Q3, Q4, and Q5 are connected to the current source I2, and the current source I2 is grounded;

[0020] The bases of Q3 and Q4 are respectively connected to the positive and negative inputs of the operational amplifier, and the collectors are respectively connected to the sources of Mn3 and Mn4;

[0021] The gates of Mn3 and Mn4 are connected to the power supply vb, and the drains are connected to the power supply voltage VDD;

[0022] The collector of Q5 is connected to the source of Mn5, and the base is connected to the feedback module;

[0023] The gate of Mn5 is connected to the power supply vb, and the drain is connected to the feedback module and the adjustment module.

[0024] Preferably, the adjustment module includes bipolar transistors Q6 and Q7, NMOS transistor Mn7, PMOS transistors Mp1 and Mp0, and current source I3;

[0025] The drain of Mp1 is connected to the drain of Mn5, the source is connected to the power supply voltage VDD, and the gate is connected to the gate and drain of Mp0;

[0026] The source of Mp0 is connected to the power supply voltage VDD, and the drain is connected to the drain of Mn7;

[0027] The gate of Mn7 is connected to the power supply vb, and the source is connected to the collectors of Q6 and Q7;

[0028] The emitters of Q6 and Q7 are connected to the current source I3, and the current source I3 is grounded;

[0029] The bases of Q6 and Q7 are respectively connected to the positive and negative inputs of the operational amplifier.

[0030] The adjustment module provides a bias for Mp1, so that the collector current of Q5 is equal to 0.5*I3 - Ib(Q6).

[0031] Preferably, the feedback module includes an NMOS transistor Mn6, whose source is connected to the base of Q5, the gate is connected to the drain of Mn5, and the drain is connected to the current mirror module.

[0032] Preferably, the current mirror module includes PMOS transistors Mp2, Mp3, and Mp4;

[0033] The sources of Mp2, Mp3, and Mp4 are connected to the power supply voltage VDD, the gates are connected to the drain of Mn6, and the drains are respectively connected to the drain of Mn6, the positive and negative inputs of the operational amplifier.

[0034] Preferably, by configuring the mirror ratio k, the input bias current Ib0 of Q1 and Q2 = the base current Ib1 of Q5, realizing the complete elimination of the input bias current.

[0035] Preferably, the current amplification factors of Q1, Q2, and Q5 are the same, all being β.

[0036] Preferably, the input bias current Ib0 of Q1 and Q2 = I1 / (2*(β + 1)), the adjustment module makes the collector current of Q5 equal to 0.5*I3 - Ib(Q6), the base current Ib1 of Q5 = I3 / 2*(β + 1), set I2 = 1.5*I3, then Ib(Q3) = Ib(Q4) = Ib(Q5) = Ib(Q6) = Ib(Q7), then configure the mirror ratio k of Mp2 and Mp3 and Mp2 and Mp4 = 2 + (I1 / (I3)), so that Ib0 + Ib(Q3) + Ib(Q5)

[0037] = k * Ib1, achieving complete elimination of the input bias current.

[0038] Advantages achieved by this application:

[0039] In the present invention, the input bias currents of the main input transistors Q1 and Q2 are Ib0 = I1 / (2 * (β + 1)). The expression of Ib0 contains both β and I1, meaning that Ib1 can vary with I1 and β, and can eliminate the new input bias current generated due to the change in the input common mode. Further, in the input common mode following module of the present invention, the base current of Q5 is Ib1 = I3 / (2 * (β + 1)). Then, the mirror ratios k of Mp2 and Mp3 and Mp2 and Mp4 are configured as k = 2 + (I1 / (I3)), such that Ib0 + Ib(Q3) + Ib(Q5) = k * Ib1, achieving complete elimination of the input bias current. Description of the Drawings

[0040] Figure 1 is the base current elimination circuit of the bipolar transistor corresponding to the existing solution;

[0041] Figure 2 is a circuit diagram for eliminating the input bias current of the present invention. Detailed Embodiments

[0042] The following further describes the present application with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and should not be used to limit the protection scope of this application.

[0043] As Figure 2 shown, the present invention improves the Figure 1 solution, mainly adding a Figure 2 base current elimination circuit on the right side. Compared with the old solution, a pair of transistors Q3 and Q4 connected to the positive and negative inputs respectively, and a common mode acquisition transistor Q5 are added. The two current sources I1 and I2 in Figure 2 are generated by one bias. That is, according to the ratio of the change in the input common mode voltage causing the change in the currents I1 and I2 in the circuit shown as Figure 2 shown, which is the ratio of these two currents. That is, ΔI1 / ΔI2 = I1 / I2.

[0044] Specifically, an input bias current elimination circuit of the present invention includes a main input module, an input common mode following module, a feedback module, a current mirror module, and an adjustment module;

[0045] The main input module includes an operational amplifier based on the main input transistors, bipolar transistors Q1 and Q2;

[0046] The main input module includes bipolar transistors Q1 and Q2 of the main input tube, their corresponding cascode devices Mn1 and Mn2, and a current source I1;

[0047] The drains of Mn1 and Mn2 are connected to the load circuit, the gates are connected to the power supply vb, and the sources are respectively connected to the collectors of Q1 and Q2;

[0048] The bases of Q2 and Q1 are respectively the positive and negative inputs of the operational amplifier, and the emitters are connected to the current source I1, and the current source I1 is grounded.

[0049] The input common-mode following module is used to achieve the input common-mode following of the main input module based on bipolar transistors Q3 and Q4 respectively connected to the positive and negative inputs of the operational amplifier, and a common-mode acquisition bipolar transistor Q5, so that the working state of Q5 is the same as that of the main input tubes Q1 and Q2. That is, when the input common mode changes, the slight change Δβ in the current amplification factor β of Q1 and Q2 will also be reflected in Q5, that is, Q5 will generate the same size of Δβ.

[0050] The input common-mode following module includes bipolar transistors Q3 and Q4, a common-mode acquisition bipolar transistor Q5, and their corresponding cascode devices Mn3, Mn4, Mn5, and a current source I2;

[0051] The emitters of Q3, Q4, and Q5 are connected to the current source I2, and the current source I2 is grounded;

[0052] The bases of Q3 and Q4 are respectively connected to the positive and negative inputs of the operational amplifier, and the collectors are respectively connected to the sources of Mn3 and Mn4;

[0053] The gates of Mn3 and Mn4 are connected to the power supply vb, and the drains are connected to the power supply voltage VDD;

[0054] The collector of Q5 is connected to the source of Mn5, and the base is connected to the feedback module;

[0055] The gate of Mn5 is connected to the power supply vb, and the drain is connected to the feedback module and the adjustment module.

[0056] The adjustment module includes bipolar transistors Q6 and Q7, an NMOS transistor Mn7, PMOS transistors Mp1 and Mp0, and a current source I3;

[0057] The drain of Mp1 is connected to the drain of Mn5, the source is connected to the power supply voltage VDD, and the gate is connected to the gates and drains of Mp0;

[0058] The source of Mp0 is connected to the power supply voltage VDD, and the drain is connected to the drain of Mn7;

[0059] The gate of Mn7 is connected to the power supply vb, and the source is connected to the collectors of Q6 and Q7;

[0060] The emitters of Q6 and Q7 are connected to the current source I3, and the current source I3 is grounded;

[0061] The bases of Q6 and Q7 are respectively connected to the positive and negative inputs of the operational amplifier.

[0062] The adjustment module provides a bias for Mp1, so that the collector current of Q5 is equal to 0.5*I3 - Ib(Q6).

[0063] The feedback module is used to collect the base current Ib1 of Q5 to the current mirror module;

[0064] The feedback module includes an NMOS transistor Mn6, whose source is connected to the base of Q5, the gate is connected to the drain of Mn5, and the drain is connected to the current mirror module.

[0065] The current mirror module is used to mirror and output Ib1 to the positive and negative inputs of the operational amplifier according to the ratio k, so as to eliminate the input bias current of the main input module.

[0066] The current mirror module includes PMOS transistors Mp2, Mp3, and Mp4;

[0067] The sources of Mp2, Mp3, and Mp4 are connected to the power supply voltage VDD, the gates are connected to the drain of Mn6, and the drains are respectively connected to the drain of Mn6, the positive and negative inputs of the operational amplifier.

[0068] In specific implementation, by configuring the mirror ratio k, the input bias current Ib0 of Q1 and Q2 is made equal to the base current Ib1 of Q5, so as to completely eliminate the input bias current.

[0069] The current amplification factors of Q1, Q2, and Q5 are the same, all being β.

[0070] According to Figure 2 , the input bias current Ib0 of Q1 and Q2 is I1 / (2*(β + 1)), the adjustment module makes the collector current of Q5 equal to 0.5*I3 - Ib(Q6), the base current Ib1 of Q5 is I3 / 2*(β + 1). In addition, since Q3, Q4, Q6, and Q7 are also connected to the positive and negative inputs, the base currents of these four devices also need to be eliminated. Set I2 = 1.5*I3, then Ib(Q3) = Ib(Q4) = Ib(Q5) = Ib(Q6) = Ib(Q7), and configure the mirror ratio k of Mp2 and Mp3 and Mp2 and Mp4 to be 2+(I1 / (I3)), so that Ib0 + Ib(Q3) + Ib(Q5) = k*Ib1, thus completely eliminating the input bias current.

[0071] Figure 1 Two problems of the corresponding old solution:

[0072] 1. When the β of Q1 and Q2 changes, additional Ib will be generated.

[0073] 2. When I1 changes with the input, additional Ib will also be generated.

[0074] In the solution of the present invention, the expression of Ib0 contains both β and I1, which means that Ib1 can change with I1 and β. It can eliminate the new input bias current generated due to the change of the input common mode. That is, the problems existing in the old solution can be solved.

[0075] The applicant of the present invention has made a detailed description and explanation of the embodiments of the present invention in combination with the accompanying drawings of the specification. However, those skilled in the art should understand that the above embodiments are only the preferred implementation schemes of the present invention, and the detailed description is only to help readers better understand the spirit of the present invention, rather than a limitation on the protection scope of the present invention. On the contrary, any improvement or modification made based on the spirit of the present invention should fall within the protection scope of the present invention.

Claims

1. An input bias current cancellation circuit, comprising a main input module, an input common-mode following module, a feedback module, a current mirror module, and an adjustment module, characterized in that: The main input module includes an operational amplifier based on bipolar transistors Q1 and Q2 of the main input transistors; The input common-mode following module is used to achieve the input common-mode following of the main input module based on bipolar transistors Q3 and Q4 respectively connected to the positive and negative inputs of the operational amplifier, and a common-mode acquisition bipolar transistor Q5, so that the operating state of Q5 is the same as that of the main input transistors Q1 and Q2; The adjustment module is used to adjust the collector current of Q5; The feedback module is used to collect the base current Ib1 of Q5 to the current mirror module; The current mirror module is used to mirror and output Ib1 to the positive and negative inputs of the operational amplifier according to the ratio k to cancel the input bias current of the main input module.

2. An input bias current cancellation circuit according to claim 1, characterized in that: The main input module includes bipolar transistors Q1 and Q2 of the main input transistors and their corresponding cascode devices Mn1 and Mn2, and current source I1; The drains of Mn1 and Mn2 are connected to the load circuit, the gates are connected to the power supply vb, and the sources are respectively connected to the collectors of Q1 and Q2; The bases of Q2 and Q1 are respectively the positive and negative inputs of the operational amplifier, and the emitters are connected to the current source I1, and the current source I1 is grounded.

3. An input bias current cancellation circuit according to claim 2, characterized in that: The input common-mode following module includes bipolar transistors Q3, Q4, a common-mode acquisition bipolar transistor Q5 and their corresponding cascode devices Mn3, Mn4, Mn5, and current source I2; The emitters of Q3, Q4, and Q5 are connected to the current source I2, and the current source I2 is grounded; The bases of Q3 and Q4 are respectively connected to the positive and negative inputs of the operational amplifier, and the collectors are respectively connected to the sources of Mn3 and Mn4; The gates of Mn3 and Mn4 are connected to the power supply vb, and the drains are connected to the power supply voltage VDD; The collector of Q5 is connected to the source of Mn5, and the base is connected to the feedback module; The gate of Mn5 is connected to the power supply vb, and the drain is connected to the feedback module and the adjustment module.

4. An input bias current cancellation circuit according to claim 3, characterized in that: The adjustment module includes bipolar transistors Q6 and Q7, an NMOS transistor Mn7, PMOS transistors Mp1 and Mp0, and a current source I3; The drain of Mp1 is connected to the drain of Mn5, the source is connected to the power supply voltage VDD, and the gate is connected to the gate and drain of Mp0; The source of Mp0 is connected to the power supply voltage VDD, and the drain is connected to the drain of Mn7; The gate of Mn7 is connected to the power supply vb, and the source is connected to the collectors of Q6 and Q7; The emitter-collectors of Q6 and Q7 are connected to the current source I3, and the current source I3 is grounded; The bases of Q6 and Q7 are respectively connected to the positive and negative inputs of the operational amplifier.

5. An input bias current cancellation circuit according to claim 4, characterized in that: The adjustment module provides a bias for Mp1, such that the collector current of Q5 is equal to 0.5*I3 - Ib(Q6).

6. An input bias current cancellation circuit according to claim 4, wherein: The feedback module includes an NMOS transistor Mn6, whose source is connected to the base of Q5, gate is connected to the drain of Mn5, and drain is connected to the current mirror module.

7. An input bias current cancellation circuit according to claim 5, wherein: The current mirror module includes PMOS transistors Mp2, Mp3, and Mp4; The sources of Mp2, Mp3, and Mp4 are connected to the power supply voltage VDD, gates are connected to the drain of Mn6, and drains are respectively connected to the drain of Mn6, the positive and negative inputs of the operational amplifier.

8. An input bias current cancellation circuit according to claim 7, wherein: By configuring the mirror ratio k, the input bias current Ib0 of Q1 and Q2 is made equal to the base current Ib1 of Q5, achieving complete cancellation of the input bias current.

9. An input bias current cancellation circuit according to claim 8, wherein: The current amplification factors of Q1, Q2, and Q5 are the same, all being β.

10. An input bias current cancellation circuit according to claim 9, wherein: The input bias current Ib0 of Q1 and Q2 = I1 / (2*(β + 1)), the adjustment module makes the collector current of Q5 equal to 0.5*I3 - Ib(Q6), the base current Ib1 of Q5 = I3 / 2*(β + 1), setting I2 = 1.5*I3, then Ib(Q3) = Ib(Q4) = Ib(Q5) = Ib(Q6) = Ib(Q7), and then configuring the mirror ratio k of Mp2 and Mp3 and Mp2 and Mp4 to be 2 + (I1 / (I3)), such that Ib0 + Ib(Q3) + Ib(Q5) = k*Ib1, achieving complete cancellation of the input bias current.

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