LDO circuits and power management devices

Abstract

The present invention discloses an LDO circuit and a power management device. The circuit includes a source-end cross-coupling module, a first current mirror module, a second current mirror module, a third current mirror module and an output module; the source-end cross-coupling module is used to generate a bias current that turns on the LDO circuit, the first current mirror module is used to unidirectionally conduct the power supply voltage to the second input end of the source-end cross-coupling module, the second current mirror module is used to form a symmetrical structure with the first current mirror module, the third current mirror module is used to follow the current change of the output module caused by the change of the load current, and the output module is used to make a corresponding current change to the change of the load current, and transmit the generated current change to the third current mirror module. The present application can quickly respond to the change of the load current, so that the output voltage can be restored to stability in a short time, and it can be done without additional current, is suitable for low-power occasions, has a simple circuit structure, and has certain application value.

Description

Technical Field

[0001] The present invention relates to the field of power electronics and semiconductor technology, and in particular to an LDO circuit and a power management device. Background Art

[0002] LDO (Low Dropout Regulator) is a common power management device. It is widely used in portable and communication devices due to its low static power consumption, low cost and no output ripple.

[0003] The load transient characteristic of LDO refers to the phenomenon that the output voltage overshoots and undershoots when the load current changes suddenly. It takes time to recover from overshoot or undershoot to the stable output voltage, which is the transient response time. Since the load current of LDO will change in different application scenarios, how to respond quickly and reduce the output voltage jump caused by transient load jump has become a major research difficulty. In the current existing technology, there is no solution to this problem. Summary of the invention

[0004] In view of this, the present invention provides an LDO circuit and a power management device.

[0005] The present invention provides the following technical solutions:

[0006] In a first aspect, an LDO circuit is provided in an embodiment of the present disclosure, wherein the LDO circuit includes a source cross-coupling module, a first current mirror module, a second current mirror module, a third current mirror module and an output module;

[0007] The first control end of the source cross-coupling module is connected to the input voltage, the second control end of the source cross-coupling module is connected to the reference voltage, the first input end of the source cross-coupling module is connected to the power supply voltage, the second input end of the source cross-coupling module is connected to the first output end of the first current mirror module, the first output end of the source cross-coupling module is connected to the first input end of the second current mirror, and the second output end of the source cross-coupling module is connected to the first input end of the third current mirror;

[0008] The input end of the first current mirror module is connected to the power supply voltage, the second output end of the first current mirror module is connected to the second input end of the second current mirror module, and the output end of the second current mirror module is grounded;

[0009] The control end of the third current mirror module is connected to the first bias voltage, the second input end of the third current mirror module is connected to the first output end of the output module, and the output end of the third current mirror module is grounded;

[0010] The input end of the output module is connected to the power supply voltage, the second output end of the output module is connected to the output voltage, and the control end of the output module is connected to the second output end of the first current mirror module;

[0011] The source-end cross-coupling module is used to generate a bias current for turning on the LDO circuit, the first current mirror module is used to unidirectionally conduct the power supply voltage to the second input end of the source-end cross-coupling module, the second current mirror module is used to form a symmetrical structure with the first current mirror module, the third current mirror module is used to follow the current change of the output module caused by the change of the load current, the output module is used to make a corresponding current change to the change of the load current, and transmit the generated current change to the third current mirror module.

[0012] Furthermore, the LDO circuit further includes a fourth current mirror module;

[0013] The control end of the fourth current mirror module is connected to the second bias voltage, the input end of the fourth current mirror module is connected to the first input end of the third current mirror, the output end of the fourth current mirror module is grounded, and the fourth current mirror module is used to provide a constant bias current for the LDO circuit.

[0014] Further, the source-end cross-coupling module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor;

[0015] The control ends of the first transistor and the second transistor are both connected to the input voltage, the control ends of the third transistor and the fourth transistor are both connected to the reference voltage, the input ends of the first transistor and the fourth transistor are both connected to the power supply voltage, the input ends of the second transistor and the third transistor are both connected to the first output end of the first current mirror module, the output end of the first transistor is connected to the input end of the seventh transistor, the output end of the fourth transistor is connected to the input end of the tenth transistor, the output end of the second transistor is connected to the input end of the ninth transistor, and the output end of the third transistor is connected to the input end of the eighth transistor;

[0016] The control end of the seventh transistor is connected to the control end of the eighth transistor, the control end of the ninth transistor is connected to the control end of the tenth transistor, the output ends of the seventh transistor and the tenth transistor are connected to the first input end of the third current mirror, the output ends of the eighth transistor and the ninth transistor are connected to the first input end of the second current mirror, the control end of the seventh transistor is short-circuited with the output end, and the control end of the tenth transistor is short-circuited with the output end.

[0017] Further, the first current mirror module includes a fifth transistor, a sixth transistor and an eighteenth transistor;

[0018] The input ends of the fifth transistor, the sixth transistor and the eighteenth transistor are connected to the power supply voltage, the output end of the fifth transistor is connected to the input end of the second transistor, the output end of the sixth transistor is connected to the input end of the third transistor, the output end of the eighteenth transistor is connected to the second input end of the second current mirror module, the control end of the sixth transistor is connected to the control end of the eighteenth transistor, the control end of the fifth transistor is short-circuited with the output end, and the control end of the sixth transistor is short-circuited with the output end.

[0019] Further, the second current mirror module includes an eleventh transistor, a twelfth transistor and a seventeenth transistor;

[0020] The input end of the eleventh transistor is connected to the output end of the eighth transistor, the input end of the twelfth transistor is connected to the output end of the ninth transistor, the input end of the seventeenth transistor is connected to the output end of the eighteenth transistor, the output ends of the eleventh transistor, the twelfth transistor and the seventeenth transistor are grounded respectively, the control end of the eleventh transistor is short-circuited with the output end of the eleventh transistor, and the control end of the twelfth transistor is short-circuited with the output end of the twelfth transistor.

[0021] Further, the third current mirror module includes a fourteenth transistor, a sixteenth transistor and a nineteenth transistor;

[0022] The control ends of the fourteenth transistor, the sixteenth transistor and the nineteenth transistor are all connected to the first bias voltage, the input end of the fourteenth transistor is connected to the output end of the seventh transistor, the input end of the sixteenth transistor is connected to the output end of the tenth transistor, the input end of the nineteenth transistor is connected to the first output end of the output module, the output ends of the fourteenth transistor, the sixteenth transistor and the nineteenth transistor are grounded, and the control end of the nineteenth transistor is short-circuited with the input end.

[0023] Further, the fourth current mirror module includes a thirteenth transistor and a fifteenth transistor;

[0024] The control terminals of the thirteenth transistor and the fifteenth transistor are both connected to the second bias voltage, the input terminal of the thirteenth transistor is connected to the input terminal of the fourteenth transistor, the input terminal of the fifteenth transistor is connected to the input terminal of the sixteenth transistor, and the output terminals of the thirteenth transistor and the fifteenth transistor are grounded.

[0025] Further, the output module includes a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor and a twenty-fifth transistor;

[0026] Input terminals of the 20th transistor, the 21st transistor, the 22nd transistor and the 25th transistor are connected to the power supply voltage, the output terminal of the 20th transistor is connected to the input terminal of the 19th transistor, the output terminal of the 21st transistor is connected to the input terminal of the 23rd transistor, the output terminal of the 22nd transistor is connected to the input terminal of the 24th transistor, the output terminal of the 22nd transistor is also connected to the control terminal of the 25th transistor, the output terminals of the 23rd transistor, the 24th transistor and the 25th transistor are connected to the output voltage, the control terminal of the 20th transistor is connected to the control terminal of the 21st transistor, the 22nd transistor is connected to the third bias voltage, the control terminals of the 23rd transistor and the 24th transistor are connected to the output terminal of the 18th transistor, and the control terminal of the 21st transistor is short-circuited to the output terminal.

[0027] Furthermore, the LDO circuit also includes a compensation capacitor;

[0028] A first end of the compensation capacitor is connected to the output end of the eighteenth transistor, a second end of the compensation capacitor is grounded, and the compensation capacitor is used to absorb reactive power generated in the LDO circuit.

[0029] In a second aspect, an embodiment of the present disclosure provides a power management device, wherein the power management device includes a power supply and the LDO circuit described in the first aspect.

[0030] The embodiments of the present application have the following advantages:

[0031] The LDO circuit provided by the embodiment of the present application includes a source cross-coupling module, a first current mirror module, a second current mirror module, a third current mirror module and an output module; the first control end of the source cross-coupling module is connected to the input voltage, the second control end of the source cross-coupling module is connected to the reference voltage, the first input end of the source cross-coupling module is connected to the power supply voltage, the second input end of the source cross-coupling module is connected to the first output end of the first current mirror module, the first output end of the source cross-coupling module is connected to the first input end of the second current mirror, the second output end of the source cross-coupling module is connected to the first input end of the third current mirror, and the source cross-coupling module is used to generate a bias current that turns on the LDO circuit; the input end of the first current mirror module is connected to the power supply voltage, the second output end of the first current mirror module is connected to the second input end of the second current mirror module The first current mirror module is connected to the second input end of the source-end cross-coupling module; the output end of the second current mirror module is grounded, and the second current mirror module is used to form a symmetrical structure with the first current mirror module; the control end of the third current mirror module is connected to the first bias voltage, the second input end of the third current mirror module is connected to the first output end of the output module, the output end of the third current mirror module is grounded, and the third current mirror module is used to follow the current change of the output module caused by the change of the load current; the input end of the output module is connected to the power supply voltage, the second output end of the output module is connected to the output voltage, the control end of the output module is connected to the second output end of the first current mirror module, and the output module is used to make a corresponding current change to the change of the load current, and transmit the generated current change to the third current mirror module. The present application can quickly respond to the change of load current, so that the output voltage can be restored to stability in a short time, and it can be done without additional current, and can be applied in low-power occasions. The circuit structure is simple and has certain application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work. In each of the drawings, similar components are numbered similarly.

[0033] Figure 1 A schematic diagram of the structure of an LDO circuit provided in an embodiment of the present application is shown;

[0034] Figure 2A hardware structure diagram of a power management device provided in an embodiment of the present application is shown.

[0035] Description of main components symbols:

[0036] 10-LDO circuit; 100-source cross-coupling module; 110-first current mirror module; 120-second current mirror module; 130-third current mirror module; 140-output module; M1-first transistor; M2-second transistor; M3-third transistor; M4-fourth transistor; M5-fifth transistor; M6-sixth transistor; M7-seventh transistor; M8-eighth transistor; M9-ninth transistor; M10-tenth transistor; M11-eleventh transistor; M12-twelfth transistor Transistor; M13-the thirteenth transistor; M14-the fourteenth transistor; M15-the fifteenth transistor; M16-the sixteenth transistor; M17-the seventeenth transistor; M18-the eighteenth transistor; M19-the nineteenth transistor; M20-the twentieth transistor; M21-the twenty-first transistor; M22-the twenty-second transistor; M23-the twenty-third transistor; M24-the twenty-fourth transistor; M25-the twenty-fifth transistor; C1-compensation capacitor; 20-power management device; 21-power supply. DETAILED DESCRIPTION

[0037] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0038] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0039] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of the template are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0042] Example 1

[0043] like Figure 1 , which is a schematic diagram of the structure of an LDO circuit 10 in an embodiment of the present application. The LDO circuit in the embodiment of the present application can be applied in low-power applications, and includes a source-end cross-coupling module 100, a first current mirror module 110, a second current mirror module 120, a third current mirror module 130, and an output module 140;

[0044] The first control terminal of the source cross-coupling module 100 is connected to the input voltage, the second control terminal of the source cross-coupling module 100 is connected to the reference voltage, the first input terminal of the source cross-coupling module 100 is connected to the power supply voltage, the second input terminal of the source cross-coupling module 100 is connected to the first output terminal of the first current mirror module 110, the first output terminal of the source cross-coupling module 100 is connected to the first input terminal of the second current mirror, the second output terminal of the source cross-coupling module 100 is connected to the first input terminal of the third current mirror, and the source cross-coupling module is used to generate a bias current for turning on the LDO circuit;

[0045] The input end of the first current mirror module 110 is connected to the power supply voltage, the second output end of the first current mirror module 110 is connected to the second input end of the second current mirror module 120, and the first current mirror module is used to unidirectionally conduct the power supply voltage to the second input end of the source cross-coupling module;

[0046] The output end of the second current mirror module 120 is grounded, and the second current mirror module is used to form a symmetrical structure with the first current mirror module;

[0047] The control end of the third current mirror module 130 is connected to the first bias voltage, the second input end of the third current mirror module 130 is connected to the first output end of the output module 140, the output end of the third current mirror module 130 is grounded, and the third current mirror module is used to follow the current change of the output module caused by the change of the load current;

[0048] The input end of the output module 140 is connected to the power supply voltage, the second output end of the output module 140 is connected to the output voltage, the control end of the output module 140 is connected to the second output end of the first current mirror module 110, and the output module is used to make corresponding current changes to the changes in the load current and transmit the generated current changes to the third current mirror module.

[0049] In an optional implementation, the LDO circuit provided in the embodiment of the present application also includes a fourth current mirror module; the control end of the fourth current mirror module is connected to the second bias voltage, the input end of the fourth current mirror module is connected to the first input end of the third current mirror 130, the output end of the fourth current mirror module is grounded, and the fourth current mirror module is used to provide a constant bias current for the LDO circuit.

[0050] In the embodiment of the present application, the source-end cross-coupling module 100 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10.

[0051] Wherein, the control terminals of the first transistor M1 and the second transistor M2 are both connected to the input voltage, the control terminals of the third transistor M3 and the fourth transistor M4 are both connected to the reference voltage, the input terminals of the first transistor M1 and the fourth transistor M4 are both connected to the power supply voltage, the input terminals of the second transistor M2 and the third transistor M3 are both connected to the first output terminal of the first current mirror module 110, the output terminal of the first transistor M1 is connected to the input terminal of the seventh transistor M7, the output terminal of the fourth transistor M4 is connected to the input terminal of the tenth transistor M10, the output terminal of the second transistor M2 is connected to the input terminal of the ninth transistor M9, and the output terminal of the third transistor M3 is connected to the input terminal of the eighth transistor M8;

[0052] Further, the control end of the seventh transistor M7 is connected to the control end of the eighth transistor M8, the control end of the ninth transistor M9 is connected to the control end of the tenth transistor M10, the output ends of the seventh transistor M7 and the tenth transistor M10 are connected to the first input end of the third current mirror 130, the output ends of the eighth transistor M8 and the ninth transistor M9 are connected to the first input end of the second current mirror 120, the control end of the seventh transistor M7 is short-circuited with the output end, and the control end of the tenth transistor M10 is short-circuited with the output end.

[0053] In this embodiment, a source-end cross-coupled input is formed by M1-M4 and M7-M10, which can break through the limitation of tail current, generate bias current, and provide conduction current for transistors on each branch, so that no additional current needs to be applied in the circuit, thereby significantly improving the output slew rate.

[0054] Specifically, the fifth transistor M5, the sixth transistor M6, and the eighteenth transistor M18 constitute a first current mirror module 110, the input ends of the fifth transistor M5, the sixth transistor M6, and the eighteenth transistor M18 are connected to the power supply voltage, the output end of the fifth transistor M5 is connected to the input end of the second transistor M2, the output end of the sixth transistor M6 is connected to the input end of the third transistor M3, the output end of the eighteenth transistor M18 is connected to the second input end of the second current mirror module 120, the control end of the sixth transistor M6 is connected to the control end of the eighteenth transistor M18, the control end of the fifth transistor M5 is short-circuited with the output end, and the control end of the sixth transistor M6 is short-circuited with the output end.

[0055] In this embodiment, the first current mirror module 110 composed of the fifth transistor M5, the sixth transistor M6, and the eighteenth transistor M18 is a current mirror of the output stage, and can also be considered as a load in the form of a diode connection, which can unidirectionally conduct the power supply voltage to the input ends of the second transistor M2 and the third transistor M3.

[0056] The eleventh transistor M11, the twelfth transistor M12 and the seventeenth transistor M17 form a second current mirror module 120, the input end of the eleventh transistor M11 is connected to the output end of the eighth transistor M8, the input end of the twelfth transistor M12 is connected to the output end of the ninth transistor M9, the input end of the seventeenth transistor M17 is connected to the output end of the eighteenth transistor M18, the output ends of the eleventh transistor M11, the twelfth transistor M12 and the seventeenth transistor M17 are grounded respectively, the control end of the eleventh transistor M11 is short-circuited with the output end of the eleventh transistor M11, and the control end of the twelfth transistor M12 is short-circuited with the output end of the twelfth transistor M12.

[0057] Depend on Figure 1 It can be seen that the second current mirror module and the first current mirror module are a symmetrical circuit structure, and the functions of M11, M12, and M17 are the same as those of M5, M6, and M18.

[0058] Specifically, the fourteenth transistor M14, the sixteenth transistor M16, and the nineteenth transistor M19 form a third current mirror module 130, the control ends of the fourteenth transistor M14, the sixteenth transistor M16, and the nineteenth transistor M19 are all connected to the first bias voltage, the input end of the fourteenth transistor M14 is connected to the output end of the seventh transistor M7, the input end of the sixteenth transistor M16 is connected to the output end of the tenth transistor M10, the input end of the nineteenth transistor M19 is connected to the first output end of the output module 140, the output ends of the fourteenth transistor M14, the sixteenth transistor M16, and the nineteenth transistor M19 are grounded, and the control end of the nineteenth transistor M19 is short-circuited with the input end.

[0059] In this embodiment, the function of the third current mirror module 130 is mainly to change the current of the bias circuit where the fourteenth transistor M14 and the sixteenth transistor M16 are located by following the branch where the nineteenth transistor M19 is located, that is, the current change of the output module, so that the current of the bias circuit where the fourteenth transistor M14 and the sixteenth transistor M16 are located changes, that is, the tail current of the operational amplifier changes.

[0060] It should be noted that the control ends of the fourteenth transistor M14, the sixteenth transistor M16 and the nineteenth transistor M19 are connected to the first bias voltage VBN through the first bias voltage, so that the fourteenth transistor M14, the sixteenth transistor M16 and the nineteenth transistor M19 operate in the saturation range.

[0061] The thirteenth transistor M13 and the fifteenth transistor M15 form a fourth current mirror module, the control ends of the thirteenth transistor M13 and the fifteenth transistor M15 are both connected to the second bias voltage, the input end of the thirteenth transistor M13 is connected to the input end of the fourteenth transistor M14, the input end of the fifteenth transistor M15 is connected to the input end of the sixteenth transistor M16, and the output ends of the thirteenth transistor M13 and the fifteenth transistor M15 are grounded.

[0062] It can be understood that the control terminal of the fourth current mirror module is connected to the second bias voltage V BIAS connection to provide a constant bias current to the entire circuit.

[0063] Further, the twentieth transistor M20 , the twenty-first transistor M21 , the twenty-second transistor M22 , the twenty-third transistor M23 , the twenty-fourth transistor M24 , and the twenty-fifth transistor M25 constitute the output module 140 . Input terminals of the 20th transistor M20, the 21st transistor M21, the 22nd transistor M22 and the 25th transistor M25 are connected to the power supply voltage, the output terminal of the 20th transistor M20 is connected to the input terminal of the 19th transistor M19, the output terminal of the 21st transistor M21 is connected to the input terminal of the 23rd transistor M23, the output terminal of the 22nd transistor M22 is connected to the input terminal of the 24th transistor M24, the output terminal of the 22nd transistor M22 is also connected to the control terminal of the 25th transistor M25, the output terminals of the 23rd transistor M23, the 24th transistor M24 and the 25th transistor M25 are connected to the output voltage, the control terminal of the 20th transistor M20 is connected to the control terminal of the 21st transistor M21, the 22nd transistor M22 is connected to the third bias voltage, the control terminals of the 23rd transistor M23 and the 24th transistor M24 are connected to the output terminal of the 18th transistor M18, and the control terminal of the 21st transistor M21 is short-circuited with the output terminal.

[0064] In the present application, the output module 140 can make a current change corresponding to the change of the load current, and transmit the generated current change to the third current mirror module 130, thereby generating the subsequent current mirror chain reaction.

[0065] It should be noted that the third bias voltage VBP is connected to the 22nd transistor M22 to provide a bias voltage for the 22nd transistor M22 branch, so that the 22nd transistor M22 operates in a saturation range. The output voltage VOUT is connected to the input voltage VIN to form a buffer area.

[0066] The principle of the LDO circuit provided in this embodiment is as follows:

[0067] When the load iload current suddenly increases, the current on the 24th transistor M24, the 23rd transistor M23, and the 25th transistor M25 increases. Since the 23rd transistor M23 is connected to the 21st transistor M21, the current on the 21st transistor M21 will also increase. Since the 20th transistor M20 mirrors the current of the 21st transistor M21, and the 19th transistor M19 is connected to the 20th transistor M20, the current on the 19th transistor M19 will also increase. Since the 14th transistor M14 and the 16th transistor M16 in the third current mirror module 130 follow the current change of the branch where the 19th transistor M19 is located, the current on the 14th transistor M14 and the 16th transistor M16 will also increase. Since the current on the 14th transistor M14 increases, the 7th transistor M7 is connected to the 14th transistor M14, so the current on the 7th transistor M7 will also increase, and then the current on the 8th transistor M8 connected thereto increases. Because the third transistor M3 is connected to the eighth transistor M8, the current on the third transistor M3 will also increase, and the current on the sixth transistor M6 connected thereto will also increase. Because the eighteenth transistor M18 and the sixth transistor M6 form a current mirror, the current on the eighteenth transistor M18 branch will also increase, and point A will be charged at this time, so that the voltage at point A is raised. The control ends of the twenty-third transistor M23 and the twenty-fourth transistor M24 are connected to point A in a source follower form, so that the output voltage VOUT will also be rapidly raised. While the output voltage VOUT is raised, the twenty-third transistor M23 passes a larger current. Due to the chain reaction generated by the current mirror module, the current will quickly increase the current on the eighteenth transistor M18 branch, accelerating the rise of the voltage at point A until the output voltage returns to stability.

[0068] Therefore, the circuit of the present application can accelerate the time required for the output undershoot to recover to a stable state due to a sudden increase in current, that is, improve the speed of transient response.

[0069] Similarly, when the load current iload decreases, the current on the 24th transistor M24, the 23rd transistor M23, and the 25th transistor M25 decreases, because the 23rd transistor M23 is connected to the 21st transistor M21, so the current on the 21st transistor M21 will also decrease. Also, because the 20th transistor M20 mirrors the current of the 21st transistor M21, and the 19th transistor M19 is connected to the 20th transistor M20, the current on the 19th transistor M19 will also decrease. Also, because the 14th transistor M14 and the 16th transistor M16 in the third current mirror module 130 follow the current change of the branch where the 19th transistor M19 is located, the current on the 14th transistor M14 and the 16th transistor M16 will also decrease. Since the current on the 14th transistor M14 decreases, the 7th transistor M7 is connected to the 14th transistor M14, so the current on the 7th transistor M7 will also decrease, and then the current on the 8th transistor M8 connected thereto will decrease. Because the third transistor M3 is connected to the eighth transistor M8, the current on the third transistor M3 will also decrease, and the current on the sixth transistor M6 connected thereto will also decrease. Because the eighteenth transistor M18 and the sixth transistor M6 form a current mirror, the current on the branch of the eighteenth transistor M18 will also decrease, and the point A will be discharged at this time, causing the voltage at point A to drop. The control ends of the twenty-third transistor M23 and the twenty-fourth transistor M24 are connected to point A in a source follower form, so that the output voltage VOUT will also drop rapidly. When the output voltage VOUT drops, the twenty-third transistor M23 passes a smaller current, which will quickly reduce the current of the eighteenth transistor M18, accelerate the discharge of point A, and play a role similar to positive feedback, causing the voltage at point A to drop rapidly, and the output voltage VOUT also drops rapidly until the output voltage returns to stability.

[0070] Therefore, the circuit of the present application can accelerate the time required for the output overshoot to recover to a stable state due to a sudden decrease in current, that is, improve the speed of transient response.

[0071] In an optional implementation, the LDO circuit provided in the embodiment of the present application further includes a compensation capacitor C1; a first end of the compensation capacitor C1 is connected to the output end of the eighteenth transistor M18, and a second end of the compensation capacitor C1 is grounded, and the compensation capacitor C1 is used to absorb reactive power generated in the LDO circuit.

[0072] The components in the circuit of the present application will generate reactive power when in use, and it is usually inductive. The reactive power will reduce the capacity utilization efficiency of the power supply, which can be improved by appropriately adding compensation capacitors in the circuit.

[0073] It can be understood that the compensation capacitor C1 in this embodiment is used to absorb the reactive power generated in the circuit and improve the system power factor. That is to say, the role of the compensation capacitor C1 is to improve the power factor of the inductive load circuit, mainly because when the alternating current passes through the transistor, the current lags behind the voltage by 90 degrees, and when passing through the compensation capacitor C1, the current leads the voltage by 90 degrees. Therefore, the role of the compensation capacitor is to use the leading current of the capacitor to offset the lagging current generated by the inductive load.

[0074] The LDO circuit provided by the embodiment of the present application includes a source cross-coupling module, a first current mirror module, a second current mirror module, a third current mirror module and an output module; the first control end of the source cross-coupling module is connected to the input voltage, the second control end of the source cross-coupling module is connected to the reference voltage, the first input end of the source cross-coupling module is connected to the power supply voltage, the second input end of the source cross-coupling module is connected to the first output end of the first current mirror module, the first output end of the source cross-coupling module is connected to the first input end of the second current mirror, the second output end of the source cross-coupling module is connected to the The first input terminal is connected; the input terminal of the first current mirror module is connected to the power supply voltage, the second output terminal of the first current mirror module is connected to the second input terminal of the second current mirror module, and the output terminal of the second current mirror module is grounded; the control terminal of the third current mirror module is connected to the first bias voltage, the second input terminal of the third current mirror module is connected to the first output terminal of the output module, and the output terminal of the third current mirror module is grounded; the input terminal of the output module is connected to the power supply voltage, the second output terminal of the output module is connected to the output voltage, and the control terminal of the output module is connected to the second output terminal of the first current mirror module. The present application can quickly respond to changes in load current, so that the output voltage can be restored to stability in a short time, and it can be done without additional current, and is suitable for low power consumption occasions. The circuit structure is simple and has certain application value.

[0075] Example 2

[0076] In addition, if Figure 2 As shown, an embodiment of the present application provides a power management device 20, and the power management device 20 includes a power supply 21 and the LDO circuit 10 described in the embodiment.

[0077] The power management device 20 provided in the embodiment of the present application can quickly respond to changes in load current so that the output voltage can return to stability in a short time, and this can be done without the need for additional current. It can be used in low-power applications, has high practical value, and has certain application value.

[0078] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow chart, and the combination of boxes in the structure diagram and / or the flow chart, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0079] In addition, the functional modules or units in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0080] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0081] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. An LDO circuit, characterized in that: The LDO circuit includes a source end cross-coupling module, a first current mirror module, a second current mirror module, a third current mirror module and an output module; The first control end of the source cross-coupling module is connected to the input voltage, the second control end of the source cross-coupling module is connected to the reference voltage, the first input end of the source cross-coupling module is connected to the power supply voltage, the second input end of the source cross-coupling module is connected to the first output end of the first current mirror module, the first output end of the source cross-coupling module is connected to the first input end of the second current mirror, and the second output end of the source cross-coupling module is connected to the first input end of the third current mirror; The input end of the first current mirror module is connected to the power supply voltage, the second output end of the first current mirror module is connected to the second input end of the second current mirror module, and the output end of the second current mirror module is grounded; The control end of the third current mirror module is connected to the first bias voltage, the second input end of the third current mirror module is connected to the first output end of the output module, and the output end of the third current mirror module is grounded; The input end of the output module is connected to the power supply voltage, the second output end of the output module is connected to the output voltage, and the control end of the output module is connected to the second output end of the first current mirror module; The source-end cross-coupling module is used to generate a bias current for turning on the LDO circuit, the first current mirror module is used to unidirectionally conduct the power supply voltage to the second input end of the source-end cross-coupling module, the second current mirror module is used to form a symmetrical structure with the first current mirror module, the third current mirror module is used to follow the current change of the output module caused by the change of the load current, the output module is used to make a corresponding current change to the change of the load current, and transmit the generated current change to the third current mirror module.

2. The LDO circuit according to claim 1, characterized in that: The LDO circuit also includes a fourth current mirror module; The control end of the fourth current mirror module is connected to the second bias voltage, the input end of the fourth current mirror module is connected to the first input end of the third current mirror, the output end of the fourth current mirror module is grounded, and the fourth current mirror module is used to provide a constant bias current for the LDO circuit.

3. The LDO circuit according to claim 2, characterized in that: The source-end cross-coupling module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; The control terminals of the first transistor and the second transistor are both connected to the input voltage, the control terminals of the third transistor and the fourth transistor are both connected to the reference voltage, the input terminals of the first transistor and the fourth transistor are both connected to the power supply voltage, the input terminals of the second transistor and the third transistor are both connected to the first output terminal of the first current mirror module, the output terminal of the first transistor is connected to the input terminal of the seventh transistor, the output terminal of the fourth transistor is connected to the input terminal of the tenth transistor, the output terminal of the second transistor is connected to the input terminal of the ninth transistor, and the output terminal of the third transistor is connected to the input terminal of the eighth transistor; The control end of the seventh transistor is connected to the control end of the eighth transistor, the control end of the ninth transistor is connected to the control end of the tenth transistor, the output ends of the seventh transistor and the tenth transistor are connected to the first input end of the third current mirror, the output ends of the eighth transistor and the ninth transistor are connected to the first input end of the second current mirror, the control end of the seventh transistor is short-circuited with the output end, and the control end of the tenth transistor is short-circuited with the output end.

4. The LDO circuit according to claim 3, characterized in that: The first current mirror module includes a fifth transistor, a sixth transistor and an eighteenth transistor; The input ends of the fifth transistor, the sixth transistor and the eighteenth transistor are connected to the power supply voltage, the output end of the fifth transistor is connected to the input end of the second transistor, the output end of the sixth transistor is connected to the input end of the third transistor, the output end of the eighteenth transistor is connected to the second input end of the second current mirror module, the control end of the sixth transistor is connected to the control end of the eighteenth transistor, the control end of the fifth transistor is short-circuited with the output end, and the control end of the sixth transistor is short-circuited with the output end.

5. The LDO circuit according to claim 4, characterized in that: The second current mirror module includes an eleventh transistor, a twelfth transistor and a seventeenth transistor; The input end of the eleventh transistor is connected to the output end of the eighth transistor, the input end of the twelfth transistor is connected to the output end of the ninth transistor, the input end of the seventeenth transistor is connected to the output end of the eighteenth transistor, the output ends of the eleventh transistor, the twelfth transistor and the seventeenth transistor are grounded respectively, the control end of the eleventh transistor is short-circuited with the output end of the eleventh transistor, and the control end of the twelfth transistor is short-circuited with the output end of the twelfth transistor.

6. The LDO circuit according to claim 5, characterized in that: The third current mirror module includes a fourteenth transistor, a sixteenth transistor and a nineteenth transistor; The control ends of the fourteenth transistor, the sixteenth transistor and the nineteenth transistor are all connected to the first bias voltage, the input end of the fourteenth transistor is connected to the output end of the seventh transistor, the input end of the sixteenth transistor is connected to the output end of the tenth transistor, the input end of the nineteenth transistor is connected to the first output end of the output module, the output ends of the fourteenth transistor, the sixteenth transistor and the nineteenth transistor are grounded, and the control end of the nineteenth transistor is short-circuited with the input end.

7. The LDO circuit according to claim 6, characterized in that: The fourth current mirror module includes a thirteenth transistor and a fifteenth transistor; The control terminals of the thirteenth transistor and the fifteenth transistor are both connected to the second bias voltage, the input terminal of the thirteenth transistor is connected to the input terminal of the fourteenth transistor, the input terminal of the fifteenth transistor is connected to the input terminal of the sixteenth transistor, and the output terminals of the thirteenth transistor and the fifteenth transistor are grounded.

8. The LDO circuit according to claim 7, characterized in that: The output module includes a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor and a twenty-fifth transistor; Input terminals of the 20th transistor, the 21st transistor, the 22nd transistor and the 25th transistor are connected to the power supply voltage, the output terminal of the 20th transistor is connected to the input terminal of the 19th transistor, the output terminal of the 21st transistor is connected to the input terminal of the 23rd transistor, the output terminal of the 22nd transistor is connected to the input terminal of the 24th transistor, the output terminal of the 22nd transistor is also connected to the control terminal of the 25th transistor, the output terminals of the 23rd transistor, the 24th transistor and the 25th transistor are connected to the output voltage, the control terminal of the 20th transistor is connected to the control terminal of the 21st transistor, the 22nd transistor is connected to the third bias voltage, the control terminals of the 23rd transistor and the 24th transistor are connected to the output terminal of the 18th transistor, and the control terminal of the 21st transistor is short-circuited to the output terminal.

9. The LDO circuit according to claim 8, characterized in that: The LDO circuit also includes a compensation capacitor; A first end of the compensation capacitor is connected to the output end of the eighteenth transistor, a second end of the compensation capacitor is grounded, and the compensation capacitor is used to absorb reactive power generated in the LDO circuit.

10. A power management device, characterized in that: The power management device comprises a power supply and the LDO circuit according to any one of claims 1 to 9.

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