Asynchronous FIFO memory

Abstract

The present application provides an asynchronous FIFO memory, which comprises a synchronous FIFO memory and an asynchronous buffer. Data is written into the synchronous FIFO memory if there is a write request, the synchronous FIFO memory has a FIFO mode and a continuous mode, in the FIFO mode, the oldest written data is not allowed to be overwritten by the written data, in the continuous mode, the oldest written data is allowed to be overwritten by the written data. Data is read from the asynchronous buffer if there is a read request, the asynchronous buffer buffers the data read from the synchronous FIFO memory, the asynchronous buffer is not allowed to be written into when it is full, and the capacity of the asynchronous buffer is less than that of the synchronous FIFO memory. In this way, the area of the memory is saved, and the utilization of the memory is improved.

Description

Technical field

[0001] The present invention relates to the field of memory technology, and in particular to an asynchronous FIFO (First in First out) memory. [Background Technology]

[0002] Asynchronous FIFO memory can be used to quickly and conveniently transfer data between different clock domains in a system. It has been widely used in network interfaces, image processing, sensor data acquisition and processing, and other fields.

[0003] In the prior art, asynchronous FIFO memory can be implemented using dual-port memory or two single-port static random access memories (SRAMs), but this method requires a large memory area and has low utilization. Asynchronous FIFO memory can also be implemented using dual-port SRAMs, but this method requires a larger area.

[0004] Therefore, it is urgent to propose a new technical solution to solve the above problems. [Summary of the invention]

[0005] One of the purposes of the present invention is to provide an asynchronous FIFO memory with small area and high efficiency.

[0006] According to one aspect of the present invention, the present invention provides an asynchronous FIFO memory, which includes: a synchronous FIFO memory and an asynchronous buffer. If there is a write request, data is written to the synchronous FIFO memory, and the synchronous FIFO memory has a FIFO mode and a continuous mode. In the FIFO mode, the written data is not allowed to overwrite the oldest written data, and in the continuous mode, the written data is allowed to overwrite the oldest written data; if there is a read request, data is read from the asynchronous buffer, and the asynchronous buffer caches the data read from the synchronous FIFO memory. When the asynchronous buffer is full, writing is not allowed, and the capacity of the asynchronous buffer is smaller than the capacity of the synchronous FIFO memory.

[0007] Compared with existing technologies, this invention uses a synchronous FIFO memory and a small asynchronous buffer to implement the functions of an asynchronous FIFO memory. This can be applied to data transfer between different clock domains in the system, saving memory area and improving memory utilization. It is suitable for both stable clock reading scenarios and I2C / SPI / I3C protocol scenarios.

Brief Description of the Drawings

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive effort. Among them:

[0009] Figure 1 1 is a schematic structural diagram of an asynchronous FIFO memory in one embodiment of the present invention; [Specific implementation method]

[0010] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0011] The term "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, nor does it refer to separate or selective embodiments that are mutually exclusive of other embodiments. Unless otherwise specified, the terms "connected," "connected," and "connected" herein, indicating electrical connection, refer to direct or indirect electrical connection.

[0012] In the present invention, unless otherwise specified or limited, the terms "connected," "connected," and "coupled" should be understood broadly; for example, they may refer to direct connection or indirect connection through an intermediary. Those skilled in the art will understand the specific meanings of these terms in the present invention based on specific circumstances.

[0013] The present invention uses a synchronous FIFO memory and an asynchronous buffer with a very small capacity to realize the function of the asynchronous FIFO memory, can be applied to data transmission between different clock domains in the system, saves memory area and improves memory utilization.

[0014] Figure 1 FIG. 1 is a schematic diagram of the structure of the asynchronous FIFO memory 100 in one embodiment of the present invention. Figure 1 As shown, the asynchronous FIFO memory 100 includes a synchronous FIFO memory 110 and an asynchronous buffer (asynchronous buffer) 120 .

[0015] The synchronous FIFO memory 110 can be a single-port static random access memory SRAM. If there is a write request, the data is written to the synchronous FIFO memory 110. The synchronous FIFO memory 110 has a FIFO mode and a continuous mode. In the FIFO mode, the written data is not allowed to overwrite the oldest written data, and in the continuous mode, the written data is allowed to overwrite the oldest written data. It should be noted that the oldest written data in the synchronous FIFO memory 110 is the oldest data that has been written but not read out from the asynchronous buffer 120, that is, if the written data has been read out of the asynchronous FIFO memory 100, then the data cannot be called the oldest written data.

[0016] If a read request is received, data is read from the asynchronous buffer 120. The asynchronous buffer 120 stores data read from the synchronous FIFO memory 110. When the asynchronous buffer 120 is full, writes are not permitted. The capacity of the asynchronous buffer 120 is smaller than that of the synchronous FIFO memory 110. It should be noted that a read request here refers to a request to read from the asynchronous FIFO, and a write request here refers to a request to write to the asynchronous FIFO. When the synchronous FIFO memory 110 is not empty, the asynchronous buffer 120 is not full, and there is no write request, data is read from the synchronous FIFO memory 110 and written to the asynchronous buffer 120. At this point, the asynchronous buffer 120 is effectively a small asynchronous FIFO memory.

[0017] In fact, the capacity of the asynchronous buffer 120 is much smaller than that of the synchronous FIFO memory 110 , for example, the capacity of the asynchronous buffer is less than 1 / 10 of that of the synchronous FIFO memory, which can save the area of ​​the entire asynchronous FIFO memory 100 .

[0018] In one embodiment, the synchronous FIFO memory 110 has a write pointer wptr, a first read pointer rptr, and a second read pointer buffer_rptr.

[0019] After writing data into the synchronous FIFO memory, the write pointer is incremented by 1.

[0020] The first read pointer rptr points to the oldest data in the synchronous FIFO memory 110 that has not been read from the asynchronous buffer 120. Specifically, the first read pointer rptr is incremented by 1 after valid data is read from the asynchronous buffer 120. Alternatively, in continuous mode, the first read pointer rptr is also incremented by 1 after the oldest data that has been written but not read from the asynchronous buffer 120 is overwritten. In this way, the first read pointer rptr always points to the oldest data in the synchronous FIFO memory 110 that has not been read from the asynchronous buffer 120. More specifically, regardless of whether continuous mode or FIFO mode is used, the first read pointer rptr is incremented by 1 after valid data is read from the asynchronous buffer 120. If invalid data is read from the asynchronous buffer 120, the first read pointer rptr is not incremented by 1.

[0021] Data is read from the synchronous FIFO memory 110 according to the second read pointer buffer_rptr and buffered in the asynchronous buffer 120. After data is read from the synchronous FIFO memory 110 and written to the asynchronous buffer 120, the second read pointer buffer_rptr is incremented by 1. The first read pointer rptr does not exceed the second read pointer buffer_rptr in the reading order. Therefore, if the first read pointer rptr is incremented by 1 after the first read pointer rptr is equal to the second read pointer buffer_rptr, the second read pointer buffer_rptr must also be incremented by 1. Therefore, in continuous mode, after overwriting the oldest data not yet written to the asynchronous buffer 110, the first read pointer rptr is equal to the second read pointer buffer_rptr. The first read pointer rptr is incremented by 1, and the second read pointer is also incremented by 1.

[0022] Whether the synchronous FIFO memory 110 is empty or full is determined based on the write pointer wptr and the second read pointer buffer_rptr of the synchronous FIFO memory 110. Whether the asynchronous FIFO memory 100 is empty or full is determined based on the write pointer wptr and the first read pointer rptr of the synchronous FIFO memory 110. In the present invention, the write pointer wptr and the second read pointer buffer_rptr are used as the addresses for reading and writing the synchronous FIFO memory 110, respectively.

[0023] In one embodiment, when the asynchronous buffer 120 is empty, reading the asynchronous buffer 120 returns a predetermined value, such as 0. After writing data to the asynchronous buffer 120, the write pointer of the asynchronous buffer 120 is incremented by 1, and after reading data from the asynchronous buffer 120, the read pointer of the asynchronous buffer 120 is incremented by 1. Whether the asynchronous buffer 120 is full or empty is determined based on the write and read pointers of the asynchronous buffer 120. Specifically, the read and write pointers of the asynchronous buffer 120 are converted from binary to Gray code, and then, after secondary synchronization, are transferred to the write clock domain and the read clock domain, respectively, to generate an empty signal in the read clock domain and a full signal in the write clock domain of the asynchronous buffer 120.

[0024] like Figure 1 As shown, the asynchronous FIFO memory 100 further includes an invalid data amount counter 130. The invalid data amount counter 130 records the amount of invalid data in the asynchronous buffer 130 in continuous mode. Invalid data in the asynchronous buffer 130 is data in the asynchronous buffer 120 that has been overwritten in the synchronous FIFO. If invalid data is read as valid data, it will cause a jump in the valid data. Therefore, it is necessary to ensure that when the read data is invalid, subsequent devices are aware that the data is invalid. In FIFO mode, all data read from the asynchronous buffer 120 is valid. In continuous mode, the data read from the asynchronous buffer 120 is valid only when the invalid data amount count value Invalid_data_cnt of the invalid data amount counter 130 is 0; otherwise, the data read from the asynchronous buffer 120 is invalid.

[0025] In continuous mode, if written data overwrites data in the synchronous FIFO memory 110 that has been written to the asynchronous buffer 120 but not read from the asynchronous buffer 120, the invalid data amount counter 130 is incremented by 1. If the invalid data amount count value Invalid_data_cnt of the invalid data amount counter 130 is not 0, the invalid data amount counter 130 is decremented by 1 after data is read from the asynchronous buffer 120.

[0026] In this way, the present invention can use a single-port synchronous FIFO memory 110 and an asynchronous buffer 120 with a very small depth to realize an asynchronous FIFO memory.

[0027] In the description of this specification, reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0028] Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention, and that those skilled in the art may make changes, modifications and variations to the above embodiments within the scope of the present invention.

Claims

1. An asynchronous FIFO memory, characterized in that: It includes: Synchronous FIFO memory and asynchronous buffer, If there is a write request, the data is written into the synchronous FIFO memory, wherein the synchronous FIFO memory has a FIFO mode and a continuous mode. In the FIFO mode, the written data is not allowed to overwrite the oldest written data, and in the continuous mode, the written data is allowed to overwrite the oldest written data; If there is a read request, data is read from the asynchronous buffer. The asynchronous buffer caches the data read from the synchronous FIFO memory. When the asynchronous buffer is full, writing is not allowed. The capacity of the asynchronous buffer is smaller than the capacity of the synchronous FIFO memory. When the synchronous FIFO memory is not empty, the asynchronous buffer is not full and there is no write request, reading data from the synchronous FIFO memory and writing it into the asynchronous buffer, The capacity of the asynchronous buffer is less than 1 / 10 of the capacity of the synchronous FIFO memory. The synchronous FIFO memory has a write pointer, a first read pointer and a second read pointer, Reading data from the synchronous FIFO memory according to the second read pointer and buffering the data into the asynchronous buffer, The first read pointer points to the oldest data in the synchronous FIFO memory that has not been read from the asynchronous buffer, and the first read pointer does not exceed the second read pointer in the reading sequence.

2. The asynchronous FIFO memory according to claim 1, wherein: After writing data into the synchronous FIFO memory, the write pointer is incremented by 1; After valid data is read from the asynchronous buffer, the first read pointer is incremented by 1, or, in a continuous mode, after the oldest written data that has not been read from the asynchronous buffer is overwritten, the first read pointer is incremented by 1, so that the first read pointer points to the oldest data in the synchronous FIFO memory that has not been read from the asynchronous buffer; After data is read from the synchronous FIFO memory and written into the asynchronous buffer, the second read pointer is incremented by 1. After the oldest data not written into the asynchronous buffer is overwritten in the continuous mode, the first read pointer is incremented by 1 and the second read pointer is incremented by 1.

3. The asynchronous FIFO memory according to claim 2, wherein: Determine whether the synchronous FIFO is empty or full according to the write pointer and the second read pointer of the synchronous FIFO memory, Whether the asynchronous FIFO memory is empty or full is determined according to the write pointer and the first read pointer of the synchronous FIFO memory.

4. The asynchronous FIFO memory according to claim 1, wherein: When the asynchronous buffer is empty, the return value is a predetermined value. After writing data to the asynchronous buffer, the write pointer of the asynchronous buffer is incremented by 1. After data is read from the asynchronous buffer, the read pointer of the asynchronous buffer is incremented by 1.

5. The asynchronous FIFO memory according to claim 4, wherein: Whether the asynchronous buffer is full or empty is determined according to the write pointer and the read pointer of the asynchronous buffer.

6. The asynchronous FIFO memory according to claim 1, wherein: It also includes: The invalid data amount counter records the invalid data amount in the asynchronous buffer in the continuous mode, wherein the invalid data in the asynchronous buffer is the data in the asynchronous buffer that has been overwritten in the synchronous FIFO memory.

7. The asynchronous FIFO memory according to claim 6, wherein: In FIFO mode, each data read from the asynchronous buffer is valid; In the continuous mode, the data read from the asynchronous buffer is valid only when the invalid data amount count value of the invalid data amount counter is 0.

8. The asynchronous FIFO memory according to claim 6, wherein: In the continuous mode, if the written data overwrites the data in the synchronous FIFO memory that has been written to the asynchronous buffer but not read from the asynchronous buffer, the invalid data amount count value of the invalid data amount counter is increased by 1; When the invalid data amount count value is not 0, after data is read out from the asynchronous buffer, the invalid data amount count value of the invalid data amount counter is reduced by 1.

9. The asynchronous FIFO memory according to claim 1, wherein: The oldest data in the synchronous FIFO memory is the oldest data that has been written but not read from the asynchronous buffer. The synchronous FIFO memory is a single-port static random access memory SRAM.

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