Thread storage location allocation method, device, chip, equipment and storage medium

Abstract

The present invention relates to the field of memory data processing technology, and in particular to a thread storage location allocation method, apparatus, chip, computing device, and computer-readable storage medium. The method comprises: allocating a virtual cache to a thread; calculating the access frequency of a physical memory area in a predetermined time period; selecting a low-access frequency physical memory area within a first preset range in order of access frequency from small to large; determining a low-access frequency virtual cache according to a mapping relationship; increasing the value of a low-access frequency counter corresponding to the low-access frequency virtual cache by a preset unit amount; sorting the virtual caches in order of the value of the low-access frequency counter from small to large; selecting at least one virtual cache within the sorted second preset range, and establishing a mapping relationship between it and the first physical memory area. In the above manner, a suitable physical memory area can be allocated to the virtual cache to take into account the memory area, access power consumption, and delay.

Description

Technical Field

[0001] The present invention relates to the field of memory data processing technology, and in particular to a thread storage location allocation method, device, chip, computing device and computer-readable storage medium. Background Art

[0002] In existing operating systems, memory is managed through a memory management unit (MMU). To improve the utilization of physical memory, when a user accesses memory, the MMU can allocate a virtual cache for the thread accessed by the user and translate the virtual cache into an actual physical memory area. After the system has run for a period of time, the mapping relationship between the virtual cache and the actual physical memory area is adjusted to prevent memory management fragmentation caused by frequent memory requests and releases. At the same time, the MMU can also control access to physical memory areas to improve the security of the operating system.

[0003] Furthermore, for actual physical memory, the larger the capacity of a single block, the greater the power consumption and latency during read and write accesses. A smaller capacity results in lower power consumption and latency during read and write accesses. However, assuming the capacity of a single physical memory block is the same as the total capacity of multiple physical memory blocks, the area occupied by a single physical memory block is smaller than the total area occupied by multiple physical memory blocks.

[0004] Currently, the method for adjusting the mapping relationship between virtual cache and actual physical memory areas is to centrally map the virtual cache to one or several actual physical memory areas, so that subsequent virtual cache requests can obtain sufficiently large and continuous physical memory. This method only solves the problem of memory management fragmentation, but cannot allocate appropriate physical memory areas for the virtual cache corresponding to each thread based on physical memory area, access power consumption, and latency. Summary of the Invention

[0005] Based on the above situation, the main purpose of the present invention is to provide a thread storage location allocation method, device, chip, computing device and computer-readable storage medium to allocate a suitable physical memory area for the virtual cache, taking into account the memory area, access power consumption and latency.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] According to one aspect of an embodiment of the present application, a thread storage location allocation method is provided, comprising: allocating a virtual cache to a thread; the number of virtual caches being multiple, and establishing mapping relationships between the multiple virtual caches and multiple physical memory areas, wherein the multiple physical memory areas include a first physical memory area and a second physical memory area, the first physical memory area belonging to first memory hardware, the second physical memory area belonging to second memory hardware, and the capacity of a single piece of the first memory hardware being smaller than the capacity of a single piece of the second memory hardware; calculating the access frequency of each physical memory area within each predetermined time period; selecting, in ascending order of access frequency, physical memory areas within a first preset range as low-access-frequency physical memory areas; determining, based on the mapping relationship, a virtual cache corresponding to the low-access-frequency physical memory area as a low-access-frequency virtual cache; increasing the value of a pre-established low-access-frequency counter corresponding to the low-access-frequency virtual cache by a preset unit amount, wherein the initial value of the low-access-frequency counter is a preset minimum value; sorting the virtual caches in ascending order of the low-access-frequency counter value; and selecting at least one of the sorted virtual caches within a second preset range and establishing a mapping relationship with the first physical memory area.

[0008] Preferably, before sorting the virtual cache in ascending order according to the values ​​of the low access frequency counter, the method also includes: determining whether the total remaining capacity of all first physical memory areas is less than or equal to a preset capacity value; if so, executing the step of sorting the virtual cache in ascending order according to the values ​​of the low access frequency counter; if not, establishing a mapping relationship between the virtual cache and the first physical memory area.

[0009] Preferably, before sorting the virtual caches in ascending order of the values ​​of the low access frequency counters, the method includes: allocating the same virtual cache as the last application to the thread that applies for the cache again; selecting at least one virtual cache within the second preset range before sorting, and establishing a mapping relationship between it and the first physical memory area, including: determining whether the virtual cache corresponding to the thread that applies for the cache again is within the second preset range before sorting; if so, establishing a mapping relationship between the virtual cache corresponding to the thread that applies for the cache again and the first physical memory area.

[0010] Preferably, at least one virtual cache is selected from the virtual caches within the first second preset range of the sort, and a mapping relationship is established between it and the first physical memory area, including: when the system is in an idle state, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the first second preset range, and a mapping relationship is established between it and the first physical memory area.

[0011] Preferably, when the system is in an idle state, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the second preset range, and a mapping relationship is established between it and the first physical memory area, including: when the system is in an idle state, determining whether the total remaining capacity of all first physical memory areas is less than or equal to a preset capacity value; if not, selecting a virtual cache that does not perform direct memory operations from the virtual caches within the second preset range, and establishing a mapping relationship between it and the first physical memory area.

[0012] Preferably, after sorting the virtual caches in ascending order of the values ​​of the low access frequency counters, the method further comprises: selecting at least one virtual cache within the third preset range after the sorting, and establishing a mapping relationship between the virtual cache and the second physical memory area.

[0013] Preferably, at least one is selected from the virtual caches within the third preset range of the sort, and a mapping relationship is established between it and the second physical memory area, including: when the system is in an idle state, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the third preset range, and a mapping relationship is established between it and the second physical memory area.

[0014] Preferably, the number of low access frequency counters is fixed; after selecting at least one from the virtual caches within the third preset range after sorting and establishing a mapping relationship with the second physical memory area, the method further includes: marking the selected virtual cache and the virtual cache that establishes a mapping relationship with the second physical memory area; releasing the correspondence between the marked virtual cache and the low access frequency counter; resetting the value of the low access frequency counter whose correspondence is released to the initial value, so as to be used for subsequently establishing a correspondence with the virtual cache corresponding to the newly applied thread, and when subsequently executing the step of sorting the virtual caches in order from small to large in terms of the values ​​of the low access frequency counters, the low access frequency counters that have not been released from the correspondence and the low access frequency counters that have been released from the correspondence are sorted separately, and when subsequently executing the step of selecting at least one from the virtual caches within the second preset range before sorting and establishing a mapping relationship with the first physical memory area, the second preset range before sorting includes each part of the two separated sorts.

[0015] Preferably, the number of low access frequency counters is fixed; after selecting at least one from the virtual caches within the first second preset range of the sort and establishing a mapping relationship with the first physical memory area, the method further includes: marking the selected virtual cache that establishes a mapping relationship with the first physical memory area; releasing the correspondence between the marked virtual cache and the low access frequency counter; resetting the value of the low access frequency counter whose correspondence has been released to an initial value, so as to be used for subsequently establishing a correspondence with the virtual cache corresponding to the newly applied thread, and when subsequently executing the step of sorting the virtual caches in order from small to large in terms of the values ​​of the low access frequency counters, the low access frequency counters that have not been released from the correspondence and the low access frequency counters that have been released from the correspondence are sorted separately, and when subsequently executing the step of selecting at least one from the virtual caches within the first second preset range of the sort and establishing a mapping relationship with the first physical memory area, the first second preset range of the sort includes a portion of each of the two separated sorts.

[0016] Preferably, the conditions for pre-establishing a low access frequency counter for the virtual cache include: the capacity applied for the virtual cache is greater than or equal to a preset threshold; and / or, within a predetermined time period, the number of applications for the virtual cache is greater than or equal to a preset number; and / or, within a predetermined time period, the total time that the virtual cache occupies the physical memory area is greater than or equal to a preset time.

[0017] Preferably, after increasing the value of the pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, the method includes: recording the value of the low access frequency counter so that when the same step is executed again after the next startup, accumulation is performed based on the recorded value of the low access frequency counter.

[0018] Preferably, the method further comprises: restoring the value of the low access frequency counter to an initial value each time the computer is powered on.

[0019] According to another aspect of an embodiment of the present application, a thread storage location allocation device is provided, comprising: a first allocation module, configured to allocate a virtual cache to a thread; a plurality of virtual caches, a mapping relationship being established between the plurality of virtual caches and a plurality of physical memory areas, wherein the plurality of physical memory areas include a first physical memory area and a second physical memory area, the first physical memory area belonging to a first memory hardware, the second physical memory area belonging to a second memory hardware, and the capacity of a single piece of the first memory hardware being smaller than the capacity of a single piece of the second memory hardware; a calculation module, configured to calculate the access frequency of each physical memory area within each predetermined time period; a selection module, configured to calculate the access frequency of each physical memory area in ascending order of access frequency; , selecting a physical memory area within a first preset range as a low access frequency physical memory area; a determination module, used to determine, according to a mapping relationship, a virtual cache corresponding to the low access frequency physical memory area as a low access frequency virtual cache; an increase module, used to increase the value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, wherein the initial value of the low access frequency counter is a preset minimum value; a sorting module, used to sort the virtual caches in ascending order of the values ​​of the low access frequency counter; a first mapping module, used to select at least one from the virtual caches within a second preset range before sorting, and establish a mapping relationship between it and the first physical memory area.

[0020] Preferably, the device also includes: a judgment module, used to judge whether the remaining total capacity of all first physical memory areas is less than or equal to a preset capacity value; a control module, used to control the sorting module to execute the step of sorting the virtual cache in ascending order according to the value of the low access frequency counter when the judgment module judges to be yes; and a second mapping module, used to establish a mapping relationship between the virtual cache and the first physical memory area when the judgment module judges to be no.

[0021] Preferably, the device also includes: a second allocation module, used to allocate the same virtual cache as the last application to the thread that applies for cache again; the first mapping module includes: a first judgment submodule, used to judge whether the virtual cache corresponding to the thread that applies for cache again is within the first second preset range of the sort; the first mapping submodule is used to establish a mapping relationship between the virtual cache corresponding to the thread that applies for cache again and the first physical memory area when the judgment submodule judges that it is yes.

[0022] Preferably, the first mapping module includes: a second mapping submodule for selecting a virtual cache that does not perform direct memory operations from the virtual caches within the second preset range when the system is in an idle state, and establishing a mapping relationship between the virtual cache and the first physical memory area.

[0023] Preferably, the first mapping module also includes: a judgment unit, used to judge whether the total remaining capacity of all the first physical memory areas is less than or equal to a preset capacity value when the system is in an idle state; a control unit, used to select a virtual cache that does not perform direct memory operations from the virtual caches within the first second preset range when the judgment unit judges to be no, and establish a mapping relationship between it and the first physical memory area.

[0024] Preferably, the device comprises: a third mapping module, configured to select at least one virtual cache from the sorted virtual caches within a third preset range, and establish a mapping relationship between the virtual cache and the second physical memory area.

[0025] Preferably, the third mapping module includes: a third mapping submodule for selecting a virtual cache that does not perform direct memory operations from the virtual caches within the third preset range when the system is in an idle state, and establishing a mapping relationship between the virtual cache and the second physical memory area.

[0026] Preferably, the number of low access frequency counters is fixed. The apparatus further comprises: a first marking module for marking the selected virtual cache that is mapped to the second physical memory region after the second mapping module performs the step of selecting at least one virtual cache within the third preset range after sorting and establishing a mapping relationship with the second physical memory region; a first undoing module for undoing the mapping relationship between the marked virtual cache and the low access frequency counter; and a first resetting module for resetting the value of the undoed low access frequency counter to an initial value for use in subsequently establishing a mapping relationship with the virtual cache corresponding to a newly requested thread. When the sorting module subsequently performs the step of sorting the virtual caches in ascending order of the values ​​of the low access frequency counters, the low access frequency counters that have not been undoed and the virtual caches that have been undoed are sorted separately. When the first mapping module subsequently performs the step of selecting at least one virtual cache within the second preset range before sorting and establishing a mapping relationship with the first physical memory region, the second preset range before sorting includes a portion of each of the two separated sorts.

[0027] Preferably, the number of low access frequency counters is fixed. The apparatus further comprises: a second marking module configured to mark the selected virtual cache that has been mapped to the first physical memory region after the first mapping module selects at least one virtual cache within a second preset range before sorting and establishes a mapping relationship between the selected virtual cache and the first physical memory region; a second undoing module configured to undo the mapping relationship between the marked virtual cache and the low access frequency counter; and a second resetting module configured to reset the value of the undoed low access frequency counter to an initial value for use in subsequently establishing a mapping relationship with the virtual cache corresponding to a newly requested thread, and to sort the low access frequency counters that have not been undoed and the virtual caches that have been undoed separately when the sorting module subsequently sorts the virtual caches in ascending order of the values ​​of the low access frequency counters, and to select at least one virtual cache within the second preset range before sorting and establish a mapping relationship between the virtual cache and the first physical memory region when the first mapping module subsequently selects at least one virtual cache within the second preset range before sorting and establishes a mapping relationship between the virtual cache and the first physical memory region, the second preset range before sorting includes a portion of each of the two separated sorts.

[0028] Preferably, the conditions for pre-establishing a low access frequency counter for the virtual cache include: the capacity applied for the virtual cache is greater than or equal to a preset threshold; and / or, within a predetermined time period, the number of applications for the virtual cache is greater than or equal to a preset number; and / or, within a predetermined time period, the total time that the virtual cache occupies the physical memory area is greater than or equal to a preset time.

[0029] Preferably, the device further comprises: a recording module for recording the value of the low access frequency counter, so that when the same step is executed again after the device is powered on next time, accumulation is performed based on the recorded value of the low access frequency counter.

[0030] Preferably, the device further comprises: a recovery module, configured to restore the value of the low access frequency counter to an initial value each time the device is powered on.

[0031] According to another aspect of an embodiment of the present application, a thread storage location allocation method is provided, comprising: allocating a virtual cache to a thread; the number of virtual caches being multiple, and establishing a mapping relationship between the multiple virtual caches and multiple physical memory areas, wherein the multiple physical memory areas include a first physical memory area and a second physical memory area, the first physical memory area belonging to first memory hardware, the second physical memory area belonging to second memory hardware, and the capacity of a single piece of the first memory hardware being smaller than the capacity of a single piece of the second memory hardware; calculating the access frequency of each physical memory area within each predetermined time period; selecting, in order of access frequency from small to large, physical memory areas within a first preset range as low-access-frequency physical memory areas; determining, based on the mapping relationship, a virtual cache corresponding to the low-access-frequency physical memory area as a low-access-frequency virtual cache; reducing the value of a pre-established low-access-frequency counter corresponding to the low-access-frequency virtual cache by a preset unit amount, wherein the initial value of the low-access-frequency counter is a preset maximum value; sorting the virtual caches in order of the low-access-frequency counter value from large to small; and selecting at least one of the sorted virtual caches within a second preset range and establishing a mapping relationship with the first physical memory area.

[0032] Preferably, before sorting the virtual cache in descending order according to the values ​​of the low access frequency counter, the method also includes: determining whether the total remaining capacity of all first physical memory areas is less than or equal to a preset capacity value; if so, executing the step of sorting the virtual cache in descending order according to the values ​​of the low access frequency counter; if not, establishing a mapping relationship between the virtual cache and the first physical memory area.

[0033] Preferably, before sorting the virtual caches in descending order of the values ​​of the low access frequency counters, the method includes: allocating the same virtual cache as the last application to the thread that applies for the cache again; selecting at least one virtual cache within the second preset range before sorting, and establishing a mapping relationship between it and the first physical memory area, including: determining whether the virtual cache corresponding to the thread that applies for the cache again is within the second preset range before sorting; if so, establishing a mapping relationship between the virtual cache corresponding to the thread that applies for the cache again and the first physical memory area.

[0034] Preferably, at least one virtual cache is selected from the virtual caches within the first second preset range of the sort, and a mapping relationship is established between it and the first physical memory area, including: when the system is in an idle state, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the first second preset range, and a mapping relationship is established between it and the first physical memory area.

[0035] Preferably, when the system is in an idle state, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the second preset range, and a mapping relationship is established between it and the first physical memory area, including: when the system is in an idle state, determining whether the total remaining capacity of all first physical memory areas is less than or equal to a preset capacity value; if not, selecting a virtual cache that does not perform direct memory operations from the virtual caches within the second preset range, and establishing a mapping relationship between it and the first physical memory area.

[0036] Preferably, after sorting the virtual caches in descending order of the values ​​of the low access frequency counters, the method further comprises: selecting at least one virtual cache within the third preset range after the sorting, and establishing a mapping relationship between it and the second physical memory area.

[0037] Preferably, at least one is selected from the virtual caches within the third preset range of the sort, and a mapping relationship is established between it and the second physical memory area, including: when the system is in an idle state, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the third preset range, and a mapping relationship is established between it and the second physical memory area.

[0038] Preferably, the number of low access frequency counters is fixed; after selecting at least one from the virtual caches within the third preset range after sorting and establishing a mapping relationship with the second physical memory area, the method further includes: marking the selected virtual cache and the virtual cache that establishes a mapping relationship with the second physical memory area; releasing the correspondence between the marked virtual cache and the low access frequency counter; resetting the value of the low access frequency counter whose correspondence is released to the initial value, so as to be used for subsequently establishing a correspondence with the virtual cache corresponding to the newly applied thread, and when subsequently executing the step of sorting the virtual caches in order from small to large in terms of the values ​​of the low access frequency counters, the low access frequency counters that have not been released from the correspondence and the low access frequency counters that have been released from the correspondence are sorted separately, and when subsequently executing the step of selecting at least one from the virtual caches within the second preset range before sorting and establishing a mapping relationship with the first physical memory area, the second preset range before sorting includes each part of the two separated sorts.

[0039] Preferably, the number of low access frequency counters is fixed; after selecting at least one from the virtual caches within the first second preset range of the sort and establishing a mapping relationship with the first physical memory area, the method further includes: marking the selected virtual cache that establishes a mapping relationship with the first physical memory area; releasing the correspondence between the marked virtual cache and the low access frequency counter; resetting the value of the low access frequency counter whose correspondence has been released to an initial value, so as to be used for subsequently establishing a correspondence with the virtual cache corresponding to the newly applied thread, and when subsequently executing the step of sorting the virtual caches in order from small to large in terms of the values ​​of the low access frequency counters, the low access frequency counters that have not been released from the correspondence and the low access frequency counters that have been released from the correspondence are sorted separately, and when subsequently executing the step of selecting at least one from the virtual caches within the first second preset range of the sort and establishing a mapping relationship with the first physical memory area, the first second preset range of the sort includes a portion of each of the two separated sorts.

[0040] Preferably, the conditions for pre-establishing a low access frequency counter for the virtual cache include: the capacity applied for the virtual cache is greater than or equal to a preset threshold; and / or, within a predetermined time period, the number of applications for the virtual cache is greater than or equal to a preset number; and / or, within a predetermined time period, the total time that the virtual cache occupies the physical memory area is greater than or equal to a preset time.

[0041] Preferably, after reducing the value of the pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, the method includes: recording the value of the low access frequency counter so that when the same step is executed again after the next startup, accumulation is performed based on the recorded value of the low access frequency counter.

[0042] Preferably, the method further comprises: restoring the value of the low access frequency counter to an initial value each time the computer is powered on.

[0043] According to another aspect of an embodiment of the present application, a system-on-chip is provided, comprising a memory management unit, first memory hardware, and second memory hardware, wherein the capacity of a single piece of the first memory hardware is smaller than the capacity of a single piece of the second memory hardware. When the system-on-chip runs a thread, the memory management unit can allocate the storage location of the thread using any one of the two thread storage location allocation methods mentioned above.

[0044] According to another aspect of an embodiment of the present application, a computing device is provided, including: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute any one of the two thread storage location allocation methods mentioned above.

[0045] According to another aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which an execution program is stored. When the execution program is executed, any one of the two thread storage location allocation methods mentioned above is implemented.

[0046] In the thread storage location allocation method provided in the embodiment of the present application, the access frequency of the physical memory area is calculated once every predetermined time period, and after sorting the physical memory areas based on the access frequency, a low-access frequency virtual cache corresponding to a part of the physical memory areas with a lower access frequency in the virtual cache is selected, and the value of the low-access frequency counter of the low-access frequency virtual cache is increased by a preset unit amount. As time accumulates, the number of counts increases, and it is finally possible to accurately determine which are low-access frequency threads and which are high-access frequency threads. After establishing a mapping relationship between at least one virtual cache with a lower value of the low-access frequency counter and the first physical memory area based on the determined result, the system operating power consumption can be effectively reduced, the system operation smoothness can be improved, and at the same time, the area occupied by the memory hardware can be ensured to be of an appropriate size.

[0047] Other beneficial effects of the present invention will be explained through the introduction of specific technical features and technical solutions in the specific implementation methods. Those skilled in the art should be able to understand the beneficial technical effects brought about by the introduction of these technical features and technical solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

[0049] Figure 1 A schematic diagram of a process flow of a thread storage location allocation method provided by an embodiment of the present invention;

[0050] Figure 2 A schematic diagram of the mapping relationship between virtual cache and physical memory provided by an embodiment of the present invention;

[0051] Figure 3 A schematic diagram of the correspondence between physical memory areas and counters provided in an embodiment of the present invention;

[0052] Figure 4 A flowchart illustrating some steps in a thread storage location allocation method provided by an embodiment of the present invention;

[0053] Figure 5 A flowchart illustrating some steps in a thread storage location allocation method provided by an embodiment of the present invention;

[0054] Figure 6 A schematic flow chart of the sub-steps of step 174 in the thread storage location allocation method provided in an embodiment of the present invention;

[0055] Figure 7 A flowchart of the steps after step 160 in the thread storage location allocation method provided by an embodiment of the present invention;

[0056] Figure 8 A flowchart of the steps after step 170 in the thread storage location allocation method provided by an embodiment of the present invention;

[0057] Figure 9 A schematic diagram of the modular structure of a thread storage location allocation device provided by an embodiment of the present invention;

[0058] Figure 10 A schematic diagram of the modular structure of a system-on-chip provided in an embodiment of the present invention;

[0059] Figure 11 A schematic diagram of the modular structure of a computing device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0060] The present invention is described below based on the following embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail. In order to avoid obscuring the essence of the present invention, well-known methods, processes, procedures, and components are not described in detail.

[0061] Furthermore, persons of ordinary skill in the art will appreciate that the figures provided herein are for illustration purposes only and are not necessarily drawn to scale.

[0062] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include," "comprising," and similar words should be construed in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to."

[0063] In the description of the present invention, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0064] The system-on-chip (SoC) is managed by the memory management unit (MMU) when it is running. The MMU mainly has the following functions: virtual address translation, access permission control and extended physical memory management. Virtual address translation refers to the translation of the virtual cache address accessed by the user into the actual physical address when the user accesses the memory, so that the system can access the actual physical address. Access permission control refers to the access permission control of some virtual cache addresses, so as to manage the access permission and scope of user programs. For example, the code segment is generally set to read-only. If a user program writes to the code segment, the system will trigger an exception. Extended physical memory management refers to the management of the system's physical memory resources, providing user programs with operation interfaces such as the application and release of physical memory.

[0065] During system operation, threads will continuously apply for and release memory according to task requirements, which will lead to memory fragmentation. The MMU can adjust the mapping relationship between the virtual cache and the physical memory area to make thread storage more centralized, so as to retain a large enough continuous address memory for subsequent threads to apply for storage.

[0066] For physical memory hardware, larger single-block capacity results in higher power consumption and higher latency during read and write accesses. Smaller single-block capacity results in lower power consumption and lower latency during read and write accesses. However, given the same capacity (i.e., the same number of bits), the area occupied by a single physical memory block is smaller than the combined area occupied by multiple physical memory blocks.

[0067] Currently, the MMU can only solve the problem of memory management fragmentation by adjusting the mapping relationship between the virtual cache and the physical memory area, but cannot allocate a more appropriate physical memory area to the virtual cache corresponding to the thread based on the physical memory area, access power consumption and latency.

[0068] Since the operating system generally randomly allocates virtual cache to threads, if you want to reduce system power consumption by allocating high-access-frequency threads to small-capacity memory areas, and save physical memory area by allocating low-access-frequency threads to large-capacity memory areas, how to determine whether the thread or its corresponding virtual cache has high access frequency or low access frequency becomes a difficulty in achieving this goal.

[0069] Based on this, the inventors of the present application came up with the idea of ​​first calculating the access frequency of each physical memory area, and then, based on the mapping relationship between the physical memory area and the virtual cache, determining all virtual caches mapped to the physical memory area with a high access frequency and the threads corresponding to this portion of the virtual cache as having a high access frequency. However, since a physical memory area generally has a mapping relationship with multiple virtual caches, when the access frequency calculated for a physical memory area is high, among the multiple virtual caches corresponding to the physical memory area, some may have a truly high access frequency, while others may actually have a low access frequency. If all virtual caches corresponding to the physical memory area are directly determined to have a high access frequency, some virtual caches that themselves have a low access frequency will be determined to have a high access frequency, resulting in an inaccurate determination result.

[0070] To address the above issue, the inventors discovered through research that when the calculated access frequency of a physical memory region is low, all corresponding virtual caches are likely to have low access frequencies. Based on this, the inventors employed reverse engineering to find the physical memory regions with low access frequencies through calculation. They then determined all virtual caches corresponding to these low-access physical memory regions and their corresponding threads as having low access frequencies, effectively eliminating the possibility of inaccurate determinations.

[0071] To further eliminate contingencies, for example, when a thread is actually a high-access-frequency thread, but is dormant during calculations and not actually running, resulting in it being determined as a low-access-frequency thread, contingencies can be eliminated by calculating once in each predetermined time period. As time and the number of calculations accumulate, contingencies can be eliminated. Furthermore, for statistical purposes, a low-access-frequency counter is established for the virtual cache. The value of the low-access-frequency counter corresponding to all virtual caches mapped to the physical memory addresses with low access frequencies obtained each time is changed by a preset unit amount (for example, it can be increased by 1). As time accumulates, it can be determined that the virtual cache with a smaller low-access-frequency counter value has a higher access frequency, and vice versa.

[0072] After accurately obtaining threads with low access frequency and threads with high access frequency, the operating system maps at least part of the virtual cache with high access frequency to the first physical memory area to achieve the goal of taking into account the area occupied by physical memory, access power consumption and delay.

[0073] The thread storage location allocation method provided in the embodiments of the present application includes but is not limited to being used in smart electronic devices such as mobile phones, computers, and servers.

[0074] Based on the above concept, according to one aspect of the embodiment of the present application, a thread storage location allocation method is provided. Figure 1, the figure shows the process of the method provided by an embodiment of the present application. The method is executed by a computing device, such as a mobile phone, a computer, a server, etc. As shown in the figure, the method includes:

[0075] Step 110: Allocate a virtual cache for the thread; there are multiple virtual caches, and a mapping relationship is established between the multiple virtual caches and the multiple physical memory areas, wherein the multiple physical memory areas include a first physical memory area and a second physical memory area, the first physical memory area belongs to the first memory hardware, the second physical memory area belongs to the second memory hardware, and the capacity of a single piece of the first memory hardware is smaller than the capacity of a single piece of the second memory hardware.

[0076] In this step, when the system starts up, a thread accesses and requests memory. It's understandable that this could be a first-time or second-time request. There can be one thread, with multiple virtual caches allocated to each thread making a first-time request. There can also be multiple threads, with at least one virtual cache allocated to each thread.

[0077] When a thread applies for memory, the operating system will first allocate a virtual cache (that is, a virtual memory area) for the thread, and establish a mapping relationship between the virtual cache and the physical memory area. The operating system is aware of this mapping relationship.

[0078] Since the capacity of a single piece of first memory hardware is smaller than the capacity of a single piece of second memory hardware, the first physical memory area consumes less power and has a shorter latency when accessed than the second physical memory area. However, if the capacities are the same, the area occupied by the total amount of the first memory hardware will be larger than the area occupied by the total amount of the second memory hardware.

[0079] See also Figure 2 The figure shows the corresponding relationship between threads, virtual cache and physical memory area in an embodiment provided by the present application. Taking the embodiment shown in the figure as an example, the system includes a single block of 32k first memory hardware (SmallRam, referred to as R s ) and a second memory hardware with a single block capacity of 64k (BigRam, referred to as R b ), R s Every 8k is divided into a first physical memory area, there are 4 first physical memory areas in total, R bEvery 8KB is divided into a second physical memory region, for a total of eight second physical memory regions. After receiving a thread, the system matches it with a virtual cache. In the figure, PageT0, PageT1, PageT2…PageTn represent the virtual caches matched to the threads, and Page0, Page1, Page2…Pagen represent physical memory addresses. Physical memory addresses correspond to physical memory regions. The MMU establishes a mapping relationship between the virtual caches PageT0, PageT1, PageT2…PageTn and the physical memory addresses Page0, Page1, Page2…Pagen.

[0080] Step 120: Calculate the access frequency of each physical memory region within each predetermined time period.

[0081] like Figure 3 As shown, in this step, an access counter can be assigned to each physical memory area. When a physical memory area is accessed once, the value of its corresponding access counter is increased by 1. The predetermined time period can be, for example, 1 second. The access counter records the number of accesses to each physical memory area in each 1-second interval, and the ratio between the number of accesses to each physical memory area and the total number of accesses to all physical memory areas in 1 second is calculated to obtain the access frequency F of each physical memory area. It should be noted that since the access frequency of each physical memory area is calculated once in each predetermined time period, all counters can be cleared after the calculation of a single predetermined time period is completed to facilitate the calculation of the access frequency in the next predetermined time period.

[0082] It is understandable that the access frequency of the physical memory area can also be achieved through existing digital circuits, such as infinite impulse response filters, etc., which will not be elaborated here.

[0083] Step 130: Selecting a physical memory area within the first preset range as a low-access-frequency physical memory area in ascending order of access frequency.

[0084] It should be noted that, in this step, sorting and selection are performed once every predetermined time period described in step 120 .

[0085] by Figure 3For example, as shown in the figure, if the counter values of the physical memory regions from bottom to top are 9, 5, 1, 12, 3, 6, 0, 4, 0, 2, 5, 3 respectively, the corresponding access frequencies are F0 = 0.18, F1 = 0.1, F2 = 0.02, F3 = 0.24, F4 = 0.06, F5 = 0.12, F6 = 0, F7 = 0.08, F8 = 0, F9 = 0.04, F10 = 0.1, F11 = 0.06 respectively. After sorting in ascending order, we get F6 = F8 < F2 < F9 < F4 < F11 < F7 < F1 = F10 < F5 < F0 < F3. The first preset range can be 25% of the total number of physical memory regions, that is, 0.25 * 12 = 3. Then the selected physical memory regions with low access frequencies are the second physical memory regions corresponding to F6 and F8 and the first physical memory region corresponding to F2.

[0086] Step 140: According to the mapping relationship, determine the virtual cache corresponding to the physical memory region with low access frequency as the virtual cache with low access frequency.

[0087] Please refer to Figure 2 and Figure 3 , if the physical memory addresses of the second physical memory regions corresponding to F6 and F8 are Page300 - Page350 and Page400 - Page450, and the physical memory address of the first physical memory region corresponding to F2 is Page50 - Page100, then the virtual caches mapped to Page300 - Page350, Page400 - Page45, Page50 - Page100 in the virtual cache can be, for example, PageT2, PageT7, PageT10, PageT12, PageT16, PageT17, PageT22, PageT25, PageT26 and PageT28. These virtual caches PageT2, PageT7, PageT10, PageT12, PageT16, PageT17, PageT22, PageT25, PageT26 and PageT28 are the virtual caches with low access frequency.

[0088] It also needs to be noted that in this step, the virtual cache with low access frequency is also determined every predetermined time period.

[0089] Step 150: Increase the value of the pre - established low - access - frequency counter corresponding to the virtual cache with low access frequency by a preset unit amount, where the initial value of the low - access - frequency counter is the preset minimum value.

[0090] Such as Figure 2As shown in , a specific method for pre-establishing a low access frequency counter for the virtual cache can be that the software counts the virtual cache. Specifically, the low access frequency counters corresponding to the virtual caches PageT0 and PageT1 matched by thread Thread0 are represented as Thread0_LFP_cnt0 and Thread0_LFP_cnt1, respectively, and the access frequency counter corresponding to the virtual cache PageT2 matched by thread Thread1 is represented as Thread1 LFP cnt2.

[0091] The initial value of the low access frequency counter is a preset minimum value, which means that during the operation, the value of the low access frequency counter only increases, not decreases, and during the operation, when the value of the low access frequency counter increases to a certain extent, if the reset condition is met, the value of the low access frequency counter can be reinitialized to the preset minimum value. Therefore, among all the values ​​of the low access frequency counter in the entire operation process, the initial value is always the minimum. The preset minimum value can be, for example, 0, 1, 10, etc., and the specific value is not limited here. The purpose of setting the initial value of the low access frequency counter to the minimum value is to enable the subsequent value of the low access frequency counter to increase over a wide range to facilitate sufficient counting.

[0092] It should be noted that, in some embodiments, low access frequency counters may be pre-established for all virtual caches at once, and in this embodiment, the step of pre-establishing low access frequency counters for all virtual caches has no sequential relationship with the above steps 110-140.

[0093] In some other embodiments, a low access frequency counter may be pre-established only for the low access frequency virtual cache determined in step 140, and when a new low access frequency virtual cache is determined in the next predetermined time period, a low access frequency counter may be pre-established for the new low access frequency virtual cache. For this embodiment, the step of pre-establishing low access frequency counters for all virtual caches needs to be performed after the above-mentioned step 140.

[0094] In this step, increasing the value of the low access frequency counter by the preset unit amount may specifically be adding 1 to the value of the low access frequency counter corresponding to the low access frequency virtual cache.

[0095] like Figure 2As shown in, for example, when the low access frequency virtual cache determined in a certain unit time is PageT2, PageT7, PageT10, PageT12, PageT16, PageT17, PageT22, PageT25, PageT26 and PageT28, wherein the thread corresponding to PageT2, PageT7, PageT10, PageT12, PageT16, PageT17 is Thread1, and PageT22, PageT25, PageT26 and PageT28 correspond to thread Thread2, then the values ​​of the low access frequency counters Thread1_LFP_cnt2, Thread1_LFP_cnt7, Thread1_LFP_cnt10, Thread1_LFP_cnt12, Thread1_LFP_cnt16, Thread1_LFP_cnt17, Thread2_LFP_cnt22, Thread1_LFP_cnt25, Thread1_LFP_cnt26 and Thread1_LFP_cnt28 are all increased by 1.

[0096] It should be noted that the above steps 130 to 150 are performed once in each predetermined time period, so that as time accumulates, the value of the low access frequency counter corresponding to the virtual cache with low access frequency will become larger and larger, and then the system can accurately determine which threads are low access frequency threads and which threads are high access frequency threads based on the value of the low access frequency counter corresponding to each virtual cache.

[0097] Step 160: Sort the virtual caches in ascending order of the values ​​of the low access frequency counters.

[0098] In this step, the virtual caches are sorted in ascending order according to the values ​​of the low access frequency counters, which is equivalent to sorting the threads corresponding to the virtual caches in descending order according to the actual access frequencies.

[0099] Step 170: Select at least one virtual cache in the sorted first second preset range, and establish a mapping relationship between the virtual cache and the first physical memory area.

[0100] The second preset range may be 30% of the total number of virtual caches. For example, when the total number of virtual caches is 10, the first three virtual caches with the highest access frequency are selected in order.

[0101] After sorting the threads corresponding to the virtual caches from high to low according to their actual access frequencies, in this step, at least one virtual cache corresponding to a thread with a smaller value of a low access frequency counter (i.e., a higher access frequency) is adjusted so that it is mapped to the first physical memory area. In this way, while ensuring that the area occupied by the memory hardware is appropriate, threads with high access frequencies are stored in the first physical memory area with relatively low power consumption and latency, thereby reducing system operating power consumption and improving smoothness.

[0102] It should be noted that in step 170, if the system finds through the mapping relationship table that the virtual cache matching the current thread is mapped to the second physical memory area, it will be adjusted and mapped to the first physical memory area; if it is found that the virtual cache matching the current thread has been mapped to the first physical memory area, no adjustment will be made.

[0103] In the thread storage location allocation method provided in the embodiment of the present application, the access frequency of the physical memory area is calculated once every predetermined time period, and after sorting the physical memory areas based on the access frequency, a low-access frequency virtual cache corresponding to a part of the physical memory areas with a lower access frequency in the virtual cache is selected, and the value of the low-access frequency counter of the low-access frequency virtual cache is increased by a preset unit amount. As time accumulates, the number of counts increases, and it is finally possible to accurately determine which are low-access frequency threads and which are high-access frequency threads. After establishing a mapping relationship between at least one virtual cache with a lower value of the low-access frequency counter and the first physical memory area based on the determined result, the system operating power consumption can be effectively reduced, the system operation smoothness can be improved, and at the same time, the area occupied by the memory hardware can be ensured to be of an appropriate size.

[0104] The present embodiment also provides another thread storage location allocation method. Specifically, step 150 is replaced by the following steps: reducing the value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, wherein the initial value of the low access frequency counter is a preset maximum value. Step 160 is replaced by the following steps: sorting the virtual caches in descending order of the value of the low access frequency counter. The remaining steps remain consistent with the thread storage location allocation method provided in the above embodiment.

[0105] It is understood that decreasing the value of the pre-established low-access frequency counter corresponding to the low-access frequency virtual cache, whose initial value is the preset maximum value, by a preset unit and sorting the virtual caches in descending order of the low-access frequency counter value, and increasing the value of the pre-established low-access frequency counter corresponding to the low-access frequency virtual cache by a preset unit in step 150 and sorting the virtual caches in ascending order of the low-access frequency counter value in step 160, respectively, serve the same purpose in their respective solutions. The low-access frequency counter is counted by increasing the preset unit and decreasing the preset unit, respectively, and the virtual caches are sorted in descending order of the low-access frequency counter value by decreasing the preset unit, such that the virtual caches corresponding to the lower low-access frequency counters at the front of the sort have higher access frequencies. Using the method of step 150, the virtual caches are sorted in ascending order of the low-access frequency counter value in step 160, similarly such that the virtual caches corresponding to the lower low-access frequency counters at the front of the sort have higher access frequencies. Therefore, the two have corresponding technical features and solve the same technical problems in their corresponding solutions.

[0106] It should also be noted that the initial value of the low access frequency counter is a preset maximum value, which is the opposite of the preset minimum value described above. This means that during operation, the value of the low access frequency counter only decreases, not increases, and the initial value is always the largest among all the values ​​of the low access frequency counter during the entire operation process. Specifically, the preset maximum value can be, for example, 999, 9999, 99999, etc. The specific value is not limited here.

[0107] In order to ensure smooth adjustment of the mapping relationship, this application proposes an implementation method. Figure 4 , the figure shows a further partial step process of the thread storage location allocation method provided by an embodiment of the present application. As shown in the figure, before step 160, the following steps are also included:

[0108] Step 1501: Determine whether the total remaining capacity of all first physical memory areas is less than or equal to a preset capacity value.

[0109] The preset capacity value is the reserved swap area capacity value preset in the first physical memory area. Its purpose is to continue to provide storage for the threads running in the first physical memory area by reserving the swap area when the remaining capacity of the first physical memory area is insufficient. The preset capacity value can be set accordingly based on the total capacity of all first physical memory areas. Figure 3 Taking the total capacity of all first physical memories as 32k as an example, the preset capacity value can be set to 8k.

[0110] If the answer in step 1501 is yes, then step 160 is executed.

[0111] If the result of step 1501 is no, step 1503 is executed: a mapping relationship is established between the virtual cache and the first physical memory area.

[0112] In this embodiment, when the total remaining capacity of all first physical memory regions is greater than a preset capacity value, the virtual caches matched by any thread are mapped to the first physical memory region. That is, all threads are stored in the first physical memory region. Based on the low power consumption and short latency of accessing the first physical memory region, this can significantly reduce system power consumption and improve system operation smoothness. When the total remaining capacity of all first physical memory regions is less than or equal to the preset capacity value, the virtual caches are sorted, and at least one highly accessed virtual cache is selected from the sort and mapped and stored in the first physical memory region, thereby maintaining low power consumption and short latency for the system.

[0113] It is understandable that this embodiment is also applicable to another thread storage location allocation method provided in the embodiments of this application. However, it should be noted that when used as a further embodiment of another thread storage location allocation method, steps 150 and 160 mentioned in each embodiment are correspondingly adjusted to replace steps 150 and 160 in the other thread storage location allocation method, and the same applies hereinafter.

[0114] For the situation where memory is requested again after the thread is released, this application proposes an implementation method. For details, please refer to Figure 5 , the figure shows a further partial step process of the thread storage location allocation method provided by an embodiment of the present application. As shown in the figure, before step 160, the method further includes:

[0115] Step 1502: Allocate the same virtual cache as the last time the thread applied for the cache again.

[0116] When the same thread accesses memory at different times, the virtual cache matched by the MMU is the same. That is, when the thread applies to access memory for the first time, the MMU first matches it with a virtual cache. When the thread is released and applies to access memory again, the MMU will match it with the same virtual cache as the last application.

[0117] In subsequent step 160 , after allocating the same virtual cache to the re-applying thread, the system sorts the virtual cache according to the values ​​of the low access frequency counter corresponding to the virtual cache counted in steps 120 to 150 .

[0118] Step 170 includes the following steps:

[0119] Step 171 : Determine whether the virtual cache corresponding to the thread that applies for cache again is within the first second preset range of the sorting.

[0120] If the result of step 171 is yes, step 173 is executed: a mapping relationship is established between the virtual cache corresponding to the thread that applies for cache again and the first physical memory area.

[0121] In this step, according to the sorting situation, if the virtual cache corresponding to the re-applying thread is within the first second preset range in the sorting, it indicates that the thread is a high-access frequency thread. By establishing a mapping relationship between the virtual cache corresponding to the thread and the first physical memory area, the system power consumption can be effectively reduced and the smoothness of the system operation can be improved.

[0122] In this embodiment, by establishing a mapping relationship between the virtual cache corresponding to the re-applied high-access frequency thread and the first physical memory area, it is ensured that the virtual cache corresponding to the high-access frequency thread can be mapped to the first physical memory area in a timely manner, thereby reducing power consumption and latency in a timely manner.

[0123] It is understandable that this implementation is also applicable to another thread storage location allocation method provided in an embodiment of the present application.

[0124] See also Figure 6 , the figure shows the sub-step process of step 170. As shown in the figure, in some embodiments, step 170 includes the following steps:

[0125] Step 174: When the system is in an idle state, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the second preset range, and a mapping relationship is established between the virtual cache and the first physical memory area.

[0126] Direct Memory Access (DMA), also known as block data transfer, does not perform save and restore operations during data transfer. DMA operations are independent of CPU access, so forcibly moving data can lead to data inconsistencies.

[0127] The idle state in this step refers to the state when the system has no thread task execution requirements.

[0128] In this embodiment, when the system is in an idle state, a virtual cache that does not perform direct memory operations is selected from the virtual cache within the second preset range, and a mapping relationship is established between it and the first physical memory area. This reduces system power consumption and shortens access latency while ensuring that the transferred data will not be lost.

[0129] It is understandable that this implementation is also applicable to another thread storage location allocation method provided in an embodiment of the present application.

[0130] Please continue reading Figure 6 In some embodiments, step 174 includes the following steps:

[0131] Step 1741: When the system is in an idle state, determine whether the total remaining capacity of all first physical memory areas is less than or equal to a preset capacity value.

[0132] If the answer in step 1741 is no, then the following steps are performed:

[0133] Step 1743: Select a virtual cache that does not perform direct memory operations from the virtual caches within the second preset range, and establish a mapping relationship between the virtual cache and the first physical memory area.

[0134] It is understandable that the migration can be performed only when the remaining total capacity of the first physical memory area meets the capacity required after the virtual cache migration. Otherwise, the storage data address of the virtual cache will be discontinuous, resulting in data loss.

[0135] Therefore, in this embodiment, when the system is in an idle state, it is first determined whether the remaining total capacity of all first physical memory areas meets the storage requirements of the virtual cache to be moved. When the storage requirements are met, the virtual cache is moved to ensure that the data can be completely moved and to prevent data loss.

[0136] It is understandable that this implementation is also applicable to another thread storage location allocation method provided in an embodiment of the present application.

[0137] See also Figure 7 , the figure shows the process of steps after step 160. As shown in the figure, in some embodiments, the following steps are further included after step 160:

[0138] Step 1601: Select at least one virtual cache from the sorted virtual caches within the third preset range, and establish a mapping relationship between the virtual cache and the second physical memory area.

[0139] The third preset range may specifically be 30% of the total virtual buffer amount.

[0140] In this embodiment, the virtual caches in the third preset range after the sorting have a low access frequency. Therefore, after establishing a mapping relationship between at least one of the virtual caches and the second physical memory area, it will not cause a significant increase in power consumption and latency. Furthermore, it can also free up a certain amount of space in the first physical memory area to store threads with high access frequency, so as to take into account power consumption, latency and the area occupied by memory hardware at the same time.

[0141] It is understandable that this implementation is also applicable to another thread storage location allocation method provided in an embodiment of the present application.

[0142] In some embodiments, the step of selecting at least one virtual cache in the third preset range after sorting and establishing a mapping relationship between the virtual cache and the second physical memory area includes:

[0143] When the system is in an idle state, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the third preset range, and a mapping relationship is established between the virtual cache and the second physical memory area.

[0144] In this embodiment, when the system is in an idle state, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the third preset range, and a mapping relationship is established between it and the second physical memory area, so that the low-access frequency virtual cache is transferred while ensuring that the transferred data will not be lost.

[0145] It is understandable that this implementation is also applicable to another thread storage location allocation method provided in an embodiment of the present application.

[0146] Please refer again Figure 7 In some embodiments, the number of low access frequency counters is fixed, and after step 1601, the following steps are further included:

[0147] Step 1603: Mark the selected virtual cache that has a mapping relationship with the second physical memory area.

[0148] Step 1605: cancel the correspondence between the marked virtual cache and the low access frequency counter.

[0149] It should be noted that the marked virtual cache will no longer have a corresponding low access frequency counter.

[0150] It's understandable that during actual operating system operation, a large amount of virtual cache is allocated and released. If a large number of low-frequency counters are established for these virtual caches, this will occupy a large amount of operating system memory, thereby impacting the operating system's computing power. Therefore, by setting the number of low-frequency counters to a fixed value, such as 50, 100, or 500, we ensure that the memory usage of these low-frequency counters remains within a reasonable range.

[0151] Considering that a fixed number of low access frequency counters cannot count more virtual caches, for the virtual cache moved to the second physical memory area, it can be basically determined that the corresponding thread is a low access frequency thread, so it is meaningless to count it using the low access frequency counter later.

[0152] Therefore, in steps 1603 to 1605, the virtual cache moved to the second physical memory area is marked, and the correspondence between the marked virtual cache and the low access frequency counter is released. On the one hand, this ensures that the low access frequency counter will not be allocated to the marked virtual cache in the future. On the other hand, the low access frequency counter that has been released from the correspondence is released so that it can be used to count the virtual cache corresponding to the newly applied thread, thereby determining the access frequency of threads corresponding to more virtual caches.

[0153] Step 1607: reset the value of the low access frequency counter whose correspondence has been released to the initial value, so as to be used for subsequently establishing a correspondence with the virtual cache corresponding to the newly applied thread, and when step 160 is subsequently executed, the low access frequency counters whose correspondence has not been released and the low access frequency counters whose correspondence has been released are sorted separately, and when step 170 is subsequently executed, the first second preset range of the sorting includes a part of each of the two separated sorts.

[0154] In this step, the value of the low access frequency counter whose correspondence is released is reset to the initial value so that it is ready for counting the virtual cache corresponding to the newly applied thread in the future. Furthermore, since only some of the low access frequency counters are released and reset, the other part of the low access frequency counters still have the previously recorded values. Based on this, if the values ​​of all the low access frequency counters are still sorted uniformly when step 160 is subsequently executed, the values ​​between the low access frequency counters whose correspondence is released and the low access frequency counters that have not been released are not comparable, resulting in the sorting having no reference value. Therefore, when step 160 is subsequently executed, the low access frequency counters that have not been released and the virtual cache that has been released are sorted separately to ensure that the subsequent results are accurate and reliable.

[0155] It is understandable that this implementation is also applicable to another thread storage location allocation method provided in an embodiment of the present application.

[0156] See also Figure 8 , the figure shows the steps after step 170. As shown in the figure, in some embodiments, the number of low access frequency counters is fixed, and the following steps are further included after step 170:

[0157] Step 1701: Mark the selected virtual cache that has a mapping relationship with the first physical memory area.

[0158] Step 1703: cancel the correspondence between the marked virtual cache and the low access frequency counter.

[0159] It should be noted that the marked virtual cache will no longer have a corresponding low access frequency counter.

[0160] Step 1705: reset the value of the low access frequency counter whose correspondence has been released to the initial value, so as to be used for subsequently establishing a correspondence with the virtual cache corresponding to the newly applied thread, and when step 160 is subsequently executed, the low access frequency counters whose correspondence has not been released and the low access frequency counters whose correspondence has been released are sorted separately, and when step 170 is subsequently executed, the first second preset range of the sorting includes a part of each of the two separated sorts.

[0161] It can be understood that the functions of steps 1701 to 1705 are the same as those of steps 1603 to 1607 above. The difference is that steps 1701 to 1705 are to release the low access frequency counter corresponding to the virtual cache moved to the first physical memory area, while steps 1603 to 1607 above are to release the low access frequency counter corresponding to the virtual cache moved to the second physical memory area. The rest of the operations are basically the same and will not be repeated here.

[0162] It is understandable that this implementation is also applicable to another thread storage location allocation method provided in an embodiment of the present application.

[0163] In some embodiments of the present application, the condition for pre-establishing a low access frequency counter for the virtual cache includes: the capacity requested by the virtual cache is greater than or equal to a preset threshold.

[0164] Specifically, the process of pre-establishing a low access frequency counter for the virtual cache may include the following steps:

[0165] Determine whether the capacity of the virtual cache application is greater than or equal to a preset threshold;

[0166] If the judgment result is yes, a low access frequency counter is established for the virtual cache.

[0167] The preset threshold can be set to 1kB, for example. That is, only when the requested capacity of the virtual cache is greater than 1kB is a virtual cache counter established for it and the low access frequency value counted. It is understandable that since the number of virtual caches is large during system operation, establishing low access frequency counters and counting low access frequency values ​​for all virtual caches would occupy a large amount of memory space and computing power. Based on this, by establishing a low access frequency counter for virtual caches with a requested capacity greater than the preset threshold, the memory space and computing power occupied can be reduced.

[0168] It is understandable that this implementation is also applicable to another thread storage location allocation method provided in an embodiment of the present application.

[0169] In some embodiments of the present application, the condition for pre-establishing a low access frequency counter for the virtual cache includes: within a predetermined time period, the number of applications to the virtual cache is greater than or equal to a preset number.

[0170] Specifically, the process of pre-establishing a low access frequency counter for the virtual cache may include the following steps:

[0171] Recording the number of applications and / or releases of each virtual cache within a predetermined time period using a counter;

[0172] A low access frequency counter is established for the virtual cache corresponding to the counter whose count value is greater than or equal to the preset number of times.

[0173] The predetermined time period may be 1 second, 1 minute, or 1 hour, etc. The preset number of times may be, for example, 10, 20, 50, 100, etc.

[0174] Similarly, by establishing a low access frequency counter for a virtual cache whose number of requests and / or releases within a predetermined time period is greater than or equal to a preset number, the occupation of memory space and computing power can be reduced.

[0175] It is understandable that this implementation is also applicable to another thread storage location allocation method provided in an embodiment of the present application.

[0176] In some embodiments of the present application, the condition for pre-establishing a low access frequency counter for the virtual cache includes: within a predetermined time period, the total time length of the virtual cache occupying the physical memory area is greater than or equal to a preset time length.

[0177] Specifically, the process of pre-establishing a low access frequency counter for the virtual cache may include the following steps:

[0178] Record the time nodes of each virtual cache application and release;

[0179] By taking the difference between the time node of each request and the time node of each release, the duration of each virtual cache occupying the physical memory area is obtained;

[0180] Summing up the duration of each virtual cache occupying the physical memory area within the predetermined time period to obtain a total duration of the virtual cache occupying the physical memory area within the predetermined time period;

[0181] A low access frequency counter is established for a virtual cache whose total occupation time of the physical memory area is greater than or equal to a preset time.

[0182] The predetermined time period may be 1 second, 1 minute, or 1 hour, and the preset duration may be 10 milliseconds, 10 seconds, 10 minutes, or the like.

[0183] Similarly, by establishing a low access frequency counter for a virtual cache whose total occupation time of the physical memory area within a predetermined time period is greater than or equal to a preset time period, the occupation of memory space and computing power can be reduced.

[0184] It is understandable that this implementation is also applicable to another thread storage location allocation method provided in an embodiment of the present application.

[0185] It should be noted that, for the above-mentioned multiple conditions for pre-establishing a low access frequency counter for the virtual cache, one can select one and apply it, or multiple conditions can be combined. That is, a low access frequency counter is established for the virtual cache only when it meets multiple conditions at the same time.

[0186] In some embodiments, after step 150, the method further includes the following steps:

[0187] The value of the low access frequency counter is recorded so that when step 150 is executed again after the computer is powered on next time, the value of the low access frequency counter is accumulated based on the recorded value.

[0188] Specifically, the system may be configured with a power-off retention data cache space, for example, via a flash disk, to achieve storage of low-access frequency values ​​during power off.

[0189] By recording and retaining the value of the low access frequency counter before the last shutdown, and accumulating it based on the recorded value of the low access frequency counter when the computer is turned on next time, the memory allocation after the next startup can be made more accurate and reasonable, thereby improving the system's low power management capabilities.

[0190] It is understandable that this implementation is also applicable to another thread storage location allocation method provided in an embodiment of the present application.

[0191] In some embodiments, the method further includes the following steps: restoring the value of the low access frequency counter to an initial value each time the computer is powered on.

[0192] Specifically, in an implementation where the system does not include a power-off retentive data cache, the value of the low-access frequency counter becomes a random number at each startup. Accumulating this random number would result in inaccurate calculation results. Therefore, at each startup, all low-access frequency counters are reset to zero, increasing their values ​​by a preset unit from zero. This ensures the accuracy of the calculation results and accurately determines the high-access frequency virtual cache and the low-access frequency virtual cache.

[0193] It is understandable that this implementation is also applicable to another thread storage location allocation method provided in an embodiment of the present application.

[0194] According to one aspect of the embodiment of the present application, a thread storage location allocation device is provided. Figure 9 The figure shows the structure of a thread storage location allocation device. As shown in the figure, the thread storage location allocation device 200 includes a first allocation module 210, a calculation module 220, a selection module 230, a determination module 240, an increase module 250, a sorting module 260, and a first mapping module 270. The first allocation module 210 is used to allocate virtual caches to threads. There are multiple virtual caches, and mapping relationships are established between the multiple virtual caches and multiple physical memory regions. The multiple physical memory regions include a first physical memory region and a second physical memory region. The first physical memory region belongs to a first memory hardware, the second physical memory region belongs to a second memory hardware, and the capacity of a single piece of the first memory hardware is smaller than the capacity of a single piece of the second memory hardware. The calculation module 220 is used to calculate the access frequency of each physical memory region within each predetermined time period. The selection module 230 is used to select physical memory regions within a first preset range as low-access-frequency physical memory regions in ascending order of access frequency. The determination module 240 is used to determine, based on the mapping relationship, the virtual cache corresponding to the low-access-frequency physical memory region as the low-access-frequency virtual cache. The increasing module 250 is configured to increase the value of a pre-established low access frequency counter corresponding to a low access frequency virtual cache by a preset unit amount, wherein the initial value of the low access frequency counter is a preset minimum value. The sorting module 260 is configured to sort the virtual caches in ascending order of the low access frequency counter value. The first mapping module 270 is configured to select at least one virtual cache within a second preset range before sorting and establish a mapping relationship between the virtual cache and the first physical memory region.

[0195] According to another aspect of an embodiment of the present application, another thread storage location allocation device is provided. Specifically, the increase module 250 is replaced by a decrease module, which is used to reduce the value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, wherein the initial value of the low access frequency counter is a preset maximum value. The function of the sorting module 260 is also replaced by a function for sorting the virtual caches in descending order of the value of the low access frequency counter. The functions of the remaining modules remain the same.

[0196] In some embodiments, the device further includes a judgment module, a control module, and a second mapping module. The judgment module is configured to determine whether the total remaining capacity of all first physical memory regions is less than or equal to a preset capacity value. The control module is configured to, when the judgment module determines that the remaining capacity is yes, control the sorting module to execute the step of sorting the virtual cache in ascending order of the values ​​of the low access frequency counter. The second mapping module is configured to establish a mapping relationship between the virtual cache and the first physical memory region when the judgment module determines that the remaining capacity is no.

[0197] It can be understood that this implementation is also applicable to another thread storage location allocation device provided in an embodiment of the present application.

[0198] In some embodiments, the apparatus further includes a second allocation module configured to allocate the same virtual cache memory to the thread that re-applies for cache memory as the thread that previously applied for cache memory. The first mapping module includes a first judgment submodule and a first mapping submodule. The first judgment submodule is configured to determine whether the virtual cache memory corresponding to the thread that re-applies for cache memory is within a first second preset range of the sorting order. The first mapping submodule is configured to establish a mapping relationship between the virtual cache memory corresponding to the thread that re-applies for cache memory and the first physical memory area when the judgment submodule determines that the virtual cache memory is within a first second preset range of the sorting order.

[0199] It can be understood that this implementation is also applicable to another thread storage location allocation device provided in an embodiment of the present application.

[0200] In some embodiments, the first mapping module includes a second mapping submodule, which is used to select a virtual cache that does not perform direct memory operations from the virtual caches within the second preset range when the system is in an idle state, and establish a mapping relationship between it and the first physical memory area.

[0201] It can be understood that this implementation is also applicable to another thread storage location allocation device provided in an embodiment of the present application.

[0202] In some embodiments, the second mapping submodule includes: a judgment unit and a control unit. The judgment unit is configured to determine, when the system is in an idle state, whether the total remaining capacity of all first physical memory regions is less than or equal to a preset capacity value. The control unit is configured to, if the judgment unit determines that the remaining capacity is not, select a virtual cache within the virtual caches within the second preset range that has not performed direct memory operations, and establish a mapping relationship between the virtual cache and the first physical memory region.

[0203] It can be understood that this implementation is also applicable to another thread storage location allocation device provided in an embodiment of the present application.

[0204] In some embodiments, the apparatus includes a third mapping module configured to select at least one virtual cache from the sorted virtual caches within a third preset range and establish a mapping relationship between the virtual cache and the second physical memory area.

[0205] It can be understood that this implementation is also applicable to another thread storage location allocation device provided in an embodiment of the present application.

[0206] In some embodiments, the third mapping module includes a third mapping submodule, which is used to select a virtual cache that does not perform direct memory operations from the virtual caches within the third preset range when the system is in an idle state, and establish a mapping relationship between it and the second physical memory area.

[0207] It can be understood that this implementation is also applicable to another thread storage location allocation device provided in an embodiment of the present application.

[0208] In some embodiments, the number of low access frequency counters is fixed; the apparatus further comprises: a first marking module, a first removing module, and a first resetting module. The first marking module is configured to mark the selected virtual cache mapped to the second physical memory region after the second mapping module selects at least one virtual cache within the third preset range after sorting and establishes a mapping relationship between the selected virtual cache and the second physical memory region. The first removing module is configured to remove the mapping relationship between the marked virtual cache and the low access frequency counter. The first resetting module is configured to reset the value of the removed low access frequency counter to an initial value for subsequent mapping with the virtual cache corresponding to a newly requested thread. When the sorting module subsequently sorts the virtual caches in ascending order of the low access frequency counter values, the low access frequency counters that have not been removed from the mapping relationship are sorted separately from the virtual caches that have been removed from the mapping relationship. When the first mapping module subsequently selects at least one virtual cache within the second preset range before sorting and establishes a mapping relationship between the selected virtual cache and the first physical memory region, the second preset range before sorting includes portions of each of the two separated sorts.

[0209] It can be understood that this implementation is also applicable to another thread storage location allocation device provided in an embodiment of the present application.

[0210] In some embodiments, the number of low access frequency counters is fixed; the apparatus further comprises: a second marking module, a second removing module, and a second resetting module. The second marking module is configured to mark the selected virtual cache mapped to the first physical memory region after the first mapping module selects at least one virtual cache within a second preset range before sorting and establishes a mapping relationship between the selected virtual cache and the first physical memory region. The second removing module is configured to remove the mapping relationship between the marked virtual cache and the low access frequency counter. The second resetting module is configured to reset the value of the removed low access frequency counter to an initial value for subsequent mapping with the virtual cache corresponding to a newly requested thread. Furthermore, when the sorting module subsequently sorts the virtual caches in ascending order of the low access frequency counter values, the low access frequency counters that have not been removed from the mapping relationship are sorted separately from the virtual caches that have been removed from the mapping relationship. Furthermore, when the first mapping module subsequently selects at least one virtual cache within the second preset range before sorting and establishes a mapping relationship between the virtual cache and the first physical memory region, the second preset range before sorting includes portions of each of the two separated sorts.

[0211] It can be understood that this implementation is also applicable to another thread storage location allocation device provided in an embodiment of the present application.

[0212] In some embodiments, the conditions for pre-establishing a low access frequency counter for the virtual cache include: the capacity of the virtual cache application is greater than or equal to a preset threshold; and / or, within a predetermined time period, the number of virtual cache application times is greater than or equal to a preset number; and / or, within a predetermined time period, the total time the virtual cache occupies the physical memory area is greater than or equal to a preset time.

[0213] It can be understood that this implementation is also applicable to another thread storage location allocation device provided in an embodiment of the present application.

[0214] In some embodiments, the device further includes a recording module for recording the value of the low access frequency counter so that when the same step is executed again after the device is powered on next time, accumulation is performed based on the recorded value of the low access frequency counter.

[0215] It can be understood that this implementation is also applicable to another thread storage location allocation device provided in an embodiment of the present application.

[0216] In some embodiments, the apparatus further comprises: a recovery module, configured to restore the value of the low access frequency counter to an initial value each time the apparatus is powered on.

[0217] It can be understood that this implementation is also applicable to another thread storage location allocation device provided in an embodiment of the present application.

[0218] According to one aspect of the embodiment of the present application, a system-on-chip is also provided, also known as a SOC (System on Chip, SoC for short). Figure 10 As shown in the figure, the SoC 300 includes a memory management unit 310, a first memory hardware 320, and a second memory hardware 330. The capacity of a single piece of the first memory hardware 320 is smaller than the capacity of a single piece of the second memory hardware 330. When the SoC 300 runs a thread, the memory management unit 310 can allocate the thread's storage location using either of the two thread storage location allocation methods provided in the above embodiments.

[0219] According to one aspect of the embodiment of the present application, a computing device is also provided. The specific embodiment of the present application does not limit the specific implementation method of the computing device. For details, please refer to Figure 11 , the figure shows the structure of the computing device.

[0220] like Figure 11As shown in , the computing device may include: a processor (processor) 402 , a communication interface (Communications Interface) 404 , a memory (memory) 406 , and a communication bus 408 .

[0221] Processor 402, communication interface 404, and memory 406 communicate with each other via communication bus 408. Communication interface 404 is used to communicate with other devices, such as clients or other server network elements. Processor 402 is used to execute program 410, which may specifically perform the relevant steps of either of the two thread storage location allocation methods provided in the above embodiments.

[0222] Specifically, the program 410 may include program code including computer-executable instructions.

[0223] Processor 402 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application. The one or more processors included in the computing device may be processors of the same type, such as one or more CPUs, or may be processors of different types, such as one or more CPUs and one or more ASICs.

[0224] The memory 406 is used to store the program 410. The memory 406 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0225] An embodiment of the present invention further provides a computer-readable storage medium, such as a CD, which stores an execution program. When the execution program is executed, it implements any one of the two thread storage location allocation methods provided in the above embodiments.

[0226] It should be noted that the computer-readable storage medium described in the embodiments of the present disclosure is not limited to the embodiments given above, and can also be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the embodiments of the present disclosure, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or device.

[0227] Among them, the flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or part of the code, which contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, as well as the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or can be implemented using a combination of dedicated hardware and computer instructions. The numbering of each step in this article is only for convenience of description and reference, and is not used to limit the order of execution. The specific execution order is determined by the technology itself, and those skilled in the art can determine various allowable and reasonable orders based on the technology itself.

[0228] It should be noted that the use of step numbers (letters or numbers) to refer to certain specific method steps in the present invention is solely for the purpose of descriptive convenience and brevity, and is in no way intended to limit the order of these method steps. Those skilled in the art will appreciate that the order of the relevant method steps is determined by the technology itself and should not be unduly limited by the presence of step numbers. Those skilled in the art can determine various permissible and reasonable step orders based on the technology itself.

[0229] It is particularly important to note that the selection of these specific numerical values, the relationships between them, and the numerical ranges not only requires the inventor to have a theoretical foundation far beyond the level of ordinary technicians in the field, but also requires creative attempts and selections based on the expected target design results, supplemented by several arduous experiments, before the expected target results are finally obtained. The determination of these numerical values ​​is something that ordinary technicians in the field will never be able to achieve. First, the initial selection interval for these proportional relationships is (0, ∞). Personnel with only ordinary technical knowledge in the field cannot narrow down such a large initial selection interval to determine the approximate range for subsequent experimental selection. Furthermore, they do not have the creative ability to construct a feasibility experiment to accurately determine the specific numerical range that will ultimately be selected to achieve the best results within this narrowed approximate range.

[0230] Those skilled in the art will appreciate that, provided there is no conflict, the above preferred solutions can be freely combined and superimposed.

[0231] It should be understood that the above-mentioned embodiments are merely illustrative and non-restrictive. Without departing from the basic principles of the present invention, various obvious or equivalent modifications or substitutions that can be made by those skilled in the art to the above-mentioned details will be included in the scope of the claims of the present invention.

Claims

1. A thread storage location allocation method, characterized by: include: Allocate virtual buffers for threads; There are multiple virtual caches, and a mapping relationship is established between the multiple virtual caches and multiple physical memory areas, wherein the multiple physical memory areas include a first physical memory area and a second physical memory area, the first physical memory area belongs to first memory hardware, the second physical memory area belongs to second memory hardware, and the capacity of a single piece of the first memory hardware is smaller than the capacity of a single piece of the second memory hardware; Calculating the access frequency of each of the physical memory regions within each predetermined time period; Selecting, in ascending order of access frequency, a physical memory area within a first preset range as a low-access-frequency physical memory area; According to the mapping relationship, the virtual cache corresponding to the low-access-frequency physical memory area is determined as the low-access-frequency virtual cache; Increasing the value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, wherein the initial value of the low access frequency counter is a preset minimum value; sorting the virtual caches in ascending order of values ​​of the low access frequency counters; At least one virtual cache is selected from the virtual caches within the first second preset range of the sort, and a mapping relationship is established between the virtual cache and the first physical memory area.

2. The thread storage location allocation method according to claim 1, characterized in that: Before sorting the virtual caches in ascending order of the values ​​of the low access frequency counters, the method further includes: Determining whether the total remaining capacity of all the first physical memory areas is less than or equal to a preset capacity value; If so, executing the step of sorting the virtual cache in ascending order of the values ​​of the low access frequency counter; If not, a mapping relationship is established between the virtual cache and the first physical memory area.

3. The thread storage location allocation method according to claim 1, wherein: Before sorting the virtual caches in ascending order of the values ​​of the low access frequency counters, the method includes: allocating the same virtual cache as the thread that applied for the cache again; The selecting at least one virtual cache from the first second preset range of the sort and establishing a mapping relationship between it and the first physical memory area includes: determining whether the virtual cache corresponding to the thread that applies for cache again is within the first second preset range of the sort; if so, establishing a mapping relationship between the virtual cache corresponding to the thread that applies for cache again and the first physical memory area.

4. The thread storage location allocation method according to claim 1, wherein: The selecting at least one virtual cache in the sorted first second preset range and establishing a mapping relationship between the virtual cache and the first physical memory area includes: When the system is in an idle state, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the first second preset range, and a mapping relationship is established between the virtual cache and the first physical memory area.

5. The thread storage location allocation method according to claim 4, characterized in that: When the system is in an idle state, selecting a virtual cache that does not perform direct memory operations from the virtual caches within the first second preset range and establishing a mapping relationship between the virtual cache and the first physical memory area includes: When the system is in an idle state, determining whether the total remaining capacity of all the first physical memory areas is less than or equal to a preset capacity value; If not, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the first second preset range, and a mapping relationship is established between the virtual cache and the first physical memory area.

6. The thread storage location allocation method according to claim 1, characterized in that: After sorting the virtual caches in ascending order of the values ​​of the low access frequency counters, the method further includes: At least one virtual cache is selected from the sorted virtual caches within the third preset range, and a mapping relationship is established between the virtual cache and the second physical memory area.

7. The thread storage location allocation method according to claim 6, characterized in that: The selecting at least one virtual cache in the third preset range after sorting and establishing a mapping relationship between the virtual cache and the second physical memory area includes: When the system is in an idle state, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the second third preset range, and a mapping relationship is established between the virtual cache and the second physical memory area.

8. The thread storage location allocation method according to claim 6, characterized in that: The number of the low access frequency counters is fixed; After selecting at least one virtual cache in the third preset range after sorting and establishing a mapping relationship between the virtual cache and the second physical memory area, the method further includes: Marking the selected virtual cache that establishes a mapping relationship with the second physical memory area; Undoing the correspondence between the marked virtual cache and the low access frequency counter; The value of the low access frequency counter whose correspondence is released is reset to the initial value, so as to be used for subsequently establishing a correspondence with the virtual cache corresponding to the newly applied thread, and when the step of sorting the virtual cache in ascending order according to the value of the low access frequency counter is subsequently performed, the low access frequency counter that has not been released from the correspondence and the low access frequency counter that has been released from the correspondence are sorted separately, and when the step of selecting at least one from the virtual cache within the first second preset range of the sort and establishing a mapping relationship with the first physical memory area is subsequently performed, the first second preset range of the sort includes each part of the two separated sorts.

9. The thread storage location allocation method according to any one of claims 1 to 8, characterized in that: The number of the low access frequency counters is fixed; After selecting at least one virtual cache in the sorted first second preset range and establishing a mapping relationship between the virtual cache and the first physical memory area, the method further includes: Marking the selected virtual cache that establishes a mapping relationship with the first physical memory area; Undoing the correspondence between the marked virtual cache and the low access frequency counter; The value of the low access frequency counter whose correspondence is released is reset to the initial value, so as to be used for subsequently establishing a correspondence with the virtual cache corresponding to the newly applied thread, and when the step of sorting the virtual cache in ascending order according to the value of the low access frequency counter is subsequently performed, the low access frequency counter that has not been released from the correspondence and the low access frequency counter that has been released from the correspondence are sorted separately, and when the step of selecting at least one from the virtual cache within the first second preset range of the sort and establishing a mapping relationship with the first physical memory area is subsequently performed, the first second preset range of the sort includes each part of the two separated sorts.

10. The thread storage location allocation method according to any one of claims 1 to 8, characterized in that: Conditions for pre-establishing low access frequency counters for the virtual cache include: The capacity of the virtual cache request is greater than or equal to a preset threshold; and / or, The number of virtual cache requests within a predetermined time period is greater than or equal to a predetermined number; and / or, Within the predetermined time period, the total time length for which the virtual cache occupies the physical memory area is greater than or equal to the preset time length.

11. The thread storage location allocation method according to any one of claims 1 to 8, characterized in that: After increasing the value of the pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, the method includes: The value of the low access frequency counter is recorded so that when the same step is executed again after the computer is powered on next time, the value of the low access frequency counter is accumulated based on the recorded value.

12. The thread storage location allocation method according to any one of claims 1 to 8, characterized in that: The method further comprises: The value of the low access frequency counter is restored to the initial value each time the computer is powered on.

13. A thread storage location allocation device, characterized in that: include: A first allocation module, configured to allocate a virtual cache to a thread; There are multiple virtual caches, and a mapping relationship is established between the multiple virtual caches and multiple physical memory areas, wherein the multiple physical memory areas include a first physical memory area and a second physical memory area, the first physical memory area belongs to first memory hardware, the second physical memory area belongs to second memory hardware, and the capacity of a single piece of the first memory hardware is smaller than the capacity of a single piece of the second memory hardware; a calculation module, configured to calculate the access frequency of each of the physical memory regions within each predetermined time period; A selection module is configured to select, in ascending order of access frequency, a physical memory area within a first preset range as a low-access-frequency physical memory area; a determining module, configured to determine, according to the mapping relationship, a virtual cache corresponding to the low-access-frequency physical memory area as a low-access-frequency virtual cache; an increasing module, configured to increase the value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, wherein the initial value of the low access frequency counter is a preset minimum value; A sorting module, configured to sort the virtual cache in ascending order of the value of the low access frequency counter; The first mapping module is configured to select at least one virtual cache from the virtual caches within the first second preset range of the sort, and establish a mapping relationship between the virtual cache and the first physical memory area.

14. The thread storage location allocation device according to claim 13, characterized in that: The device further comprises: a determination module, configured to determine whether the total remaining capacity of all the first physical memory areas is less than or equal to a preset capacity value; a control module, configured to control the sorting module to execute the step of sorting the virtual cache in ascending order of the values ​​of the low access frequency counter when the determination module determines that the virtual cache is in the order of the low access frequency counter; The second mapping module is configured to establish a mapping relationship between the virtual cache and the first physical memory area when the judgment of the judgment module is negative.

15. The thread storage location allocation device according to claim 13, characterized in that: The device further comprises: a second allocation module, configured to allocate the same virtual cache as the previous application to the thread that applies for the cache again; The first mapping module includes: a first judgment submodule, used to judge whether the virtual cache corresponding to the thread that applies for cache again is within the first second preset range of the sort; and a first mapping submodule, used to establish a mapping relationship between the virtual cache corresponding to the thread that applies for cache again and the first physical memory area when the judgment submodule judges that it is yes.

16. The thread storage location allocation device according to claim 13, characterized in that: The first mapping module includes: The second mapping submodule is configured to select a virtual cache that does not perform direct memory operations from the virtual caches within the first second preset range when the system is in an idle state, and establish a mapping relationship between the virtual cache and the first physical memory area.

17. The thread storage location allocation device according to claim 16, characterized in that: The second mapping submodule includes: a determining unit, configured to determine, when the system is in an idle state, whether the total remaining capacity of all the first physical memory areas is less than or equal to a preset capacity value; The control unit is configured to select a virtual cache that does not perform direct memory operations from the virtual caches within the first second preset range and establish a mapping relationship between the virtual cache and the first physical memory area when the judgment of the judgment unit is no.

18. The thread storage location allocation device according to claim 13, characterized in that: The device comprises: The third mapping module is configured to select at least one virtual cache from the sorted virtual caches within the third preset range and establish a mapping relationship between the virtual cache and the second physical memory area.

19. The thread storage location allocation device according to claim 18, characterized in that: The third mapping module includes: The third mapping submodule is configured to select a virtual cache that does not perform direct memory operations from the virtual caches within the third preset range when the system is in an idle state, and establish a mapping relationship between the virtual cache and the second physical memory area.

20. The thread storage location allocation device according to claim 18, wherein: The number of the low access frequency counters is fixed; The device further comprises: a first marking module configured to mark the selected virtual cache that has a mapping relationship with the second physical memory area after the second mapping module executes the step of selecting at least one virtual cache in the sorted third preset range and establishing a mapping relationship between the virtual cache and the second physical memory area; A first releasing module, configured to release the correspondence between the marked virtual cache and the low access frequency counter; A first resetting module is configured to reset the value of the low access frequency counter whose correspondence has been released to an initial value, so as to establish a correspondence with the virtual cache corresponding to the newly applied thread in the subsequent process, and when the sorting module subsequently executes the step of sorting the virtual cache in ascending order according to the value of the low access frequency counter, the low access frequency counter whose correspondence has not been released and the low access frequency counter whose correspondence has been released are sorted separately, and when the first mapping module subsequently executes the step of selecting at least one virtual cache within the first second preset range of the sorting and establishing a mapping relationship with the first physical memory area, the first second preset range of the sorting includes a portion of each of the two separate sorts.

21. The thread storage location allocation device according to any one of claims 13 to 20, characterized in that: The number of the low access frequency counters is fixed; The device further comprises: a second marking module, configured to mark the selected virtual cache that has a mapping relationship with the first physical memory area after the first mapping module executes the step of selecting at least one virtual cache from the virtual caches within the second preset range before sorting and establishing a mapping relationship with the first physical memory area; A second releasing module, configured to release the correspondence between the marked virtual cache and the low access frequency counter; A second reset module is configured to reset the value of the low access frequency counter whose correspondence has been released to an initial value, so as to establish a correspondence with the virtual cache corresponding to the newly applied thread in the subsequent process, and when the sorting module subsequently executes the step of sorting the virtual cache in ascending order according to the value of the low access frequency counter, the low access frequency counter whose correspondence has not been released and the low access frequency counter whose correspondence has been released are sorted separately, and when the first mapping module subsequently executes the step of selecting at least one virtual cache within the first second preset range of the sorting and establishing a mapping relationship with the first physical memory area, the first second preset range of the sorting includes a portion of each of the two separate sorts.

22. The thread storage location allocation device according to any one of claims 13 to 20, characterized in that: Conditions for pre-establishing low access frequency counters for the virtual cache include: The capacity of the virtual cache request is greater than or equal to a preset threshold; and / or, The number of virtual cache requests within a predetermined time period is greater than or equal to a predetermined number; and / or, Within the predetermined time period, the total time length for which the virtual cache occupies the physical memory area is greater than or equal to the preset time length.

23. The thread storage location allocation device according to any one of claims 13 to 20, characterized in that: The device further comprises: The recording module is used to record the value of the low access frequency counter so that when the same step is executed again after the computer is turned on next time, the value of the low access frequency counter is accumulated based on the recorded value.

24. The thread storage location allocation device according to any one of claims 13 to 20, characterized in that: The device further comprises: The recovery module is used to restore the value of the low access frequency counter to an initial value each time the computer is powered on.

25. A thread storage location allocation method, characterized in that: include: Allocate virtual buffers for threads; There are multiple virtual caches, and a mapping relationship is established between the multiple virtual caches and multiple physical memory areas, wherein the multiple physical memory areas include a first physical memory area and a second physical memory area, the first physical memory area belongs to first memory hardware, the second physical memory area belongs to second memory hardware, and the capacity of a single piece of the first memory hardware is smaller than the capacity of a single piece of the second memory hardware; Calculating the access frequency of each of the physical memory regions within each predetermined time period; Selecting, in ascending order of access frequency, a physical memory area within a first preset range as a low-access-frequency physical memory area; According to the mapping relationship, the virtual cache corresponding to the low-access-frequency physical memory area is determined as the low-access-frequency virtual cache; Decrease the value of a pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, wherein the initial value of the low access frequency counter is a preset maximum value; sorting the virtual caches in descending order of values ​​of the low access frequency counters; At least one virtual cache is selected from the virtual caches within the first second preset range of the sort, and a mapping relationship is established between the virtual cache and the first physical memory area.

26. The thread storage location allocation method according to claim 25, characterized in that: Before sorting the virtual caches in descending order of the values ​​of the low access frequency counters, the method further includes: Determining whether the total remaining capacity of all the first physical memory areas is less than or equal to a preset capacity value; If so, executing the step of sorting the virtual cache in descending order of the values ​​of the low access frequency counter; If not, a mapping relationship is established between the virtual cache and the first physical memory area.

27. The thread storage location allocation method according to claim 25, characterized in that: Before sorting the virtual caches in descending order of the values ​​of the low access frequency counters, the method includes: allocating the same virtual cache as the thread that applied for the cache again; The selecting at least one virtual cache from the first second preset range of the sort and establishing a mapping relationship between it and the first physical memory area includes: determining whether the virtual cache corresponding to the thread that applies for cache again is within the first second preset range of the sort; if so, establishing a mapping relationship between the virtual cache corresponding to the thread that applies for cache again and the first physical memory area.

28. The thread storage location allocation method according to claim 25, characterized in that: The selecting at least one virtual cache in the sorted first second preset range and establishing a mapping relationship between the virtual cache and the first physical memory area includes: When the system is in an idle state, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the first second preset range, and a mapping relationship is established between the virtual cache and the first physical memory area.

29. The thread storage location allocation method according to claim 28, characterized in that: When the system is in an idle state, selecting a virtual cache that does not perform direct memory operations from the virtual caches within the first second preset range and establishing a mapping relationship between the virtual cache and the first physical memory area includes: When the system is in an idle state, determining whether the total remaining capacity of all the first physical memory areas is less than or equal to a preset capacity value; If not, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the first second preset range, and a mapping relationship is established between the virtual cache and the first physical memory area.

30. The thread storage location allocation method according to claim 25, wherein: After sorting the virtual caches in descending order of the values ​​of the low access frequency counters, the method further includes: At least one virtual cache is selected from the sorted virtual caches within the third preset range, and a mapping relationship is established between the virtual cache and the second physical memory area.

31. The thread storage location allocation method according to claim 30, characterized in that: The selecting at least one virtual cache in the third preset range after sorting and establishing a mapping relationship between the virtual cache and the second physical memory area includes: When the system is in an idle state, a virtual cache that does not perform direct memory operations is selected from the virtual caches within the second third preset range, and a mapping relationship is established between the virtual cache and the second physical memory area.

32. The thread storage location allocation method according to claim 30, characterized in that: The number of the low access frequency counters is fixed; After selecting at least one virtual cache in the third preset range after sorting and establishing a mapping relationship between the virtual cache and the second physical memory area, the method further includes: Marking the selected virtual cache that establishes a mapping relationship with the second physical memory area; Undoing the correspondence between the marked virtual cache and the low access frequency counter; The value of the low access frequency counter whose correspondence is released is reset to the initial value, so as to be used for subsequently establishing a correspondence with the virtual cache corresponding to the newly applied thread, and when the step of sorting the virtual cache in ascending order according to the value of the low access frequency counter is subsequently performed, the low access frequency counter that has not been released from the correspondence and the low access frequency counter that has been released from the correspondence are sorted separately, and when the step of selecting at least one from the virtual cache within the first second preset range of the sort and establishing a mapping relationship with the first physical memory area is subsequently performed, the first second preset range of the sort includes each part of the two separated sorts.

33. The thread storage location allocation method according to any one of claims 25 to 32, characterized in that: The number of the low access frequency counters is fixed; After selecting at least one virtual cache in the sorted first second preset range and establishing a mapping relationship between the virtual cache and the first physical memory area, the method further includes: Marking the selected virtual cache that establishes a mapping relationship with the first physical memory area; Undoing the correspondence between the marked virtual cache and the low access frequency counter; The value of the low access frequency counter whose correspondence is released is reset to the initial value, so as to be used for subsequently establishing a correspondence with the virtual cache corresponding to the newly applied thread, and when the step of sorting the virtual cache in ascending order according to the value of the low access frequency counter is subsequently performed, the low access frequency counter that has not been released from the correspondence and the low access frequency counter that has been released from the correspondence are sorted separately, and when the step of selecting at least one from the virtual cache within the first second preset range of the sort and establishing a mapping relationship with the first physical memory area is subsequently performed, the first second preset range of the sort includes each part of the two separated sorts.

34. The thread storage location allocation method according to any one of claims 25 to 32, characterized in that: Conditions for pre-establishing low access frequency counters for the virtual cache include: The capacity of the virtual cache request is greater than or equal to a preset threshold; and / or, Within a predetermined time period, the number of virtual cache requests and / or releases is greater than or equal to a preset number; and / or, Within the predetermined time period, the total time length for which the virtual cache occupies the physical memory area is greater than or equal to the preset time length.

35. The thread storage location allocation method according to any one of claims 25 to 32, characterized in that: After reducing the value of the pre-established low access frequency counter corresponding to the low access frequency virtual cache by a preset unit amount, the method includes: The value of the low access frequency counter is recorded so that when the same step is executed again after the computer is powered on next time, the value of the low access frequency counter is accumulated based on the recorded value.

36. The thread storage location allocation method according to any one of claims 25 to 32, characterized in that: The method further comprises: The value of the low access frequency counter is restored to the initial value each time the computer is powered on.

37. A system-on-chip, characterized in that: The system comprises a memory management unit, first memory hardware, and second memory hardware, wherein the capacity of a single piece of the first memory hardware is smaller than the capacity of a single piece of the second memory hardware. When the system-on-chip runs a thread, the memory management unit can allocate the storage location of the thread using the thread storage location allocation method described in any one of claims 1 to 12 or the thread storage location allocation method described in any one of claims 25 to 36.

38. A computing device, characterized in that include: A processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the thread storage location allocation method according to any one of claims 1 to 12 or the thread storage location allocation method according to any one of claims 25 to 36.

39. A computer-readable storage medium, characterized in that The computer-readable storage medium stores an execution program, which, when executed, implements the thread storage location allocation method according to any one of claims 1 to 12 or the thread storage location allocation method according to any one of claims 25 to 36.

Images