A frequency configuration method, system and related device of a field programmable gate array

Abstract

The application provides a frequency configuration method of a field programmable gate array, comprising: obtaining a configuration instruction; judging whether a frequency key-value pair currently supported by a system contains a target frequency in the configuration instruction; if not, generating configuration data corresponding to the target frequency according to the configuration instruction, and updating the frequency key-value pair by using the configuration data; and taking the target frequency as a working frequency of the field programmable gate array. The application can be set as frequency setting data which has been pre-stored, or configuration data can be generated according to self needs, stored to a corresponding module and then frequency setting is performed. Frequency setting and updating can be effectively realized, and a phenomenon that an accelerator frequency cannot meet customer needs and cannot be used is avoided. The application also provides a frequency configuration system of a field programmable gate array, a computer readable storage medium and an electronic device, which have the above beneficial effects.

Description

Technical Field

[0001] This application relates to the field of electronic devices, and in particular to a frequency configuration method, system and related apparatus for a field-programmable gate array. Background Technology

[0002] With the rise of 5G, IoT, cloud computing, and big data industries, data volume has exploded. This massive amount of data places higher demands on the computing power of computing systems, and the computing power of a simple CPU is far from sufficient to meet the needs of the internet industry. Therefore, heterogeneous computing is gaining popularity, with technologies such as GPUs for image processing and AI computing, ASICs for specialized computing scenarios, and flexibly programmable FPGA accelerators. We can offload large amounts of data requiring parallel processing to heterogeneous accelerators, while the CPU only handles task scheduling and result processing. This improves data processing efficiency and frees up CPU resources.

[0003] FPGAs (Field-Programmable Gate Arrays) are widely used in network offloading and finance due to their superior performance, including high customization, high programmability, excellent parallel computing capabilities, and low latency. However, precisely because of their high customization and wide range of applications, customized FPGA accelerators cannot meet the application requirements of all customers. Customers need to modify FPGA accelerators according to their specific applications; for example, differences in optical module frequencies and DDR operating frequencies all impose different requirements on the operating frequency of the FPGA accelerator. Summary of the Invention

[0004] The purpose of this application is to provide a frequency configuration method for a field-programmable gate array (FPGA), a frequency configuration system for an FPGA, a computer-readable storage medium, and an electronic device, which can adjust the operating frequency of the FPGA according to actual usage requirements.

[0005] To address the aforementioned technical problems, this application provides a frequency configuration method for field-programmable gate arrays (FPGAs), the specific technical solution of which is as follows:

[0006] Get configuration commands;

[0007] Determine whether the frequency key-value pairs currently supported by the system contain the target frequency specified in the configuration command;

[0008] If not, generate configuration data corresponding to the target frequency according to the configuration instructions, and update the frequency key-value pair using the configuration data;

[0009] The target frequency is used as the operating frequency of the field-programmable gate array.

[0010] Optional, also includes:

[0011] Obtain master control settings instructions;

[0012] The master control device of the field-programmable gate array is determined according to the master control setting instructions; the master control device includes an operating system and a basic input / output system.

[0013] Optionally, before determining whether the frequency key-value pairs currently supported by the system contain the target frequency in the configuration instruction, the following steps are also included:

[0014] Receive frequency query command;

[0015] The frequency key-value pair stored in the flash memory is queried according to the frequency query instruction.

[0016] Optionally, if the frequency key-value pairs currently supported by the system include the target frequency in the configuration instruction, the following may also be included:

[0017] Based on the index value corresponding to the target frequency in the frequency key-value pair, the target frequency is set as the operating frequency of the current system.

[0018] Optionally, setting the target frequency as the operating frequency of the current system according to the index value corresponding to the target frequency in the frequency key-value pair includes:

[0019] Determine the index value corresponding to the target frequency in the frequency key-value pair;

[0020] The corresponding configuration data is read from the electrically erasable programmable read-only memory according to the serial number value;

[0021] The correctness of the configuration data is verified.

[0022] If the correctness verification passes, the configuration data will be applied to the current system.

[0023] Optionally, after setting the target frequency to the operating frequency of the current system, the method further includes:

[0024] Determine whether the target frequency has been set successfully;

[0025] If not, rewrite the configuration data into the clock chip.

[0026] Optionally, after applying the configuration data to the current system, the method further includes:

[0027] Perform a reset operation to cause the field-programmable gate array to operate at the target frequency.

[0028] This application also provides a frequency configuration system for a field-programmable gate array, including:

[0029] The instruction acquisition module is used to acquire configuration instructions;

[0030] The judgment module is used to determine whether the frequency key-value pairs supported by the current system contain the target frequency in the configuration instruction;

[0031] A configuration module is used to generate configuration data corresponding to the target frequency according to the configuration instruction when the judgment result of the judgment module is negative, and to update the frequency key-value pair using the configuration data;

[0032] The frequency setting module is used to set the target frequency as the operating frequency of the field-programmable gate array.

[0033] Optional, also includes:

[0034] The master control device determination module is used to acquire master control setting instructions; determine the master control device of the field programmable gate array according to the master control setting instructions; the master control device includes an operating system and a basic input / output system.

[0035] Optional, also includes:

[0036] A frequency query module is used to receive a frequency query instruction and query the frequency key-value pair stored in flash memory according to the frequency query instruction.

[0037] Optional, also includes:

[0038] The second frequency setting module is used to set the target frequency as the operating frequency of the current system if the frequency key-value pair supported by the current system contains the target frequency in the configuration instruction, according to the serial number value corresponding to the target frequency in the frequency key-value pair.

[0039] Optionally, the second frequency setting module is a module for performing the following steps:

[0040] Determine the index value corresponding to the target frequency in the frequency key-value pair;

[0041] The corresponding configuration data is read from the electrically erasable programmable read-only memory according to the serial number value;

[0042] The correctness of the configuration data is verified.

[0043] If the correctness verification passes, the configuration data will be applied to the current system.

[0044] Optional, also includes:

[0045] The frequency detection module is used to determine whether the target frequency has been successfully set after setting the target frequency to the current system's operating frequency; if not, the configuration data is rewritten to the clock chip.

[0046] Optional, also includes:

[0047] A reset module is used to perform a reset operation to cause the field-programmable gate array to operate at the target frequency.

[0048] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0049] This application also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method described above when it invokes the computer program in the memory.

[0050] This application provides a frequency configuration method for a field-programmable gate array (FPGA), comprising: acquiring a configuration instruction; determining whether the frequency key-value pair supported by the current system contains the target frequency in the configuration instruction; if not, generating configuration data corresponding to the target frequency according to the configuration instruction, and updating the frequency key-value pair using the configuration data; and using the target frequency as the operating frequency of the FPGA.

[0051] After obtaining the configuration command, this application first determines whether the target frequency setting exists in the current system. If not, it generates configuration data based on the configuration command and applies it to the current system. Based on this, users can adjust the operating frequency of the field-programmable gate array (FPGA) according to their own needs. They can either set it to pre-stored frequency settings or generate configuration data and store it in the corresponding module before setting the frequency. This effectively enables frequency setting and updating, avoiding the phenomenon of accelerator frequencies not meeting customer requirements and thus becoming unusable.

[0052] This application also provides a frequency configuration system for a field-programmable gate array, a computer-readable storage medium, and an electronic device, which have the aforementioned beneficial effects, and will not be elaborated here. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0054] Figure 1 A flowchart illustrating a frequency configuration method for a field-programmable gate array (FPGA) provided in this application embodiment;

[0055] Figure 2This is a schematic diagram of the structure corresponding to the FPGA frequency setting process implemented on the HOST side in the embodiments of this application;

[0056] Figure 3 This is a schematic diagram of a frequency configuration system structure for a field-programmable gate array (FPGA) provided in an embodiment of this application.

[0057] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0058] Field-Programmable Gate Arrays (FPGAs) are widely used in network offloading and financial fields due to their superior performance, including high customization, high programmability, excellent parallel computing performance, and low latency. However, precisely because of their high customization and wide range of applications, customized FPGA accelerators cannot meet the application requirements of all customers. Customers need to modify FPGA accelerators according to their own applications; for example, differences in optical module frequencies and DDR operating frequencies all impose different requirements on the operating frequency of the FPGA accelerator. Since users often need to modify FPGA accelerators according to their specific applications, thus requiring different operating frequencies, the core of this application is to provide a frequency configuration method for FPGAs, enabling users to adjust the FPGA's operating frequency according to their own needs to meet their application requirements.

[0059] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0060] Please refer to Figure 1 , Figure 1 A flowchart illustrating a frequency configuration method for a field-programmable gate array (FPGA) provided in this application embodiment is included. The method comprises:

[0061] S101: Obtain configuration instructions;

[0062] S102: Determine whether the frequency key-value pairs supported by the current system contain the target frequency in the configuration instruction; if not, proceed to S103;

[0063] S103: Generate configuration data corresponding to the target frequency according to the configuration instruction, and update the frequency key-value pair using the configuration data;

[0064] S104: Use the target frequency as the operating frequency of the field-programmable gate array.

[0065] Step S101 aims to obtain configuration instructions. The method of obtaining these instructions is not limited; they can be issued by the user to adjust the FPGA's operating frequency. Furthermore, the specific content of the configuration instructions is not limited; they can include specific frequency parameters or frequency-related indicator parameters, allowing the specific operating frequency to be determined through these indicator parameters.

[0066] Before determining whether the frequency key-value pairs supported by the current system include the target frequency in the configuration command, a frequency query command can be received first to retrieve the frequency key-value pairs stored in flash memory. These frequency key-value pairs can include commonly used operating frequencies for quick adjustment. The frequency key-value pairs can be set via an adjustment interface, allowing users to directly adjust the interface to regulate the operating frequency. This adjustment interface is set by registering the clock chip's frequency. If the user only needs to adjust the clock chip's frequency configuration based on the adjustment interface, this can be done through the unified, extensible firmware interface, eliminating the need to recompile and update the BIOS after each code change. This avoids the cumbersome process of adjusting frequency configuration and improves the efficiency of electromagnetic interference testing. The adjustment interface is essentially a specific application of the frequency key-value pairs; it acts as an indicator parameter, meaning the configuration command can include only the adjustment interface while still clearly specifying the operating frequency the user needs to set.

[0067] Next, it is determined whether the frequency key-value pairs supported by the current system include the target frequency in the configuration instruction. If the frequency key-value pairs supported by the current system include the target frequency in the configuration instruction, the target frequency can be set as the operating frequency of the current system according to the corresponding index value in the frequency key-value pairs. Specifically, the index value corresponding to the target frequency in the frequency key-value pairs can be determined, and then the corresponding configuration data can be read from the electrically erasable programmable read-only memory according to the index value, thereby directly applying the configuration data to complete the setting of the operating frequency.

[0068] In addition, it should be noted that if the frequency key-value pairs currently supported by the system do not include the target frequency in the configuration command, the frequency key-value pairs can be updated using the configuration data, that is, the target frequency can be added to the frequency key-value pairs. This makes it easier for users to directly apply the target frequency in the future without having to perform the process of generating configuration data again, which can speed up the efficiency of setting the system to the target frequency next time.

[0069] As a preferred implementation, after acquiring the configuration data, a correctness check can be performed on the configuration data. If the correctness check passes, the configuration data is applied to the current system. This avoids abnormal operating frequency settings caused by abnormal configuration data. The correctness check mainly refers to verifying the format and content of the configuration data; the specific check process can be set by those skilled in the art.

[0070] If the frequency key-value pairs currently supported by the system do not include the target frequency in the configuration command, then configuration data is generated according to the configuration command. This configuration data is used to update the frequency key-value pairs and applied to the system, so that the system runs according to the target frequency corresponding to the configuration data. Therefore, the configuration command must at least contain data related to the target frequency, and may further include files necessary for generating the configuration data, thereby quickly generating the configuration data and quickly setting the system's operating frequency.

[0071] This application provides a frequency configuration method for a field-programmable gate array (FPGA), comprising: acquiring a configuration instruction; determining whether the frequency key-value pair supported by the current system contains the target frequency in the configuration instruction; if not, generating configuration data corresponding to the target frequency according to the configuration instruction, and updating the frequency key-value pair using the configuration data; and using the target frequency as the operating frequency configuration instruction for the FPGA. This application determines whether the current system has a set value for the target frequency; if not, it generates configuration data according to the configuration instruction and applies it to the current system. Based on this, users can adjust the operating frequency of the FPGA according to their own needs, either by setting it to pre-stored frequency setting data or by generating configuration data according to their own needs, storing it in the corresponding module, and then setting the frequency. This effectively realizes frequency setting and updating, avoiding the phenomenon that the accelerator frequency does not meet customer needs and thus cannot be used.

[0072] Based on the above embodiments, if the frequency key-value pairs supported by the current system include the target frequency in the configuration command, the target frequency can be set directly through the frequency key-value pairs. The complete process in this case is as follows:

[0073] Step 1: Obtain configuration commands;

[0074] The second step is to determine whether the frequency key-value pairs supported by the current system contain the target frequency in the configuration command; if yes, proceed to the third step; if no, proceed to the fourth step.

[0075] The third step is to set the current system's operating frequency to the target frequency using frequency key-value pairs;

[0076] Step 4: Generate configuration data corresponding to the target frequency according to the configuration instructions, and update the frequency key-value pair using the configuration data;

[0077] Step 5: Use the target frequency as the operating frequency of the field-programmable gate array.

[0078] There are no restrictions on how to set the current system's operating frequency using frequency key-value pairs. You can directly set the frequency according to the target frequency in the configuration command using the corresponding operation method of the frequency key-value pairs.

[0079] Based on the above embodiments, as a preferred embodiment, after setting the target frequency to the current system's operating frequency, it can be determined whether the target frequency was set successfully; if not, the configuration data is rewritten to the clock chip. Since the configuration data may contain application errors or other application failures, this application can verify the system after setting the target frequency to the operating frequency, specifically verifying whether the current system is truly operating at the target frequency. If the system does not actually operate at the target frequency, it indicates that the configuration data may fail to take effect. In this case, the configuration data can be rewritten to the clock chip and re-verified until successful.

[0080] To enable configurable operating frequencies both in-band and out-of-band, see [link / reference]. Figure 2 , Figure 2 This is a schematic diagram of the structure corresponding to the HOST terminal implementing the field-programmable gate array frequency setting process provided in the embodiments of this application. Figure 2 It includes the following modules:

[0081] It consists of a host end and an FPGA accelerator end. The main function of the host end is to issue instructions and data, and to reserve two links for the user: the basic input / output system and the operating system. The FPGA accelerator end is responsible for frequency configuration and the execution of acceleration tasks. The functions of each module of the FPGA accelerator are as follows:

[0082] PCIe interface module: Primarily responsible for data transmission. If the user selects the Basic Input / Output System (PIS) path, the PIS can directly send data to the MCU main control module via the PCIe SMBUS interface; if the user selects the Operating System (OS), the OS sends data to the FPGA via the PCIe interface, and the FPGA then sends the data to the MCU main control module via the I2C link.

[0083] MCU main control module: responsible for receiving and parsing information sent by the HOST terminal; performing relevant frequency setting operations according to the parsed instructions, such as updating the clock chip frequency configuration and adding frequency configuration information;

[0084] FLASH storage module: FLASH storage space is relatively small and is mainly used to store frequency key-value pairs (serial number-frequency). For example, the frequency corresponding to key-value pair number 1 is 266MHz for FPGA chip and 322MHz for optical port.

[0085] EEPROM storage module: Stores specific configuration data for different frequencies.

[0086] Clock module: Generates frequencies that enable the field-programmable gate array (FPGA) chip and optical port to operate normally.

[0087] Field Programmable Gate Array (FPGA) Module: The main chip of the FPGA accelerator, responsible for implementing application services.

[0088] Optical port module: Responsible for enabling external communication through the optical port.

[0089] As can be seen, this application embodiment implements both in-band and out-of-band methods for configuring accelerator chip frequencies. For users equipped with a basic input / output system, frequency updates can be performed through a graphical interface; for users without a basic input / output system, frequency updates can be performed through a general-purpose OS executable program. Furthermore, this solution provides a method for user-defined frequencies, allowing users to generate their own frequency configuration data and perform frequency updates, whereas traditional solutions often only allow configuration of a few fixed frequencies. This application embodiment enables customization of the FPGA accelerator's operating frequency, effectively expanding the application scenarios of the FPGA accelerator and avoiding the drawbacks of frequent accelerator firmware updates due to unmet frequency requirements.

[0090] The key to this embodiment lies in building an FPGA accelerator chip frequency setting system, which allows users to configure the frequency in both in-band and out-of-band methods. Simultaneously, the system supports customer-defined system frequencies, enabling users to generate configuration data according to their needs and update the frequency through this system. This avoids the situation where the field-programmable gate array accelerator frequency does not meet customer requirements, rendering it unusable.

[0091] Based on the above embodiments, as a preferred embodiment, after applying the configuration data to the current system, a reset operation is performed to cause the field-programmable gate array (FPGA) to operate at the target frequency. The purpose of the reset operation is to apply the configuration data, thereby enabling the current system to restart with the configuration data and achieve the goal of operating at the target frequency. The complete execution process corresponding to this embodiment is as follows:

[0092] Step 1: Obtain configuration commands;

[0093] The second step is to determine whether the frequency key-value pairs supported by the current system contain the target frequency in the configuration command; if yes, proceed to the third step; if no, proceed to the fourth step.

[0094] The third step is to set the current system's operating frequency to the target frequency using frequency key-value pairs;

[0095] Step 4: Generate configuration data corresponding to the target frequency according to the configuration instructions, and update the frequency key-value pair using the configuration data;

[0096] Step 5: Use the target frequency as the operating frequency of the field-programmable gate array.

[0097] Step 6: Perform a reset operation to cause the field-programmable gate array to operate at the target frequency.

[0098] In another embodiment of this application, before obtaining the configuration instruction, a master control setting instruction can be obtained first, thereby determining the master control device of the field-programmable gate array based on the master control setting instruction. The master control device includes an operating system and a basic input / output system. The complete execution process corresponding to this embodiment is as follows:

[0099] Step 1: Obtain the master control setting instruction, and determine the master control device of the field programmable gate array based on the master control setting instruction;

[0100] Step 2: Obtain configuration commands;

[0101] Step 3: Determine whether the frequency key-value pairs currently supported by the system contain the target frequency in the configuration command; if not, proceed to step 4.

[0102] Step 4: Generate configuration data corresponding to the target frequency according to the configuration instructions, and update the frequency key-value pair using the configuration data;

[0103] Step 5: Use the target frequency as the operating frequency of the field-programmable gate array.

[0104] The frequency setting process can be different depending on the main control device. The specific process is as follows:

[0105] If the main control device is a basic input / output system, the process of executing the frequency configuration method of the field-programmable gate array provided in this application can be as follows:

[0106] 1. The basic input / output system sends a view command to the MCU to view all frequencies currently supported by the system;

[0107] 2. The MCU receives instructions and reads frequency key-value pairs stored in flash memory, such as (1-266MHz (FPGA frequency)-322MHz (optical port frequency)), and uploads all key-value pairs to the basic input / output system;

[0108] 3. The basic input / output system checks all uploaded key-value pairs. If there is no target frequency, the EDA software of the clock chip must first be used to generate the configuration data for the target frequency, and then an update command is issued to send the newly generated configuration data to the MCU. The MCU stores the newly generated configuration data in the EEPROM, generates new key-value pairs and stores them in the FLASH, updates all key-value pairs and uploads them to the HOST.

[0109] 4. When issuing configuration commands from the basic input / output system, the sequence number corresponding to the target frequency must be specified.

[0110] 5. The MCU reads the corresponding configuration data stored in the EEPROM based on the serial number value;

[0111] 6. The MCU verifies the correctness of the configuration data. If the verification is successful, the data is configured into the clock chip.

[0112] 7. Check if the update was successful. If the new frequency configuration was not successful, the original frequency configuration data needs to be rewritten into the clock chip to prevent the clock chip from malfunctioning.

[0113] 8. Upload the updated results to the basic input / output system.

[0114] 9. Perform a reset operation to enable the FPGA accelerator to operate at the new frequency.

[0115] In this embodiment, when configuring the target frequency, a configuration command corresponding to the target frequency's sequence number needs to be issued so that the MCU can read the corresponding configuration data based on the sequence number and configure it to the clock chip. Other configuration methods may also be used in other embodiments of this application, which will not be listed here.

[0116] If the main control device is an operating system, the process of executing the frequency configuration method for the field-programmable gate array provided in this application can be as follows:

[0117] 1. The operating system sends a viewing command to the FPGA, and the FPGA forwards the command to the MCU;

[0118] 2. The MCU receives the instruction and reads the frequency key-value pairs stored in the FLASH, and returns all the key-value pairs to the FPGA; the FPGA then returns the data to the server OS.

[0119] 3. The server operating system checks all uploaded key-value pairs. If there is no target frequency, it performs a configuration data generation operation, sends the newly generated configuration data to the FPGA, and the FPGA forwards it to the MCU for storage.

[0120] 4. The server operating system issues configuration commands, and the sequence number value corresponding to the target frequency must be specified when issuing the configuration commands;

[0121] 5. The FPGA acquires the instruction and forwards it to the MCU. The MCU reads the corresponding configuration data stored in the EEPROM based on the sequence number value;

[0122] 6. The MCU verifies the correctness of the configuration data. If the verification is successful, the data is configured into the clock chip.

[0123] 7. Check if the operating frequency is configured successfully. If the new frequency configuration is unsuccessful, the original frequency configuration data needs to be rewritten into the clock chip to prevent the clock chip from malfunctioning.

[0124] 8. The MCU returns the update result to the FPGA, and the FPGA then returns the result to the server operating system via the PCIe interface;

[0125] 9. Perform a reset operation to enable the FPGA accelerator to operate at the new frequency.

[0126] In the above process, the server operating system acts as the execution entity, making it convenient for users to adjust the running frequency.

[0127] As can be seen from the above, the embodiments of this application can use the basic input / output system and the operating system to set the operating frequency respectively. Users can choose to execute the frequency configuration of the field programmable gate array according to the actual situation of their own application, which is convenient for users to set.

[0128] In the above embodiments, the frequency configuration method for field-programmable gate arrays (FPGAs) has been described in detail. This application also provides embodiments corresponding to the frequency configuration system for FPGAs. It should be noted that this application describes the embodiments of the device portion from two perspectives: one based on functional modules and the other based on hardware. The frequency configuration system for FPGAs provided in the embodiments of this application is described below. The frequency configuration system described below can be referred to in correspondence with the frequency configuration method for FPGAs described above.

[0129] See Figure 3 This application also provides a frequency configuration system for a field-programmable gate array, comprising:

[0130] The instruction acquisition module is used to acquire configuration instructions;

[0131] The judgment module is used to determine whether the frequency key-value pairs supported by the current system contain the target frequency in the configuration instruction;

[0132] A configuration module is used to generate configuration data corresponding to the target frequency according to the configuration instruction when the judgment result of the judgment module is negative, and to update the frequency key-value pair using the configuration data;

[0133] The frequency setting module is used to set the target frequency as the operating frequency of the field-programmable gate array.

[0134] In this embodiment, after the instruction acquisition module acquires the configuration instruction, it first uses a judgment module to determine whether the current system has a set value for the target frequency. If it does not exist, the configuration module and frequency setting module generate configuration data according to the configuration instruction and apply it to the current system. Based on this, users can adjust the operating frequency of the field-programmable gate array according to their own needs. They can either set it to pre-stored frequency setting data or generate configuration data according to their own needs, store it in the corresponding module, and then set the frequency. This effectively realizes frequency setting and updating, avoiding the phenomenon that the accelerator frequency does not meet customer needs and thus cannot be used.

[0135] Based on the above embodiments, as a preferred embodiment, it further includes:

[0136] The master control device determination module is used to acquire master control setting instructions; determine the master control device of the field programmable gate array according to the master control setting instructions; the master control device includes an operating system and a basic input / output system.

[0137] Based on the above embodiments, as a preferred embodiment, it further includes:

[0138] A frequency query module is used to receive a frequency query instruction and query the frequency key-value pair stored in flash memory according to the frequency query instruction.

[0139] Based on the above embodiments, as a preferred embodiment, it further includes:

[0140] The second frequency setting module is used to set the target frequency as the operating frequency of the current system if the frequency key-value pair supported by the current system contains the target frequency in the configuration instruction, according to the serial number value corresponding to the target frequency in the frequency key-value pair.

[0141] Based on the above embodiments, as a preferred embodiment, the second frequency setting module is a module for performing the following steps:

[0142] Determine the index value corresponding to the target frequency in the frequency key-value pair;

[0143] The corresponding configuration data is read from the electrically erasable programmable read-only memory according to the serial number value;

[0144] The correctness of the configuration data is verified.

[0145] If the correctness verification passes, the configuration data will be applied to the current system.

[0146] Based on the above embodiments, as a preferred embodiment, it further includes:

[0147] The frequency detection module is used to determine whether the target frequency has been successfully set after setting the target frequency to the current system's operating frequency; if not, the configuration data is rewritten to the clock chip.

[0148] Based on the above embodiments, as a preferred embodiment, it further includes:

[0149] A reset module is used to perform a reset operation to cause the field-programmable gate array to operate at the target frequency.

[0150] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed, can perform at least the following steps:

[0151] Get configuration commands;

[0152] Determine whether the frequency key-value pairs currently supported by the system contain the target frequency specified in the configuration command;

[0153] If not, generate configuration data corresponding to the target frequency according to the configuration instructions, and update the frequency key-value pair using the configuration data;

[0154] The target frequency is used as the operating frequency of the field-programmable gate array.

[0155] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0156] The computer-readable storage medium in this embodiment allows adjustment of the operating frequency of the field-programmable gate array (FPGA) according to its own usage requirements. It can be set to pre-stored frequency settings or generate configuration data and store it in the corresponding module before setting the frequency. This effectively enables frequency setting and updating, avoiding the phenomenon of accelerator frequencies not meeting customer needs and thus becoming unusable.

[0157] This application also provides a terminal, see [link to application]. Figure 4 The present application provides a structural diagram of a terminal, as shown in the embodiment. Figure 4 As shown, it may include a processor 1410 and a memory 1420.

[0158] The processor 1410 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 1410 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 1410 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 1410 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 1410 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0159] The memory 1420 may include one or more computer-readable storage media, which may be non-transitory. The memory 1420 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 1420 is at least used to store the following computer program 1421, which, after being loaded and executed by the processor 1410, is capable of implementing the relevant steps of the method disclosed in any of the foregoing embodiments. At least the following steps can be implemented:

[0160] Determine whether the frequency key-value pairs supported by the current system include the target frequency in the configuration instruction; if not, generate configuration data corresponding to the target frequency according to the configuration instruction, and update the frequency key-value pairs using the configuration data; use the target frequency as the operating frequency of the field-programmable gate array.

[0161] In addition, the resources stored in the memory 1420 may also include an operating system 1422 and data 1423, and the storage method may be temporary storage or permanent storage. Among them, the operating system 1422 may include Windows, Linux, Android, etc.

[0162] In some embodiments, the terminal may further include a display screen 1430, an input / output interface 1440, a communication interface 1450, a sensor 1460, a power supply 1470, and a communication bus 1480.

[0163] certainly, Figure 4 The structure of the terminal shown does not constitute a limitation on the terminal in the embodiments of this application. In practical applications, the terminal may include more than [other components]. Figure 4 More or fewer components as shown, or combinations of certain components.

[0164] In this embodiment, the terminal can adjust the operating frequency of the field-programmable gate array (FPGA) according to its own usage needs. It can either set the frequency to pre-stored frequency settings or generate its own configuration data, store it in the corresponding module, and then set the frequency. This effectively enables frequency setting and updating, avoiding the phenomenon where the accelerator frequency does not meet customer requirements, leading to unusable operation.

[0165] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. As the system provided in the embodiments corresponds to the method provided in the embodiments, the description is relatively simple; relevant parts can be found in the method section.

[0166] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0167] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A frequency configuration method for a field-programmable gate array (FPGA), characterized in that, include: Get configuration commands; Determine whether the frequency key-value pairs currently supported by the system contain the target frequency specified in the configuration command; If not, generate configuration data corresponding to the target frequency according to the configuration instructions, and update the frequency key-value pair using the configuration data; The target frequency is used as the operating frequency of the field-programmable gate array.

2. The frequency configuration method according to claim 1, characterized in that, Also includes: Obtain master control settings instructions; The master control device of the field-programmable gate array is determined according to the master control setting instructions; the master control device includes an operating system and a basic input / output system.

3. The frequency configuration method according to claim 1, characterized in that, Before determining whether the frequency key-value pairs currently supported by the system contain the target frequency specified in the configuration directive, the following steps are also included: Receive frequency query command; The frequency key-value pair stored in the flash memory is queried according to the frequency query instruction.

4. The frequency configuration method according to claim 1, characterized in that, If the frequency key-value pairs currently supported by the system include the target frequency in the configuration directive, they also include: Based on the index value corresponding to the target frequency in the frequency key-value pair, the target frequency is set as the operating frequency of the current system.

5. The frequency configuration method according to claim 4, characterized in that, Setting the target frequency as the operating frequency of the current system according to the index value corresponding to the target frequency in the frequency key-value pair includes: Determine the index value corresponding to the target frequency in the frequency key-value pair; The corresponding configuration data is read from the electrically erasable programmable read-only memory according to the serial number value; The correctness of the configuration data is verified. If the correctness verification passes, the configuration data will be applied to the current system.

6. The frequency configuration method according to claim 5, characterized in that, After setting the target frequency to the current system's operating frequency, the method further includes: Determine whether the target frequency has been set successfully; If not, rewrite the configuration data into the clock chip.

7. The frequency configuration method according to claim 5, characterized in that, After applying the configuration data to the current system, the following is also included: Perform a reset operation to cause the field-programmable gate array to operate at the target frequency.

8. A frequency configuration system for a field-programmable gate array (FPGA), characterized in that, include: The instruction acquisition module is used to acquire configuration instructions; The judgment module is used to determine whether the frequency key-value pairs supported by the current system contain the target frequency in the configuration instruction; A configuration module is used to generate configuration data corresponding to the target frequency according to the configuration instruction when the judgment result of the judgment module is negative, and to update the frequency key-value pair using the configuration data; The frequency setting module is used to set the target frequency as the operating frequency of the field-programmable gate array.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the frequency configuration method as described in any one of claims 1-7.

10. An electronic device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program, and the processor, when calling the computer program in the memory, implements the steps of the frequency configuration method as described in any one of claims 1-7.

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