A device, method and storage server compatible with encrypted serial ports and universal serial ports

Abstract

The application provides a device, a method and a storage server compatible with an encrypted serial port and a general serial port, the device comprising a serial port chip, an encryption module and a programmable logic chip; the programmable logic chip is connected with the control end of the encryption module; the input end of the encryption module is connected with the serial port chip through a first capacitor module; the output end is connected with the encrypted serial port through a second capacitor module; the serial port signal is encrypted through the encryption module after receiving the encrypted signal, and is output to the encrypted serial port; the serial port chip is further connected with the general serial port through a first resistor module and a third capacitor module in sequence; the encryption module is not powered on when no encrypted signal is received, and the serial port chip is output to the general serial port. Based on the device, the application further provides a method compatible with the encrypted serial port and the general serial port and a storage server. The application performs a laminated pad design on the serial port, uses the encrypted serial port as the general serial port when there is no encryption requirement, and realizes the compatibility of the encrypted serial port and the general serial port.

Description

Technical Field

[0001] This invention belongs to the field of hard disk encryption technology, and specifically relates to a device, method, and storage server that are compatible with both encrypted serial ports and general serial ports. Background Technology

[0002] With the rapid development of science and technology, companies and users are increasingly emphasizing information security. As a crucial medium for data storage, the security of hard drives is directly related to the user's interests. Encrypting hard drives to protect important information, mitigate the risk of accidental leaks, and reduce data loss through traditional means such as loss or theft is a current trend. Hard drive encryption refers to encrypting a computer user's hard drive to prevent information leakage. There are five methods for computer hard drive encryption: modifying the hard drive partition table information, adding a serial password to the hard drive boot process, implementing encrypted user management of the hard drive, implementing write protection for a specific logical drive, and encrypting disk sector data.

[0003] Existing computer motherboards often only support encrypted SATA serial ports or general SATA, and are not compatible with both. This results in the need for two types of motherboards to meet the needs of different customers, which is troublesome to manage and costly. Summary of the Invention

[0004] To address the aforementioned technical issues, this invention proposes a device, method, and storage server compatible with both encrypted and general-purpose serial ports. The encrypted port is encrypted using an encryption chip, and the serial port employs a stacked pad design. For customers without encryption requirements, the encrypted serial port can be used as a regular serial port, thus achieving compatibility with both encrypted and general-purpose serial ports.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A device compatible with both encrypted and general-purpose serial ports includes a serial port chip, an encryption module, and a programmable logic chip.

[0007] The programmable logic chip is connected to the control terminal of the encryption module; the input terminal of the encryption module is connected to the serial port chip through a first capacitor module; the output terminal of the encryption module is connected to the encrypted serial port through a second capacitor module; when the programmable logic chip receives an encryption signal, it encrypts the serial port signal through the encryption module and outputs it to the encrypted serial port.

[0008] The serial port chip is also connected to the general serial port in sequence through a first resistor module and a third capacitor module; when the programmable logic chip does not receive an encryption signal, it controls the encryption module to not be powered on, and the serial port chip outputs to the general serial port.

[0009] Furthermore, the device also includes a motherboard;

[0010] The motherboard is communicatively connected to the programmable logic chip; the motherboard is used to send instructions to the programmable logic chip regarding whether serial port signals need to be encrypted.

[0011] Furthermore, the number of capacitors in the first capacitor module is equal to the number of channels in a set of serial port signals; the number of capacitors in the second capacitor module is equal to the number of channels in a set of serial port signals; and the number of capacitors in the third capacitor module is equal to the number of channels in a set of serial port signals.

[0012] Furthermore, the number of resistors in the first resistor module is equal to the number of channels of a set of serial port signals.

[0013] Furthermore, the first capacitor module and the first resistor module constitute the first stack of pads.

[0014] Furthermore, the second capacitor module and the third capacitor module constitute a second stack of pads.

[0015] Furthermore, the serial port chip is a SATA serial port chip.

[0016] This invention also proposes a method compatible with both encrypted and general-purpose serial ports, implemented using a device compatible with both encrypted and general-purpose serial ports, comprising the following steps:

[0017] Receives encrypted signals for serial port encryption, controls the encryption module to encrypt the serial port signals, and outputs them to the encrypted serial port;

[0018] Alternatively, if no encryption signal is received, the encryption module can be kept off power, and the serial port chip can output to a general serial port.

[0019] Furthermore, the method also includes sending an instruction from the motherboard to the programmable logic chip regarding whether the serial port signal needs to be encrypted.

[0020] The present invention also proposes a storage server, including a device compatible with encrypted serial ports and general serial ports.

[0021] The effects described in the invention are merely those of the embodiments, and not all the effects of the invention. One of the above technical solutions has the following advantages or beneficial effects:

[0022] This invention proposes a device, method, and storage server compatible with both encrypted and general-purpose serial ports. The device includes a serial port chip, an encryption module, and a programmable logic chip. The programmable logic chip is connected to the control terminal of the encryption module. The input terminal of the encryption module is connected to the serial port chip via a first capacitor module. The output terminal of the encryption module is connected to the encrypted serial port via a second capacitor module. When the programmable logic chip receives an encryption signal, it encrypts the serial port signal through the encryption module and outputs it to the encrypted serial port. The serial port chip is also connected to the general-purpose serial port sequentially via a first resistor module and a third capacitor module. When the programmable logic chip does not receive an encryption signal, it controls the encryption module to remain powered off, and the serial port chip outputs to the general-purpose serial port. In this device, the first capacitor module and the first resistor module form a first stack of pads; the second capacitor module and the third capacitor module form a second stack of pads. Based on this device compatible with both encrypted and general-purpose serial ports, a method compatible with both encrypted and general-purpose serial ports and a storage server are also proposed. In this invention, the encrypted serial port is encrypted using an encryption chip located between the encryption chip and the encrypted serial port. This chip transparently and in real-time encrypts written data and decrypts read data, effectively preventing information theft, unauthorized reading, and modification. Simultaneously, the serial port employs a stacked pad design, allowing customers without encryption requirements to use it as a general-purpose serial port. This effectively solves the problem that existing computer motherboards often only support either encrypted or general-purpose serial ports, lacking compatibility between the two. This necessitates two types of motherboards to meet different customer needs, leading to cumbersome management and high costs. Attached Figure Description

[0023] like Figure 1 This is a schematic diagram of the connection of a device compatible with both encrypted serial ports and general serial ports according to Embodiment 1 of the present invention;

[0024] like Figure 2 This is a schematic diagram of a method compatible with both encrypted serial ports and general serial ports according to Embodiment 2 of the present invention. Detailed Implementation

[0025] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0026] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0028] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0029] When a component is referred to as being "on" or "above" another component, "connected to," or "joined to" another component, the component may be directly on, directly connected to, or directly joined to the other component, or there may be intermediate components. However, when a component is referred to as being "directly on" another component, "directly connected to," or "directly joined to" another component, there are no intermediate components. Therefore, the term "connection" can refer to a physical connection, an electrical connection, etc., and may or may not have intermediate components.

[0030] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0031] Example 1

[0032] Embodiment 1 of this invention proposes a device compatible with encrypted serial ports and general serial ports, which solves the problem that existing computer motherboards often only support encrypted serial ports or general serial ports and cannot be compatible with both. This results in the need for two types of motherboards to meet different customer needs, which is troublesome to manage and costly.

[0033] Co-lay refers to a design where two components share certain pads.

[0034] The present invention proposes a device compatible with both encrypted and general serial ports, comprising a serial port chip, an encryption module, and a programmable logic chip;

[0035] The programmable logic chip is connected to the control terminal of the encryption module; the input terminal of the encryption module is connected to the serial port chip through the first capacitor module; the output terminal of the encryption module is connected to the encrypted serial port through the second capacitor module; when the programmable logic chip receives an encryption signal, it encrypts the serial port signal through the encryption module and outputs it to the encrypted serial port.

[0036] The serial port chip is also connected to the general serial port in sequence through the first resistor module and the third capacitor module; when the programmable logic chip does not receive the encryption signal, it controls the encryption module to not be powered on, and the serial port chip outputs to the general serial port.

[0037] The encryption module in this application uses an encryption chip. An encryption chip is a general term for a type of security chip that integrates various symmetric and asymmetric algorithms, has an extremely high level of security, and can ensure that the keys and information data stored inside cannot be illegally read or tampered with.

[0038] The encryption chip used in this application can be the BHD5 chip. The hard disk data encryption chip BHD5-AS5 embeds a hardware-implemented 256-bit AES encryption algorithm and the State Cryptography Administration's SM1 cryptographic algorithm, enabling full-disk or partition encryption of the storage disk. Furthermore, the BHD5-AS5 chip embeds hardware-implemented State Cryptography Administration's SM2 and SM3 cryptographic algorithms, enabling identity verification and ensuring data security. It is suitable for commercial, defense, and government applications with high data security requirements.

[0039] The device also includes a motherboard; the motherboard is communicatively connected to the programmable logic chip; the motherboard is used to send instructions to the programmable logic chip on whether or not to encrypt the serial port signals.

[0040] The number of capacitors in the first capacitor module is equal to the number of channels in a set of serial port signals; the number of capacitors in the second capacitor module is equal to the number of channels in a set of serial port signals; the number of capacitors in the third capacitor module is equal to the number of channels in a set of serial port signals.

[0041] The number of resistors in the first resistor module is equal to the number of channels in a set of serial port signals.

[0042] The first capacitor module and the first resistor module form the first stack of pads; the second capacitor module and the third capacitor module form the second stack of pads.

[0043] like Figure 1 This is a schematic diagram of the device connection for an embodiment 1 of the present invention, which is compatible with both encrypted serial ports and general serial ports; in this application, the serial port is a SATA serial port.

[0044] SATA stands for Serial Advanced Technology Attachment. It's a computer bus primarily used for data transfer between the motherboard and various storage devices (such as hard drives and optical disc drives). It gets its name from its serial data transmission method and also boasts advantages like simple structure and hot-swapping support. The SATA bus uses an embedded clock frequency signal, providing stronger error correction capabilities than before. It can check transmission commands (not just data) and automatically correct errors, improving data transmission reliability. The most significant difference between SATA and previous models is the use of thinner ribbon cables, which improves airflow within the computer case and increases the overall platform stability.

[0045] This application enables SATA port encryption and also incorporates a colay design for the SATA port, allowing customers without encryption requirements to use the encrypted SATA port as a regular SATA port.

[0046] In this application, the programmable logic chip uses a CPLD (Complex Programmable Logic Device), which is a more complex logic element than a PLD. A CPLD is a digital integrated circuit whose logic functions are constructed by the user according to their own needs. Its basic design method involves using an integrated development software platform, employing schematic diagrams, hardware description languages, and other methods to generate corresponding target files. The code is then transferred to the target chip via a download cable ("in-system" programming) to realize the designed digital system.

[0047] exist Figure 1 In this circuit, a set of SATA signals consists of four signals. The SATA signals are encrypted by an encryption chip, and the encryption chip and the SATA chip are connected by four capacitors C1, C2, C3, and C4.

[0048] When the motherboard uses an encryption scheme, capacitors C1, C2, C3, and C4 between the encryption chip and the SATA chip are powered on, and the encryption chip output signal and the encryption port are connected through four capacitors C5, C6, C7, and C8.

[0049] When the motherboard uses an encryption scheme, the four capacitors C5, C6, C7, and C8 between the encryption chip output signal and the encryption port are powered on, and the motherboard encrypts the hard drive through the encryption chip.

[0050] When the motherboard uses an unencrypted solution, capacitors C1, C2, C3, C4, C5, C6, C7, and C8 between the encryption chip and the SATA port / SATA chip are not powered on.

[0051] When the motherboard is an unencrypted solution, the CPLD will detect that the motherboard is in a general-purpose state and control the encryption chip to not power on.

[0052] When the motherboard uses an unencrypted scheme, the four resistors R1, R2, R3, R4 and the four capacitors C9, C10, C11, C12 between the SATA chip and the SATA port are powered on, and the four SATA signals output by the SATA chip are directly output to the SATA port.

[0053] In this application, C1, C2, C3, C4 and R1, R2, R3 and R4 constitute a stacked pad design; C9, C10, C11, C12 and C5, C6, C7 and C8 constitute a stacked pad design.

[0054] In the device proposed in Embodiment 1 of this invention, which is compatible with both encrypted and general-purpose serial ports, the encrypted serial port is encrypted by an encryption chip located between the encryption chip and the encrypted serial port. This chip transparently and in real-time encrypts written data and decrypts read data, effectively preventing information theft, unauthorized reading, and modification. Simultaneously, the serial port features a stacked pad design, allowing customers without encryption requirements to use the encrypted serial port as a general-purpose serial port.

[0055] Example 2

[0056] Based on the device compatible with both encrypted and general-purpose serial ports proposed in Embodiment 1 of this invention, Embodiment 2 of this invention proposes a method compatible with both encrypted and general-purpose serial ports. This method is implemented based on a device compatible with both encrypted and general-purpose serial ports.

[0057] The device includes a serial port chip, an encryption module, and a programmable logic chip.

[0058] The programmable logic chip is connected to the control terminal of the encryption module; the input terminal of the encryption module is connected to the serial port chip through the first capacitor module; the output terminal of the encryption module is connected to the encrypted serial port through the second capacitor module; when the programmable logic chip receives an encryption signal, it encrypts the serial port signal through the encryption module and outputs it to the encrypted serial port.

[0059] The serial port chip is also connected to the general serial port in sequence through the first resistor module and the third capacitor module; when the programmable logic chip does not receive the encryption signal, it controls the encryption module to not be powered on, and the serial port chip outputs to the general serial port.

[0060] The encryption module in this application uses an encryption chip. An encryption chip is a general term for a type of security chip that integrates various symmetric and asymmetric algorithms, has an extremely high level of security, and can ensure that the keys and information data stored inside cannot be illegally read or tampered with.

[0061] The encryption chip used in this application can be the BHD5 chip. The hard disk data encryption chip BHD5-AS5 embeds a hardware-implemented 256-bit AES encryption algorithm and the State Cryptography Administration's SM1 cryptographic algorithm, enabling full-disk or partition encryption of the storage disk. Furthermore, the BHD5-AS5 chip embeds hardware-implemented State Cryptography Administration's SM2 and SM3 cryptographic algorithms, enabling identity verification and ensuring data security. It is suitable for commercial, defense, and government applications with high data security requirements.

[0062] The device also includes a motherboard; the motherboard is communicatively connected to the programmable logic chip; the motherboard is used to send instructions to the programmable logic chip on whether or not to encrypt the serial port signals.

[0063] The number of capacitors in the first capacitor module is equal to the number of channels in a set of serial port signals; the number of capacitors in the second capacitor module is equal to the number of channels in a set of serial port signals; the number of capacitors in the third capacitor module is equal to the number of channels in a set of serial port signals.

[0064] The number of resistors in the first resistor module is equal to the number of channels in a set of serial port signals.

[0065] The first capacitor module and the first resistor module form the first stack of pads; the second capacitor module and the third capacitor module form the second stack of pads.

[0066] SATA stands for Serial Advanced Technology Attachment. It's a computer bus primarily used for data transfer between the motherboard and various storage devices (such as hard drives and optical disc drives). It gets its name from its serial data transmission method and also boasts advantages like simple structure and hot-swapping support. The SATA bus uses an embedded clock frequency signal, providing stronger error correction capabilities than before. It can check transmission commands (not just data) and automatically correct errors, improving data transmission reliability. The most significant difference between SATA and previous models is the use of thinner ribbon cables, which improves airflow within the computer case and increases the overall platform stability.

[0067] This application enables SATA port encryption and also incorporates a colay design for the SATA port, allowing customers without encryption requirements to use the encrypted SATA port as a regular SATA port.

[0068] In this application, the programmable logic chip uses a CPLD (Complex Programmable Logic Device), which is a more complex logic element than a PLD. A CPLD is a digital integrated circuit whose logic functions are constructed by the user according to their own needs. Its basic design method involves using an integrated development software platform, employing schematic diagrams, hardware description languages, and other methods to generate corresponding target files. The code is then transferred to the target chip via a download cable ("in-system" programming) to realize the designed digital system.

[0069] like Figure 2 This is a schematic diagram of a method compatible with both encrypted serial ports and general serial ports according to Embodiment 2 of the present invention.

[0070] In step S200, an encryption signal for serial port encryption is received, the encryption module is controlled to encrypt the serial port signal, and output to the encrypted serial port; or when no encryption signal is received, the encryption module is controlled not to power on, and the serial port chip outputs to the general serial port.

[0071] The method also includes sending a command from the motherboard to the programmable logic chip indicating whether the serial port signal needs to be encrypted.

[0072] In Embodiment 1, the first capacitor module and the first resistor module constitute a first stack of pads; the second capacitor module and the third capacitor module constitute a second stack of pads.

[0073] Combination Figure 1 The method flow proposed in Embodiment 2 of the present invention is described in detail using the examples disclosed herein. Figure 1 In the middle, a set of SATA signals has 4 signals. The SATA signals are encrypted by an encryption chip. The encryption chip and the SATA chip are connected by four capacitors C1, C2, C3 and C4.

[0074] When the motherboard uses an encryption scheme, capacitors C1, C2, C3, and C4 between the encryption chip and the SATA chip are powered on, and the encryption chip output signal and the encryption port are connected through four capacitors C5, C6, C7, and C8.

[0075] When the motherboard uses an encryption scheme, the four capacitors C5, C6, C7, and C8 between the encryption chip output signal and the encryption port are powered on, and the motherboard encrypts the hard drive through the encryption chip.

[0076] When the motherboard uses an unencrypted solution, capacitors C1, C2, C3, C4, C5, C6, C7, and C8 between the encryption chip and the SATA port / SATA chip are not powered on.

[0077] When the motherboard is an unencrypted solution, the CPLD will detect that the motherboard is in a general-purpose state and control the encryption chip to not power on.

[0078] When the motherboard uses an unencrypted scheme, the four resistors R1, R2, R3, R4 and the four capacitors C9, C10, C11, C12 between the SATA chip and the SATA port are powered on, and the four SATA signals output by the SATA chip are directly output to the SATA port.

[0079] In this application, C1, C2, C3, C4 and R1, R2, R3 and R4 constitute a stacked pad design; C9, C10, C11, C12 and C5, C6, C7 and C8 constitute a stacked pad design.

[0080] When the CPLD receives the encryption signal sent by the motherboard, the CPLD controls the encryption chip to encrypt the serial port signal and outputs it to the encryption port. During the encryption process, capacitors C1, C2, C3, and C4 are powered on, and C5, C6, C7, and C8 are powered on.

[0081] When the CPLD does not receive the encryption signal sent by the motherboard, C1, C2, C3, C4, C5, C6, C7, and C8 are not powered on, while R1, R2, R3, R4 and four capacitors C9, C10, C11, and C12 are powered on, and the four SATA signals output by the SATA chip are directly output to the SATA port.

[0082] In Embodiment 2 of this invention, the encrypted serial port is encrypted using an encryption chip located between the encryption chip and the encrypted serial port. This chip transparently and in real-time encrypts written data and decrypts read data, effectively preventing information theft, unauthorized reading, and modification. Furthermore, the serial port features a stacked pad design, allowing customers without encryption requirements to use it as a general-purpose serial port.

[0083] The description of the relevant parts of the method compatible with encrypted serial ports and general serial ports provided in Embodiment 2 of this application can be found in the detailed description of the corresponding parts of the device compatible with encrypted serial ports and general serial ports provided in Embodiment 1 of this application, and will not be repeated here.

[0084] Example 3

[0085] Embodiment 3 of the present invention also proposes a storage server, which includes a device compatible with encrypted serial ports and general serial ports, the device including a serial port chip, an encryption module and a programmable logic chip;

[0086] The programmable logic chip is connected to the control terminal of the encryption module; the input terminal of the encryption module is connected to the serial port chip through the first capacitor module; the output terminal of the encryption module is connected to the encrypted serial port through the second capacitor module; when the programmable logic chip receives an encryption signal, it encrypts the serial port signal through the encryption module and outputs it to the encrypted serial port.

[0087] The serial port chip is also connected to the general serial port in sequence through the first resistor module and the third capacitor module; when the programmable logic chip does not receive the encryption signal, it controls the encryption module to not be powered on, and the serial port chip outputs to the general serial port.

[0088] The encryption module in this application uses an encryption chip. An encryption chip is a general term for a type of security chip that integrates various symmetric and asymmetric algorithms, has an extremely high level of security, and can ensure that the keys and information data stored inside cannot be illegally read or tampered with.

[0089] The device also includes a motherboard; the motherboard is communicatively connected to the programmable logic chip; the motherboard is used to send instructions to the programmable logic chip on whether or not to encrypt the serial port signals.

[0090] The number of capacitors in the first capacitor module is equal to the number of channels in a set of serial port signals; the number of capacitors in the second capacitor module is equal to the number of channels in a set of serial port signals; the number of capacitors in the third capacitor module is equal to the number of channels in a set of serial port signals.

[0091] The number of resistors in the first resistor module is equal to the number of channels in a set of serial port signals.

[0092] The first capacitor module and the first resistor module form the first stack of pads; the second capacitor module and the third capacitor module form the second stack of pads.

[0093] like Figure 1 This is a schematic diagram of the device connection for an embodiment 1 of the present invention, which is compatible with both encrypted serial ports and general serial ports; in this application, the serial port is a SATA serial port.

[0094] SATA stands for Serial Advanced Technology Attachment. It's a computer bus primarily used for data transfer between the motherboard and various storage devices (such as hard drives and optical disc drives). It gets its name from its serial data transmission method and also boasts advantages like simple structure and hot-swapping support. The SATA bus uses an embedded clock frequency signal, providing stronger error correction capabilities than before. It can check transmission commands (not just data) and automatically correct errors, improving data transmission reliability. The most significant difference between SATA and previous models is the use of thinner ribbon cables, which improves airflow within the computer case and increases the overall platform stability.

[0095] This application enables SATA port encryption and also incorporates a colay design for the SATA port, allowing customers without encryption requirements to use the encrypted SATA port as a regular SATA port.

[0096] In this application, the programmable logic chip uses a CPLD (Complex Programmable Logic Device), which is a more complex logic element than a PLD. A CPLD is a digital integrated circuit whose logic functions are constructed by the user according to their own needs. Its basic design method involves using an integrated development software platform, employing schematic diagrams, hardware description languages, and other methods to generate corresponding target files. The code is then transferred to the target chip via a download cable ("in-system" programming) to realize the designed digital system.

[0097] exist Figure 1 In this circuit, a set of SATA signals consists of four signals. The SATA signals are encrypted by an encryption chip, and the encryption chip and the SATA chip are connected by four capacitors C1, C2, C3, and C4.

[0098] When the motherboard uses an encryption scheme, capacitors C1, C2, C3, and C4 between the encryption chip and the SATA chip are powered on, and the encryption chip output signal and the encryption port are connected through four capacitors C5, C6, C7, and C8.

[0099] When the motherboard uses an encryption scheme, the four capacitors C5, C6, C7, and C8 between the encryption chip output signal and the encryption port are powered on, and the motherboard encrypts the hard drive through the encryption chip.

[0100] When the motherboard uses an unencrypted solution, capacitors C1, C2, C3, C4, C5, C6, C7, and C8 between the encryption chip and the SATA port / SATA chip are not powered on.

[0101] When the motherboard is an unencrypted solution, the CPLD will detect that the motherboard is in a general-purpose machine state and control the encryption chip to not power on.

[0102] When the motherboard uses an unencrypted scheme, the four resistors R1, R2, R3, R4 and the four capacitors C9, C10, C11, C12 between the SATA chip and the SATA port are powered on, and the four SATA signals output by the SATA chip are directly output to the SATA port.

[0103] In this application, C1, C2, C3, C4 and R1, R2, R3 and R4 constitute a stacked pad design; C9, C10, C11, C12 and C5, C6, C7 and C8 constitute a stacked pad design.

[0104] The working process of the device includes: when the CPLD receives the encryption signal sent by the motherboard, the CPLD controls the encryption chip to encrypt the serial port signal and outputs it to the encryption port. During the encryption process, capacitors C1, C2, C3, and C4 are powered on, and C5, C6, C7, and C8 are powered on.

[0105] When the CPLD does not receive the encryption signal sent by the motherboard, C1, C2, C3, C4, C5, C6, C7, and C8 are not powered on, while R1, R2, R3, R4 and four capacitors C9, C10, C11, and C12 are powered on, and the four SATA signals output by the SATA chip are directly output to the SATA port.

[0106] The storage server proposed in Embodiment 3 of this invention includes a device compatible with both encrypted serial ports and general serial ports. In this device, the encrypted serial port is encrypted by an encryption chip located between the encryption chip and the encrypted serial port. It transparently and in real time encrypts written data and decrypts read data, effectively preventing information theft, unauthorized reading and modification. At the same time, the serial port is designed with stacked pads, so customers who do not have encryption requirements can use the encrypted serial port as a general serial port.

[0107] The description of the relevant parts of the storage server provided in Embodiment 3 of this application can be found in the detailed description of the corresponding parts of the device compatible with encrypted serial ports and general serial ports provided in Embodiment 1 of this application, and will not be repeated here.

[0108] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that the elements inherent in a process, method, article, or apparatus that includes a list of elements are included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Additionally, portions of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0109] While specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art can make other modifications or variations based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. An apparatus compatible with an encrypted serial port and a general serial port, characterized by, The device comprises a serial port chip, an encryption module and a programmable logic chip. The programmable logic chip is connected to the control end of the encryption module; the input end of the encryption module is connected to the serial port chip through a first capacitor module; the output end of the encryption module is connected to an encrypted serial port through a second capacitor module; when the programmable logic chip receives an encryption signal, the encryption module encrypts the serial port signal and outputs the encrypted signal to the encrypted serial port; The serial port chip is further connected to a general serial port through a first resistor module and a third capacitor module in sequence; when the programmable logic chip does not receive an encryption signal, the encryption module is not powered on, and the serial port chip outputs to the general serial port; The number of capacitors in the first capacitor module is equal to the number of channels of a group of serial port signals; the number of capacitors in the second capacitor module is equal to the number of channels of a group of serial port signals; the number of capacitors in the third capacitor module is equal to the number of channels of a group of serial port signals; The number of resistors in the first resistor module is equal to the number of channels of a group of serial port signals; The first capacitor module and the first resistor module constitute a first stacked pad; The second capacitor module and the third capacitor module constitute a second stacked pad.

2. The apparatus for compatible encryption serial port and general serial port according to claim 1, characterized in that, The device further comprises a mainboard; The mainboard is in communication connection with the programmable logic chip; the mainboard is used to send an instruction to the programmable logic chip on whether the serial port signal needs to be encrypted.

3. The apparatus for compatible encryption serial port and general serial port according to any one of claims 1 to 2, characterized in that, The serial port chip is a SATA serial port chip.

4. A method for compatibility between encrypted serial ports and general serial ports, implemented based on the device for compatibility between encrypted serial ports and general serial ports according to any one of claims 1 to 3, characterized in that, The method comprises the following steps: Receiving an encryption signal for encrypting a serial port, controlling an encryption module to encrypt a serial port signal, and outputting the encrypted signal to an encrypted serial port; Or when no encryption signal is received, controlling the encryption module not to be powered on, and the serial port chip outputs to a general serial port.

5. The method of claim 4, wherein, The method further comprises sending an instruction to the programmable logic chip on whether the serial port signal needs to be encrypted through the mainboard.

6. A storage server, comprising: The device comprises a serial port chip, an encryption module and a programmable logic chip.

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