A method for calculating node voltage drop in a 2.5d integrated circuit power distribution network

Abstract

The application relates to a 2.5D integrated circuit power distribution network node voltage drop calculation method, which comprises the following steps: constructing an equivalent circuit model of a 2.5D integrated circuit; calculating the resistance between any two points in the power distribution network of the equivalent circuit model; calculating the voltage drop of the power distribution network in a silicon interposer according to the equivalent circuit model; calculating the voltage drop of the power distribution network in a chiplet according to the equivalent circuit model; judging whether the voltage drop of the power distribution network in the chiplet meets the chiplet noise tolerance; if not, modifying the distribution of the through silicon via in the silicon interposer and the position of the chiplet on the silicon interposer, and returning to the step of optimizing the voltage drop of the power distribution network in the chiplet; and if yes, selecting the distribution of the through silicon via in the silicon interposer and the optimal position of the chiplet on the silicon interposer according to the voltage drop of the power distribution network in the chiplet. The method can quickly calculate the PDN node IR-drop in a 2.5D integrated circuit with complex structure, and determine the placement position of the chiplet on the interposer.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a method for calculating the voltage drop of nodes in a 2.5D integrated circuit power distribution network. Background Technology

[0002] 2.5D integration technology refers to a packaging structure that interconnects chips with different functions through silicon interposers. In recent years, the urgent need for high-performance, high-bandwidth, and low-cost systems has spurred the rapid development of 2.5D integration technology. However, the realization of high-performance integrated systems has led to a gradual decrease in chip supply voltage. Furthermore, as the metal linewidth of the Power Distribution Network (PDN) becomes increasingly narrow, the voltage drop (IR-drop) at the nodes in the PDN continues to increase. Excessive IR-drop not only affects chip latency but can also cause logic errors in severe cases. To ensure that each chip functions properly, the voltage drop of the PDN nodes within each chip needs to be considered.

[0003] Currently, research on IR-drop based on interposers in 2.5D integrated circuits is limited, and there are no methods for calculating node IR-drop in 2.5D integrated PDNs. Current research on 2.5D integrated circuits mainly focuses on the simulation, testing, and optimization of IR-drop. J Kim, VCK Chekuri, NM Rahman, and others built a 2.5D integrated circuit based on interposers and chiplets, and conducted collaborative analysis and optimization of the chip, interposer, and PDN network, resulting in a 27.17% reduction in overall IR-drop from the interposer to the chip. However, this method still has shortcomings; it only simulates, tests, and optimizes the model and does not provide a deeper explanation of the theoretical formulas for IR-drop in 2.5D integrated PDN nodes. Huanyu He, Jian-Qiang Lu, and others proposed a theoretical calculation of IR-drop based on 3D integration technology. However, the method has the following shortcomings: it is not applicable to 2.5D integrated circuits, and it only calculates the maximum IR-drop on the chip without studying the node IR-drop. Therefore, this method is not applicable to the study of node IR-drop in 2.5D integrated PDN.

[0004] In summary, existing methods for studying 2.5D integrated circuits mainly focus on the simulation and optimization of chip IR-drop, without studying the theoretical formula for IR-drop in 2.5D integrated circuit PDN nodes. Furthermore, existing methods lead to excessively long simulation times for large-scale integrated circuits. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this invention provides a method for calculating the node voltage drop in a 2.5D integrated circuit power distribution network. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] This invention provides a method for calculating the node voltage drop in a 2.5D integrated circuit power distribution network, comprising the following steps:

[0007] S1. Construct an equivalent circuit model of a 2.5D integrated circuit. The power distribution network of the equivalent circuit model includes a power distribution network in the silicon insertion layer, a power distribution network in the die, a silicon via array in the silicon insertion layer, and a micro solder ball array.

[0008] S2. Calculate the resistance between any two points in the power distribution network of the equivalent circuit model;

[0009] S3. Based on the equivalent circuit model, calculate the voltage drop of the power distribution network in the silicon insertion layer using the resistance between any two points and the resistance of the silicon via in the silicon insertion layer;

[0010] S4. Based on the equivalent circuit model, and in conjunction with the voltage drop of the power distribution network in the silicon insertion layer, the resistance between any two points, the resistance of the redistribution layer in the power distribution network of the silicon insertion layer, the resistance of the silicon via in the die, and the resistance of the micro solder ball, calculate the voltage drop of the power distribution network in the die.

[0011] S5. Determine whether the voltage drop of the power distribution network node in the chip meets the chip noise tolerance. If not, modify the distribution of the vias in the silicon insertion layer and the position of the chip on the silicon insertion layer, and repeat steps S2-S4 to optimize the voltage drop of the power distribution network in the chip. If yes, select the distribution of the vias in the silicon insertion layer and the optimal position of the chip on the silicon insertion layer based on the voltage drop of the power distribution network in the chip.

[0012] In one embodiment of the present invention, the equivalent circuit model includes a silicon insertion layer and a plurality of chips, wherein,

[0013] The plurality of core particles are distributed on the silicon insertion layer, and each core particle is connected to the silicon insertion layer by a micro solder ball array;

[0014] The silicon insertion layer includes a silicon substrate, a silicon via array in the silicon insertion layer, a power distribution network in the silicon insertion layer, and a redistribution layer. The silicon substrate is part of the silicon insertion layer and is located at the bottom layer of the silicon insertion layer. The silicon via array in the silicon insertion layer is distributed in the silicon substrate. The power distribution network in the silicon insertion layer is disposed on the upper side of the silicon substrate. The redistribution layer is disposed on the upper side of the silicon substrate.

[0015] The chip includes a power distribution network and a through-silicon via array. The power distribution network is connected to the through-silicon via array via a micro solder ball array, and the power distribution network in the silicon insertion layer is connected to the through-silicon via array via the redistribution layer and the micro solder ball array.

[0016] In one embodiment of the present invention, step S2 includes:

[0017] In the case of DC circuit, the power distribution network is a purely resistive network. Therefore, the resistance formula between any two points u1(x1,y1) and u2(x2,y2) in the power distribution network is:

[0018]

[0019]

[0020]

[0021] Where m is the reference size of the source distribution network, and r is the resistance of the unit PDN network.

[0022] In one embodiment of the present invention, step S3 includes:

[0023] Since the voltage drop of the redistribution layer in the equivalent circuit model is related to the position of the chip, the voltage drop of the redistribution layer is not considered. The voltage drop of the power distribution network in the silicon insertion layer is calculated using the resistance between any two points and the resistance of the silicon via in the silicon insertion layer.

[0024] In one embodiment of the present invention, the voltage drop of the power distribution network in the silicon insertion layer is expressed as:

[0025]

[0026]

[0027]

[0028] R vn_TSV =R vn +R TSV

[0029] Rvi1(j)_TSV =R vi +R TSV

[0030] R vi2(t)_TSV =R vi +2R TSV

[0031] R in(j / t)_TSV =R in +R TSV

[0032] Where p1(x1,y1) are the node coordinates connecting the chip to the PDN network node in the silicon insertion layer, I load R represents the load current source. vn R is the resistance between the voltage source and the load node. vi R is the resistance between the voltage source and the current source. in Let n be the resistance between the current source and the load, n be the number of voltage sources, z be the number of load current sources, and Gx be the resistance between the current source and the load. i G represents the equivalent conductance between the i-th equivalent current source and the load current source after adding a correction factor, where Is(i) represents the i-th equivalent current source. i It represents the equivalent conductance between the i-th equivalent current source and the load current source.

[0033] In one embodiment of the present invention, the voltage drop of the power distribution network in the chip is expressed as:

[0034] ΔV(x,y)=ΔV(x1,y1)+ΔV(x c ,y c )

[0035]

[0036] R vn_chiplet =R vn +R(k)

[0037] R vi_chiplet =R vn +2R(k)

[0038] R in_chiplet =R vn +R(k)

[0039] R(k)=(k-1)R TSV_chiplet +k×R μ_solder +R rdl

[0040] L rdl =|x1-x2|+|y1-y2|

[0041]

[0042] Wherein, ΔV(x) c ,y c ) is the midpoint of the core (x) c ,y c The voltage drop of R TSV_chiplet R represents the resistance of the TSV in the chip. μ_solder R represents the resistance of the micro solder balls. rdl The redistribution layer resistance is given by p1(x1,y1), where p1(x1,y1) is the node coordinates connecting the core to the power distribution network node in the silicon insertion layer, p2(x2,y2) is the relative position coordinates of the core center on the silicon insertion layer, and W... rdl H represents the width of the RDL in the Interposer. rdl This indicates the height of the RDL in the Interposer.

[0043] In one embodiment of the present invention, step S5, optimizing the voltage drop of the power distribution network, includes:

[0044] The voltage drop of the power distribution network in the core is optimized using the particle swarm optimization algorithm.

[0045] In one embodiment of the present invention, step S5, which selects the distribution of silicon vias in the silicon insertion layer and the optimal position of the die on the silicon insertion layer based on the voltage drop of the power distribution network, includes:

[0046] The condition where the voltage drop of the power distribution network in the chip is at its minimum is selected as the distribution of silicon vias in the silicon insertion layer and the optimal position of the chip on the silicon insertion layer.

[0047] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0048] The calculation method of this invention proposes a theoretical formula for calculating the IR-drop of PDN nodes based on 2.5D integrated circuits. First, an equivalent circuit model of the 2.5D integrated circuit is established. Then, based on this model, the voltage drop of the power distribution network in the silicon insertion layer and the voltage drop of the power distribution network in the chip are calculated separately. These are then summed to obtain the total node voltage drop. The distribution of silicon vias in the silicon insertion layer and the distribution position of the chips are optimized. The calculation results are accurate, and the theoretical analysis model has a very short calculation time, which can calculate the IR-drop of PDN network nodes in a very short time. It can quickly calculate the IR-drop of PDN nodes in complex 2.5D integrated circuits. At the same time, based on the IR-drop of PDN network nodes in the chiplet and combined with the requirements, the method places the chiplet on the interposer in a reasonable way to achieve performance optimization. Attached Figure Description

[0049] Figure 1 A flowchart illustrating a method for calculating the node voltage drop of a 2.5D integrated circuit power distribution network, provided in an embodiment of the present invention;

[0050] Figure 2 A flowchart illustrating another method for calculating the node voltage drop of a 2.5D integrated circuit power distribution network provided in an embodiment of the present invention;

[0051] Figures 3a-3b A schematic diagram of the equivalent circuit model of a 2.5D integrated circuit provided in an embodiment of the present invention;

[0052] Figures 4a-4c A schematic diagram of the PDN structure and equivalent circuit used in the insertion layer and the core provided in this embodiment of the invention;

[0053] Figure 5 This is a schematic diagram of the relative positions of p1 and p2 coordinates and RDL provided in an embodiment of the present invention;

[0054] Figure 6 This invention provides an optimal solution for the placement of a Chiplet on an Interposer, as provided in an embodiment of the invention.

[0055] Figures 7a-7c A comparison chart of theoretical formulas and simulation results for IR-drop of PDN nodes in Chiplet provided in this embodiment of the invention. Detailed Implementation

[0056] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0057] Example 1

[0058] Please see Figure 1 and Figure 2 , Figure 1 This is a flowchart illustrating a method for calculating the node voltage drop of a 2.5D integrated circuit power distribution network according to an embodiment of the present invention. Figure 2 This is a flowchart illustrating another method for calculating the node voltage drop of a 2.5D integrated circuit power distribution network, provided in an embodiment of the present invention.

[0059] This method for calculating the node voltage drop in a 2.5D integrated circuit power distribution network can accurately and quickly calculate the node IR-drop. Based on this, the placement of the chipplet is optimized by calculating the IR-drop of the PDN node. The specific steps include:

[0060] S1. Construct an equivalent circuit model of a 2.5D integrated circuit. The power distribution network of the equivalent circuit model includes the power distribution network in the silicon insertion layer, the power distribution network in the die, the silicon through-hole array in the silicon insertion layer, and the micro solder ball array.

[0061] Please see Figures 3a-3b , Figures 3a-3b This is a schematic diagram of the equivalent circuit model of a 2.5D integrated circuit provided in an embodiment of the present invention. Figure 3a This is an overall schematic diagram. Figure 3b This is a side view.

[0062] like Figure 3a As shown, the equivalent circuit model of a 2.5D integrated circuit includes a PCB package substrate, a silicon interposer, and several chiplets.

[0063] Specifically, the silicon interposer is located on the top of the PCB package substrate, and several chiplets are distributed on the silicon interposer. Each chiplet is connected to the silicon interposer through a micro solder ball array.

[0064] Specifically, the silicon interposer includes a silicon substrate, a via array (TSV2) in the silicon interposer, a power distribution network (Power / ground1, i.e., PDN) in the silicon interposer, and a redistribution layer (RDL). The silicon substrate is part of the silicon interposer and is located at its bottom layer. The via array (TSV2) is distributed within the silicon substrate. The power distribution network (Power / ground1) is located above the silicon substrate, and the redistribution layer (RDL) is located above the power distribution network (Power / ground1).

[0065] Each chiplet includes a power distribution network (PDN) Power / ground2, a through-silicon via (TSV) array (TSV1), and a micro-solder ball array. The PDN Power / ground2 and TSV1 are located in alternating layers and are connected via the micro-solder ball array. The PDN Power / ground1 in the silicon insertion layer is connected to the TSV1 via a redistribution layer (RDL) and the micro-solder ball array.

[0066] S2. Calculate the resistance between any two points in the power distribution network of the equivalent circuit model.

[0067] Please see Figures 4a-4c , Figures 4a-4c This is a schematic diagram of a PDN structure and equivalent circuit used in an insertion layer and a core, provided for an embodiment of the present invention. Figure 4a For chip-sized on-chip PDN, Figure 4b For micro-solder ball arrays and through-silicon via arrays (TSV1), Figure 4c This is an on-chip PDN for a silicon interposer. Both the chiplet and the interposer have similar structures, both being mesh-like structures. The main differences are that the silicon interposer requires consideration of an RDL layer, while the chiplet can have multiple chip layers. Since this embodiment focuses on the DC circuit scenario, the power distribution network (PDN) is a purely resistive network. Figures 4a-4c As shown. The formula for the resistance between any two points u1(x1,y1) and u2(x2,y2) in a power distribution network with a reference size of m is:

[0068]

[0069]

[0070]

[0071] Where m is the reference size of the source distribution network, and r is the resistance of the unit PDN network.

[0072] S3. Based on the equivalent circuit model, calculate the voltage drop of the power distribution network in the silicon insertion layer using the resistance between any two points and the resistance of the silicon via in the silicon insertion layer.

[0073] Specifically, since the voltage drop of the redistribution layer RDL in the equivalent circuit model is related to the position of the chiplet, the voltage drop of the redistribution layer RDL is not considered. The voltage drop of the power distribution network in the silicon insertion layer is calculated using the resistance between any two points and the resistance of the silicon via in the silicon insertion layer. That is, the PDN node voltage drop IR-drop caused by the remaining part in the insertion layer Interposer can be expressed as:

[0074]

[0075]

[0076]

[0077] R vn_TSV=R vn +R TSV (7)

[0078] R vi1(j)_TSV =R vi +R TSV (8)

[0079] R vi2(t)_TSV =R vi +2R TSV (9)

[0080] R in(j / t)_TSV =R in +R TSV (10)

[0081] Where p1(x1,y1) are the node coordinates connecting the chip to the PDN network node in the silicon insertion layer, I load R represents the load current source. vn R is the resistance between the voltage source and the load node. vi R is the resistance between the voltage source and the current source. in Let n be the resistance between the current source and the load, n be the number of voltage sources, z be the number of load current sources, and Gx be the resistance between the current source and the load. i G represents the equivalent conductance between the i-th equivalent current source and the load current source after adding a correction factor, where Is(i) represents the i-th equivalent current source. i It represents the equivalent conductance between the i-th equivalent current source and the load current source.

[0082] S4. Based on the equivalent circuit model, and combining the voltage drop of the power distribution network in the silicon insertion layer, the resistance between any two points, the resistance of the redistribution layer in the power distribution network of the silicon insertion layer, the resistance of the silicon via in the die, and the resistance of the micro solder balls, calculate the voltage drop of the power distribution network in the die.

[0083] Specifically, when calculating the voltage drop IR-drop of the PDN nodes in the chipplet, the voltage drop of the redistribution layer (RDL) can be taken into account. Therefore, the voltage drop IR-drop of the PDN nodes in the chipplet includes the voltage drop IR-drop of the PDN nodes in the interposer layer and the voltage drop IR-drop of the PDN nodes in the chipplet itself. Thus, the voltage drop IR-drop of the PDN in the chipplet can be calculated by combining the voltage drop of the PDN in the silicon interposer layer, the resistance between any two points, the resistance of the redistribution layer, the resistance of the TSV1 in the chipplet, and the resistance of the solder balls, and is expressed as:

[0084] ΔV(x,y)=ΔV(x1,y1)+ΔV(x c,y c (11)

[0085]

[0086] R vn_chiplet =R vn +R(k) (13)

[0087] R vi_chiplet =R vn +2R(k) (14)

[0088] R in_chiplet =R vn +R(k) (15)

[0089] R(k)=(k-1)R TSV_chiplet +k×R μ_solder +R rdl (16)

[0090] L rdl =|x1-x2|+|y1-y2| (17)

[0091]

[0092] Where ΔV(x,y) is the IR-drop of the PDN node in the Chiplet, ΔV(x1,y1) is the voltage drop IR-drop at point p1(x1,y1) in the Interposer of the insertion layer, and ΔV(x c ,y c ) is the midpoint of the chiplet (x) c ,y c The voltage drop of R TSV_chiplet R represents the resistance of the TSV in the chiplet. μ_solder R represents the resistance of the micro solder balls. rdl W represents the resistance of the redistribution layer RDL. rdl H represents the width of the RDL in the Interposer. rdl Indicates the height of the RDL in the Interposer; such as Figure 5 As shown, Figure 5 The diagram shows the relative positions of p1 and p2 and the RDL provided in this embodiment of the invention. The blue network at the bottom is part of the PDN node network of the Interposer, the red part is the RDL layer, and the gold network at the top is part of the PDN node network of the Chiplet. p1(x1,y1) is the node coordinate of the chip connected to the power distribution network node in the silicon insertion layer Interposer, and p2(x2,y2) is the relative position coordinate of the center of the chip on the silicon insertion layer Interposer.

[0093] S5. Determine whether the voltage drop of the power distribution network nodes in the chip meets the chip noise tolerance. If not, modify the distribution of silicon vias in the silicon insertion layer and the position of the chip on the silicon insertion layer, and repeat steps S2-S4 to optimize the voltage drop of the power distribution network in the chip. If yes, select the optimal distribution of silicon vias in the silicon insertion layer and the optimal position of the chip on the silicon insertion layer based on the voltage drop of the power distribution network in the chip.

[0094] Specifically, the chip noise margin refers to the voltage drop threshold.

[0095] If the maximum voltage drop of the power distribution network in the chip is greater than or equal to the voltage drop threshold, then the distribution of TSV2 in the silicon insertion layer and the position of the chiplet on the silicon insertion layer interposer do not meet the requirements. Therefore, the distribution of TSV2 in the silicon insertion layer and the placement of the chiplet on the silicon insertion layer interposer are modified, and steps S2-S4 are repeated to recalculate the voltage drop of the power distribution network in the chip until the maximum voltage drop of the power distribution network in the chip is less than the voltage drop threshold. Specifically, the distribution of TSVs and the position of the chiplets can be optimized using a particle swarm optimization algorithm to minimize the chiplet voltage drop.

[0096] If the maximum voltage drop of the power distribution network in the chip is less than the voltage drop threshold, there are multiple possible distributions of TSV2 in the silicon insertion layer and the placement of the chip on the silicon insertion layer interposer. The optimal distribution of TSV2 in the silicon insertion layer and the optimal position of the chip are selected when the voltage drop of the power distribution network in the chip is minimized. Figure 6 As shown, Figure 6 This invention provides an optimal solution for the placement of a Chiplet on an Interposer, as provided in an embodiment of the invention.

[0097] The calculation method implemented here is based on a theoretical formula for calculating the IR-drop of PDN nodes using 2.5D integrated circuits. First, an equivalent circuit model of the 2.5D integrated circuit is established. Then, based on this model, the voltage drop of the power distribution network in the silicon insertion layer and the voltage drop of the power distribution network in the chip are calculated, thus obtaining the total voltage drop of the power distribution network. Optimization is then performed to obtain the distribution of silicon vias in the silicon insertion layer and the chip position. The calculation results are accurate, and the theoretical analysis model has a very short calculation time, enabling rapid calculation of the IR-drop of PDN network nodes in a short period. This allows for fast calculation of the IR-drop of PDN nodes in complex 2.5D integrated circuits. Furthermore, based on the IR-drop of PDN network nodes in the chiplet and combined with requirements, this method optimizes the placement of the chiplet on the interposer to achieve optimal performance.

[0098] Furthermore, this embodiment verifies the above method through experiments.

[0099] Specifically, an analysis model is built using the theoretical formulas in step 2, and a simulation model is built using ADS. The simulation results of the analysis model built using the theoretical formulas and the simulation model built using ADS are then compared.

[0100] like Figures 7a-7c As shown, Figures 7a-7c This is a comparison chart of the theoretical formula and simulation results of PDN node IR-drop in Chiplet provided in this embodiment of the invention. Figure 7a A comparison of the theoretical formula and simulation results for the IR-drop of the Chiplet1 node. Figure 7b A comparison of the theoretical formula and simulation results for the IR-drop of the first-layer chip node in Chiplet2. Figure 7c A comparison of the theoretical formula and simulation results for the IR-drop of the second-layer chip node in Chiplet2.

[0101] like Figure 7a As shown, the maximum IR-drop error of the PDN network node in Chiplet1 is 0.36498mV, located at point (3,3). This error is less than 1‰ of the supply voltage. The maximum percentage error of the PDN network node ((theoretical calculation - model simulation) / model simulation * 100%) is 2.62%, also located at point (3,3). The table below shows the results of comparing the theoretical analysis model and the simulation model.

[0102] Theoretical analysis model Simulation model error(%) Maximum IR-drop(mV) 22.03 21.8845 0.67 Average IR-drop (mV) 17.082 16.8618 1.31 Minimum IR-drop(mV) 14.2896 13.9246 2.62

[0103] like Figure 7bAs shown, the maximum IR-drop error of the PDN network node in the first layer of Chiplet2 is 0.85638mV, located at point (1,2). This error is less than 1‰ of the supply voltage. The maximum percentage error of the PDN network node is 3.59%, located at point (2,3), with an error value of 0.81587mV.

[0104] like Figure 7c As shown, the maximum IR-drop error of the PDN network node in the second layer of Chiplet2 is 0.868996mV, located at point (1,2). This error is less than 1‰ of the supply voltage. The maximum percentage error of the PDN network node is 3.28%, located at point (2,3), with an error value of 0.820871mV.

[0105] The theoretical analysis model takes 0.465 seconds to calculate.

[0106] Based on the above results, the maximum error of the theoretical analysis model is 3.59%, and the calculation time is less than 1 second. This demonstrates that the theoretical analysis model in this embodiment can quickly and accurately calculate the IR-drop of PDN network nodes. Furthermore, based on the theoretical analysis model, the appropriate placement of chiplets can be implemented according to requirements.

[0107] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for calculating the node voltage drop in a 2.5D integrated circuit power distribution network, characterized in that, Including the following steps: S1. Construct an equivalent circuit model of a 2.5D integrated circuit; the equivalent circuit model includes a silicon insertion layer and several chips, wherein the chips are distributed on the silicon insertion layer, and each chip is connected to the silicon insertion layer through a micro solder ball array; the silicon insertion layer includes a silicon substrate, a through-silicon via (TSV) array in the silicon insertion layer, a power distribution network in the silicon insertion layer, and a redistribution layer, wherein the silicon substrate is part of the silicon insertion layer and is located at the bottom layer of the silicon insertion layer, the TSV array in the silicon insertion layer is distributed in the silicon substrate, the power distribution network in the silicon insertion layer is disposed on the upper side of the silicon substrate, and the redistribution layer is disposed on the upper side of the silicon substrate; each chip includes a power distribution network in the chip and a TSV array in the chip, the power distribution network in the chip is connected to the TSV array in the chip through a micro solder ball array, and the power distribution network in the silicon insertion layer is connected to the TSV array in the chip through the redistribution layer and the micro solder ball array; The power distribution network of the equivalent circuit model includes a power distribution network in the silicon insertion layer, a power distribution network in the chip, a silicon via array in the silicon insertion layer, and a micro solder ball array. S2. Calculate the resistance between any two points in the power distribution network of the equivalent circuit model; S3. Based on the equivalent circuit model, calculate the voltage drop of the power distribution network in the silicon insertion layer using the resistance between any two points and the resistance of the silicon via in the silicon insertion layer; S4. Based on the equivalent circuit model, and in conjunction with the voltage drop of the power distribution network in the silicon insertion layer, the resistance between any two points, the resistance of the redistribution layer in the power distribution network of the silicon insertion layer, the resistance of the silicon via in the die, and the resistance of the micro solder ball, calculate the voltage drop of the power distribution network in the die. S5. Determine whether the voltage drop of the power distribution network node in the chip meets the chip noise tolerance. If not, modify the distribution of the vias in the silicon insertion layer and the position of the chip on the silicon insertion layer, and repeat steps S2-S4 to optimize the voltage drop of the power distribution network in the chip. If yes, select the distribution of the vias in the silicon insertion layer and the optimal position of the chip on the silicon insertion layer based on the voltage drop of the power distribution network in the chip.

2. The method for calculating the node voltage drop of a 2.5D integrated circuit power distribution network according to claim 1, characterized in that, Step S2 includes: In the case of DC circuit, the power distribution network is a purely resistive network. Therefore, any two points in the power distribution network... and The formula for the resistance between them is: Where m is the reference size of the source distribution network, and r is the resistance of the unit PDN network.

3. The method for calculating the node voltage drop of a 2.5D integrated circuit power distribution network according to claim 1, characterized in that, Step S3 includes: Since the voltage drop of the redistribution layer in the equivalent circuit model is related to the position of the chip, the voltage drop of the redistribution layer is not considered. The voltage drop of the power distribution network in the silicon insertion layer is calculated using the resistance between any two points and the resistance of the silicon via in the silicon insertion layer.

4. The method for calculating the node voltage drop of a 2.5D integrated circuit power distribution network according to claim 3, characterized in that, The voltage drop of the power distribution network in the silicon insertion layer is expressed as: in, These are the coordinates of the nodes connecting the chip to the PDN network nodes in the silicon insertion layer. Indicates the load current source. The resistance between the voltage source and the load node. The resistance between the voltage source and the current source. Let n be the resistance between the current source and the load, n be the number of voltage sources, and z be the number of load current sources. This represents the equivalent conductance between the i-th equivalent current source and the load current source after adding a correction factor. This represents the i-th equivalent current source. It represents the equivalent conductance between the i-th equivalent current source and the load current source.

5. The method for calculating the node voltage drop of a 2.5D integrated circuit power distribution network according to claim 1, characterized in that, The voltage drop of the power distribution network in the core is expressed as: in, Midpoint of the core voltage drop, This indicates the resistance of the TSV within the chip. This indicates the resistance value of the micro solder balls. For the redistribution layer resistance, The coordinates of the nodes connecting the chip to the power distribution network nodes in the silicon insertion layer. These are the relative position coordinates of the core center on the silicon insertion layer. This indicates the width of the RDL in the Interposer. This indicates the height of the RDL in the Interposer.

6. The method for calculating the node voltage drop of a 2.5D integrated circuit power distribution network according to claim 1, characterized in that, Step S5 optimizes the voltage drop of the power distribution network, including: The voltage drop of the power distribution network in the core is optimized using the particle swarm optimization algorithm.

7. The method for calculating the node voltage drop of a 2.5D integrated circuit power distribution network according to claim 1, characterized in that, Step S5 involves selecting the distribution of silicon vias in the silicon insertion layer and the optimal position of the die on the silicon insertion layer based on the voltage drop of the power distribution network, including: The distribution of silicon vias in the silicon insertion layer and the optimal position of the core are selected when the voltage drop of the power distribution network in the core is at its minimum.

Images