Data driving circuit and display device including the same

Abstract

A data driving circuit and a display apparatus including the same are provided. The present disclosure provides a display apparatus including a display panel configured to display an image, a scan driving circuit configured to provide a scan signal to the display panel, and a data driving circuit configured to provide a data voltage to the display panel, wherein the data driving circuit includes a data controller configured to change output timing of the data voltage based on independent control of each of at least one latch.

Description

Technical Field

[0001] This disclosure relates to a data driving circuit and a display device including the data driving circuit. Background Technology

[0002] With the development of information technology, the market for display devices, which serve as the connection medium between users and information, has been growing. Consequently, the use of display devices such as light-emitting diodes (LEDs), quantum dot displays (QDDs), and liquid crystal displays (LCDs) has increased.

[0003] The aforementioned display devices all include a display panel containing sub-pixels, a drive unit configured to output drive signals for driving the display panel, and a power supply unit configured to generate power to be supplied to the display panel or the drive unit.

[0004] In each display device, when a drive signal (e.g., a scan signal, a data signal, etc.) is provided to a subpixel formed in the display panel, an image can be displayed through a selected subpixel that transmits light or emits light directly. Summary of the Invention

[0005] Therefore, this disclosure relates to a data driving unit and a display device including the data driving unit, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0006] The purpose of this disclosure is to prevent or mitigate display defects (so-called color mixing) caused by time delay of scan signals by changing the output timing of the data voltage based on independent control of each of at least one latch, thereby increasing effectiveness during high-speed driving.

[0007] Further advantages, objects, and features of this disclosure will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art upon examination of the following, or may be learned by practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, its claims, and the accompanying drawings.

[0008] To achieve these and other advantages, and in accordance with the purposes of this disclosure, as embodied and broadly described herein, a display device includes: a display panel configured to display an image; a scan drive circuit configured to provide a scan signal to the display panel; and a data drive circuit configured to provide a data voltage to the display panel. The data drive circuit includes a data controller configured to change the output timing of the data voltage based on independent control of each of at least one latch.

[0009] The data controller can independently control the sampling time or hold time of each data signal by controlling the latch enable signal applied to the latch, thereby changing the output timing of the data voltage.

[0010] The latches included in the data drive circuit can store data signals simultaneously, and in response to the latch enable signal, the output timing can be different for each of at least one latch.

[0011] The latches included in the data driving circuit may include a latch that outputs one of the data signals first and a latch that outputs one of the data signals last, and the output timing of the output data signals may be gradually changed for the latches located in between.

[0012] The data drive circuit can be controlled to gradually delay the timing of the data voltage output from the right side of the display panel toward the center, and also gradually delay the timing of the data voltage output from the left side of the display panel toward the center.

[0013] The data driving circuit can first output data voltage in the left and right parts of the display panel, and finally output data voltage in the center part of the display panel.

[0014] The data controller may include a plurality of delayers configured to delay a latch enable signal, and each of the plurality of delayers may add a delay value to an undelayed latch enable signal to output a delayed latch enable signal.

[0015] In another aspect of this disclosure, a data driving circuit includes: a plurality of latches configured to store data signals; a plurality of digital-to-analog converters configured to convert the data signals output from the plurality of latches into data voltages; a plurality of output circuits configured to amplify and output the data voltages output from the digital-to-analog converters; and a data controller configured to control the plurality of latches such that the output timing of changing the data voltages is adjusted for each of at least one channel.

[0016] The plurality of latches can store data signals simultaneously, and in response to a latch enable signal, the timing of each output in at least one latch can be different.

[0017] Multiple latches may include one of the latches that outputs one of the data signals first and one of the latches that outputs one of the data signals last, and the output timing of the data signals may vary gradually for the latches located in between.

[0018] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0020] Figure 1 This is a schematic block diagram illustrating a light-emitting display device. Figure 2 It is shown schematically. Figure 1 The diagram shows the configuration of the sub-pixels;

[0021] Figure 3 and Figure 4 This is a diagram used to describe the configuration of the in-panel gate-in-the-in-the-inside (GIP) type scan drive unit. Figure 5A and Figure 5B This is a diagram showing an example of the arrangement of a GIP-type scan drive unit, and Figures 6A to 6D This is an illustrative diagram showing an example of the shape of a display panel;

[0022] Figure 7 This is a diagram illustrating a portion of a light-emitting display device according to an embodiment of the present disclosure. Figure 8 This is a waveform diagram showing the output state of the data voltage according to an embodiment of the present disclosure. Figure 9 It is used to indicate the application of the display panel. Figure 8 The diagram shows the region of data voltage, and Figure 10 and Figure 11 These are diagrams illustrating aspects before and after the application of embodiments of this disclosure; and

[0023] Figure 12 This is an illustrative configuration diagram of a data-driven unit according to an embodiment of the present disclosure, and Figure 13 This shows the output as... Figure 8 An illustrative configuration diagram of the control method for the data voltage latch shown. Detailed Implementation

[0024] Reference will now be made in detail to preferred embodiments of the present disclosure, examples of which are shown in the accompanying drawings. Wherever possible, the same reference numerals are used in all the drawings to denote the same or similar parts.

[0025] The display device according to this disclosure can be implemented as a television, video player, personal computer (PC), home theater, automotive electronics, smartphone, etc., but is not limited thereto. The display device according to this disclosure can be implemented as LED, QDD, LCD, etc. However, for ease of description, a light-emitting display device based on direct light emission from inorganic light-emitting diodes or organic light-emitting diodes will be given as an example below.

[0026] Figure 1 It schematically shows the configuration of the light-emitting display device, and Figure 2 It is shown schematically. Figure 1 The diagram shows the sub-pixel.

[0027] like Figure 1 and Figure 2 As shown, the light-emitting display device may include an image providing unit (circuit) 110, a timing controller 120, a scanning driving unit (circuit) 130, a data driving unit (circuit) 140, a display panel 150, a power supply unit (circuit) 180, etc.

[0028] The image providing unit (setting system or host system) 110 can output various drive signals along with image data signals provided externally or stored in internal memory. The image providing unit 110 can provide data signals and various drive signals to the timing controller 120.

[0029] The timing controller 120 can output a gating timing control signal GDC for controlling the operation timing of the scan drive unit 130, a data timing control signal DDC for controlling the operation timing of the data drive unit 140, and various synchronization signals (Vsync as a vertical synchronization signal and Hsync as a horizontal synchronization signal). The timing controller 120 can provide the data signal DATA provided from the image providing unit 110 together with the data timing control signal DDC to the data drive unit 140. The timing controller 120 can be formed as an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

[0030] The scan drive unit 130 can output a scan signal (or scan voltage) in response to a gating timing control signal GDC provided from the timing controller 120. The scan drive unit 130 can provide scan signals to sub-pixels included in the display panel 150 via gating lines GL1 to GLm. The scan drive unit 130 can be formed as an IC or can be formed directly on the display panel 150 using a GIP method, but is not limited thereto.

[0031] The data driving unit 140 can sample and latch the data signal DATA in response to the data timing control signal DDC provided from the timing controller 120, convert the digital data signal into an analog data voltage based on the gamma reference voltage, and output the analog data voltage. The data driving unit 140 can provide data voltage to the sub-pixels included in the display panel 150 via data lines DL1 to DLn. The data driving unit 140 can be formed as an IC and mounted on the display panel 150 or mounted on a printed circuit board, but is not limited thereto.

[0032] The power supply unit 180 can generate a first power with a high potential and a second power with a low potential based on an externally supplied input voltage, and output the first power and the second power through a first power line EVDD and a second power line EVSS. In addition to the first power and the second power, the power supply unit 180 can generate and output voltages required to drive the scan drive unit 130 (e.g., gating voltages including gating high voltage and gating low voltage) or voltages required to drive the data drive unit 140 (including drain voltage and half-drain voltage).

[0033] The display panel 150 can display images in response to drive signals including scan signals and data voltages, first power, second power, etc. The sub-pixels of the display panel 150 emit light directly. The display panel 150 can be manufactured based on a rigid or flexible substrate such as glass, silicon, or polyimide. Furthermore, the light-emitting sub-pixels can include pixels containing red, green, and blue, or pixels containing red, green, blue, and white. However, this disclosure is not limited thereto. For example, color combinations such as yellow, magenta, and cyan are also possible.

[0034] For example, a sub-pixel SP can be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS, and can include pixel circuitry with switching transistors, driving transistors, capacitors, organic light-emitting diodes (OLEDs), etc. Since the sub-pixel SP used in a light-emitting display device emits light directly, the circuit configuration is complex. Furthermore, various compensation circuits exist for compensating for degradation of the OLED emitting light, as well as driving transistors that provide the driving current required to drive the OLED. Therefore, it should be noted that the sub-pixel SP is simply shown in block form.

[0035] Meanwhile, in the above description, the timing controller 120, the scan drive unit 130, and the data drive unit 140 have been described as separate components. However, depending on the implementation method of the light-emitting display device, one or more of the timing controller 120, the scan drive unit 130, and the data drive unit 140 can be integrated into a single IC.

[0036] Figure 3 and Figure 4 This is a diagram used to describe the configuration of the GIP-type scan drive unit. Figure 5A and Figure 5B This is a diagram showing an example of the arrangement of a GIP-type scan drive unit, and Figures 6A to 6D This is an illustrative diagram showing an example of the shape of a display panel.

[0037] like Figure 3As shown, the GIP-type scan drive unit 130 may include a shift register 131 and a level shifter 135. The level shifter 135 can generate a drive clock signal Clk and a start signal Vst based on signals and voltages output from the timing controller 120 and the power supply unit 180. The drive clock signal Clk can be generated in the form of j different phases (j is an integer greater than or equal to 2), such as two-phase, four-phase, and eight-phase.

[0038] The shift register 131 can be operated based on the signals Clk and Vst output from the level shifter 135, and output scan signals Scan[1] to Scan[m] that can turn on or off the transistors formed on the display panel. The shift register 131 can be formed as a thin film on the display panel using the GIP method.

[0039] like Figure 3 and Figure 4 As shown, unlike shift register 131, level shifter 135 can be configured as an IC independently or can be included in power supply unit 180. This is just an example, and this disclosure is not limited thereto.

[0040] like Figure 5A and Figure 5B As shown, shift registers 131a and 131b, which output scan signals in the GIP-type scan drive unit, can be located in the non-display area NA of the display panel 150. Shift registers 131a and 131b can be located in the left and right non-display areas NA of the display panel 150, or in the upper and lower non-display areas NA of the display panel 150. Meanwhile, in Figure 5A and Figure 5B In the diagram, shift registers 131a and 131b are shown and described as examples in the non-display area NA. However, this disclosure is not limited thereto.

[0041] like Figures 6A to 6D As shown, the display panel 150 can be in the form of a rectangle (or quadrilateral) ( Figure 6A ), circle ( Figure 6B ), oval ( Figure 6C ) and hexagon ( Figure 6D Various shapes can be achieved. Besides... Figure 6A In addition to the commonly used rectangular display panel 150 shown, Figures 6B to 6D Each of the display panels 150 has a different shape (an uncommon shape), and is therefore also referred to as a deformable display panel.

[0042] Figure 7 This is a diagram illustrating a portion of a light-emitting display device according to an embodiment of the present disclosure. Figure 8This is a waveform diagram showing the output state of the data voltage according to an embodiment of the present disclosure. Figure 9 It is used for indicating the display panel. Figure 8 The diagram shows the region of data voltage, and Figure 10 and Figure 11 These are diagrams illustrating aspects before and after the application of embodiments of this disclosure.

[0043] like Figure 7 As shown, according to embodiments of this disclosure, the timing controller 120 and the data driving unit 140 can use communication methods to send and receive various signals. For example, the timing controller 120 and the data driving unit 140 can use communication methods such as an embedded clock point-to-point interface (EPI) based on an embedded clock method to send and receive various signals.

[0044] The data drive unit 140 may include a data controller 145 (CON), a shift register 142 (SR), a latch 144 (LAT), a digital-to-analog (DA) converter 146 (DAC), an output unit 148 (AMP), etc. The data controller 145 (CON) can control the shift register 142, the latch 144, the DA converter 146, and the output unit 148 based on various signals included in control packets and data packets sent through the EPI interface (EPI).

[0045] Shift register 142 can parallelize serial data signals provided from a timing controller. Latch 144 can store data signals input from external sources line by line under the control of shift register 142. DA converter 146 can convert the data signal output from latch 144 into a data voltage. Output unit 148 can amplify and output the data voltage output from DA converter 146.

[0046] The shift register 142, latch 144, DA converter 146, and output unit 148 can convert the data signal to be applied to the display panel 150 into a data voltage, and output the data voltage under the control of the data controller 145. Meanwhile, the latch 144 may include a first latch (sampling latch) that samples and outputs a digital data signal, and a second latch (holding latch) that holds and outputs the digital data signal output from the first latch. Furthermore, Figure 7 The internal blocks of the data-driven unit 140 shown are illustrated only by way of example and are not limited thereto.

[0047] like Figure 7 and Figure 8As shown, according to an embodiment of the present disclosure, the data driving unit 140 can independently control the latch 144 to change the output timing of the data voltage output through the output channel of the output unit 148.

[0048] More specifically, even if the data signal DATA input to the data drive unit 140 is stored in all latches 144 at the same time, its output timing can be changed for each of at least one latch 144 in response to the signal output from the data controller 145.

[0049] according to Figure 8 For example, latches 144 connected to the first to the 160th output channels (S1 to S160), the 161st to the 320th output channels (S161 to S320), the 2561st to the 2720th output channels (S2561 to S2720), and the 2721st to the 2880th output channels (S2721 to S2880) can simultaneously output data signals. Furthermore, latches 144 connected thereto can output data signals first within the latch itself.

[0050] However, although the latches 144 connected to the output channels 1281 to 1440 (S1281 to S1440) and the output channels 1441 to 1600 (S1441 to S1600) output data signals simultaneously, these latches 144 can output the data signal last among the latches.

[0051] Furthermore, the latch connected to the output channel between the latch 144 that first outputs the data signal and the latch 144 that outputs the data signal last can be changed, so that the output timing of the output data signal is gradually delayed (later).

[0052] For example, the output timing of latch 144 connected to the output channels located next to the first to 160 output channels (S1 to S160) and the 161 to 320 output channels (S161 to S320) can be defined as after the latch 144 that first outputs the data signal. That is, latch 144 connected to the output channels located next to the first to 160 output channels (S1 to S160) and the 161 to 320 output channels (S161 to S320) can have an output timing that is delayed by a first time compared to the latch 144 that first outputs the data signal.

[0053] Furthermore, the output timing of latch 144 connected to the output channels preceding output channels 1281 to 1440 (S1281 to S1440) can be defined as preceding the latch 144 that outputs the last data signal. That is, latch 144 connected to the output channels preceding output channels 1281 to 1440 (S1281 to S1440) can have an output timing that is a first time earlier than the latch 144 that outputs the last data signal.

[0054] This output mode can continue not only to the Nth data signal NDATA, but also to the (N+1)th data signal N+1DATA located thereafter.

[0055] like Figure 8 and Figure 9 As shown, the first to the 160th output channels (S1 to S160) and the 161st to the 320th output channels (S161 to S320) can provide data voltage to the right side of the display panel 150. Additionally, the 2561st to the 2720th output channels (S2561 to S2720) and the 2721st to the 2880th output channels (S2721 to S2880) can provide data voltage to the right side of the display panel 150. Furthermore, the 1281st to the 1440th output channels (S1281 to S1440) and the 1441st to the 1600th output channels (S1441 to S1600) can provide data voltage to the central portion of the display panel 150.

[0056] As from Figure 8 and Figure 9 As can be seen from the correspondence, according to Figure 7 The data driving unit 140 of the embodiment of the present disclosure shown can first output data voltages to be provided to the right and left portions of the display panel 150, and finally output data voltages to be provided to the central portion of the display panel 150.

[0057] Furthermore, the timing of the data voltage output can be gradually delayed from the left side of the display panel 150 towards the center, and the timing of the data voltage output can be gradually delayed from the right side of the display panel 150 towards the center.

[0058] The following will describe the reason for changing the output timing so that the output of data voltage based on the left and right portions of the display panel 150 as described above starts from the left and right portions of the display panel 150 and ends at the central portion of the display panel 150.

[0059] like Figure 10As shown, prior to applying this embodiment, data voltages output at the same output timing may be applied to the side portions and the central portion of the display panel. This can be seen by referring to the side portion data voltage (side portion Vdata) applied to each side portion of the display panel and the central portion data voltage (central portion Vdata) applied to the central portion of the display panel.

[0060] Scan signals with different waveforms may be applied to each side portion and the central portion of the display panel, which can be seen by referring to the side portion scan signal applied to each side portion of the display panel (side portion Scan) and the central portion scan signal applied to the central portion (central portion Scan).

[0061] The display panel may include pixels in the form of thin films, shift registers in the form of GIPs, and wires for applying signals and voltages to it. When the wires are far from the input points of the input signals and voltages, they may be affected by resistors, parasitic capacitances, etc. Furthermore, the wires may be affected by load Δd caused by signals, voltages, etc. In addition, shift registers in the form of GIPs may be affected by delays in scan signals due to factors such as the number of wires, reliability, or temperature.

[0062] The central portion scan signal (central portion Scan) applied to the central portion of the display panel may be affected by at least one of the factors mentioned above. Furthermore, due to this effect, the central portion scan signal (central portion Scan) may be skewed, with its waveform tilted compared to each side portion scan signal (side portion Scan).

[0063] Because of this potential skew, when data voltage is applied to each side and central portion of the display panel at the same output timing, the central portion of the display panel may be affected by data voltage variations prior to the end of the scan signal. Thus, when the data voltage changes before the end of the scan signal, display defects (so-called color mixing) may occur due to the influence of another data voltage in the corresponding area.

[0064] like Figure 11 As shown, after applying this embodiment, data voltages output at different output timings can be applied to each side portion and the central portion of the display panel. For example, the central portion data voltage (central portion Vdata) applied to the central portion can be output later than the side portion data voltages (side portion Vdata) applied to each side portion of the display panel.

[0065] Scan signals with different waveforms may be applied to each side portion and the central portion of the display panel, as can be seen by referring to the side portion scan signal applied to each side portion of the display panel (side portion Scan) and the central portion scan signal applied to the central portion (central portion Scan). Additionally, as referenced above... Figure 10 The central portion scan signal (central portion Scan) applied to the central portion of the display panel may be affected by the load Δd and may therefore be skewed, wherein the waveform is tilted compared to the side portion scan signal (side portion Scan) applied to each side portion.

[0066] In this embodiment, considering the skew phenomenon described above, the output timing of the data voltage to the central portion of the display panel, rather than each side portion, can be delayed. When the output timing of the data voltage to the central portion of the display panel, rather than each side portion, is delayed, the central portion data voltage can be changed after the central portion scan signal ends. That is, the data voltage for displaying the current image can be safely provided to the central portion of the display panel.

[0067] In this way, when this embodiment is applied, since the data voltage changes after the scanning signal ends, display defects (so-called color mixing) caused by the influence of other data voltages in the corresponding area can be avoided. That is, in this embodiment, the color mixing phenomenon that may occur in specific areas of the display panel, such as the central part, can be mitigated by changing the output timing of the data voltage in each area of ​​the display panel.

[0068] Meanwhile, in the above Figure 8 In this document, it should be noted that the output channels are divided into a total of 18 sections for illustrative purposes, in order to aid in understanding this disclosure. Furthermore, the data voltage output aspect can vary depending on the shape of the display panel. That is, although... Figure 6A The display panel shown is for illustrative purposes only, but when the display panel has... Figure 6B , Figure 6C and Figure 6D When the shape shown is used, the output conditions can be changed with reference to this disclosure. That is, the timing of the data voltage output can be varied according to the shape of the display panel.

[0069] Figure 12 This is an illustrative configuration diagram of a data-driven unit according to an embodiment of the present disclosure. Figure 13 This shows the output as... Figure 8 An illustrative configuration diagram of the control method for the data voltage latch shown.

[0070] like Figure 12As shown, the data driving unit according to an embodiment of this disclosure can change the latch enable signal LAT EN output from the data controller 145 to change the output timing of the data voltage as described above. The latch 144 can sample or hold the data signal in response to the latch enable signal LAT EN output from the data controller 145.

[0071] The first latch enable signal LAT EN1 and the last latch enable signal LAT ENn applied to, for example, the first channel S1 and the 2880th channel S2880 (e.g., the drive channel in the left part of the display panel) and the last channel (e.g., the drive channel in the right part of the display panel), can be the same. That is, the first latch enable signal LAT EN1 and the Nth latch enable signal LAT ENn can be configured such that the same time can be set for sampling or holding the data signal.

[0072] On the other hand, the C-th latch enable signal LATENc to the H-th latch enable signal LATENh applied to channels 1438 to 1443 can be the same or different. That is, the C-th latch enable signal LATENc to the H-th latch enable signal LATENh can be configured such that the time used for sampling or holding the data signal can be set to be the same, or at least one or more of them can be set differently.

[0073] However, the Cth latch enable signal LAT ENc to the Hth latch enable signal LAT ENh can be generated later than the first latch enable signal LAT EN1 and the Nth latch enable signal LAT ENn, or can be applied to the latch 144 with a delay. This is because the 1438th channel S1438 to the 1443rd channel S1443 can correspond to the central channel positioned corresponding to the central portion of the display panel 150. Meanwhile, in Figure 12 In this example, each latch (LAT) latches a 10-bit [9:0] data signal and then provides that data signal to the DA converter 146. However, this is only an example.

[0074] like Figure 13 As shown, the data driving unit according to an embodiment of the present disclosure may include a delay unit DEL to delay the output timing of the data voltage output to the display panel 150.

[0075] In order to output as Figure 8Given the data voltage shown, the data controller 145 can provide an undelayed latch enable signal LAT EN to the latch LAT connected to the output channel for driving the left side of the display panel 150. In response, the latch LAT provided with the undelayed latch enable signal LAT EN can latch the data signal and simultaneously send the undelayed latch enable signal LAT EN to the first delayer DEL1. Furthermore, the first delayer DEL1 can add a first delay value to the undelayed latch enable signal LAT EN and then send that signal to the second delayer DEL2. Furthermore, the second delayer DEL2 can add the first delay value and provide the delayed first latch enable signal LAT EN1 to the latch LAT assigned to it.

[0076] The second delay unit DEL2 to the fourth delay unit DEL4, etc., can gradually increase the signal delay value based on the above process to generate the delayed second latch enable signal LAT EN2 to the delayed fourth latch enable signal LAT EN4, etc., and then provide the signal to the latch LAT assigned to it.

[0077] Based on the above process, the sampling or hold time of the latch (LAT) can be controlled. Furthermore, correspondingly, the timing when the data signal is applied to the DA converter to be converted into a data voltage (or the timing when it travels to the source decoder or DAC) and the output timing when the converted data voltage is output can be as follows: Figure 8 Control is performed as shown. Meanwhile, in Figure 12 As an example, a gamma unit (GMA) for converting the data signal supplied to the DA converter 146 into a data voltage is included in the data drive unit. However, this is only an example.

[0078] As described above, this disclosure has the effect of preventing or mitigating display defects (so-called color mixing) caused by the delay of the scan signal by changing the output timing of the data voltage based on independent control of each of at least one latch. Furthermore, since this disclosure corrects the problem caused by the delay of the scan signal by adjusting the output timing of the data voltage rather than by compensating for the scan signal, it can increase effectiveness during high-speed driving.

[0079] It will be apparent to those skilled in the art that various modifications and variations may be made to this disclosure without departing from the spirit or scope thereof. Therefore, this disclosure is intended to cover any modifications and variations that fall within the scope of the appended claims and their equivalents.

[0080] Cross-reference to related applications

[0081] This application claims the benefit of Korean Patent Application No. 10-2021-0185127, filed on December 22, 2021, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A display apparatus comprising: a display panel configured to display an image; a scan driving circuit configured to provide a scan signal to the display panel; and a data driving circuit configured to provide a data voltage to a data line of the display panel, wherein the data driving circuit includes a data controller configured to change an output timing of the data voltage for each data line, wherein the data driving circuit further includes a plurality of latches, wherein the data controller independently controls a sampling time or a holding time of each data signal by controlling a latch enable signal applied to the plurality of latches to change the output timing of the data voltage, wherein the output timing of the data voltage output to a central portion of the display panel is delayed so that the data voltage output to the central portion is changed after the scan signal applied to the central portion of the display panel ends. the data controller is configured to change the output timing of the data voltage for each data line based on the independent control for each of the plurality of latches.

2. The display device according to claim 1, wherein the plurality of latches included in the data driving circuit store the data signals simultaneously, and in response to the latch enable signal, the output timing is different for each of the plurality of latches.

3. The display device according to claim 1, wherein the plurality of latches included in the data driving circuit include a first latch outputting a data signal first and a last latch outputting a data signal last, and for latches located between the first latch outputting a data signal and the last latch outputting a data signal, the output timing of the output data signal gradually changes.

4. The display device according to claim 3, wherein the data driving circuit is controlled so that the output timing of the data voltage is gradually delayed from a first side portion to a central portion of the display panel, and the output timing of the data voltage is gradually delayed from a second side portion to the central portion of the display panel.

5. The display device according to claim 2, wherein the first side portion is a right side portion, the second side portion is a left side portion, and the output timing of the data voltage is the same for the right side portion and the left side portion of the display panel.

6. The display device of claim 5, wherein, the data driving circuit first outputs the data voltage in a first side portion and a second side portion of the display panel, and then last outputs the data voltage in a central portion of the display panel.

7. The display device according to claim 2, wherein 8.The display apparatus of claim 1, wherein the data controller includes a plurality of delayers configured to delay the latch enable signal; and each of the plurality of delayers adds a delay value to an undelayed latch enable signal to output a delayed latch enable signal, or adds the delay value to the delayed latch enable signal to output a further delayed latch enable signal. the scan driving circuit is disposed in a non-display area located in a side portion of the display panel.

9. The display device according to claim 5, wherein ​ 10. The display device of claim 9, wherein, The scan signal applied to the central portion of the display panel ends later than the scan signals applied to the first side portion and the second side portion of the display panel.

11. A data driving circuit comprising: a plurality of latches configured to store data signals; a plurality of digital-to-analog converters configured to convert the data signals output from the plurality of latches into data voltages; a plurality of output circuits configured to amplify the data voltages output from the digital-to-analog converters and output the data voltages to a display panel through at least one channel; and a data controller configured to control the plurality of latches so that the output timing of the data voltages is changed for each of the at least one channel, wherein the data controller independently controls the sampling time or the hold time of each data signal by controlling a latch enable signal applied to the plurality of latches to change the output timing of the data voltages, and wherein the output timing of the data voltages output to a central portion of the display panel is delayed so that the data voltages output to the central portion are changed after a scan signal applied to the central portion of the display panel ends.

12. The data driving circuit according to claim 11, wherein, The plurality of latches store the data signals simultaneously, and the output timings are different.

13. The data driving circuit according to claim 11, wherein, The plurality of latches include a first data signal outputting latch and a last data signal outputting latch, and the output timing of the data signals gradually changes for latches among the plurality of latches located between the first data signal outputting latch and the last data signal outputting latch.

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