Data interface arrangement and method for a display device

Abstract

A device for controlling a data interface of a display apparatus can include a timing controller that encodes one data transport packet including image data according to a pixel clock to output the one data transport packet to an interface line, and a source driver that decodes the one data transport packet to recover the image data. Also, the image data includes first image data of a first color and second image data of a second color between a first delimiter signal having a first logic value and a second delimiter signal having a second logic value, a most significant bit of the first image data is closer to the first delimiter signal than a least significant bit of the first image data, and a most significant bit of the second image data is closer to the second delimiter signal than a least significant bit of the second image data.

Description

Technical Field

[0001] This disclosure relates to data interface apparatus and methods for display devices. Background Technology

[0002] As display device screen resolutions and sizes increase, the amount of digital image data transmitted for displaying images also increases. Digital image data consists of combinations of "0" and "1".

[0003] In data transmission, when the amount of data transmitted is high, the number of transitions between "0" and "1" increases, which can increase electromagnetic interference (EMI) and power consumption.

[0004] For example, when repeatedly transmitting large amounts of image data that consist of numerous logic transitions with alternating patterns of zeros and ones (e.g., for large and high-resolution screens), these types of repetitive switching of voltage levels can increase power consumption and lead to unwanted electromagnetic interference (EMI) and noise. Summary of the Invention

[0005] In order to overcome or solve the above-mentioned problems associated with related technologies, this disclosure can provide a data interface apparatus and method for a display device that reduces the number of data transformations when transmitting image data, thereby reducing EMI and power consumption.

[0006] To achieve these objectives and other advantages, and in accordance with the purposes of this disclosure, as implemented and broadly described herein, a data interface device for a display device includes a timing controller and a source driver. The timing controller is configured to encode a data transmission packet comprising image data of multiple colors according to a pixel clock to output the data transmission packet to an interface line, and the source driver is configured to receive the data transmission packet via the interface line and decode the data transmission packet according to a pixel clock to recover the image data of multiple colors. The image data of multiple colors includes first image data of a first color and second image data of a second color. The first image data of the first color and the second image data of the second color are arranged between a first delimiter signal having a first logic value and a second delimiter signal having a second logic value, and each has a plurality of bits. The most significant bit of the first image data is arranged closer to the first delimiter signal than the least significant bit of the first image data, and the most significant bit of the second image data is arranged closer to the second delimiter signal than the least significant bit of the second image data. The least significant bits of the first image data and the least significant bits of the second image data are adjacent to each other.

[0007] In another aspect of this disclosure, a data interface method for a display device includes: encoding a data transmission packet comprising image data of multiple colors according to a pixel clock to output the data transmission packet to an interface line; and receiving the data transmission packet via the interface line and decoding the data transmission packet according to the pixel clock to recover the image data of multiple colors. The image data of multiple colors includes first image data of a first color and second image data of a second color. The first image data of the first color and the second image data of the second color are arranged between a clock signal having a first logic value and a dummy signal having a second logic value, and each has multiple bits. The most significant bit of the first image data is arranged closer to the clock signal than the least significant bit of the first image data, and the most significant bit of the second image data is arranged closer to the dummy signal than the least significant bit of the second image data. Furthermore, the least significant bits of the first image data and the least significant bits of the second image data are adjacent to each other. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0009] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure;

[0010] Figure 2 This is a diagram illustrating an example configuration of a four-color data transmission packet for reducing the number of data transitions in transmitted image data according to an embodiment of the present disclosure;

[0011] Figure 3 This is a diagram illustrating an example configuration of a data transmission packet including two-color image data according to an embodiment of the present disclosure;

[0012] Figure 4A This is a graph illustrating the number of data transformations when 2-color image data is transmitted using the original logical values ​​in a comparative example;

[0013] Figure 4B This is a diagram illustrating the number of data transitions when the logic value of each of the high bits of 2-color image data is processed and transmitted based on predetermined conditions in an embodiment of this disclosure.

[0014] Figure 5 This is a diagram illustrating the configuration of each of a timing controller and driver integrated circuit for processing 4-color data transmission packets to reduce the number of data transitions according to an embodiment of the present disclosure;

[0015] Figure 6This is an example of an embodiment according to the present disclosure, including... Figure 5 A diagram illustrating the operation of the data conversion circuit in the timing controller;

[0016] Figure 7A and Figure 7B This is a diagram illustrating the inputs and outputs of each data conversion circuit according to embodiments of the present disclosure;

[0017] Figure 8A and Figure 8B These are diagrams illustrating actual examples of the inputs and outputs of each data conversion circuit according to embodiments of the present disclosure;

[0018] Figure 9 This is an example of an embodiment according to the present disclosure, including... Figure 5 A diagram illustrating the data recovery operation in a driver integrated circuit;

[0019] Figure 10A and Figure 10B This is a diagram illustrating the inputs and outputs of each data recovery according to embodiments of this disclosure; and

[0020] Figure 11A and Figure 11B The diagram illustrates a real example of the inputs and outputs of each data recovery according to an embodiment of this disclosure. Detailed Implementation

[0021] In the following description, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are illustrated. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concept of the disclosure to those skilled in the art.

[0022] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0023] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the figures used to describe various embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Similar reference numerals refer to similar elements throughout. The same elements are identified by the same reference numerals throughout the specification. As used herein, the terms "comprising," "having," "including," etc., imply that additional components may be added, unless the term "only" is used. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0024] Even without explicit statement, elements in the various embodiments of this disclosure should be interpreted as including error margins.

[0025] When describing positional relationships, for example, when the positional relationship between two components is described as "on," "above," "below," and "next to," one or more other components may be positioned between the two components unless "only" or "directly" is used.

[0026] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0027] In the following description, detailed descriptions of relevant known functions or configurations will be omitted where they are determined to unnecessarily obscure the focus of this disclosure. Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0028] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0029] The display devices according to embodiments of this disclosure can be applied to flat panel display devices such as liquid crystal display (LCD) devices, field emission display (FED) devices, plasma display panels (PDP), organic light-emitting diode (OLED) display devices, and inorganic light-emitting diode (OLED) display devices, but are not limited thereto. The display devices according to embodiments of this disclosure can be applied to bendable display devices, foldable display devices, rollable display devices, flexible display devices, etc. The inventive concept can be applied to various display devices including a timing controller TCON and a source driver SIC connected to each other via internal interface devices. In the following description, an organic light-emitting diode (OLED) display device will be used as an example, but the inventive concept is not limited to OLED display devices.

[0030] Reference Figure 1The display device according to embodiments of the present disclosure may include a display panel PNL, a timing controller TCON, a source driver SIC, and a gating driver GDRV.

[0031] The display panel PNL may include a pixel array for displaying an input image. The pixel array may include multiple pixels arranged in a matrix type based on a cross structure of multiple data lines DL and multiple gate lines GL. Each of the multiple pixels may include a red (R) subpixel with red image data applied, a green (G) subpixel with green image data applied, a blue (B) subpixel with blue image data applied, and a white (W) subpixel with white image data applied, to achieve color.

[0032] Each sub-pixel may include a light-emitting device, a driving element, a switching element, and a storage element. Internal and external compensation techniques can be applied to compensate for driving characteristic deviations (e.g., voltage threshold variations, mobility, OLED degradation, etc.) associated with the light-emitting device and / or driving element between sub-pixels. Internal compensation techniques compensate for the driving current flowing in the light-emitting device by using compensation circuitry included in each sub-pixel, regardless of characteristic variations in the driving element. In external compensation techniques, sensing circuitry located outside the display panel PNL senses driving characteristic variations of the light-emitting device and / or driving element in each sub-pixel, and the compensation circuitry corrects the image data to be applied to each sub-pixel to compensate for the sensed driving characteristic variations.

[0033] The pixel array may also include multiple touch sensors for implementing a touch user interface (UI). The touch sensors may each be implemented as capacitive touch sensors that sense touch input based on changes in capacitance before and after a touch is applied to the touch sensor, but are not limited to this.

[0034] The timing controller (TCON) can receive digital image data and timing signals from the host system. These timing signals include vertical synchronization signals, horizontal synchronization signals, and data enable signals. Based on these timing signals, the TCON can generate timing control signals for controlling the operation timing of the source driver (SIC) and the gating driver (GDRV). These timing control signals can include source timing control signals for controlling the operation timing of the source driver (SIC) and gating timing control signals for controlling the operation timing of the gating driver (GDRV).

[0035] The timing controller TCON can connect to the source driver SIC via a clock embedded interface device based on a point-to-point scheme and an encoding scheme, and can transmit data transmission packets including clock signals and image data RGBW to the source driver SIC.

[0036] Data transmission packets can be transmitted to the source driver SIC via a transmission line. The pixel clock included in the data transmission packet may only contain transition information to be recovered by the receiving circuitry; therefore, the clock embedding type can be more flexible than the clock splitting type in terms of transmission constraints. The clock embedding interface device may include transmission circuitry ( Figure 5 EPI-Tx), transmission lines and receiving circuits ( Figure 5 The EPI-Rx transmission circuit (EPI-Tx) can be embedded in the timing controller TCON, and the EPI-Rx reception circuit (EPI-Rx) can be embedded in the source driver SIC.

[0037] Clock-embedded interface devices can use data encoding schemes.

[0038] In a clock-embedded interface device based on a data encoding scheme, the transmission circuit (EPI-Tx) can encode scrambled image data RGBW based on a pixel clock, and can transmit the encoded data transmission packets to the receiving circuit (EPI-Rx) via multiple transmission lines. Before transmitting the data transmission packets, the clock-embedded interface device can transmit clock training pattern signals and control data packets to the receiving circuit (EPI-Rx) via multiple transmission lines. Clock training pattern signals may be required for clock training operations of the receiving circuit (EPI-Rx). The aforementioned gating timing control signals and source timing control signals can be encoded and may also be included in the control data packets. The encoded gating timing control signals and encoded source timing control signals can be decoded by the receiving circuit (EPI-Rx).

[0039] The receiving circuit (EPI-Rx) may include a CDR circuit. The CDR circuit receives a clock training pattern signal via a transmission line and can track the clock training pattern signal to recover the pixel clock embedded in the data transmission packets. The receiving circuit (EPI-Rx) can decode the data transmission packets based on the pixel clock recovered by the CDR circuit and can descramble the decoded data to recover the image data RGBW.

[0040] The source driver SIC may include a receiver circuit (EPI-Rx) and a digital-to-analog converter (DAC). The receiver circuit (EPI-Rx) provides the DAC with image data RGBW, recovered to be synchronized with the pixel clock, and a source timing control signal. The DAC converts the digital image data RGBW into an analog gamma-compensated voltage (e.g., a data voltage) based on the source timing control signal and outputs the data voltage to the data line DL. The data voltage output to the data line DL can be applied to the sub-pixels in synchronization with the scan signal provided to the gating line GL. Furthermore, the source driver SIC can provide the gating timing control signal recovered by the receiver circuit (EPI-Rx) to the gating driver GDRV via a separate signal line.

[0041] The gating driver GDRV can generate a scan signal that oscillates between a gating on voltage and a gating off voltage based on a gating timing control signal. The gating on voltage can be the voltage used to turn on the switching element of each sub-pixel, and the gating off voltage can be the voltage used to turn off the switching element of each sub-pixel. The gating driver GDRV can sequentially or non-sequentially output the scan signal to the gating line GL to select the sub-pixels to be charged with the data voltage via the line unit.

[0042] In the case of implementing a clock embedded interface device based on EPI, the timing controller TCON can convert each of the data transmission packets, including digital image data RGBW, clock training pattern signals, and Rx control data, into differential signal pairs based on a predetermined signal transmission standard in the EPI protocol. These differential signal pairs can then be serially transmitted to the source drivers SIC#1 through SIC#4 via data line pairs (e.g., transmission lines). When data transmission packets are transmitted in the form of differential signal pairs, electromagnetic interference (EMI) can be easily reduced.

[0043] To reduce the number of transmission lines, image data of multiple colors (e.g., R and W or G and B) can be included in a single data transmission packet. In this case, to reduce EMI and the number of data transitions, under certain conditions, the bit arrays of the first color image data and the bit arrays of the second color image data can be configured opposite each other in the single data transmission packet. Furthermore, to further reduce EMI and the number of data transitions, the high bits of the image data can be replaced with a first logic value "1" or a second logic value "0" under certain conditions. In this case, the image data in which the high bits are replaced with specific logic values ​​can be indicated by further indication data included in the single data transmission packet. The indication data can be divided for each of the multiple colors in the single data transmission packet.

[0044] When the lock signal LOCK input via the lock feedback signal line is at a low logic level, the timing controller TCON can transmit the clock training pattern signal to the source drivers SIC#1 through SIC#4. And when the lock signal LOCK is inverted to a high logic level, the timing controller TCON can begin transmitting Rx control data and data transmission packets. The lock signal LOCK of the feedback-given timing controller TCON can be switched to a low logic level only when the clock recovery circuit output of each of the source drivers SIC#1 through SIC#4 is not locked, thus ensuring the stability of interface operation.

[0045] Source drivers SIC#1 to SIC#4 can operate to meet the EPI protocol. Specifically, source drivers SIC#1 to SIC#4 can decode the indication data of data transmission packets provided by the timing controller TCON, and thus can restore the original input logic value to the replaced logic value corresponding to each high bit of the color-based image data RGBW.

[0046] Figure 2 This is a diagram illustrating an example configuration of four-color data transmission packets used to reduce the number of data transformations in transmitted image data.

[0047] Reference Figure 2 A data transmission packet TU can consist of multi-color image data arranged between a first delimiter signal DM1 having a first logic value "1" and a second delimiter signal DM2 having a second logic value "0".

[0048] The first delimiter signal DM1, which has a first logic value of "1", and the second delimiter signal DM2, which has a second logic value of "0", can be the distinguishing signals of the definition 1 data transmission packet TU.

[0049] Image data of multiple colors can be composed of image data of a first color and image data of a second color. The first color image data and the second color image data can be selected differently from R image data D1, W image data D2, G image data D3, and B image data D4. For example, R image data D1 and W image data D2 can be included in one data transmission packet TU, and G image data D3 and B image data D4 can be included in another data transmission packet TU. Each of R image data D1, W image data D2, G image data D3, and B image data D4 can consist of multiple bits (e.g., 10 bits).

[0050] The bit arrays D(0) to D(9) of the first color image data (hereinafter referred to as the first image data) and the bit arrays D(0) to D(9) of the second color image data (hereinafter referred to as the second image data) can be configured to be opposite each other in a data transmission packet TU (for example, the bit arrays of the first color and the second color can be arranged such that their least significant bit D0 is located at the center of the transmission packet TU).

[0051] For example, the most significant bit (MSB) D1(9) of the first image data D1 can be arranged closer to the first delimiter signal DM1 than the least significant bit (LSB) D1(0) of the first image data D1, and the MSB D2(9) of the second image data D2 can be arranged closer to the second delimiter signal DM2 than the LSB D2(0) of the second image data D2, and the LSB D1(0) of the first image data D1 can be adjacent to the LSB D2(0) of the second image data D2 (e.g., the least significant bits from both the first and second image data are arranged around the center of the transmission packet TU, see [reference]). Figure 2 With this configuration, the number of data transformations can be reduced, and EMI and power consumption can be lowered.

[0052] In a plurality of pixels operating on the same scan signal, the probability that the high bits of image data of the same color to be provided to adjacent pixels have the same logic value can be high. For example, when a first pixel is adjacent to a second pixel, the logic values ​​of their corresponding high bits can be the same in the R image data to be provided to the R sub-pixels of the first pixel and the R image data to be provided to the R sub-pixels of the second pixel. In the following description, "high bit" may refer to a number of high bits including the MSB in the total number of bits, and "low bit" may refer to a number of low bits including the LSB in the total number of bits. The number of bits included in the "high bits" and the number of bits included in the "low bits" may vary based on the total number of bits and design specifications.

[0053] Because the data interface device according to this embodiment is based on a serial transmission scheme, image data of the same color to be provided to adjacent pixels can be included in different data transmission packets (TUs) and transmitted sequentially. Therefore, when the logic values ​​of the high bits are the same in the image data of the same color (hereinafter referred to as specific conditions), the image data of the same color transmitted with lower priority can be processed, such that the logic values ​​of the high bits have a first logic value "1" or a second logic value "0" that are different from the original logic values. The logic values ​​of the high bits can be transmitted together with indication information about whether processing is performed, thereby further reducing the number of data transitions.

[0054] In this embodiment, the first indication data IND1 and the second indication data IND2 arranged in the data transmission packet TU between the first delimiter signal DM1 and the first image data D1 can be indication information about whether the processing is performed or not.

[0055] The high bits of the first image data D1 can be relatively close to the first delimiter signal DM1 having a first logic value "1", and therefore can be processed under certain conditions to have a first logic value "1" associated with the setting of the first indication data IND1 having a first logic value "1", thereby increasing or maximizing the effect of reducing the number of data transitions.

[0056] Furthermore, the high bits of the second image data D2 can be relatively close to the second delimiter signal DM2, which has a second logic value of "0", and therefore can be processed under certain conditions to have a second logic value of "0" associated with the setting of the first logic value of "1" of the second indication data IND2, thereby increasing or maximizing the effect of reducing the number of data transitions.

[0057] In this case, the first indicator data IND1 can be arranged adjacent to the MSB D1(9) of the first image data D1, and the second indicator data IND2 can be arranged adjacent to the first delimiter signal DM1, thereby increasing or maximizing the effect of reducing the number of data transitions.

[0058] The source driver can decode the data transmission packet TU based on the pixel clock, and the logic value obtained by processing each high bit of the first image data D1 can be restored to the original logic value by referring to the first image data D1 corresponding to the previous clock (e.g., image data of the same color transmitted with higher priority).

[0059] Furthermore, when the high-bit logic values ​​in the same color image data to be provided to adjacent pixels are different, since the logic values ​​cannot be restored to the original logic values ​​by using the source driver, the "logic value processing" performed by the timing controller can be omitted, and the image data can be transmitted to the source driver intact.

[0060] Figure 3 This is a diagram illustrating a configuration example of a single data transmission packet containing two-color image data (e.g., image data of two sub-pixels (here, a red sub-pixel and a white sub-pixel)).

[0061] Reference Figure 3 , Figure 2 The first image data D1 and the second image data D2 shown can each be 10-bit R image data R(0) to R(9) and 10-bit W image data W(0) to W(9), respectively. Furthermore, Figure 2 The first indication data IND1 shown can be "IND(R)", and Figure 2 The second indicator data IND2 shown can be "IND(W)".

[0062] The MSB R(9) of the R image data can be arranged closer to the first delimiter signal DM1 than the LSB R(0) of the R image data, and the MSB W(9) of the W image data can be arranged closer to the second delimiter signal DM2 than the LSB W(0) of the W image data, and the LSB R(0) of the R image data and the LSB W(0) of the W image data can be adjacent to each other (e.g., the LSB of each sub-pixel can be arranged around the center of the I data transmission packet).

[0063] The first indicator data IND(R) can be arranged adjacent to the MSB R(9) of the R image data, and the second indicator data IND(W) can be arranged adjacent to the first delimiter signal DM1.

[0064] When the image data R(0) to R(9) meet certain conditions, the high bits R(5) to R(9) of the image data R(0) to R(9) and the first indicator data IND(R) can be encoded as all having the first logic value "1".

[0065] When the W image data W(0) to W(9) meet certain conditions, the high bits W(5) to W(9) of the W image data W(0) to W(9) and the first indicator data IND(W) can be encoded as all having the second logic value "0".

[0066] Figure 4A This is a graph illustrating the number of data transformations when 2-color image data is transmitted in its original logical value, as exemplified in the comparative examples of this disclosure. Figure 4B This is a diagram illustrating the number of data transformations when the logic value of each of the high bits of a 2-color image data is processed and transmitted based on predetermined conditions in an embodiment of this disclosure.

[0067] Reference Figure 4A A comparison example could be an instance where R image data and W image data, each with a bit value of "0101010101", are included in a first data transmission packet. According to the comparison example, the number of transitions in the data of the I data transmission packet could be 19.

[0068] Reference Figure 4B The implementation could be an example in which R image data and W image data, each having a bit value of "0101010101", are included in a first data transmission packet, and could be an implementation in which, under certain conditions, the logic value of the high bits of the R image data is replaced with "1" and the logic value of the high bits of the W image data is replaced with "0". According to the implementation, with... Figure 4ACompared to the comparison example, the number of transitions in a 1-data-transmitting packet can be 11 and can be reduced by about 42%. For example, if there is a specific condition where the original logical value of the image data of a subpixel is an alternating pattern of zeros and ones as “0101010101”, the specific pattern with high transitions can be identified and replaced with 1s to avoid transitions, and then decoded later.

[0069] Figure 5 This is a diagram illustrating the configuration of each of the timing controller and driver integrated circuits used to process 4-color data transmission packets to reduce the number of data transitions. Figure 6 Examples include Figure 5 A diagram illustrating the operation of the data conversion circuit in the timing controller. Figure 7A and Figure 7B This is a diagram illustrating the inputs and outputs of each data conversion circuit.

[0070] Figure 8A and Figure 8B This is a diagram illustrating a real example of the inputs and outputs of each data conversion circuit. Figure 9 Examples include Figure 5 A diagram illustrating the data recovery operation in a driver integrated circuit. Figure 10A and Figure 10B This is a diagram illustrating the inputs and outputs for each data recovery. Figure 11A and Figure 11B This is a diagram illustrating a real-world example of the inputs and outputs for each data recovery.

[0071] Reference Figure 5 The timing controller TCON can encode the data transmission packets of two-color image data (RGBW) containing multiple colors based on the pixel clock, and can output the encoded data transmission packets to the interface line. The timing controller TCON may include a first receiving circuit V-RX, a first memory MEM1, a data conversion circuit DTR, and a first transmission circuit EPI-TX.

[0072] The first receiving circuit V-RX can be connected to the host system through a first interface (e.g., Vx1) and can receive 4-color image data RGBW from the host system based on the pixel clock.

[0073] The first memory MEM1 can store the high bits of each of the four-color image data RGBW received by the first receiving circuit V-RX and synchronized with the pixel clock.

[0074] As in Figure 6In this circuit, the Data Transmission Transmission Circuit (DTR) can perform data processing operations on a unit basis, consisting of two-color image data that constitute a data transmission packet. The two-color image data can include first image data of a first color and second image data of a second color, each having a relative bit array within the same data transmission packet.

[0075] The data conversion circuit DTR can compare the high bits of the 2-color image data input from the first receiving circuit V-RX according to the nth pixel clock with the high bits of the 2-color image data stored in the first memory MEM1 according to the (n-1)th pixel clock using units of the same color and units of bits with a one-to-one relationship.

[0076] The Data Transformation Circuit (DTR) can process the first and second image data differently under specific conditions to reduce the number of data transformations.

[0077] When the logic value of the high-order bits remains unchanged as a result of a comparison based on the first image data (e.g., the high-order bits of the image data of two adjacent sub-pixels are the same), the Data Transmission Circuit (DTR) can set the first indication data of the 1-data transmission packet to "1" and can replace the high-order bits of the first image data from their original logic values ​​to "1". Furthermore, when the logic value of the high-order bits changes as a result of a comparison based on the first image data (e.g., the high-order bits of the image data of two adjacent sub-pixels are different), the DTR can set the first indication data of the 1-data transmission packet to "0" and can retain the high-order bits of the first image data at their original logic values ​​(e.g., no conversion / encoding is performed in this case).

[0078] For example, the data conversion circuit DTR can be based on pixel clock processing. Figure 7A The first image data R(0) to R(9) are used to generate Figure 7B The first image data R'(0) to R'(9). Specifically, the data conversion circuit DTR can provide the data to be provided as shown in... Figure 8A The high bits of the first image data of each of the four pixels in the image are compared to the first image data to be provided to the adjacent pixels, so that each can generate a first image data of the same type as the first image data of the adjacent pixels. Figure 8B The first indication data and the first image data are shown as logical values. Here, adjacent pixels can correspond to the previous pixel clock and the current pixel clock that are adjacent to each other, respectively.

[0079] When the logic value of the high-order bit remains unchanged as a result of a comparison based on the second image data, the Data Transmission Circuit (DTR) can set the second indicator data of the 1 data transmission packet to "1" and can replace the high-order bit of the second image data with "0" from its original logic value. Furthermore, when the logic value of the high-order bit changes as a result of a comparison based on the second image data, the DTR can set the second indicator data of the 1 data transmission packet to "0" and can retain the high-order bit of the second image data at its original logic value.

[0080] The first transmission circuit, EPI-TX, can serially transmit 4-color image data (RGBW) encoded by the data conversion circuit (DTR) to the interface line in data transmission packets.

[0081] The source driver SiC can receive data transmission packets via an interface line and decode the data transmission packets according to the pixel clock to recover multi-color image data (RGBW). The source driver SiC may include a second receiving circuit (EPI-RX), a second memory (MEM2), a data recovery circuit (DRV), a digital-to-analog converter (DAC), and an output buffer (BUF).

[0082] The second receiving circuit, EPI-RX, can receive data transmission packets via the interface line.

[0083] Data recovery circuit DRV, such as Figure 9 The system can perform data recovery operations on a unit basis, consisting of two-color image data constituting a single data transmission packet. When the indicator data for each data transmission packet is "0", the data recovery circuit DRV can completely recover the two-color image data constituting the data transmission packet and store the recovery result in the second memory MEM2 (e.g., no decoding / recovery is performed when the indicator data is "0"). When the indicator data for each data transmission packet is "1", the data recovery circuit DRV can replace and recover the high-order logic values ​​of the two-color image data constituting the data transmission packet with the high-order logic values ​​of the image data stored in the second memory MEM2 (e.g., decoding / recovery is performed when the indicator data is "1").

[0084] In other words, when the first indication data of a 1 data transmission packet is "1", the data recovery circuit DRV can replace and restore the high-order logic value of the first image data corresponding to the current pixel clock to the high-order logic value of the first image data corresponding to the previous pixel clock (e.g., using the same data previously stored in MEM2, since it is the same). On the other hand, when the first indication data of a 1 data transmission packet is "0", the data recovery circuit DRV can perfectly restore the high-order logic value of the first image data corresponding to the current pixel clock (e.g., not using the data previously stored in MEM2, since the incoming image data is different from the data previously stored in MEM2).

[0085] For example, the data conversion circuit DTR can be decoded based on the pixel clock. Figure 10A The first image data R'(0) to R'(9) are used to recover the first image data R'(0) to R'(9) into Figure 10B The first image data R(0) to R(9). In detail, the data recovery circuit DRV can be relative to, for example... Figure 11A The image data, where the indicator data in each of the four pixels is "1", is shown. The high-order logic values ​​are then replaced with the high-order logic values ​​of the image data stored in the second memory. Therefore, the image data can be restored to have the following characteristics: Figure 11B The first image data showing the original logical values. Relative to, for example... Figure 11A The image data to be provided to each of the four pixels in the first image data where the indicator data is "0" is shown. The data recovery circuit DRV can perfectly preserve the logic value of the high bits, so it can be used as shown in... Figure 11B In this way, the image data is restored to the first image data.

[0086] The data recovery circuit (DRV) can provide the recovered 4-color image data (RGBW) to the digital-to-analog converter (DAC).

[0087] A digital-to-analog converter (DAC) can convert 4-color image data (RGBW) into data voltage. The 4-color image data (RGBW) can be output to the data line through the output buffer (BUF).

[0088] According to this disclosure, the bit arrays of the first color image data and the second color image data can be configured to be opposite each other in a data transmission packet, thereby reducing the number of data transitions (e.g., the least significant bits of the image data of two adjacent sub-pixels can be arranged at the center of the data transmission packet).

[0089] According to this disclosure, when the high-bit logic values ​​of image data of the same color to be provided to adjacent pixels are the same, the image data of the same color transmitted at a lower priority can be processed such that the high-bit logic values ​​have a first logic value "1" and a second logic value "0" that are different from the original logic values, and can be transmitted together with indication information about whether processing is performed (e.g., whether data decoding / recovery should be performed), thereby further reducing the number of data transformations.

[0090] As described above, in this embodiment, the number of data transitions when transmitting image data can be reduced, thereby reducing EMI and power consumption.

[0091] The effects of this disclosure are not limited to the examples above, and various other effects may be included in this specification.

[0092] While this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0093] Cross-references to related applications

[0094] This application claims priority to Korean Patent Application No. 10-2021-0186095, filed in Korea on December 23, 2021, the entire contents of which are incorporated herein by reference as if fully set forth herein.

Claims

1. An apparatus for controlling a data interface of a display device, the apparatus comprising: A timing controller configured to encode a data transmission packet containing image data of multiple colors according to a pixel clock to output the data transmission packet to an interface line; as well as A source driver, configured to receive the data transmission packet via the interface line and decode the data transmission packet according to the pixel clock to recover the multi-color image data. The image data of multiple colors includes first image data of a first color and second image data of a second color. The first image data of the first color and the second image data of the second color are arranged between a first delimiter signal having a first logic value and a second delimiter signal having a second logic value different from the first logic value. Wherein, the most significant bit of the first image data is arranged to be closer to the first delimiter signal than the least significant bit of the first image data, and In this configuration, the most significant bit of the second image data is arranged to be closer to the second delimiter signal than the least significant bit of the second image data. The timing controller is further configured as follows: A first indicator data and a second indicator data are arranged between the first delimiter signal and the first image data within the data transmission packet. Wherein, when the first indication data has the first logical value, all the high bits of the first image data have the first logical value, and Specifically, when the second indication data has the first logic value, all the high bits of the second image data have the second logic value.

2. The apparatus of claim 1, wherein, The least significant bits of the first image data and the least significant bits of the second image data are arranged adjacent to each other within the data transmission packet.

3. The apparatus of claim 1, wherein, The least significant bits of the first image data and the least significant bits of the second image data are arranged in the center of the data transmission packet.

4. The apparatus of claim 1, wherein, When the first indication data has the second logic value, the high bits of the first image data have the original logic value, and Wherein, when the second indication data has the second logic value, the high bits of the second image data have the original logic value.

5. The apparatus according to claim 1, wherein, The first indication data is arranged to be adjacent to the most significant bit of the first image data, and The second indication data is arranged adjacent to the first delimiter signal.

6. The apparatus of claim 1, wherein, The timing controller is configured as follows: When the logic value of the high bit of the first image data corresponding to the previous pixel clock is the same as the logic value of the high bit of the first image data corresponding to the current pixel clock, the first indication data is set to the first logic value, and the high bit of the first image data corresponding to the current pixel clock is replaced from its original logic value to the first logic value. When the logic value of the high bit of the first image data corresponding to the previous pixel clock is different from the logic value of the high bit of the first image data corresponding to the current pixel clock, the first indication data is set to the second logic value and the high bit of the first image data corresponding to the current pixel clock is kept at the original logic value.

7. The apparatus of claim 6, wherein, The source driver is configured as follows: When the first indication data has the first logic value, the high-bit logic value of the first image data corresponding to the current pixel clock is replaced with the high-bit logic value of the first image data corresponding to the previous pixel clock, and When the first indication data has the second logic value, the logic value of the high bit of the first image data corresponding to the current pixel clock is maintained.

8. The apparatus of claim 1, wherein, The timing controller is configured as follows: When the logic value of the high bit of the second image data corresponding to the previous pixel clock is the same as the logic value of the high bit of the second image data corresponding to the current pixel clock, the second indication data is set to the first logic value, and the high bit of the second image data corresponding to the current pixel clock is replaced from its original logic value to the second logic value. When the logic value of the high bit of the second image data corresponding to the previous pixel clock is different from the logic value of the high bit of the second image data corresponding to the current pixel clock, the second indication data is set to the second logic value and the high bit of the second image data corresponding to the current pixel clock is kept at the original logic value.

9. The apparatus of claim 8, wherein, The source driver is configured as follows: When the second indication data has the first logic value, the high-bit logic value of the second image data corresponding to the current pixel clock is replaced with the high-bit logic value of the second image data corresponding to the previous pixel clock, and When the second indication data has the second logic value, the logic value of the high bit of the second image data corresponding to the current pixel clock is maintained.

10. A method for controlling a display device, the method comprising the following steps: A data transmission packet containing image data of multiple colors is encoded according to a pixel clock to output the data transmission packet to the interface line. as well as The interface line receives the data transmission packet and decodes the data transmission packet according to the pixel clock to recover the multi-color image data. The image data of multiple colors includes first image data of a first color and second image data of a second color. The first image data of the first color and the second image data of the second color are arranged between a clock signal having a first logic value and a dummy signal having a second logic value different from the first logic value. Wherein, the most significant bit of the first image data is arranged to be closer to the clock signal than the least significant bit of the first image data, and In this configuration, the most significant bit of the second image data is arranged to be closer to the dummy signal than the least significant bit of the second image data. The encoding step further includes the following steps: A first indication data and a second indication data are arranged between the clock signal and the first image data within the data transmission packet. Wherein, when the first indication data has the first logical value, all the high bits of the first image data have the first logical value, and Specifically, when the second indication data has the first logic value, all the high bits of the second image data have the second logic value.

11. The method of claim 10, wherein, The least significant bits of the first image data and the least significant bits of the second image data are arranged adjacent to each other within the data transmission packet.

12. The method of claim 10, wherein, When the first indication data has the second logic value, the high bits of the first image data have the original logic value, and When the second indication data has the second logic value, the high bits of the second image data have the original logic value.

13. The method of claim 10, wherein, The first indication data is arranged to be adjacent to the most significant bit of the first image data, and The second indication data is arranged adjacent to the clock signal.

14. The method of claim 10, wherein, The encoding step includes the following steps: When the logic value of the high-order bit of the first image data corresponding to the previous pixel clock is the same as the logic value of the high-order bit of the first image data corresponding to the current pixel clock, the first indication data is set to the first logic value, and the high-order bit of the first image data corresponding to the current pixel clock is replaced from its original logic value with the first logic value; and When the logic value of the high bit of the first image data corresponding to the previous pixel clock is different from the logic value of the high bit of the first image data corresponding to the current pixel clock, the first indication data is set to the second logic value and the high bit of the first image data corresponding to the current pixel clock is kept at the original logic value.

15. The method of claim 14, wherein, The decoding step includes the following steps: When the first indication data has the first logic value, the high-bit logic value of the first image data corresponding to the current pixel clock is replaced with the high-bit logic value of the first image data corresponding to the previous pixel clock; and When the first indication data has the second logic value, the logic value of the high bit of the first image data corresponding to the current pixel clock is maintained.

16. The method of claim 10, wherein, The encoding step includes the following steps: When the logic value of the high bit of the second image data corresponding to the previous pixel clock is the same as the logic value of the high bit of the second image data corresponding to the current pixel clock, the second indication data is set to the first logic value, and the high bit of the second image data corresponding to the current pixel clock is replaced from its original logic value to the second logic value; and When the logic value of the high bit of the second image data corresponding to the previous pixel clock is different from the logic value of the high bit of the second image data corresponding to the current pixel clock, the second indication data is set to the second logic value and the high bit of the second image data corresponding to the current pixel clock is kept at the original logic value.

17. The method of claim 16, wherein, The decoding step includes the following steps: When the second indication data has the first logic value, the high-bit logic value of the second image data corresponding to the current pixel clock is replaced with the high-bit logic value of the second image data corresponding to the previous pixel clock; and When the second indication data has the second logic value, the logic value of the high bit of the second image data corresponding to the current pixel clock is maintained.

18. An apparatus for controlling a data interface of a display device, the apparatus comprising: A timing controller configured to encode a data transmission packet containing image data of multiple colors according to a pixel clock for outputting the data transmission packet to an interface line. The image data of multiple colors includes first image data of a first color and second image data of a second color. The first image data of the first color and the second image data of the second color are arranged between a first delimiter signal having a first logic value and a second delimiter signal having a second logic value different from the first logic value. In this configuration, the least significant bits of the first image data and the least significant bits of the second image data are arranged adjacent to each other within the data transmission packet. The timing controller is further configured as follows: A first indicator data and a second indicator data are arranged between the first delimiter signal and the first image data within the data transmission packet. Wherein, when the first indication data has the first logical value, all the high bits of the first image data have the first logical value, and Specifically, when the second indication data has the first logic value, all the high bits of the second image data have the second logic value.

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