Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel comprises: a pixel circuit and a light emitting element; an initialization signal line, an initialization signal comprising an enable level and a disable level, the enable level of the initialization signal being used for initializing a target node of the pixel circuit; the initialization signal line extends along a first direction, the initialization signal line comprising a first initialization signal line and a second initialization signal line, the pixel circuit comprising a first pixel circuit connected with the first initialization signal line and a second pixel circuit connected with the second initialization signal line, the first pixel circuit and the second pixel circuit being arranged along a second direction; one frame refresh period of the display panel comprises a first stage, in the first stage, the first initialization signal line transmits the enable level and the second initialization signal line transmits the disable level. Embodiments of the present application can shorten the time length of the frame refresh period of the display panel, which helps to improve the refresh rate of the display panel.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a display panel and a display device. Background Technology

[0002] With the development of display technology, the display effect of display panels has been continuously improved, resulting in the increasingly widespread application of display panels. Display panels are gradually evolving towards higher resolution and higher refresh rates.

[0003] However, the current display panel refresh cycle (i.e., one frame time) is relatively long, making it difficult to improve the refresh rate of the display panel. Summary of the Invention

[0004] This application provides a display panel and a display device that can solve the problems of long screen refresh cycle and difficulty in improving the refresh rate of the display panel.

[0005] In a first aspect, this application provides a display panel, comprising: a pixel circuit and a light-emitting element, the pixel circuit being used to drive the light-emitting element to emit light; an initialization signal line for transmitting an initialization signal, the initialization signal including an enable level and a disable level, the enable level of the initialization signal being used to initialize a target node of the pixel circuit; the initialization signal line extending along a first direction, the initialization signal line including a first initialization signal line and a second initialization signal line, the pixel circuit including a first pixel circuit and a second pixel circuit, the first initialization signal line being electrically connected to the first pixel circuit, and the second initialization signal line being electrically connected to the second pixel circuit; the first pixel circuit and the second pixel circuit being arranged along a second direction, the first direction intersecting the second direction; a screen refresh cycle of the display panel including a first stage, in which the first initialization signal line transmits an enable level, and the second initialization signal line transmits a disable level.

[0006] Secondly, this application provides a display device, which includes a display panel as provided in the first aspect.

[0007] The display panel and display device of this application have a first initialization signal line electrically connected to a first pixel circuit and a second initialization signal line electrically connected to a second pixel circuit. In the first stage of the display panel's screen refresh cycle, the first initialization signal line provides an enable level to the first pixel circuit to initialize the target node of the first pixel circuit, and the second initialization signal line provides a disable level to the second pixel circuit. In this way, the initialization processes of different pixel circuits no longer need to be unified and can be performed time-sharingly. Therefore, for a pixel circuit, initialization can be performed without waiting for other pixel circuits to complete their light-emitting stage. In other words, the initialization process of a pixel circuit can overlap with the data writing stage and / or light-emitting stage of other pixel circuits, thereby shortening the screen refresh cycle of the display panel and helping to improve the refresh rate of the display panel. Attached Figure Description

[0008] To more clearly illustrate the technical solution of this application, the drawings used in this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0009] Figure 1 This is a circuit diagram of a display panel;

[0010] Figure 2 This is a schematic diagram of a pixel circuit.

[0011] Figure 3 for Figure 1 The display panel shown corresponds to a certain type of driving timing diagram;

[0012] Figure 4 A circuit diagram of a display panel provided in this application;

[0013] Figure 5 for Figure 4 The diagram shown is a driving timing diagram corresponding to a display panel.

[0014] Figure 6 A circuit diagram of a pixel circuit in a display panel provided in this application;

[0015] Figure 7 for Figure 6 The diagram shows a driving timing sequence corresponding to a pixel circuit.

[0016] Figure 8 for Figure 4 The diagram shown is another driving timing diagram corresponding to the display panel.

[0017] Figure 9 for Figure 6 The diagram shows a driving timing sequence corresponding to a pixel circuit.

[0018] Figure 10 Another circuit diagram of the display panel provided in this application;

[0019] Figure 11 for Figure 10 The diagram shown is a driving timing diagram corresponding to a display panel.

[0020] Figure 12 Another circuit diagram of the pixel circuit in the display panel provided in this application;

[0021] Figure 13 Another circuit diagram of the pixel circuit in the display panel provided in this application;

[0022] Figure 14 Another circuit diagram of the pixel circuit in the display panel provided in this application;

[0023] Figure 15 Another circuit diagram of the display panel provided in this application;

[0024] Figure 16 Another circuit diagram of the display panel provided in this application;

[0025] Figure 17 Another circuit diagram of the display panel provided in this application;

[0026] Figure 18 Another circuit diagram of the display panel provided in this application;

[0027] Figure 19 Another circuit diagram of the display panel provided in this application;

[0028] Figure 20 Another circuit diagram of the display panel provided in this application;

[0029] Figure 21 A circuit diagram of the first shift register in the display panel provided in this application;

[0030] Figure 22 Another circuit diagram of the first shift register in the display panel provided in this application;

[0031] Figure 23 Another circuit diagram of the first shift register in the display panel provided in this application;

[0032] Figure 24 Another circuit diagram of the first shift register in the display panel provided in this application;

[0033] Figure 25Another circuit diagram of the first shift register in the display panel provided in this application;

[0034] Figure 26 A circuit diagram of a first initialization signal output circuit in a display panel provided in this application;

[0035] Figure 27 Another circuit diagram of the first shift register in the display panel provided in this application;

[0036] Figure 28 Another circuit diagram of the pixel circuit in the display panel provided in this application;

[0037] Figure 29 A schematic diagram of the structure of the display device provided in this application. Detailed Implementation

[0038] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0039] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0040] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0041] It should be noted that the transistors in this application can be either N-type or P-type transistors. For N-type transistors, the enable level is high and the disable level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are turned off. For P-type transistors, the enable level is low and the disable level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are turned off. In specific implementations, the gate of each transistor is used as its control terminal, and depending on the signal and type of the gate of each transistor, its first terminal can be used as the source and its second terminal as the drain, or its first terminal as the drain and its second terminal as the source; this distinction is not made here.

[0042] In this application, the term "electrical connection" can refer to a direct electrical connection between two components, or an electrical connection between two components via one or more other components.

[0043] In this application, the first node, the second node, the third node, and each connecting node are defined only for the convenience of describing the circuit structure, and the first node, the second node, the third node, and each connecting node are not actual circuit units.

[0044] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0045] Before describing the technical solution provided in this application, in order to facilitate understanding of this application, this application first specifically explains the problems existing in the related technologies:

[0046] Figure 1 This is a circuit diagram of a display panel. For example... Figure 1 As shown, in related technologies, the pixel circuits 10' in the display panel are electrically connected to the scan signal line SCAN' and the initialization signal line vref', respectively. The scan signal line SCAN' is used to provide a scan signal to the pixel circuits 10', which can be used to control the transistors in the pixel circuits 10' to turn on / off. Moreover, multiple rows of pixel circuits 10' in the display panel typically share the same initialization signal line vref', which can provide an initialization signal to the multiple rows of pixel circuits 10'.

[0047] Figure 2This is a schematic diagram of a pixel circuit. For example... Figure 2 As shown, the pixel circuit 10' may include an initialization transistor T1'. To reduce the number of scan signal lines in the display panel, this application first considers electrically connecting the gate and first terminal of the initialization transistor T1' to the initialization signal line vref', and electrically connecting the second terminal of the initialization transistor T1' to the target node Nm' in the pixel circuit 10'. When the initialization signal line vref' transmits an enable level, the initialization transistor T1' is turned on, transmitting the enable level of the initialization signal line vref' to the target node Nm' in the pixel circuit 10' to initialize the target node Nm'.

[0048] In other words, the enable level provided by the initialization signal line vref' is used not only to control the initialization transistor T1' to turn on, but also to initialize the target node Nm'. However, further research by the inventors of this application revealed that, in this way, when the i-th row pixel circuit is in the data writing stage or the light-emitting stage, other pixel circuits besides the i-th row pixel circuit cannot be initialized. This is because once other pixel circuits besides the i-th row pixel circuit are initialized, the initialization transistor T1' in the i-th row pixel circuit will also turn on, meaning the i-th row pixel circuit will also be initialized. This would affect the data signal writing of the i-th row pixel circuit or affect the normal driving of the light-emitting element of the i-th row pixel circuit to emit light. Here, i is a positive integer.

[0049] To facilitate understanding, the following will be combined with... Figure 3 Please provide an explanation.

[0050] Figure 3 This is a driving timing diagram corresponding to a display panel. For example... Figure 3 As shown, taking a 3-row pixel circuit as an example, when the j-th row of pixel circuits is in the data writing stage, the scan signal line SCANj corresponding to the j-th row of pixel circuits outputs an enable level (e.g., low level), where j is a positive integer. When the j-th row of pixel circuits is in the light-emitting stage, the light-emitting control signal line EMITj corresponding to the j-th row of pixel circuits outputs an enable level (e.g., low level). For example, when the 1st row of pixel circuits is in the light-emitting stage, the light-emitting control signal line EMIT1 corresponding to the 1st row of pixel circuits outputs an enable level. When the 2nd row of pixel circuits is in the light-emitting stage, the light-emitting control signal line EMIT2 corresponding to the 2nd row of pixel circuits outputs an enable level. When the 3rd row of pixel circuits is in the light-emitting stage, the light-emitting control signal line EMIT3 corresponding to the 3rd row of pixel circuits outputs an enable level.

[0051] Combination Figure 1 and Figure 3 As shown, if adopting Figure 1In the circuit connection shown, during stage t1', the initialization signal line vref' needs to simultaneously provide the enable level of the initialization signal to the multi-row pixel circuit 10' so that the multi-row pixel circuit 10' can complete its initialization simultaneously. Then, the multi-row pixel circuit 10' sequentially completes the data signal writing and drives the light-emitting element to emit light. Since other pixel circuits besides the i-th row pixel circuit cannot be initialized when the i-th row pixel circuit is in the data writing or light-emitting stage, the initialization process of the next frame can only begin after the light-emitting stage of the last row pixel circuit 10' has ended. This results in a longer screen refresh cycle (i.e., one frame time) for the display panel, making it difficult to improve the refresh rate of the display panel.

[0052] In view of the inventors’ above-mentioned research findings, in order to further improve the refresh rate, this application further proposes a technical solution for initialization signal shifting, which can be applied to scenarios where the gate of the initialization transistor and the first pole of the initialization transistor are electrically connected to the initialization signal line, including but not limited to the case where the gate of the initialization transistor and the first pole of the initialization transistor are electrically connected to the initialization signal line. This application can solve the technical problem that the screen refresh cycle of the display panel is long and the refresh rate of the display panel is difficult to improve.

[0053] The technical concept of this application is as follows: For the first pixel circuit and the second pixel circuit in the display panel, a first initialization signal line is electrically connected to the first pixel circuit, and a second initialization signal line is electrically connected to the second pixel circuit. In the first stage of the display panel's screen refresh cycle, the first initialization signal line provides an enable level to the first pixel circuit to initialize the target node of the first pixel circuit, and the second initialization signal line provides a disable level to the second pixel circuit. In this way, the initialization process of different pixel circuits no longer needs to be unified and can be performed in a time-sharing manner. Therefore, for the pixel circuit, initialization can be performed without waiting for other pixel circuits to complete their light-emitting stage. In other words, the initialization process of the pixel circuit can overlap with the data writing stage and / or light-emitting stage of other pixel circuits, thereby shortening the screen refresh cycle of the display panel and helping to improve the refresh rate of the display panel.

[0054] The display panel provided in this application will be described below.

[0055] Figure 4 A circuit diagram of a display panel provided in this application. Figure 4As shown, the display panel 40 may include pixel circuitry 41 and light-emitting elements 42. Pixel circuitry 41 can be used to drive light-emitting elements 42 to emit light. Exemplarily, light-emitting elements 42 include, but are not limited to, organic light-emitting diodes (OLEDs), inorganic light-emitting diodes (LEDs), or quantum dot (QD) diodes. Inorganic light-emitting diodes include, but are not limited to, mini light-emitting diodes (mini LEDs), micro light-emitting diodes (micro LEDs), or quantum dot light-emitting diodes (QLEDs).

[0056] The display panel 40 may include an initialization signal line vref, which is electrically connected to the pixel circuit 41 and is used to transmit an initialization signal. The initialization signal may include an enable level and a disable level. The enable level of the initialization signal can be used to initialize the target node of the pixel circuit 41. The enable and disable levels of the initialization signal will be described below. Figure 5 Examples will be given.

[0057] The initialization signal line vref can extend along the first direction X. The initialization signal line vref can include a first initialization signal line vref1 and a second initialization signal line vref2. Pixel circuit 41 can include a first pixel circuit 410 and a second pixel circuit 420. The first pixel circuit 410 and the second pixel circuit 420 can be arranged along the second direction Y. The first direction X intersects the second direction Y. For example, the first direction X can be the row direction of the display panel, and the second direction Y can be the column direction of the display panel. That is, it can be understood that the first pixel circuit 410 and the second pixel circuit 420 are pixel circuits in different rows. It should be noted that along the second direction Y, the first pixel circuit 410 and the second pixel circuit 420 can be adjacent, meaning there are no other pixel circuits between them. Of course, along the second direction Y, the first pixel circuit 410 and the second pixel circuit 420 can also not be adjacent, meaning there can be other pixel circuits between them.

[0058] The first initialization signal line vref1 is electrically connected to the first pixel circuit 410, and the second initialization signal line vref2 is electrically connected to the second pixel circuit 420. It should be noted that vref1 and vref2 are merely exemplary labels, used only to illustrate that there are two different pixel row connections on the display panel that transmit different initialization signals. The panel may include multiple initialization signal lines, each electrically connected to a pixel circuit in a different row, providing an initialization signal to the target node of the corresponding pixel circuit.

[0059] Figure 5 for Figure 4 The diagram shown illustrates a driving timing scheme for the display panel. (Combined with...) Figure 4 and Figure 5 As shown, the enable level of the initialization signal can be low, and the disable level can be high. Taking the first initialization signal line vref1 as an example, when the first initialization signal line vref1 provides the enable level of the initialization signal, it can be used to initialize the target node of the first pixel circuit 410. (Continue to see...) Figure 4 and Figure 5 A screen refresh cycle H of the display panel can include a first stage h1. The screen refresh cycle H can be understood as the period during which the display panel displays one frame. Within one screen refresh cycle H, the multi-row pixel circuits of the display panel can drive the corresponding light-emitting elements to light up row by row. The first stage h1 can be a portion of the screen refresh cycle H. In the first stage h1, the first initialization signal line vref1 transmits an enable level, and the second initialization signal line vref2 transmits a disable level. That is, in the first stage h1, the first initialization signal line vref1 can provide an enable level to the first pixel circuit 410 to initialize the target node of the first pixel circuit 410. In the first stage h1 where the target node of the first pixel circuit 410 is initialized, the second initialization signal line vref2 can provide a disable level to the second pixel circuit 420, and the target node of the second pixel circuit 420 is not initialized. In other words, the initialization process of the first pixel circuit 410 and the initialization process of the second pixel circuit 420 can be performed in a time-sharing manner.

[0060] It should be noted that, Figure 5 The example given is that the enable level is low and the disable level is high. However, in other embodiments, such as when the thin-film transistor in the pixel circuit 41 is an N-type transistor, the enable level can also be high and the disable level can also be low. This application does not limit this.

[0061] In the display panel of this application, a first initialization signal line is electrically connected to a first pixel circuit, and a second initialization signal line is electrically connected to a second pixel circuit. During the first stage of the display panel's screen refresh cycle, the first initialization signal line provides an enable level to the first pixel circuit to initialize the target node of the first pixel circuit, while the second initialization signal line provides a disable level to the second pixel circuit. This eliminates the need for unified initialization processes for different pixel circuits, allowing them to be performed in a time-sharing manner. Therefore, for a pixel circuit, initialization can begin without waiting for other pixel circuits to complete their light-emitting phase. In other words, the initialization process of a pixel circuit can overlap with the data writing phase and / or light-emitting phase of other pixel circuits, thereby shortening the screen refresh cycle of the display panel and contributing to an improved refresh rate.

[0062] Figure 6 This is a circuit diagram of a pixel circuit in the display panel provided in this application. Figure 6 As shown, according to some embodiments of this application, the pixel circuit 41 may optionally include a driving module 601 and a data writing module 602. The control terminal of the data writing module 602 is electrically connected to the first scan line S1, which transmits a scan signal. In some specific examples, the control terminal of the driving module 601 may be electrically connected to a first node N1, a first terminal of the driving module 601 may be electrically connected to a second node N2, and a second terminal of the driving module 601 may be electrically connected to a third node N3. The driving module 601 can be used to provide driving current to the light-emitting element 42. The first terminal of the data writing module 602 may be electrically connected to the data signal line data, and the second terminal of the data writing module 602 may be electrically connected to the second node N2.

[0063] Figure 7 for Figure 6 The diagram shows a driving timing sequence corresponding to a pixel circuit. (Combined with...) Figure 6 and Figure 7 As shown, a screen refresh cycle H of the display panel may include a light-emitting cycle T of at least one pixel circuit. A light-emitting cycle T of the pixel circuit may include an initialization phase t1 and a data writing phase t2. In the data writing phase t2, the data writing module 602 may provide a data signal to the driving module 601 in response to a first scan signal. Specifically, in the data writing phase t2, the data writing module 602 may be turned on under the control of the first scan line S1, transmitting the data signal from the data signal line data to the second node N2, thereby writing the data signal to the driving module 601.

[0064] Combination Figure 6 and Figure 7As shown, for ease of explanation, t1-1 represents the initialization stage t1 of the first pixel circuit 410, and t2-1 represents the data writing stage t2 of the first pixel circuit 410. S1-1 represents the first scan line S1 connected to the data writing module 602 in the first pixel circuit 410, and S1-2 represents the first scan line S1 connected to the data writing module 602 in the second pixel circuit 420. In the initialization stage t1-1 of the first pixel circuit 410, the first initialization signal line vref1 can transmit an enable level to initialize the target node of the first pixel circuit 410. The initialization stage t1-1 of the first pixel circuit 140 is the aforementioned first stage h1. In the initialization stage t1-1 of the first pixel circuit 140, the second initialization signal line vref2 can provide a disable level to the second pixel circuit 420, and the target node of the second pixel circuit 420 is not initialized.

[0065] During the data writing phase t2-1 of the first pixel circuit 410, the first initialization signal line vref1 can transmit a disabled level. The data writing module 602 in the first pixel circuit 410 can provide a data signal to the driving module 601 in response to the first scan signal. That is, the first initialization signal line vref1 does not continuously output an enabled level, but can switch between an enabled level and a disabled level. In other words, the initialization signal transmitted by the first initialization signal line vref1 is a pulse signal.

[0066] During the data writing phase t2-1 of the first pixel circuit 410, the first initialization signal line vref1 transmits an enable level, so that the first pixel circuit 140 no longer performs initialization, thereby avoiding the impact of initialization on data signal writing and ensuring that the first pixel circuit 140 can successfully write data signals.

[0067] See also Figure 6 and Figure 7 In some specific embodiments, optionally, a light emission cycle T of the pixel circuit may include an initialization phase t1 and a data writing phase t2. The initialization phase t1 in the same light emission cycle T may precede the data writing phase t2, that is, the initialization phase t1 in the same light emission cycle T is earlier than the data writing phase t2. Initializing the pixel circuit 41 first can make the potential of the target node in the pixel circuit 41 reach the expected potential, ensuring that the data signal can be successfully written to the driving module 601.

[0068] Figure 8 for Figure 4 The diagram shown illustrates another driving timing scheme for the display panel. (Combined with...) Figure 4 and Figure 8As shown, according to some embodiments of this application, optionally, a screen refresh cycle H of the display panel may further include a second stage h2. The second stage h2 may not overlap with the first stage h1, meaning the second stage h2 and the first stage h1 are different time periods. In the second stage h2, the first initialization signal line vref1 transmits a disabled level, and the second initialization signal line vref2 transmits an enabled level. That is, in the second stage h2, the second initialization signal line vref2 can provide an enabled level to the second pixel circuit 420 to initialize the target node of the second pixel circuit 420. In the second stage h2 where the target node of the second pixel circuit 420 is initialized, the first initialization signal line vref1 can provide a disabled level to the first pixel circuit 410, and the target node of the first pixel circuit 410 is not initialized.

[0069] As mentioned earlier, the first initialization signal line vref1 does not continuously output an enable level, but can switch between enable and disable levels. Similarly, the second initialization signal line vref2 does not continuously output a disable level, but can switch between enable and disable levels. In other words, both the initialization signal transmitted by the first initialization signal line vref1 and the initialization signal transmitted by the second initialization signal line vref2 can be pulse signals. For example, the period of the initialization signal transmitted by the first initialization signal line vref1 and the period of the initialization signal transmitted by the second initialization signal line vref2 can be the same, and there can be a phase difference between the initialization signals transmitted by the first initialization signal line vref1 and the second initialization signal line vref2.

[0070] Thus, the initialization process of the first pixel circuit 410 and the initialization process of the second pixel circuit 420 can be performed in a time-sharing manner. Therefore, the initialization process of the first pixel circuit 410 can overlap with the data writing phase and / or light emission phase of the second pixel circuit 420, or the initialization process of the second pixel circuit 420 can overlap with the data writing phase and / or light emission phase of the first pixel circuit 410, thereby shortening the screen refresh cycle of the display panel and helping to improve the refresh rate of the display panel.

[0071] Combination Figure 4 , Figure 6 and Figure 8As shown, for ease of explanation, t1-2 represents the initialization stage t1 of the second pixel circuit 420, and t2-2 represents the data writing stage t2 of the second pixel circuit 420. In some specific embodiments, optionally, during the initialization stage t1-2 of the second pixel circuit 420, i.e., the aforementioned second stage h2, the second initialization signal line vref2 provides an enable level for the initialization signal, used to initialize the target node of the second pixel circuit 420. Simultaneously, the data writing module 602 in the first pixel circuit 410 transmits the data signal to the driving module 601 in response to the first scan signal. That is, the data writing stage t2-1 of the first pixel circuit 410 and the initialization stage t1-2 of the second pixel circuit 420 can overlap.

[0072] In other words, the initialization process of the second pixel circuit 420 can be performed simultaneously with the data signal writing process of the first pixel circuit 410, thereby shortening the duration of one frame refresh cycle H of the display panel and helping to improve the refresh rate of the display panel.

[0073] Figure 9 for Figure 6 The diagram shows a driving timing sequence corresponding to a pixel circuit. (Combined with...) Figure 6 and Figure 9 As shown, according to some embodiments of this application, optionally, a light emission cycle T corresponding to the pixel circuit 41 may include at least two initialization stages t1 and at least two data writing stages t2, with the initialization stages t1 and data writing stages t2 alternating in the same light emission cycle T. Figure 9 Taking a light emission cycle T consisting of two initialization phases t1 and two data writing phases t2 as an example, as follows: Figure 9 As shown, in chronological order, the first initialization stage t1 in the same emission cycle T can be located before the first data writing stage t2, the first data writing stage t2 can be located before the second initialization stage t1, and the second initialization stage t1 can be located in the second data writing stage t2.

[0074] Thus, on the one hand, the pixel circuit 41 can be initialized at least twice within one light emission cycle T to ensure that the potential of the target node in the pixel circuit 41 successfully reaches the expected potential, which helps to ensure the successful writing of data signals; on the other hand, the pixel circuit 41 writes data signals at least twice within one light emission cycle T, which is equivalent to adjusting the bias state of the threshold voltage of the driving module in the pixel circuit 41 at least twice, which is beneficial to the recovery of the threshold voltage of the driving module in the pixel circuit 41.

[0075] Figure 10 Another circuit diagram of the display panel provided in this application. Figure 10As shown, according to some embodiments of this application, optionally, the display panel 40 may further include a first light-emitting control signal line EM1, which is electrically connected to the first pixel circuit 410. The first light-emitting control signal line EM1 can be used to transmit a light-emitting control signal to the first pixel circuit 410. The light-emitting control signal may include an enable level and a disable level. When the first light-emitting control signal line EM1 transmits an enable level to the first pixel circuit 410, the first pixel circuit 410 drives the light-emitting element 42 to emit light.

[0076] The pixel circuit 41 may further include a third pixel circuit 430, and the third pixel circuit 430 and the first pixel circuit 410 may be arranged along the second direction Y. It should be noted that... Figure 10 The positions of the first pixel circuit 410 and the third pixel circuit 430 shown are merely illustrative. Along the second direction Y, the first pixel circuit 410 and the third pixel circuit 430 may be adjacent or not adjacent, and this application does not limit this. Furthermore, the third pixel circuit 430 may be the same as or different from the second pixel circuit 420, and this application does not limit this.

[0077] The initialization signal line vref may also include a third initialization signal line vref3, which is electrically connected to the third pixel circuit 430.

[0078] Figure 11 for Figure 10 The diagram shown illustrates a driving timing scheme for the display panel. (Combined with...) Figure 10 and Figure 11As shown, S1-1 represents the first scan line S1 connected to the data writing module 602 in the first pixel circuit 410, S1-2 represents the first scan line S1 connected to the data writing module 602 in the second pixel circuit 420, and S1-3 represents the first scan line S1 connected to the data writing module 602 in the third pixel circuit 430. EM1 represents the first light emission control signal line connected to the first pixel circuit 410, EM2 represents the second light emission control signal line connected to the second pixel circuit 420, and EM3 represents the third light emission control signal line connected to the third pixel circuit 430. One light emission cycle T of the pixel circuit may also include a light emission stage t3, where t3-1 represents the light emission stage t3 of the first pixel circuit 410. During the light emission stage t3-1 of the first pixel circuit 410, the first light emission control signal line EM1 provides an enable level, and the first pixel circuit 410 drives the light-emitting element 42 to emit light. Meanwhile, during the light-emitting phase t3-1 of the first pixel circuit 410, the third initialization signal line vref3 provides an enable level for the initialization signal, used to initialize the target node of the third pixel circuit 430. That is, when the first pixel circuit 410 is in the light-emitting phase t3-1, the third pixel circuit 430 can be initialized, and the initialization phase t1-3 of the third pixel circuit 430 can at least partially overlap with the light-emitting phase t3-1 of the first pixel circuit 410.

[0079] Thus, for example, the third pixel circuit 430 can be initialized without waiting for other pixel circuits (such as the first pixel circuit 410) to complete the light-emitting stage. In other words, the initialization process of the third pixel circuit 430 can overlap with the light-emitting stage of other pixel circuits, thereby shortening the screen refresh cycle of the display panel and helping to improve the refresh rate of the display panel.

[0080] Figure 12 Another circuit diagram of the pixel circuit in the display panel provided in this application. (See diagram below.) Figure 12 As shown, according to some embodiments of this application, optionally, the pixel circuit 41 may include a driving module 601 and a first initialization module 603. The control terminal of the driving module 601 may be electrically connected to the first node N1, the first terminal of the driving module 601 may be electrically connected to the second node N2, and the second terminal of the driving module 601 may be electrically connected to the third node N3. Specifically, the target node of the pixel circuit 41 described above may be the first node N1.

[0081] Specifically, the control terminal of the first initialization module 603 can be electrically connected to the initialization signal line vref, the first terminal of the first initialization module 603 can be electrically connected to the initialization signal line vref, and the second terminal of the first initialization module 603 can be electrically connected to the first node N1. The first initialization module can be used to transmit the enable level of the initialization signal provided by the initialization signal line vref to the first node N1 to initialize the first node N1. By initializing the first node N1, it is easier to successfully write subsequent data signals to the first node N1 (i.e., the control terminal of the driver module 601).

[0082] Thus, on the one hand, the control terminal and the first terminal of the first initialization module 603 are both electrically connected to the initialization signal line vref. The initialization signal line vref is not only used to provide an initialization signal for initializing the first node N1, but also used to control the first initialization module 603 to be turned on / off. This can save the number of scanning signal lines in the display panel, which is beneficial to simplifying wiring design and reducing production costs.

[0083] On the other hand, taking the first pixel circuit and the second pixel circuit as examples, even if the control terminal and the first terminal of the first initialization module 603 are both electrically connected to the initialization signal line vref, the first initialization module 603 in the second pixel circuit can still be turned on under the control of the second initialization signal line when the first pixel circuit is in the data writing stage or the light-emitting stage, thus realizing the initialization of the target node of the second pixel circuit. At this time, the first initialization module 603 in the first pixel circuit will not be affected by the second initialization signal line. The first initialization module 603 in the first pixel circuit can be turned off under the control of the first initialization signal line, so as not to affect the data signal writing of the first pixel circuit or the driving of the light-emitting element to emit light. Therefore, for the pixel circuit, there is no need to wait for other pixel circuits to complete the light-emitting stage before the initialization of the first node N1 can be performed. In other words, the initialization process of the first node N1 can overlap with the data writing stage and / or light-emitting stage of other pixel circuits, thereby shortening the screen refresh cycle of the display panel and helping to improve the refresh rate of the display panel.

[0084] Figure 13 This is yet another circuit diagram of the pixel circuit in the display panel provided in this application. (See diagram below.) Figure 13 As shown, according to some embodiments of this application, optionally, the display panel 40 may also include a scan signal line Sn and a reference voltage signal line vf, the reference voltage signal line vf being used to provide a constant voltage signal.

[0085] The pixel circuit 41 may further include a second initialization module 604. The control terminal of the second initialization module 604 is electrically connected to the scan signal line Sn, the first terminal of the second initialization module 604 is electrically connected to the reference voltage signal line vf, and the second terminal of the second initialization module 604 is electrically connected to the first electrode of the light-emitting element 42. For example, the first electrode of the light-emitting element 42 may be the anode of the light-emitting element 42, and the second electrode of the light-emitting element 42 may be the cathode of the light-emitting element 42. The second initialization module 604 can be used to transmit the voltage signal provided by the reference voltage signal line vf to the first electrode of the light-emitting element 42 to initialize the first electrode of the light-emitting element 42.

[0086] Unless otherwise specified, this application describes the thin-film transistor in pixel circuit 41 as a P-type transistor. When the thin-film transistor in pixel circuit 41 is a P-type transistor, the reference voltage signal line vf can specifically be used to provide a constant negative voltage signal, that is, a voltage signal with a voltage value less than 0V. The negative voltage signal provided by the reference voltage signal line vf is transmitted to the first electrode of the light-emitting element 42 through the second initialization module 604 to initialize the first electrode of the light-emitting element 42, so that the potential of the first electrode of the light-emitting element 42 is pulled down to a lower potential.

[0087] In this way, by initializing the first electrode of the light-emitting element 42, the influence of residual charge from the previous frame on the light-emitting element 42 can be avoided, thus improving problems such as ghosting.

[0088] According to other embodiments of this application, alternatively, similar to initializing the first node N1 using a pulse signal, the first electrode of the light-emitting element 42 can also be initialized using a pulse signal.

[0089] Figure 14 This is yet another circuit diagram of the pixel circuit in the display panel provided in this application. (See diagram below.) Figure 14 As shown, with Figure 13 The difference in the illustrated embodiment is that the control terminal of the second initialization module 604 can be electrically connected to the initialization signal line vref, the first terminal of the second initialization module 604 can also be electrically connected to the initialization signal line vref, and the second terminal of the second initialization module 604 can be electrically connected to the first electrode of the light-emitting element 42. The second initialization module 604 can be used to transmit the enable level of the initialization signal provided by the initialization signal line vref to the first electrode of the light-emitting element 42 to initialize the first electrode of the light-emitting element 42.

[0090] In other words, Figure 14In the illustrated embodiment, the initialization signal line vref is used not only to provide an initialization signal for initializing the first node N1, but also to control the first initialization module 603 to be turned on / off, to provide an initialization signal for initializing the first electrode of the light-emitting element 42, and to control the second initialization module 604 to be turned on / off. This can further reduce the number of scan signal lines and / or reference voltage signal lines in the display panel, which is beneficial for simplifying wiring design and reducing production costs.

[0091] Furthermore, the initialization process of the first electrode of the light-emitting element 42 by different pixel circuits can be performed in a time-sharing manner. For the pixel circuit, there is no need to wait for other pixel circuits to complete the light-emitting stage before the initialization of the first electrode of the light-emitting element 42 can be performed. In other words, the initialization process of the first electrode of the light-emitting element 42 can overlap with the data writing stage and / or light-emitting stage of other pixel circuits, thereby shortening the screen refresh cycle of the display panel and helping to improve the refresh rate of the display panel.

[0092] In some specific embodiments, optionally, the first initialization module 603 and the second initialization module 604 in the same pixel circuit can be electrically connected to the same initialization signal line vref. In other words, the first initialization module 603 and the second initialization module 604 in the same pixel circuit can be electrically connected to the initialization signal line vref corresponding to the same row of pixel lines.

[0093] Figure 15 This is yet another circuit diagram of the display panel provided in this application. Specifically, as shown... Figure 15 As shown, the control terminals of the first initialization module 603 and the second initialization module 604 in the first pixel circuit 410 can both be electrically connected to the first initialization signal line vref1. Furthermore, the first terminals of the first initialization module 603 and the second initialization module 604 in the first pixel circuit 410 can also be electrically connected to the first initialization signal line vref1. Both the first initialization module 603 and the second initialization module 604 are illustrated using P-type transistors as an example; however, both the first initialization module 603 and the second initialization module 604 can also be N-type transistors, and this embodiment does not limit the application to this.

[0094] In this way, the initialization of the first node N1 in the first pixel circuit 410 and the initialization of the first electrode of the light-emitting element 42 connected to the first pixel circuit 410 can be performed simultaneously, for example, both during the initialization phase of the first pixel circuit 410. Furthermore, in the wiring design, since the first initialization signal line vref1 is close to the first pixel circuit 410, or in other words, the first initialization signal line vref1 passes through the area where the first pixel circuit 410 is located, both the first initialization module 603 and the second initialization module 604 in the first pixel circuit 410 are electrically connected to the first initialization signal line vref1. This reduces the design of the connection lines between the first initialization module 603 and the first initialization signal line vref1, and / or reduces the design of the connection lines between the second initialization module 604 and the first initialization signal line vref1, further reducing the wiring in the display panel and simplifying the wiring design.

[0095] Similarly, the control terminals of the first initialization module 603 and the second initialization module 604 in the second pixel circuit 420 can both be electrically connected to the second initialization signal line vref2. Furthermore, the first terminals of the first initialization module 603 and the second initialization module 604 in the second pixel circuit 420 can also be electrically connected to the second initialization signal line vref2.

[0096] In this way, the initialization of the first node N1 in the second pixel circuit 420 and the initialization of the first electrode of the light-emitting element 42 connected to the second pixel circuit 420 can be performed simultaneously, for example, both during the initialization phase of the second pixel circuit 420. Furthermore, in the wiring design, since the second initialization signal line vref2 is close to the second pixel circuit 420, or in other words, the second initialization signal line vref2 passes through the area where the second pixel circuit 420 is located, both the first initialization module 603 and the second initialization module 604 in the second pixel circuit 420 are electrically connected to the second initialization signal line vref2. This reduces the design of the connection lines between the first initialization module 603 and the second initialization signal line vref2, and / or reduces the design of the connection lines between the second initialization module 604 and the second initialization signal line vref2, further reducing the traces in the display panel and simplifying the wiring design.

[0097] In some other specific embodiments, optionally, the first initialization module 603 and the second initialization module 604 in the same pixel circuit can be electrically connected to different initialization signal lines vref. In other words, the first initialization module 603 and the second initialization module 604 in the same pixel circuit can be electrically connected to the initialization signal lines vref corresponding to different rows of pixel lines.

[0098] Figure 16 This is yet another circuit diagram of the display panel provided in this application. Specifically, as shown... Figure 16 As shown, along the second direction Y, the first pixel circuit 410 and the second pixel circuit 420 can be separated by k pixel circuits 41, where k ≥ 0 and k is an integer. Figure 16 The example given is k=1, but it is understood that k can also be greater than 1, and this application does not limit this.

[0099] The control terminal of the first initialization module 603 in the first pixel circuit 410 can be electrically connected to the first initialization signal line vref1, and the control terminal of the second initialization module 604 in the first pixel circuit 410 can be electrically connected to the second initialization signal line vref2. Furthermore, the first terminal of the first initialization module 603 in the first pixel circuit 410 can be electrically connected to the first initialization signal line vref1, and the first terminal of the second initialization module 604 in the first pixel circuit 410 can be electrically connected to the second initialization signal line vref2.

[0100] The second initialization signal line vref2 is used to initialize the target node (such as the first node N1) in the second pixel circuit 420. The control terminal of the second initialization module 604 in the first pixel circuit 410 is electrically connected to the second initialization signal line vref2. In this way, the initialization of the first electrode of the light-emitting element 42 connected to the first pixel circuit 410 and the initialization of the target node in the second pixel circuit 420 can be performed simultaneously, while the initialization of the first node N1 in the first pixel circuit 410 and the initialization of the first electrode of the light-emitting element 42 connected to the first pixel circuit 410 can be performed in a time-division manner.

[0101] Thus, the selection of the initialization time period for the first electrode of the light-emitting element 42 connected to the first pixel circuit 410 is more flexible. The size of k can be flexibly adjusted according to the requirements, thereby flexibly adjusting the initialization time period for the first electrode of the light-emitting element 42 connected to the first pixel circuit 410 to meet the needs of different situations.

[0102] See also Figure 16 According to some embodiments of this application, optionally, the display panel 40 may include a display area AA and a bonding area NA1 arranged along the second direction Y, and a light-emitting element ( Figure 16 (Not shown) can be located in display area AA. Bonding area NA1 can be provided with bonding pads P, which can be used to bond with flexible circuit boards (…). Figure 16 (not shown) or driver chip ( Figure 16 Electrical connection (not shown).

[0103] Along the second direction Y, the second pixel circuit 420 can be located on the side of the first pixel circuit 410 closer to the bonding area NA1. In the same screen refresh cycle, when the display panel performs forward scanning, the second pixel circuit 420 can be scanned after the first pixel circuit 410 has been scanned.

[0104] Thus, the second initialization signal line vref2 can not only provide an initialization signal for initializing the target node (such as the first node N1) in the second pixel circuit 420, but also control the first initialization module 603 in the second pixel circuit 420 to be turned on / off, provide an initialization signal for initializing the first electrode of the light-emitting element 42 connected to the first pixel circuit 410, and control the second initialization module 604 in the first pixel circuit 410 to be turned on / off. This can further reduce the number of scan signal lines and / or reference voltage signal lines in the display panel, which is beneficial for simplifying wiring design and reducing production costs.

[0105] Figure 17 This is yet another circuit diagram of the display panel provided in this application. (See diagram below.) Figure 17 As shown, in some other embodiments, optionally, the second pixel circuit 420 may also be located on the side of the first pixel circuit 410 away from the bonding area NA1 along the second direction Y. During the same screen refresh cycle, when the display panel performs forward scanning, the first pixel circuit 410 can be scanned after the second pixel circuit 420 has been scanned. This can further reduce the number of scan signal lines and / or reference voltage signal lines in the display panel, simplifying wiring design and reducing production costs.

[0106] Figure 18 This is yet another circuit diagram of the display panel provided in this application. (See diagram below.) Figure 18 As shown, according to some embodiments of this application, optionally, the display panel 40 may further include a scan signal line S' extending along a first direction X, the scan signal line S' being electrically connected to the pixel circuit. The scan signal line S' can be used to transmit scan signals. It should be noted that the scan signal line S' here has a different meaning from the scan signal line Sn mentioned above. The scan signal line S' here represents a scan signal line electrically connected to the pixel circuit, while the scan signal line Sn mentioned above only represents a scan signal line electrically connected to the second initialization module in the pixel circuit.

[0107] The scan signal line S' may include a first scan signal line S1' and a second scan signal line S2'. The first scan signal line S1' may be electrically connected to the first pixel circuit 410, and the second scan signal line S2' may be electrically connected to the second pixel circuit 420. It should be noted that the first scan signal line S1' here has a different meaning from the first scan line S1 mentioned above. Here, the first scan signal line S1' represents a scan signal line electrically connected to the first pixel circuit 410, while the first scan line S1 mentioned above represents a scan signal line electrically connected to the data writing module in the pixel circuit.

[0108] exist Figure 18 In the illustrated embodiment, along the second direction Y, the first pixel circuit 410 and the second pixel circuit 420 are adjacent. The phase of the pulse signal provided by the first scan signal line S1' can be the same as the phase of the pulse signal provided by the second initialization signal line S2', and the period of the pulse signal provided by the first scan signal line S1' can be the same as the period of the pulse signal provided by the second initialization signal line S2'. The amplitude of the pulse signal provided by the first scan signal line S1' can be the same as or different from the amplitude of the pulse signal provided by the second initialization signal line S2'. That is, the first scan signal line S1' and the second initialization signal line S2' can be connected to the same shift register to transmit pulse signals with the same phase and period.

[0109] See also Figure 18 Along the second direction Y, the first distance y1 between the first scan signal line S1' and the first initialization signal line vref1 is greater than the second distance y2 between the first scan signal line S1' and the second initialization signal line vref2. That is, the spacing between the first scan signal line S1' and the second initialization signal line vref2 is smaller than the spacing between the first scan signal line S1' and the first initialization signal line vref1 connected to the first pixel circuit.

[0110] The advantage of doing this is that since the first scan signal line S1' and the second initialization signal line vref2 are electrically connected to the same pulse signal output terminal (such as a shift register), if the first scan signal line S1' and the second initialization signal line vref2 are close together, the trace length between at least one of the first scan signal line S1' and the second initialization signal line vref2 and the pulse signal output terminal can be reduced, which helps to simplify the wiring design and reduce production costs.

[0111] According to some embodiments of this application, optionally, the initialization signal transmitted by the initialization signal line vref can also be the same as or similar to the scan signal transmitted by the scan signal line S', specifically through multiple cascaded shift registers.

[0112] Figure 19This is yet another circuit diagram of the display panel provided in this application. (See diagram below.) Figure 19 As shown, according to some embodiments of this application, optionally, the display panel 40 may further include an initialization signal output circuit 190 and a pulse signal generator 191. The initialization signal output circuit 190 may include multiple cascaded first shift registers 190a. The pulse signal generator 191 may include clock signal terminals CK1' to CK3'. The clock signal terminals CK1' to CK3' are used to provide clock signals to the first shift registers 190a. In some examples, each stage of the first shift register 190a may be electrically connected to two of the clock signal terminals CK1' to CK3', and adjacent first shift registers 190a may be connected to different clock signal terminals. For example, the first-stage first shift register 190a may be connected to clock signal terminals CK1' and CK2', the second-stage first shift register 190a may be connected to clock signal terminals CK2' and CK3', and the third-stage first shift register 190a may be connected to clock signal terminals CK1' and CK3'. The first output terminal OUT1 of the first shift register 190a can be electrically connected to an initialization signal line vref. The first output terminal OUT1 of the first shift register 190a can be used to provide an initialization signal to the initialization signal line vref. As mentioned above, the initialization signal line vref can transmit the enable level of the initialization signal to the pixel circuit 41 to initialize the target node in the pixel circuit 41.

[0113] Multiple cascaded first shift registers 190a can sequentially provide initialization signals to each row of pixel circuits in the display panel, enabling the initialization signals to be transmitted row by row. This eliminates the need for unified initialization phases for different pixel circuits, allowing them to be performed in a time-sharing manner. Therefore, pixel circuits that are earlier in the sequence do not need to wait for the last row of pixel circuits to finish their illumination phase before initiating the next frame, shortening the time spent per frame and improving the refresh rate of the display panel.

[0114] In addition, by transmitting the initialization signal line by line, the initialization process of each row of pixel circuits in the display panel can be guaranteed to proceed sequentially, which is less prone to errors and ensures that each row of pixel circuits can drive the light-emitting elements to emit light normally.

[0115] Figure 20 This is yet another circuit diagram of the display panel provided in this application. (See diagram below.) Figure 20As shown, according to some embodiments of this application, optionally, the first shift register 190a may further include a second output terminal OUT2. The second output terminal OUT2 of the first shift register 190a is electrically connected to a scan signal line S', and the second output terminal OUT2 of the first shift register 190a is used to provide a scan signal to the scan signal line S'. The scan signal line S' can transmit the scan signal to the pixel circuit 41 to control the turn-on / off of the thin-film transistors in the pixel circuit 41.

[0116] In other words, the first shift register 190a can not only output the initialization signal to initialize the target node in the pixel circuit 41, but also output the scan signal.

[0117] In this way, the initialization signal output circuit can output both scanning signals and initialization signals, enabling the reuse of circuits or electronic components, reducing the number of signal lines and electronic components in the display panel, lowering production costs, and helping to reduce the bezel of the display panel.

[0118] It should be noted that, Figure 20 The following example illustrates the connection between the input of the next-stage first shift register 190a and the second output OUT2 of the previous-stage first shift register 190a. In other embodiments, the input of the next-stage first shift register 190a may also be connected to the first output OUT1 of the previous-stage first shift register 190a, thereby forming a cascaded structure. This application does not limit this to any particular embodiment.

[0119] See also Figure 20 According to some embodiments of this application, optionally, along the second direction Y, the first pixel circuit 410 and the second pixel circuit 420 are separated by k pixel circuits. Wherein, k≥0 and k is an integer. Figure 20 For example, let's take k=0 as an example.

[0120] The scan signal line S' may include a first scan signal line S1' and a second scan signal line S2'. The first scan signal line S1' is electrically connected to the first pixel circuit 410, and the second scan signal line S2' is electrically connected to the second pixel circuit 420.

[0121] The first shift register 190a may include a first target shift register 200a. The first output terminal OUT1 of the first target shift register 200a may be electrically connected to the first initialization signal line vref1, and the second output terminal OUT2 of the first target shift register 200a may be electrically connected to the second scan signal line S2'.

[0122] In other words, the initialization signal line vref and the scan signal line S' connected to the first shift register 190a can correspond to different row pixel circuits. For example, in some examples, the first pixel circuit 410 can be located m rows below the second pixel circuit 420, where m ≥ 1 and 1 is an integer. That is, the first shift register 190a can be electrically connected to the scan signal line S' connected to the pixel circuit in the current row, and can also be electrically connected to the initialization signal line vref connected to the pixel circuit in the m rows below.

[0123] The circuit structure of the first shift register 190a will be illustrated below with some specific embodiments.

[0124] Figure 21 This is a circuit diagram of a first shift register in a display panel provided in this application. Figure 21 As shown, according to some embodiments of this application, optionally, the first shift register 190a may include a first inverter 210 and a second inverter 220. The function of the first inverter 210 and the second inverter 220 is to achieve level flipping. For example, if the input to the first inverter 210 is a high level, then after level flipping, the first inverter 210 outputs a low level. The second inverter 220 works similarly.

[0125] The control terminal of the first inverter 210 is electrically connected to the second output terminal OUT2 of the first shift register 190a, the first input terminal of the first inverter 210 is electrically connected to the first power supply voltage signal line VGH, the second input terminal of the first inverter 210 is electrically connected to the second power supply voltage signal line VGL, and the output terminal of the first inverter 210 is electrically connected to the control terminal of the second inverter 220.

[0126] The first input terminal of the second inverter 220 is electrically connected to the first positive voltage signal line VDD, and the second input terminal of the second inverter 220 is electrically connected to the first negative voltage signal line VF. The output terminal of the second inverter 220 is the first output terminal OUT1 of the first shift register 190a. It should be noted that the first negative voltage signal line VF and the reference voltage signal line vf can represent different signal lines, but the signal output by the first negative voltage signal line VF and the signal output by the reference voltage signal line vf can be the same or different; this embodiment does not limit this.

[0127] The first output terminal OUT1 of the first shift register 190a can be electrically connected to the initialization signal line vref to output the initialization signal. The second output terminal OUT2 of the first shift register 190a can be electrically connected to the scan signal line S' to output the scan signal.

[0128] In some examples, the voltage value transmitted by the first power supply voltage signal line VGH is greater than or equal to the voltage value transmitted by the first positive voltage signal line VDD, the voltage value transmitted by the first positive voltage signal line VDD is greater than the voltage value transmitted by the first negative voltage signal line VF, and the voltage value transmitted by the first negative voltage signal line VF is greater than or equal to the voltage value transmitted by the second power supply voltage signal line VGL, i.e., VGH ≥ VDD > VF ≥ VGL. In other words, the amplitude of the enable level of the initialization signal output by the first shift register 190a can be the same as or different from the amplitude of the enable level of the scan signal output by the first shift register 190a, and the amplitude of the disable level of the initialization signal output by the first shift register 190a can be the same as or different from the amplitude of the disable level of the scan signal output by the first shift register 190a.

[0129] In this way, by adding the first inverter 210 and the second inverter 220, the same first shift register 190a can output the same or different amplitude scan signals and initialization signals to meet different driving requirements.

[0130] See also Figure 21 In some specific embodiments, optionally, the first inverter 210 includes a first P-type transistor M1 and a first N-type transistor M2, and the second inverter 220 includes a second P-type transistor M3 and a second N-type transistor M4.

[0131] The gates of the first P-type transistor M1 and the first N-type transistor M2 are both electrically connected to the second output terminal OUT2 of the first shift register 190a. The first terminal of the first P-type transistor M1 is electrically connected to the first power supply voltage signal line VGH. The first terminal of the first N-type transistor M2 is electrically connected to the second power supply voltage signal line VGL. The second terminals of the first P-type transistor M1 and the first N-type transistor M2 are both electrically connected to the first connection node X1.

[0132] The gates of the second P-type transistor M3 and the second N-type transistor M4 are both electrically connected to the first connection node X1. The first terminal of the second P-type transistor M3 is electrically connected to the first positive voltage signal line VDD. The first terminal of the second N-type transistor M4 is electrically connected to the first negative voltage signal line VF. The second terminals of the second P-type transistor M3 and the second terminals of the second N-type transistor M4 are both electrically connected to the first output terminal OUT1 of the first shift register 190a.

[0133] Taking the example where both the enable level of the initialization signal and the enable level of the scan signal are low, when the second output terminal OUT2 of the first shift register 190a outputs the enable level of the scan signal (i.e., low level), the first P-type transistor M1 is turned on, the first N-type transistor M2 is turned off, and the high-level voltage signal of the first power supply voltage signal line VGH is transmitted to the first connection node X1. The second N-type transistor M4 responds to the high level of the first connection node X1 by turning on, the second P-type transistor M3 is turned off, and the second N-type transistor M4 transmits the low-level voltage signal of the first negative voltage signal line VF to the first output terminal OUT1 of the first shift register 190a. The first output terminal OUT1 of the first shift register 190a outputs the enable level of the initialization signal (i.e., low level).

[0134] Figure 22 Another circuit diagram of the first shift register in the display panel provided in this application. (See diagram below.) Figure 22 As shown, with Figure 21 Unlike the illustrated embodiment, according to other embodiments of this application, the first shift register 190a may optionally include a third inverter 230, a fourth inverter 240, and a fifth inverter 250.

[0135] The control terminal of the third inverter 230 is electrically connected to the second connection node X2, the first input terminal of the third inverter 230 is electrically connected to the first power supply voltage signal line VGH, and the second input terminal of the third inverter 230 is electrically connected to the second power supply voltage signal line VGL. The first shift register 190a may include an output module 200, and the second connection node X2 may be electrically connected to the output terminal of the output module 200. The output module 200 can be used to output an enable level or a disable level. This application does not limit the specific circuit structure of the output module 200; the specific structure of the output module 200 will be illustrated below.

[0136] The control terminal of the fourth inverter 240 is electrically connected to the output terminal of the third inverter 230. The first input terminal of the fourth inverter 240 is electrically connected to the first power supply voltage signal line VGH, and the second input terminal of the fourth inverter 240 is electrically connected to the second power supply voltage signal line VGL. The output terminal of the fourth inverter 240 is the second output terminal OUT2 of the first shift register 190a. The second output terminal OUT2 of the first shift register 190a is electrically connected to a scan signal line S', and is used to provide a scan signal to the pixel circuit through the scan signal line S'.

[0137] The control terminal of the fifth inverter 250 is electrically connected to the output terminal of the third inverter. The first input terminal of the fifth inverter 250 is electrically connected to the first positive voltage signal line VDD. The second input terminal of the fifth inverter 250 is electrically connected to the first negative voltage signal line VF. The output terminal of the fifth inverter 250 is the first output terminal OUT1 of the first shift register 190a.

[0138] Taking an example where both the enable level of the initialization signal and the enable level of the scan signal are low, when the second connection node X2 is low, the third inverter 230 responds to the low level of the second connection node X2 by outputting a high-level signal on the first power supply voltage signal line VGH. The fourth inverter 240 responds to the high-level signal output by the third inverter 230 by outputting a low-level signal on the second power supply voltage signal line VGL. The fifth inverter 250 responds to the high-level signal output by the third inverter 230 by outputting a low-level signal on the first negative voltage signal line VF.

[0139] As mentioned above, in some examples, VGH≥VDD>VF≥VGL. That is, the amplitude of the enable level of the initialization signal output by the first shift register 190a can be the same as or different from the amplitude of the enable level of the scan signal output by the first shift register 190a, and the amplitude of the disable level of the initialization signal output by the first shift register 190a can be the same as or different from the amplitude of the disable level of the scan signal output by the first shift register 190a.

[0140] In this way, by adding a third inverter 230, a fourth inverter 240 and a fifth inverter 250, the same first shift register 190a can output the same or different amplitude scan signals and initialization signals to meet different driving requirements.

[0141] See also Figure 22 In some specific embodiments, optionally, the third inverter 230 includes a third P-type transistor M5 and a third N-type transistor M6, the fourth inverter includes a fourth P-type transistor M7 and a fourth N-type transistor M8, and the fifth inverter includes a fifth P-type transistor M9 and a fifth N-type transistor M10.

[0142] The gates of the third P-type transistor M5 and the third N-type transistor M6 are both electrically connected to the second connection node X2. The first terminal of the third P-type transistor M5 is electrically connected to the first power supply voltage signal line VGH. The first terminal of the third N-type transistor M6 is electrically connected to the second power supply voltage signal line VGL. The second terminals of the third P-type transistor M5 and the third N-type transistor M6 are both electrically connected to the third connection node X3.

[0143] The gates of the fourth P-type transistor M7 and the fourth N-type transistor M8 are both electrically connected to the third connection node X3. The first terminal of the fourth P-type transistor M7 is electrically connected to the first power supply voltage signal line VGH. The first terminal of the fourth N-type transistor M8 is electrically connected to the second power supply voltage signal line VGL. The second terminals of the fourth P-type transistor M7 and the fourth N-type transistor M8 are both electrically connected to the second output terminal OUT2 of the first shift register 190a.

[0144] The gates of the fifth P-type transistor M9 and the fifth N-type transistor M10 are both electrically connected to the third connection node X3. The first terminal of the fifth P-type transistor M9 is electrically connected to the first positive voltage signal line VDD, and the first terminal of the fifth N-type transistor M10 is electrically connected to the first negative voltage signal line VF. The second terminals of the fifth P-type transistor M9 and the fifth N-type transistor M10 are both electrically connected to the first output terminal OUT1 of the first shift register 190a.

[0145] Thus, by simply adding six transistors, from the third P-type transistor M5 to the fifth N-type transistor M10, the same first shift register 190a can output the same or different amplitude scan signals and initialization signals to meet different driving requirements.

[0146] Figure 23 Another circuit diagram of the first shift register in the display panel provided in this application. (See diagram below.) Figure 23 As shown, with Figure 21 The illustrated embodiments and Figure 22 Unlike the illustrated embodiment, according to some other embodiments of this application, the first shift register 190a may optionally include a first output module 231, a second output module 232, a third output module 233, and a fourth output module 234.

[0147] The control terminal of the first output module 231 is electrically connected to the fourth connection node X4, the first terminal of the first output module 231 is electrically connected to the second power supply voltage signal line VGL, and the second terminal of the first output module 231 is electrically connected to the second output terminal OUT2 of the shift register 190a.

[0148] The control terminal of the second output module 232 is electrically connected to the fifth connection node X5, the first terminal of the second output module 232 is electrically connected to the first power supply voltage signal line VGH, and the second terminal of the second output module 232 is electrically connected to the second output terminal OUT2 of the shift register 190a.

[0149] The control terminal of the third output module 233 is electrically connected to the fourth connection node X4, the first terminal of the third output module 233 is electrically connected to the first negative voltage signal line VF, and the second terminal of the third output module 233 is electrically connected to the first output terminal OUT1 of the shift register 190a.

[0150] The control terminal of the fourth output module 234 is electrically connected to the fifth connection node X5, the first terminal of the fourth output module 234 is electrically connected to the first positive voltage signal line VDD, and the second terminal of the fourth output module 234 is electrically connected to the first output terminal OUT1 of the shift register 190a.

[0151] Taking the example that the enable level of the initialization signal and the enable level of the scan signal are both low, when the fourth connection node X4 is enabled and the fifth connection node X5 is disabled, the first output module 231 and the third output module 233 are turned on, and the second output module 232 and the fourth output module 234 are turned off. The first output module 231 transmits the low-level voltage signal of the second power supply voltage signal line VGL to the second output terminal OUT2 of the shift register 190a, and the third output module 233 transmits the low-level voltage signal of the first negative voltage signal line VF to the first output terminal OUT1 of the shift register 190a.

[0152] When the fourth connection node X4 is disabled and the fifth connection node X5 is enabled, the first output module 231 and the third output module 233 are turned off, and the second output module 232 and the fourth output module 234 are turned on. The second output module 232 transmits the high-level voltage signal of the first power supply voltage signal line VGH to the second output terminal OUT2 of the shift register 190a, and the fourth output module 234 transmits the high-level voltage signal of the first positive voltage signal line VDD to the first output terminal OUT1 of the shift register 190a.

[0153] As mentioned above, in some examples, VGH≥VDD>VF≥VGL. That is, the amplitude of the enable level of the initialization signal output by the first shift register 190a can be the same as or different from the amplitude of the enable level of the scan signal output by the first shift register 190a, and the amplitude of the disable level of the initialization signal output by the first shift register 190a can be the same as or different from the amplitude of the disable level of the scan signal output by the first shift register 190a.

[0154] In this way, by adding the first output module 231, the second output module 232, the third output module 233 and the fourth output module 234, the same first shift register 190a can output the same or different amplitude scan signals and initialization signals to meet different driving requirements.

[0155] Figure 24 Another circuit diagram of the first shift register in the display panel provided in this application. (See diagram below.) Figure 24As shown, in some specific embodiments, the first shift register 190a may optionally include a fourth connection node control module 235, a fifth connection node control module 236, and a sixth connection node control module 237.

[0156] The fourth connection node control module 235 is electrically connected to the second clock signal line CK, the input terminal IN of the first shift register, the first power supply voltage signal line VGH, the sixth connection node X6, and the fourth connection node X4. It is used to transmit the voltage of the input terminal IN of the first shift register to the fourth connection node X4 in response to the enable level of the second clock signal line CK.

[0157] The fifth connection node control module 236 is electrically connected to the first clock signal line XCK, the fourth connection node X4, the fifth connection node X5 and the first power supply voltage signal line VGH. It is used to transmit the voltage of the first power supply voltage signal line VGH to the fifth connection node X5 in response to the enable level of the fourth connection node X4, and to transmit the enable level of the first clock signal line XCK to the fifth connection node X5 in response to the enable level of the sixth connection node X6 and the first clock signal line XCK.

[0158] The sixth connection node control module 237 is electrically connected to the second clock signal line CK, the second power supply voltage signal line VGL, the fourth connection node X4, and the sixth connection node X6. It is used to transmit the voltage of the second power supply voltage signal line VGL to the sixth connection node X6 in response to the enable level of the second clock signal line CK, and to transmit the voltage of the second clock signal line CK to the sixth connection node X6 in response to the enable level of the fourth connection node X4.

[0159] Figure 25 This is yet another circuit diagram of the first shift register in the display panel provided in this application. (Combined with...) Figure 24 and Figure 25 As shown, in some specific embodiments, optionally, the first output module 231 may include a first transistor M1', the second output module 232 may include a second transistor M2', the third output module 233 may include a third transistor M3', and the fourth output module 234 may include a fourth transistor M4'. The fourth connection node control module 235 may include a seventh transistor M7' and an eighth transistor M8', the fifth connection node control module 236 may include a ninth transistor M9', a tenth transistor M10', and an eleventh transistor M11', and the sixth connection node control module 237 may include a thirteenth transistor M13' and at least two fourteenth transistors M14'. See [link to specific circuit structure] for details. Figure 25 As shown, this will not be elaborated further. Compared to a single transistor, by setting at least two fourteenth transistors in series, the voltage withstand capability of the transistor can be improved, which is beneficial to circuit stability.

[0160] As mentioned above, in some embodiments, the first shift register 190a can be electrically connected to the scan signal line S' connected to the pixel circuit of the current row, and can also be electrically connected to the initialization signal line vref connected to the pixel circuit of the next m rows. The inventors of this application further considered that, with the above-described circuit connection method, the initialization signal line vref connected to the pixel circuit of the first m rows would require an additional shift register to provide the initialization signal.

[0161] Figure 26 This is a circuit diagram of a first initialization signal output circuit in the display panel provided in this application. Figure 26 As shown, according to some embodiments of this application, optionally, the first initialization signal output circuit 190 may further include m second shift registers 190b, where m is a positive integer. In some examples, the second shift registers 190b may also be electrically connected to the clock signal terminals CK1' to CK3' of the pulse signal generator 191. The clock signal terminals CK1' to CK3' are used to provide clock signals to the second shift registers 190b. In some examples, each stage of the second shift register 190b may be electrically connected to two of the clock signal terminals CK1' to CK3', and adjacent second shift registers 190b may be connected to different clock signal terminals. The m second shift registers 190b are located on the side of the first-stage first shift register 190a away from the second-stage first shift register 190a. The output terminals of the m second shift registers 190b may be electrically connected one-to-one with m initialization signal lines vref, and the second shift registers 190b are used to provide initialization signals to the initialization signal lines vref.

[0162] In this way, by adding m second shift registers 190b, it can be ensured that the initialization signal line vref connected to the first m rows of pixel circuits can also transmit the initialization signal, so as to realize the initialization of the first m rows of pixel circuits.

[0163] It should be noted that the circuit structure of the second shift register 190b can be the same as that of the first shift register 190a, or it can be different. The second shift register 190b can be used only to output the initialization signal.

[0164] According to other embodiments of this application, optionally, the first initialization signal output circuit 190 may not reuse the scan drive circuit, that is, it may not output a scan signal. That is, the first initialization signal output circuit 190 may be a separately added circuit that outputs an initialization signal.

[0165] Figure 27 Another circuit diagram of the first shift register in the display panel provided in this application. (See diagram below.) Figure 27As shown, according to some embodiments of this application, optionally, the first shift register 190a may include a latch 2701 and a first NAND logic operation module 2702. The latch 2701 has its clock input electrically connected to the first clock signal line CK1, and its input IN is electrically connected to the output OUT of the latch in the upper-level first shift register 190a. The first input of the first NAND logic operation module 2702 is electrically connected to the output OUT of the latch, its second input is electrically connected to the second clock signal line CK2, and its output is the first output OUT1 of the first shift register 190a, which is electrically connected to the initialization signal line vref. The first level input terminal of the first NAND logic operation module 2702 can be electrically connected to the first positive voltage signal line VDD, and the second level input terminal of the first NAND logic operation module 2702 can be electrically connected to the first negative voltage signal line VF.

[0166] Latch 2701 is used to transmit and latch the signal input at its input terminal IN, and outputs a signal through its output terminal OUT. The signal output from latch 2701 OUT and the signal from the second clock signal line CK2 are then subjected to a NAND operation by the first NAND logic operation module 2702. This controls the first NAND logic operation module 2702 to output either a high level on the first positive voltage signal line VDD or a low level on the first negative voltage signal line VF, thus obtaining the initialization signal.

[0167] In some embodiments, Figure 21 and Figure 22 The circuit structure of the output module 200 shown is similar to Figure 27 The circuit structure shown is similar. The output module 200 may also include a latch and a first NAND logic operation module. The difference is that the first level input terminal of the first NAND logic operation module in the output module 200 is electrically connected to the first power supply voltage signal line VGH, and the second level input terminal of the first NAND logic operation module in the output module 200 may be electrically connected to the second power supply voltage signal line VGL.

[0168] Figure 28 This is yet another circuit diagram of the pixel circuit in the display panel provided in this application. (See diagram below.) Figure 28As shown, taking a 7T1C pixel circuit as an example, the pixel circuit 41 may include a driving module 601, a data writing module 602, a first initialization module 603, and a second initialization module 604. The driving module 601 may include a first transistor T1, the data writing module 602 may include a second transistor T2, the first initialization module 603 may include a third transistor T3, and the second initialization module 604 may include a fourth transistor T4. Furthermore, the pixel circuit 41 may also include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0169] The gate of the first transistor T1 is electrically connected to the first node N1, the first terminal of the first transistor T1 is electrically connected to the second node N2, and the second terminal of the first transistor T1 is electrically connected to the third node N3.

[0170] The gate of the second transistor T2 is electrically connected to the scan signal line S', the first terminal of the second transistor T2 is electrically connected to the data signal line data, and the second terminal of the second transistor T2 is electrically connected to the second node N2.

[0171] The gate of the third transistor T3 can be electrically connected to the initialization signal line vref, the first terminal of the third transistor T3 can be electrically connected to the initialization signal line vref, and the second terminal of the third transistor T3 can be electrically connected to the first node N1.

[0172] The gate of the fourth transistor T4 can be electrically connected to the initialization signal line vref, the first electrode of the fourth transistor T4 can be electrically connected to the initialization signal line vref, and the second electrode of the fourth transistor T4 can be electrically connected to the first electrode of the light-emitting element 42.

[0173] The gate of the fifth transistor T5 is electrically connected to the scan signal line S', the first terminal of the fifth transistor T5 is electrically connected to the first node N1, and the second terminal of the fifth transistor T5 is electrically connected to the third node N3.

[0174] The gate of the sixth transistor T6 is electrically connected to the light-emitting control signal line EM, the first terminal of the sixth transistor T6 is electrically connected to the positive power supply voltage signal line PVDD, and the second terminal of the sixth transistor T6 is electrically connected to the second node N2.

[0175] The gate of the seventh transistor T7 is electrically connected to the light-emitting control signal line EM, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the light-emitting element 42. The second electrode of the light-emitting element 42 is electrically connected to the negative power supply voltage signal line PVEE.

[0176] The first plate of the storage capacitor Cst is electrically connected to the positive power supply voltage signal line PVDD, and the second plate of the storage capacitor Cst is electrically connected to the first node N1.

[0177] The scan signal line S' can specifically be the first scan line S1 mentioned above. The scan signal line S' can be electrically connected to the second transistor T2 and / or the fifth transistor T5 to control data signal writing and / or threshold compensation.

[0178] It should be noted that the above-described pixel circuit structure is for illustrative purposes only and does not constitute a limitation of this application. In other embodiments, the pixel circuit may also be a 7T2C pixel circuit, an 8T1C pixel circuit, a 9T1C pixel circuit, or other types of pixel circuits.

[0179] Based on the display panel provided in the above embodiments, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 29 , Figure 29 A schematic diagram of the structure of the display device provided in this application. Figure 29 The provided display device 1000 includes the display panel 40 provided in any of the above embodiments of this application. Figure 29 The embodiment uses a mobile phone as an example to describe the display device 1000. It is understood that the display device provided in this application can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices. This application does not impose specific limitations on these. The display device provided in this application has the beneficial effects of the display panel 40 provided in this application. For details, please refer to the specific descriptions of the display panel 40 in the above embodiments. These descriptions will not be repeated here.

[0180] It should be understood that the specific structures of the display panel and circuits provided in the accompanying drawings are merely examples and are not intended to limit this application. Furthermore, the above embodiments provided in this application can be combined with each other unless there is contradiction.

[0181] It should be clarified that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. According to the embodiments described above, these embodiments do not exhaustively describe all details, nor do they limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

[0182] Those skilled in the art will understand that the above embodiments are exemplary and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, specification, and claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity refers to "one" but does not exclude multiple; the terms "first" and "second" are used to identify names and not to indicate any particular order. Any reference numerals in the claims should not be construed as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A display panel, characterized in that, include: A pixel circuit and a light-emitting element, wherein the pixel circuit is used to drive the light-emitting element to emit light; An initialization signal line is used to transmit an initialization signal, which includes an enable level and a disable level. The enable level of the initialization signal is used to initialize the target node of the pixel circuit. The initialization signal line extends along a first direction and includes a first initialization signal line and a second initialization signal line. The pixel circuit includes a first pixel circuit and a second pixel circuit. The first initialization signal line is electrically connected to the first pixel circuit, and the second initialization signal line is electrically connected to the second pixel circuit. The first pixel circuit and the second pixel circuit are arranged along a second direction, and the first direction intersects the second direction. A screen refresh cycle of the display panel includes a first stage, in which the first initialization signal line transmits an enable level to initialize the target node of the first pixel circuit, and the second initialization signal line transmits a disable level, so that the target node of the second pixel circuit is not initialized. The pixel circuit includes a driving module and a data writing module. The control terminal of the data writing module is electrically connected to the first scan line, and the first scan line transmits a scanning signal. A screen refresh cycle of the display panel includes a light-emitting cycle of at least one pixel circuit. A light-emitting cycle of the pixel circuit includes an initialization phase and a data writing phase. In the data writing phase, the data writing module provides a data signal to the driving module in response to the first scan signal. During the initialization phase of the first pixel circuit, the first initialization signal line transmits an enable level; during the data writing phase of the first pixel circuit, the first initialization signal line transmits an disable level.

2. The display panel according to claim 1, characterized in that, A screen refresh cycle of the display panel also includes a second stage, in which the first initialization signal line transmits a disabled level and the second initialization signal line transmits an enabled level.

3. The display panel according to claim 1, characterized in that, During the initialization phase corresponding to the second pixel circuit, the data writing module in the first pixel circuit responds to the first scanning signal by providing a data signal to the driving module, and the second initialization signal line provides the enable level of the initialization signal for initializing the target node of the second pixel circuit.

4. The display panel according to claim 3, characterized in that, One light emission cycle corresponding to the pixel circuit includes at least two initialization phases and at least two data writing phases, with the initialization phases and data writing phases arranged alternately.

5. The display panel according to claim 1, characterized in that, The display panel further includes a first light emission control signal line, which is electrically connected to the first pixel circuit. The pixel circuit further includes a third pixel circuit, which is arranged along the second direction with the first pixel circuit. The initialization signal line further includes a third initialization signal line, which is electrically connected to the third pixel circuit. A light-emitting cycle of the pixel circuit also includes a light-emitting phase. During the light-emitting phase of the first pixel circuit, the first light-emitting control signal line provides an enable level, and the third initialization signal line provides an enable level for the initialization signal, which is used to initialize the target node of the third pixel circuit.

6. The display panel according to claim 1, characterized in that, The pixel circuit includes: The drive module, wherein the control terminal of the drive module is electrically connected to the first node; A first initialization module, wherein the control terminal of the first initialization module is electrically connected to the initialization signal line, the first terminal of the first initialization module is electrically connected to the initialization signal line, and the second terminal of the first initialization module is electrically connected to the first node, the first initialization module is used to transmit the enable level of the initialization signal provided by the initialization signal line to the first node to initialize the first node.

7. The display panel according to claim 6, characterized in that, The display panel also includes a scan signal line and a reference voltage signal line, wherein the reference voltage signal line is used to provide a constant voltage signal; The pixel circuit also includes: The second initialization module has a control terminal electrically connected to the scan signal line, a first terminal electrically connected to the reference voltage signal line, and a second terminal electrically connected to the first electrode of the light-emitting element. The second initialization module is used to transmit the voltage signal provided by the reference voltage signal line to the first electrode of the light-emitting element to initialize the first electrode of the light-emitting element.

8. The display panel according to claim 6, characterized in that, The pixel circuit also includes: The second initialization module has a control terminal electrically connected to the initialization signal line, a first terminal electrically connected to the initialization signal line, and a second terminal electrically connected to the first electrode of the light-emitting element. The second initialization module is used to transmit the enable level of the initialization signal provided by the initialization signal line to the first electrode of the light-emitting element to initialize the first electrode of the light-emitting element.

9. The display panel according to claim 8, characterized in that, The control terminal of the first initialization module in the first pixel circuit and the control terminal of the second initialization module in the first pixel circuit are both electrically connected to the first initialization signal line; The control terminal of the first initialization module in the second pixel circuit and the control terminal of the second initialization module in the second pixel circuit are both electrically connected to the second initialization signal line.

10. The display panel according to claim 8, characterized in that, Along the second direction, the first pixel circuit and the second pixel circuit are separated by k pixel circuits, where k ≥ 0 and k is an integer; The control terminal of the first initialization module in the first pixel circuit is electrically connected to the first initialization signal line, and the control terminal of the second initialization module in the first pixel circuit is electrically connected to the second initialization signal line.

11. The display panel according to claim 10, characterized in that, The display panel includes a display area and a bonding area arranged along the second direction. The light-emitting element is located in the display area, and the bonding area is provided with bonding pads for electrical connection with a flexible circuit board or a driver chip. Along the second direction, the second pixel circuit is located on the side of the first pixel circuit closer to the bonding area, or the second pixel circuit is located on the side of the first pixel circuit farther from the bonding area.

12. The display panel according to claim 1, characterized in that, The display panel further includes a scan signal line extending along the first direction, the scan signal line being electrically connected to the pixel circuit, and the scan signal line being used to transmit scan signals; The scanning signal line includes a first scanning signal line and a second scanning signal line. The first scanning signal line is electrically connected to the first pixel circuit, and the second scanning signal line is electrically connected to the second pixel circuit. Along the second direction, the first pixel circuit and the second pixel circuit are adjacent, the phase of the pulse signal provided by the first scan signal line is the same as the phase of the pulse signal provided by the second initialization signal line, and the period of the pulse signal provided by the first scan signal line is the same as the period of the pulse signal provided by the second initialization signal line. Along the second direction, the first distance between the first scan signal line and the first initialization signal line is greater than the second distance between the first scan signal line and the second initialization signal line.

13. The display panel according to claim 1, characterized in that, The display panel further includes an initialization signal output circuit, which includes multiple cascaded first shift registers. The first output terminal of each first shift register is electrically connected to an initialization signal line, and the first output terminal is used to provide an initialization signal to the initialization signal line.

14. The display panel according to claim 13, characterized in that, The display panel also includes a scan signal line, which is electrically connected to the pixel circuit. The first shift register further includes a second output terminal, which is electrically connected to one of the scan signal lines and is used to provide a scan signal to the scan signal line.

15. The display panel according to claim 14, characterized in that, Along the second direction, the first pixel circuit and the second pixel circuit are separated by k pixel circuits, where k ≥ 0 and k is an integer; The scanning signal line includes a first scanning signal line and a second scanning signal line. The first scanning signal line is electrically connected to the first pixel circuit, and the second scanning signal line is electrically connected to the second pixel circuit. The first shift register includes a first target shift register, the first output terminal of the first target shift register is electrically connected to the first initialization signal line, and the second output terminal of the first target shift register is electrically connected to the second scan signal line.

16. The display panel according to claim 15, characterized in that, The first shift register includes a first inverter and a second inverter; The control terminal of the first inverter is electrically connected to the second output terminal of the first shift register, the first input terminal of the first inverter is electrically connected to the first power supply voltage signal line, the second input terminal of the first inverter is electrically connected to the second power supply voltage signal line, and the output terminal of the first inverter is electrically connected to the control terminal of the second inverter. The first input terminal of the second inverter is electrically connected to the first positive voltage signal line, the second input terminal of the second inverter is electrically connected to the first negative voltage signal line, and the output terminal of the second inverter is the first output terminal of the first shift register.

17. The display panel according to claim 16, characterized in that, The first inverter includes a first P-type transistor and a first N-type transistor, and the second inverter includes a second P-type transistor and a second N-type transistor; The gates of the first P-type transistor and the first N-type transistor are both electrically connected to the second output terminal of the first shift register. The first terminal of the first P-type transistor is electrically connected to the first power supply voltage signal line. The first terminal of the first N-type transistor is electrically connected to the second power supply voltage signal line. The second terminals of the first P-type transistor and the first N-type transistor are both electrically connected to the first connection node. The gates of the second P-type transistor and the second N-type transistor are both electrically connected to the first connection node. The first terminal of the second P-type transistor is electrically connected to the first positive voltage signal line, and the first terminal of the second N-type transistor is electrically connected to the first negative voltage signal line. The second terminals of the second P-type transistor and the second N-type transistor are both electrically connected to the first output terminal of the first shift register.

18. The display panel according to claim 15, characterized in that, The first shift register includes: The third inverter has its control terminal electrically connected to the second connection node, its first input terminal electrically connected to the first power supply voltage signal line, and its second input terminal electrically connected to the second power supply voltage signal line. The fourth inverter has its control terminal electrically connected to the output terminal of the third inverter, its first input terminal electrically connected to the first power supply voltage signal line, its second input terminal electrically connected to the second power supply voltage signal line, and its output terminal being the second output terminal of the first shift register. The second output terminal of the first shift register is electrically connected to a scan signal line, which is used to provide a scan signal to the pixel circuit through the scan signal line. The fifth inverter has its control terminal electrically connected to the output terminal of the third inverter, its first input terminal electrically connected to the first positive voltage signal line, its second input terminal electrically connected to the first negative voltage signal line, and its output terminal being the first output terminal of the first shift register.

19. The display panel according to claim 18, characterized in that, The third inverter includes a third P-type transistor and a third N-type transistor, the fourth inverter includes a fourth P-type transistor and a fourth N-type transistor, and the fifth inverter includes a fifth P-type transistor and a fifth N-type transistor; The gate of the third P-type transistor and the gate of the third N-type transistor are both electrically connected to the second connection node. The first terminal of the third P-type transistor is electrically connected to the first power supply voltage signal line. The first terminal of the third N-type transistor is electrically connected to the second power supply voltage signal line. The second terminals of the third P-type transistor and the second terminals of the third N-type transistor are both electrically connected to the third connection node. The gate of the fourth P-type transistor and the gate of the fourth N-type transistor are both electrically connected to the third connection node. The first terminal of the fourth P-type transistor is electrically connected to the first power supply voltage signal line. The first terminal of the fourth N-type transistor is electrically connected to the second power supply voltage signal line. The second terminals of the fourth P-type transistor and the fourth N-type transistor are both electrically connected to the second output terminal of the first shift register. The gates of the fifth P-type transistor and the fifth N-type transistor are both electrically connected to the third connection node. The first terminal of the fifth P-type transistor is electrically connected to the first positive voltage signal line, and the first terminal of the fifth N-type transistor is electrically connected to the first negative voltage signal line. The second terminals of the fifth P-type transistor and the fifth N-type transistor are both electrically connected to the first output terminal of the first shift register.

20. The display panel according to claim 15, characterized in that, The first shift register includes: The first output module has its control terminal electrically connected to the fourth connection node, its first terminal electrically connected to the second power supply voltage signal line, and its second terminal electrically connected to the second output terminal of the shift register. The second output module has its control terminal electrically connected to the fifth connection node, its first terminal electrically connected to the first power supply voltage signal line, and its second terminal electrically connected to the second output terminal of the shift register. The third output module has its control terminal electrically connected to the fourth connection node, its first terminal electrically connected to the first negative voltage signal line, and its second terminal electrically connected to the first output terminal of the shift register. The fourth output module has its control terminal electrically connected to the fifth connection node, its first terminal electrically connected to the first positive voltage signal line, and its second terminal electrically connected to the first output terminal of the shift register.

21. The display panel according to claim 20, characterized in that, The first shift register also includes: The fourth connection node control module is electrically connected to the second clock signal line, the input terminal of the first shift register, the first power supply voltage signal line, the sixth connection node, and the fourth connection node. It is used to transmit the voltage at the input terminal of the first shift register to the fourth connection node in response to the enable level of the second clock signal line. The fifth connection node control module is electrically connected to the first clock signal line, the fourth connection node, the fifth connection node and the first power supply voltage signal line. It is used to transmit the voltage of the first power supply voltage signal line to the fifth connection node in response to the enable level of the fourth connection node, and to transmit the enable level of the first clock signal line to the fifth connection node in response to the enable level of the sixth connection node and the first clock signal line. The sixth connection node control module is electrically connected to the second clock signal line, the second power supply voltage signal line, the fourth connection node, and the sixth connection node. It is used to transmit the voltage of the second power supply voltage signal line to the sixth connection node in response to the enable level of the second clock signal line, and to transmit the voltage of the second clock signal line to the sixth connection node in response to the enable level of the fourth connection node.

22. The display panel according to claim 13, characterized in that, The first shift register includes: A latch, wherein the clock input terminal of the latch is electrically connected to the first clock signal line, and the input terminal of the latch is electrically connected to the output terminal of the latch in the first shift register above it; The first NAND logic operation module has its first input terminal electrically connected to the output terminal of the latch, its second input terminal electrically connected to the second clock signal line, and its output terminal being the first output terminal of the shift register, which is electrically connected to the first initialization signal line.

23. The display panel according to claim 14, characterized in that, The first initialization signal output circuit further includes m second shift registers, where m is a positive integer. The m second shift registers are located on the side of the first-stage first shift register away from the second-stage first shift register. The output terminals of the m second shift registers are electrically connected to the m initialization signal lines one by one. The second shift registers are used to provide initialization signals to the initialization signal lines.

24. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 23.

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