Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate, the substrate comprises a semiconductor substrate and an epitaxial layer on the surface of the semiconductor substrate, and the epitaxial layer comprises a gate region for forming a trench gate structure; a mask layer is on the surface of the epitaxial layer and covers the gate region, and the material of the mask layer is a semiconductor material; and a shielding structure is in the epitaxial layer on both sides of the gate region, and the length of the gate region is less than the length of the shielding structure. The application provides a semiconductor structure and a forming method thereof. The shielding structure is formed on both sides of the trench gate structure, the electric field control ability of the edge at the bottom of the trench gate structure in the silicon carbide MOSFET with the trench gate structure is improved, and the process efficiency is improved. In addition, the semiconductor material is used as the mask in the ion implantation process, the ion implantation quality is improved, the quality of the shielding structure is improved, and the device performance and the device reliability are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In a silicon carbide MOSFET with a trench gate structure, the electric field control of the bottom edge of the trench gate structure is one of the factors affecting the reliability of the gate insulating layer. In order to control the electric field, in some processes, a trench isolation structure is formed on both sides of the trench gate structure and ion implantation is performed at the bottom of the trench isolation structure to form a doped region. The doped region at the bottom of the trench isolation structure is deeper than the trench gate structure.

[0003] However, the formation of the trench isolation structure and the doped region requires additional trench etching and multiple ion implantations, which is low in process efficiency and cannot guarantee the electric field control capability, and the device reliability is low.

[0004] Therefore, it is necessary to provide a more effective and reliable technical solution to improve the process efficiency and the electric field control capability. SUMMARY

[0005] The present application provides a semiconductor structure and a forming method thereof, which can improve the electric field control capability of the bottom edge of the trench gate structure and the process efficiency in a silicon carbide MOSFET with a trench gate structure.

[0006] One aspect of the present application provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate comprising a semiconductor substrate and an epitaxial layer on the surface of the semiconductor substrate, the epitaxial layer comprising a gate region for forming a trench gate structure; forming a mask layer covering the gate region on the surface of the epitaxial layer, the material of the mask layer being a semiconductor material; forming a shielding structure in the epitaxial layer on both sides of the gate region by ion implantation process with the mask layer as a mask, the length of the gate region being less than the length of the shielding structure.

[0007] In some embodiments of the present application, the semiconductor material comprises germanium-doped polysilicon, silicon carbide, amorphous silicon carbide or SiGeC.

[0008] In some embodiments of the present application, the method of forming the mask layer comprises a chemical vapor deposition process or a sputtering process.

[0009] In some embodiments of the present application, the thickness of the mask layer is 5 microns to 10 microns.

[0010] In some embodiments of the present application, the material of the epitaxial layer is 4H-SiC, the upper surface of the epitaxial layer is a silicon surface, and the angle between the silicon surface and the horizontal plane is 0 to 4 degrees.

[0011] In some embodiments of the application, the angle between the ion implantation angle and the normal of the silicon surface is between -0.5 degrees and 5 degrees; the implanting ions of the ion implantation process are aluminum ions; the implanting energy of the ion implantation process is between 500 keV and 50 MeV; the implanting depth of the ion implantation process is between 2 microns and 15 microns; the implanting concentration of the ion implantation process is between 5E15 atom / cm 3 and 1E17 atom / cm 3 ; the temperature of the ion implantation process is between 100 degrees Celsius and 1200 degrees Celsius.

[0012] In some embodiments of the application, the method for forming the semiconductor structure further comprises: forming a trench gate structure in the gate region, the depth of the shielding structure being greater than the depth of the trench gate structure.

[0013] In some embodiments of the application, the shielding structure penetrates the epitaxial layer.

[0014] Another aspect of the application also provides a semiconductor structure, comprising: a substrate, the substrate comprising a semiconductor substrate and an epitaxial layer on the surface of the semiconductor substrate, the epitaxial layer comprising a gate region for forming a trench gate structure; a mask layer on the surface of the epitaxial layer covering the gate region, the material of the mask layer being a semiconductor material; a shielding structure in the epitaxial layer on both sides of the gate region, the length of the gate region being less than the length of the shielding structure.

[0015] In some embodiments of the application, the semiconductor material comprises germanium-doped polysilicon, silicon carbide, amorphous silicon carbide or SiGeC.

[0016] In some embodiments of the application, the thickness of the mask layer is between 5 microns and 10 microns.

[0017] In some embodiments of the application, the material of the epitaxial layer is 4H-SiC, the upper surface of the epitaxial layer is a silicon surface, and the angle between the silicon surface and the horizontal plane is between 0 degrees and 4 degrees.

[0018] In some embodiments of the application, the shielding structure has implanting ions, the implanting ions being aluminum ions; the concentration of the implanting ions is between 5E15 atom / cm 3 and 1E17 atom / cm 3 .

[0019] In some embodiments of the application, the semiconductor structure further comprises: a trench gate structure in the epitaxial layer of the gate region, the depth of the shielding structure being greater than the depth of the trench gate structure.

[0020] In some embodiments of the present application, the shielding structure penetrates through the epitaxial layer.

[0021] The present application provides a semiconductor structure and a forming method thereof. The shielding structure is formed on both sides of the trench gate structure, which can improve the electric field control ability of the bottom edge of the trench gate structure in the silicon carbide MOSFET with the trench gate structure and the process efficiency. In addition, the semiconductor material is used as a mask in the ion implantation process, which can improve the ion implantation quality and the overall process efficiency, improve the quality of the shielding structure, improve the device performance and the device reliability. BRIEF DESCRIPTION OF DRAWINGS

[0022] The following drawings in detail describe the exemplary embodiments disclosed in the present application. The same reference signs in the several views of the drawings represent similar structures. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application, and other embodiments can also achieve the same purpose of the invention in the present application. It should be understood that the drawings are not drawn to scale.

[0023] wherein:

[0024] Figures 1 to 8 The structure schematic diagram of each step in the forming method of the semiconductor structure described in the embodiments of the present application is shown. DETAILED DESCRIPTION

[0025] The following description provides specific application scenarios and requirements of the present application, which is to enable those skilled in the art to manufacture and use the content in the present application. Various local modifications of the disclosed embodiments are obvious to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the shown embodiments, but is consistent with the widest scope of the claims.

[0026] The technical solutions of the present application will be described in detail below in combination with embodiments and drawings.

[0027] Figures 1 to 8 The structure schematic diagram of each step in the forming method of the semiconductor structure described in the embodiments of the present application is shown. The forming method of the semiconductor structure described in the embodiments of the present application will be described in detail below in combination with the drawings.

[0028] Reference Figure 1 and Figure 2 are shown, wherein, Figure 1 is a top view, Figure 2 is a cross-sectional view along Figure 1A longitudinal cross-sectional view made by the dashed line XX. A substrate 100 is provided, the substrate 100 including a semiconductor substrate 101 and an epitaxial layer 102 located on the surface of the semiconductor substrate 101, the epitaxial layer 102 including a gate region 103 for forming a trench gate structure.

[0029] In some embodiments of this application, the semiconductor structure described in the embodiments of this application is, for example, a silicon carbide MOSFET with a trench gate structure.

[0030] In some embodiments of this application, the semiconductor substrate 101 is a silicon carbide substrate, and the material of the semiconductor substrate 101 is silicon carbide. The material of the epitaxial layer 102 is also silicon carbide.

[0031] In some embodiments of this application, the epitaxial layer 102 is made of 4H-SiC, and its upper surface is a silicon plane with an angle of 0 to 4 degrees relative to the horizontal plane. Various polycrystalline types of silicon carbide exist, the most common being 3C-SiC with a cubic crystal structure, and 4H-SiC and 6H-SiC with hexagonal crystal structures. Single-crystal SiC can be oriented and polished to present a main crystal plane as its surface, such as the (0001) plane, i.e., the silicon plane, with silicon as the surface. The silicon plane can be staggered so that the angle between the silicon plane and the horizontal plane is 0 to 4 degrees, for example, 1 degree, 2 degrees, or 3 degrees.

[0032] refer to Figure 3 and Figure 4 As shown, where, Figure 3 This is a top view. Figure 4 For along Figure 3 The longitudinal cross-section shown by the dashed line XX. A mask layer 110 is formed on the surface of the epitaxial layer 102, covering the gate region 103. The material of the mask layer 110 is a semiconductor material.

[0033] refer to Figure 3 As shown, the mask layer 110 also covers the area above and below the gate region 103. "Above" and "below" refer to the positions based on... Figure 3 The orientation of the structure shown.

[0034] In some embodiments of this application, the semiconductor material includes germanium-doped polycrystalline silicon, silicon carbide, amorphous silicon carbide, or SiGeC. In the germanium-doped polycrystalline silicon, the molar ratio of silicon atoms to germanium atoms is (99-50):(1-50), meaning that the number of silicon atoms accounts for 50% to 99% of the total number of silicon and germanium atoms; and the number of germanium atoms accounts for 1% to 50% of the total number of silicon and germanium atoms. In the SiGeC, the molar ratio of silicon atoms, germanium atoms, and carbon atoms is (99-50):(1-48):(1-48), meaning that the number of silicon atoms accounts for 50% to 99% of the total number of silicon, germanium, and carbon atoms; the number of germanium atoms accounts for 1% to 48% of the total number of silicon, germanium, and carbon atoms; and the number of carbon atoms accounts for 1% to 48% of the total number of silicon, germanium, and carbon atoms. The mask layer 110 serves to protect the gate region 103 from damage or doping during subsequent ion implantation processes. However, currently used mask layer materials are generally silicon oxide or silicon nitride, which offer insufficient protection when ion implantation energy is high and ion implantation depth is deep. Furthermore, silicon oxide and silicon nitride deposition rates are slow, and deposition process conditions are demanding, such as deposition temperatures exceeding 1000 degrees Celsius. This application uses the aforementioned semiconductor materials as the mask layer, which improves the protective effect of the mask layer, increases the mask layer deposition rate, reduces mask layer formation conditions, and improves process efficiency.

[0035] Specifically, in the process of depositing SiGe, the gas source is SiH4 or SiH2Cl2,GeH4; the carrier gas is N2 or Ar or He; the pressure is 80 to 600 Torr; the temperature is 500 to 1000 degrees Celsius; and the deposition rate is 0.5 to 1 micrometer / minute.

[0036] In the process of depositing SiGeC, the gas source is SiH4 or SiH2Cl2, GeH4, C3H8; the carrier gas is N2 or Ar or He; the pressure is 80 to 600 Torr; the temperature is 500 to 1000 degrees Celsius; and the deposition rate is 0.5 to 1 micrometer / minute.

[0037] In some embodiments of this application, the method for forming the mask layer 110 includes a chemical vapor deposition process or a sputtering process.

[0038] The chemical vapor deposition (CVD) process can still achieve rapid growth at low temperatures (below 1000 degrees Celsius). For example, taking germanium-doped polysilicon as the semiconductor material, the doping with germanium impurities is particularly beneficial for increasing the deposition rate. Germanium-doped polysilicon provides a localized effect of hydrogen diffusion from silicon to the germanium surface phase. Hydrogen is released from the GeH intermediate. Experiments show that doping with germanium in the polysilicon layer can significantly improve the deposition rate at low temperatures. More specifically, the hydrogen released from the germanium-covered surface, influenced by the presence of impurities, increases the CVD deposition rate. Adjusting the molar ratio of silicon to germanium atoms in the germanium-doped polysilicon can regulate the deposition rate. Polysilicon typically exhibits a columnar crystal structure with vertical boundaries. For ion-implanted hard masks, vertical boundaries are unfavorable because ions can be introduced along them; doping with additional Ge or C further reduces the number of vertical boundaries in the random structure of the polysilicon.

[0039] The sputtering process can be single-target sputtering of SiGe or dual-target sputtering of Si and Ge.

[0040] In some embodiments of this application, the thickness of the mask layer 110 is 5 micrometers to 10 micrometers. Increasing the thickness of the mask layer 110 can also increase its protective capability.

[0041] refer to Figure 5 and Figure 6 As shown, where, Figure 5 This is a top view. Figure 6 For along Figure 5 The longitudinal cross-sectional view is shown by the dashed line XX. Using the mask layer 110 as a mask, an ion implantation process is employed to form a shielding structure 120 in the epitaxial layers 102 on both sides of the gate region 103. The length of the gate region 103 is less than the length of the shielding structure 120. Here, the length refers to... Figure 5 The vertical dimension.

[0042] In some embodiments of this application, the shielding structure 120 extends through the epitaxial layer 102 to the surface of the semiconductor substrate 101.

[0043] In some embodiments of this application, the implantation angle of the ion implantation process is between -0.5 degrees and 5 degrees with the normal to the silicon surface; the implanted ions are p-type, such as aluminum ions; the implantation energy is between 500 keV and 50 MeV; the implantation depth is between 2 micrometers and 15 micrometers; and the implantation concentration is 5E15 atom / cm³. 3 Up to 1E17atom / cm 3 The temperature of the ion implantation process is between 100 degrees Celsius and 1200 degrees Celsius.

[0044] Due to the protection of the mask layer 110, even if the ion implantation process has a high implantation energy and a deep implantation depth, and even if ion implantation can be performed multiple times, the gate region 103 will not be damaged or doped by the ion implantation process.

[0045] refer to Figure 7 and Figure 8 As shown, where, Figure 7 This is a top view. Figure 8 For along Figure 7 The longitudinal cross-section is shown by the dashed line XX. A trench gate structure 130 is formed in the gate region 103, and the depth of the shielding structure 120 is greater than the depth of the trench gate structure 130. The gate region 103 can be entirely formed as the trench gate structure 130, allowing the trench gate structure 130 to directly contact the shielding structure 120. Alternatively, the gate region 103 can be partially formed as the trench gate structure 130, such as... Figure 7 and Figure 8 As shown, the trench gate structure 130 and the shielding structure 120 are separated by the epitaxial layer 102 and do not directly contact each other.

[0046] In some embodiments of this application, the method of forming the semiconductor structure may further include: forming a contact structure electrically connected to the shielding structure 120 on the shielding structure 120, and connecting the voltage through the contact structure to enable the shielding structure 120 to be connected to the voltage, thereby improving its electric field control capability.

[0047] In some embodiments of this application, the semiconductor structure described herein can also be a silicon carbide device with a planar MOSFET structure. In this case, the gate region is located above the epitaxial layer, and the shielding structure is located in the epitaxial layers on both sides of the gate region.

[0048] This application provides a method for forming a semiconductor structure, in which a shielding structure is formed on both sides of a trench gate structure. This method can improve the electric field control capability and process efficiency of the bottom edge of the trench gate structure in a silicon carbide MOSFET with a trench gate structure. In addition, using a semiconductor material as a mask during the ion implantation process can improve the ion implantation quality and overall process efficiency, improve the quality of the shielding structure, and improve device performance and device reliability.

[0049] refer to Figure 5 and Figure 6 As shown, where, Figure 5 This is a top view. Figure 6 For along Figure 5A longitudinal cross-sectional view taken along the center dotted line X-X. Embodiments of the present application also provide a semiconductor structure, comprising: a substrate 100, which comprises a semiconductor substrate 101 and an epitaxial layer 102 on the surface of the semiconductor substrate 101, wherein the epitaxial layer 102 comprises a gate region 103 for forming a trench gate structure; a mask layer 110 on the surface of the epitaxial layer 102 covering the gate region 103, wherein the material of the mask layer 110 is a semiconductor material; a shielding structure 120 in the epitaxial layer 102 on both sides of the gate region 103, wherein the length of the gate region 103 is less than the length of the shielding structure 120. Herein, the length refers to Figure 5 the dimension in the vertical direction.

[0050] In some embodiments of the present application, the semiconductor structure described in the embodiments of the present application is, for example, a silicon carbide MOSFET with a trench gate structure.

[0051] In some embodiments of the present application, the semiconductor substrate 101 is a silicon carbide substrate, and the material of the semiconductor substrate 101 is silicon carbide. The material of the epitaxial layer 102 is also silicon carbide.

[0052] In some embodiments of the present application, the material of the epitaxial layer 102 is 4H-SiC, and the upper surface of the epitaxial layer 102 is a silicon face, which has an angle of 0-4 degrees with the horizontal plane. There are various polytypes of silicon carbide, the most common of which are, for example, 3C-SiC with cubic crystal structure, 4H-SiC and 6H-SiC with hexagonal crystal structure, etc. Single crystal SiC can be oriented and polished to present a main crystal face as its surface, for example, (0001) face, i.e. silicon face, with silicon as the surface. The silicon face can be miscut so that the angle of the silicon face with the horizontal plane is 0-4 degrees, for example, 1 degree, 2 degrees or 3 degrees, etc.

[0053] Reference Figure 3 As shown, the mask layer 110 also covers the positions above and below the gate region 103. The above and below refer to the orientation of the structure shown. Figure 3 As shown, the mask layer 110 also covers the positions above and below the gate region 103. The above and below refer to the orientation of the structure shown.

[0054] In some embodiments of the present application, the semiconductor material includes germanium-doped polysilicon, silicon carbide, amorphous silicon carbide, or SiGeC, wherein the molar ratio of silicon atoms to germanium atoms in the germanium-doped polysilicon is (99-50):(1-50), i.e., the number of moles of silicon atoms accounts for 50% to 99% of the total number of moles of silicon atoms and germanium atoms; i.e., the number of moles of germanium atoms accounts for 1% to 50% of the total number of moles of silicon atoms and germanium atoms. In SiGeC, the molar ratio of silicon atoms, germanium atoms, and carbon atoms is (99-50):(1-48):(1-48), i.e., the number of moles of silicon atoms accounts for 50% to 99% of the total number of moles of silicon atoms, germanium atoms, and carbon atoms; i.e., the number of moles of germanium atoms accounts for 1% to 48% of the total number of moles of silicon atoms, germanium atoms, and carbon atoms; i.e., the number of moles of carbon atoms accounts for 1% to 48% of the total number of moles of silicon atoms, germanium atoms, and carbon atoms. The mask layer 110 serves to protect the gate region 103 from damage or doping in subsequent ion implantation processes. However, the mask layer materials currently used are generally silicon oxide or silicon nitride, which have insufficient protection effect in the case of large ion implantation energy and deep ion implantation depth. Moreover, the deposition rate of silicon oxide and silicon nitride is slow, and the deposition process conditions are high, for example, the temperature requirement is higher than 1000 degrees Celsius. The semiconductor material described above is used as the mask layer in the present application, which can improve the protection effect of the mask layer, increase the deposition rate of the mask layer, reduce the formation conditions of the mask layer, and improve the process efficiency.

[0055] In some embodiments of the present application, the thickness of the mask layer 110 is 5 microns to 10 microns. Increasing the thickness of the mask layer 110 can also increase the protection capability of the mask layer 110.

[0056] In some embodiments of the present application, the shielding structure 120 penetrates the epitaxial layer 102 to the surface of the semiconductor substrate 101.

[0057] In some embodiments of the present application, the shielding structure 120 has implanted ions therein, and the implanted ions are P-type, for example, aluminum ions; the concentration of the implanted ions is 5E15 atom / cm 3 to 1E17 atom / cm 3 .

[0058] Referring to Figure 7 and Figure 8 , wherein, Figure 7 is a top view, Figure 8 is a cross-sectional view along Figure 7FIG. 6 is a longitudinal sectional view taken along the center dotted line X-X. In some embodiments of the present application, the semiconductor structure further comprises a trench gate structure 130 in the epitaxial layer 102 of the gate region 103, and the depth of the shielding structure 120 is greater than the depth of the trench gate structure 130. In some embodiments of the present application, the gate region 103 can be entirely formed of the trench gate structure 130, so that the trench gate structure 130 directly contacts the shielding structure 120. Figure 7 and Figure 8 In some embodiments of the present application, the gate region 103 can be partially formed of the trench gate structure 130, so that the trench gate structure 130 is separated from the shielding structure 120 by the epitaxial layer 102 and does not directly contact the shielding structure 120.

[0059] In some embodiments of the present application, the semiconductor structure can further comprise a contact structure electrically connected to the shielding structure 120, so that the shielding structure 120 is connected to a voltage through the contact structure, thereby improving the electric field control capability of the shielding structure 120.

[0060] In some embodiments of the present application, the semiconductor structure described in the present application can also be a silicon carbide device of a planar MOSFET structure. In this case, the gate region is located above the epitaxial layer, and the shielding structure is located in the epitaxial layer on both sides of the gate region.

[0061] The present application provides a semiconductor structure and a forming method thereof. The shielding structure is formed on both sides of the trench gate structure, which can improve the electric field control capability of the bottom edge of the trench gate structure in a silicon carbide MOSFET having the trench gate structure and the process efficiency. In addition, the semiconductor material is used as a mask during the ion implantation process, which can improve the ion implantation quality and the overall process efficiency, improve the quality of the shielding structure, and improve the device performance and the device reliability.

[0062] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing content of the present application can be presented only in an exemplary manner and can not be limiting. Although not explicitly stated herein, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of the present application.

[0063] It should be understood that the term "and / or" used in the embodiments of the present application includes any or all combinations of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be an intermediate element.

[0064] Similarly, it will be understood that, when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, the term "directly on" means that there are no intervening elements present. It will also be understood that, when an element or layer is referred to as being "on" or extending "onto" another element or layer, it can be directly on or extend directly onto the other element or layer or intervening elements can also be present. In addition, it will be understood that the term "extends" or "extending" means to cover an area of or to extend in length or in width over, an area of the other element or layer.

[0065] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements or regions, these elements or regions should not be limited by these terms. These terms are only used to distinguish one element or region from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present application. The same reference numerals or same reference designators denote the same elements throughout the specification.

[0066] In addition, the specification of the present application describes example embodiments by reference to idealized illustrative cross-sectional and / or plan and / or elevation views. Consequently, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, the example embodiments should not be construed as limited to the precise shapes and regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the example embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a semiconductor substrate and an epitaxial layer located on the surface of the semiconductor substrate, the epitaxial layer including a gate region for forming a trench gate structure; A mask layer covering the gate region is formed on the surface of the epitaxial layer. The material of the mask layer is a semiconductor material, including germanium-doped polycrystalline silicon or SiGeC. Using the mask layer as a mask, an ion implantation process is used to form a shielding structure in the epitaxial layers on both sides of the gate region, wherein the length of the gate region is less than the length of the shielding structure. A trench gate structure is formed in the gate region, and the trench gate structure extends along the length direction of the shielding structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The methods for forming the mask layer include chemical vapor deposition or sputtering processes.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the mask layer is 5 micrometers to 10 micrometers.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The epitaxial layer is made of 4H-SiC, and the upper surface of the epitaxial layer is a silicon surface with an angle of 0 to 4 degrees between the silicon surface and the horizontal plane.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The implantation angle of the ion implantation process is between -0.5 degrees and 5 degrees with the normal to the silicon surface; the implanted ions are aluminum ions; the implantation energy is between 500 keV and 50 MeV; the implantation depth is between 2 micrometers and 15 micrometers; and the implantation concentration is 5E15 atom / cm³. 3 Up to 1E17atom / cm 3 The temperature of the ion implantation process is between 100 degrees Celsius and 1200 degrees Celsius.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The depth of the shielding structure is greater than the depth of the trench gate structure.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The shielding structure penetrates the epitaxial layer.

8. A semiconductor structure, characterized in that, include: The substrate includes a semiconductor substrate and an epitaxial layer located on the surface of the semiconductor substrate, the epitaxial layer including a gate region for forming a trench gate structure; A mask layer is located on the surface of the epitaxial layer and covers the gate region. The material of the mask layer is a semiconductor material, including germanium-doped polycrystalline silicon or SiGeC. A shielding structure is located in the epitaxial layer on both sides of the gate region, wherein the length of the gate region is less than the length of the shielding structure. A trench gate structure is located in the gate region, and the trench gate structure extends along the length direction of the shielding structure.

9. The semiconductor structure as described in claim 8, characterized in that, The thickness of the mask layer is 5 micrometers to 10 micrometers.

10. The semiconductor structure as described in claim 8, characterized in that, The epitaxial layer is made of 4H-SiC, and the upper surface of the epitaxial layer is a silicon surface with an angle of 0 to 4 degrees between the silicon surface and the horizontal plane.

11. The semiconductor structure as described in claim 8, characterized in that, The shielding structure contains implanted ions, specifically aluminum ions; the concentration of the implanted ions is 5E15 atom / cm³. 3 Up to 1E17atom / cm 3 .

12. The semiconductor structure as described in claim 8, characterized in that, The depth of the shielding structure is greater than the depth of the trench gate structure.

13. The semiconductor structure as described in claim 12, characterized in that, The shielding structure penetrates the epitaxial layer.

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