A semiconductor structure and a manufacturing method thereof

Abstract

Embodiments of the present disclosure disclose a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate having a first pad; an interposer located on the substrate, and a bottom surface of the interposer covering the first pad; wherein the interposer includes a second pad and a connection structure; the second pad is located on any surface of the interposer other than the bottom surface; one end of the connection structure is connected to the first pad, and the other end of the connection structure is connected to the second pad.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] A semiconductor structure includes a substrate and one or more chips located on the substrate. A solder pad is provided on the surface of the substrate, and the chip is electrically connected to the solder pad on the surface of the substrate through a bonding wire.

[0003] However, as semiconductor structures develop towards smaller sizes and higher integration levels, the arrangement density of the solder pads on the surface of the substrate is increasing, and short circuits are likely to occur between adjacent solder pads and adjacent bonding wires, affecting the reliability of the semiconductor structure. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor structure, including:

[0005] A substrate having a first solder pad;

[0006] An interposer located on the substrate, and the bottom surface of the interposer covers the first solder pad; wherein, the interposer includes a second solder pad and a connection structure; the second solder pad is located on any surface of the interposer except the bottom surface; one end of the connection structure is connected to the first solder pad, and the other end of the connection structure is connected to the second solder pad.

[0007] In some embodiments, the interposer further includes: a sealing layer, the bottom of the sealing layer covers the first solder pad, and the second solder pad is located on the side surface of the sealing layer.

[0008] In some embodiments, the connection structure is located within the sealing layer.

[0009] In some embodiments, the second solder pad includes a plurality of second sub-solder pad groups with different heights, and each of the second sub-solder pad groups includes a plurality of second sub-solder pads arranged and distributed in a first direction.

[0010] In some embodiments, the first solder pad includes one or more first sub-solder pad groups, and each of the first sub-solder pad groups includes a plurality of first sub-solder pads arranged and distributed in a first direction.

[0011] In some embodiments, the distance between two adjacent first sub-solder pads in the first direction in the first sub-solder pad group is less than the distance between two adjacent second sub-solder pads in the first direction in the second sub-solder pad group.

[0012] In some embodiments, the connection structure includes a plurality of sub-connection structures; wherein, the sub-connection structures have different heights.

[0013] In some embodiments, the connection structure includes a plurality of sub - connection structures arranged and distributed along a first direction; wherein, two adjacent sub - connection structures have different heights.

[0014] In some embodiments, the sub - connection structure includes a first connection sub - part and a second connection sub - part that extend in different directions and are connected to each other; the first connection sub - part is connected to the first pad, and the second connection sub - part is connected to the second pad.

[0015] In some embodiments, the extending direction of the first connection sub - part is perpendicular to the substrate, and the extending direction of the second connection sub - part is parallel to the substrate.

[0016] In some embodiments, the semiconductor structure further includes: one or more chips disposed on the substrate, pads are provided on the surface of the chips, and the pads are electrically connected to the second sub - pad group through bonding wires.

[0017] In some embodiments, among the plurality of chips, there are two stacked chips, and among the plurality of second sub - pad groups, there are two second sub - pad groups with different heights; wherein, the chip located above among the two chips is electrically connected to the second sub - pad group located above among the two second sub - pad groups, and the chip located below among the two chips is electrically connected to the second sub - pad group located below among the two second sub - pad groups.

[0018] In some embodiments, the semiconductor structure further includes: a packaging layer that at least covers the chips and the interposer.

[0019] In some embodiments, the number of the interposers is multiple, and the multiple interposers are arranged around the one or more chips.

[0020] Embodiments of the present disclosure further provide a manufacturing method of a semiconductor structure, including:

[0021] Providing a substrate, the surface of the substrate has a first pad;

[0022] Forming an interposer on the substrate, including: forming a connection structure and a second pad, the second pad is located on any surface of the interposer except the bottom surface;

[0023] One end of the connection structure is connected to the first pad, and the other end of the connection structure is connected to the second pad.

[0024] In some embodiments, when forming an interposer on the substrate, it further includes: forming a sealing layer on the substrate, the sealing layer covers the connection structure and makes the second pad located on the side surface of the sealing layer.

[0025] In some embodiments, forming a connection structure and a second pad includes:

[0026] Forming a sacrificial layer on the substrate, the sacrificial layer covering the first pad;

[0027] Etching the sacrificial layer to form a groove in the sacrificial layer;

[0028] Filling a conductive material in the groove to form the connection structure and the second pad;

[0029] Removing the sacrificial layer.

[0030] In some embodiments, the groove includes a plurality of sub-grooves uniformly arranged and distributed in a first direction, and each sub-groove includes a first groove sub-part, a second groove sub-part, and a third groove sub-part that are sequentially connected; etching the sacrificial layer includes: etching downward from the top surface of the sacrificial layer to form the first groove sub-part, the first groove sub-part exposing the first pad;

[0031] Etching downward from the top surface of the sacrificial layer to form the second groove sub-part, the depth of the second groove sub-part in the vertical direction being less than the depth of the first groove sub-part in the vertical direction;

[0032] Etching downward from the top surface of the sacrificial layer to form the third groove sub-part, the depth of the third groove sub-part in the vertical direction being greater than the depth of the second groove sub-part in the vertical direction and less than the depth of the first groove sub-part in the vertical direction.

[0033] In some embodiments, the second groove sub-parts in adjacent sub-grooves in the first direction have different depths in the vertical direction, and the third groove sub-parts in adjacent sub-grooves in the first direction have different depths in the vertical direction.

[0034] In some embodiments, filling a conductive material in the groove to form the connection structure and the second pad includes:

[0035] Filling a conductive material in the first groove sub-part and the second groove sub-part to form the connection structure, and filling a conductive material in the third groove sub-part to form the second pad.

[0036] In some embodiments, the method further includes: fixing at least one chip on the substrate, the surface of the chip having pads; and electrically connecting the pads to the second pad using bonding wires.

[0037] In some embodiments, the encapsulation layer is formed using a molding process.

[0038] The semiconductor structure and its manufacturing method provided by the embodiments of the present disclosure, wherein the semiconductor structure includes: a substrate having a first pad; an interposer located on the substrate, and the bottom surface of the interposer covers the first pad; wherein the interposer includes a second pad and a connection structure; the second pad is located on any surface of the interposer except the bottom surface; one end of the connection structure is connected to the first pad, and the other end of the connection structure is connected to the second pad. The embodiments of the present disclosure lead out the first pad located on the substrate to any surface of the interposer except the bottom surface through the connection structure to form a second pad. The interposer is located above the substrate, and its side surface has a large area, so that the arrangement density of the second pads can be less than that of the first pads, and the possibility of short circuit between adjacent second pads and between adjacent bonding wires can be reduced during wire bonding. Compared with the traditional technology, the semiconductor structure provided by the embodiments of the present disclosure can have a smaller substrate size, more pad numbers and a lower pad arrangement density. In addition, the presence of the interposer can also shorten the length of the bonding wires, thereby reducing heat generation and signal attenuation.

[0039] Details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the drawings of the specification and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0041] Figure 1a is a perspective view of the semiconductor structure provided by the embodiment of the present disclosure, Figure 1b is a schematic cross-sectional structure diagram taken along the line A-A' of Figure 1a , Figure 1c is Figure 1a a perspective view of the first pad and the connection structure in

[0042] Figure 2a is a perspective view of the semiconductor structure provided by another embodiment of the present disclosure, Figure 2b is a schematic cross-sectional structure diagram taken along the line A-A' of Figure 2a ;

[0043] Figure 3a is a perspective view of the semiconductor structure provided by another embodiment of the present disclosure, Figure 3b is a schematic cross-sectional structure diagram taken along the line A-A' of Figure 3a ;

[0044] Figure 4 A flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0045] Figures 5a to 10b A process flowchart of a semiconductor structure provided by an embodiment of the present disclosure. Detailed implementation manners

[0046] Hereinafter, the exemplary embodiments disclosed in the present disclosure will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0047] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these details. In other instances, some well-known technical features are not described in order to avoid confusion with the present disclosure; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0048] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals throughout the drawings denote the same elements.

[0049] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not imply that the present disclosure necessarily has a first element, component, region, layer, or part.

[0050] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0051] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0052] A semiconductor structure includes a substrate and one or more chips located on the substrate. The surface of the substrate is provided with bonding pads, and the chips are electrically connected to the bonding pads on the surface of the substrate through bonding wires. As the semiconductor structure develops towards smaller size and higher integration, the size of the substrate gradually decreases, and the number of bonding pads gradually increases, resulting in an increasing arrangement density of the bonding pads. During wire bonding, short circuits are likely to occur between adjacent bonding pads and adjacent bonding wires, affecting the reliability of the semiconductor structure.

[0053] Based on this, the following technical solutions of the embodiments of the present disclosure are proposed:

[0054] An embodiment of the present disclosure provides a semiconductor structure, including: a substrate having a first bonding pad; an adapter board located on the substrate, the bottom surface of the adapter board covering the first bonding pad; wherein the adapter board includes a second bonding pad and a connection structure; the second bonding pad is located on any surface of the adapter board other than the bottom surface; one end of the connection structure is connected to the first bonding pad, and the other end of the connection structure is connected to the second bonding pad.

[0055] In the embodiments of the present disclosure, a connection structure is used to lead out the first pad located on the substrate to any surface of the interposer except the bottom surface, forming a second pad. The interposer is located above the substrate, and its side surface has a relatively large area. Therefore, the arrangement density of the second pads can be smaller than that of the first pads, reducing the possibility of short circuits between adjacent second pads and between adjacent bonding wires during wire bonding. Compared with the traditional technology, the semiconductor structure provided by the embodiments of the present disclosure can have a smaller substrate size, a larger number of pads, and a lower pad arrangement density. In addition, the presence of the interposer can also shorten the length of the bonding wires, thereby reducing heat generation and signal attenuation.

[0056] The following will describe in detail the specific embodiments of the present disclosure with reference to the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the convenience of explanation, the schematic diagrams will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the protection scope of the present disclosure here.

[0057] Figure 1a 、 Figure 2a 、 Figure 3a is a perspective view of the semiconductor structure provided by the embodiments of the present disclosure, Figure 1b 、 Figure 2b 、 Figure 3b are respectively schematic cross-sectional structure diagrams taken along the lines A - A' of Figure 1a 、 Figure 2a 、 Figure 3a . Figure 1c is Figure 1a a perspective view of the first pad and the connection structure in Figures 1a to 3b . The following will further describe in detail the semiconductor structure provided by the embodiments of the present disclosure with reference to

[0058] As shown in Figures 1a to 1c , the semiconductor structure includes: a substrate 10 having a first pad P1; an interposer 16 located on the substrate 10, and the bottom surface of the interposer 16 covers the first pad P1; wherein, the interposer 16 includes a second pad P2 and a connection structure L; the second pad P2 is located on any surface of the interposer 16 except the bottom surface; one end of the connection structure L is connected to the first pad P1, and the other end of the connection structure L is connected to the second pad P2.

[0059] The substrate 10 may be a rigid printed circuit board, a flexible printed circuit board, a rigid-flexible printed circuit board, or any combination thereof. In a specific embodiment, the substrate 10 is a multi-layer circuit board internally provided with various circuit elements. In a more specific embodiment, the surface of the substrate 10 includes an insulating layer (not shown), the first pad P1 is located within the insulating layer (not shown), and the upper surface of the first pad P1 is flush with the upper surface of the insulating layer (not shown). The material of the first pad P1 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, conductive carbon, or any combination thereof. The material of the insulating layer (not shown) may be a solder mask.

[0060] In one embodiment, the adapter board 16 further includes: a sealing layer 15, the bottom of the sealing layer 15 covers the first pad P1, and the second pad P2 is located on the side surface of the sealing layer 15. However, it is not limited thereto. In other embodiments, the second pad P2 may also be located on the top surface of the sealing layer 15. The material of the sealing layer 15 is an insulating material, for example, epoxy molding compound. The material of the second pad P2 may be the same as or different from the material of the first pad P1. Optionally, the material of the second pad P2 may include metal, metal nitride, metal silicide, metal alloy, conductive carbon, or any combination thereof.

[0061] In one embodiment, the second pad P2 includes a plurality of second sub-pad groups P20 with different heights, and each of the second sub-pad groups P20 includes a plurality of second sub-pads 14 arranged and distributed in a first direction. Optionally, the first direction is parallel to the surface of the substrate 10. As Figure 1a shown, a plurality of the second sub-pad groups P20 are exposed on the side surface of the sealing layer 15 and are arranged and distributed in a direction perpendicular to the substrate 10.

[0062] See Figure 1a 、 Figure 1c, in one embodiment, the first pad P1 includes at least one first sub-pad group P10, and the first sub-pad group P10 includes a plurality of first sub-pads 11 arranged and distributed in a first direction. In a specific embodiment, the distance between two adjacent first sub-pads 11 in the first direction in the first sub-pad group P10 is less than the distance between two adjacent second sub-pads 14 in the second sub-pad group P20 in the first direction. In other words, in the first direction, the arrangement of the second sub-pads 14 is sparser than that of the first sub-pads 11. Thus, during wire bonding, it is not easy for short circuits to occur between adjacent second sub-pads 14 and between the bonding wires connected to the adjacent second sub-pads 14, improving the reliability of the semiconductor structure. It can be understood that the first sub-pads 11 and the second sub-pads 14 are in a one-to-one correspondence. The reason why the distance between two adjacent second sub-pads 14 in the first direction is greater than the distance between two adjacent first sub-pads 11 is that each first sub-pad group P10 corresponds to a plurality of second sub-pad groups P20 with different heights. Thus, the number of second sub-pads 14 in each second sub-pad group P20 is less than the number of first sub-pads 11 in each first sub-pad group P10. Therefore, the distance between adjacent second sub-pads 14 in each second sub-pad group P20 is greater than the distance between adjacent first sub-pads 11 in each first sub-pad group P10. As Figure 1c shown, each first sub-pad group P10 corresponds to 2 second sub-pad groups P20 with different heights. However, this is not limited thereto. Each first sub-pad group P10 may also correspond to more second sub-pad groups P20 with different heights, such as 3, 4, or 5.

[0063] Figures 1a to 1c Each of the shown adapter boards 16 covers a group of the first sub-pad groups P10. However, this is not limited thereto. As Figures 2a to 2b shown, in another embodiment, each adapter board 16 covers multiple groups of the first sub-pad groups P10, and the multiple groups of the first sub-pad groups P10 are arranged and distributed on the substrate 10 in a second direction. In a specific embodiment, the second direction is perpendicular to the first direction.

[0064] It should be noted that the number of the first sub-pad groups and the number of the second sub-pad groups are not limited to Figures 1a to 3b shown. The number of the first sub-pad groups and the number of the second sub-pad groups can be more or less.

[0065] Continue to refer to Figure 1c, the connection structure L is located within the sealing layer 15. The second pad P2 and the first pad P1 are connected in a one-to-one correspondence through the connection structure L. The arrangement pattern of the connection structure L is the same as that of the first pad P1. The height of the connection structure L determines the height of the second pad P2. In one embodiment, the connection structure L includes a plurality of sub-connection structures 13; wherein, the sub-connection structures 13 have different heights. In some embodiments, the connection structure L includes a plurality of sub-connection structures 13 arranged and distributed along a first direction; wherein, two adjacent sub-connection structures 13 have different heights.

[0066] In one embodiment, the sub-connection structure 13 includes a first connection sub-part 131 and a second connection sub-part 132 that extend in different directions and are connected to each other; the first connection sub-part 131 is connected to the first pad P1, and the second connection sub-part 132 is connected to the second pad P2. In a specific embodiment, the extending direction of the first connection sub-part 131 is perpendicular to the substrate 10, and the extending direction of the second connection sub-part 132 is parallel to the substrate 10. The first connection sub-part 131 and the second connection sub-part 132 can be formed simultaneously or sequentially; the materials of the first connection sub-part 131 and the second connection sub-part 132 can include metals, metal nitrides, metal silicides, metal alloys, conductive carbon, or any combination thereof. In a specific embodiment, the materials of the first pad P1, the connection structure L, and the second pad P2 are the same, for example, copper (Cu).

[0067] In one embodiment, the semiconductor structure further includes: one or more chips C disposed on the substrate 10. The surface of the chip C has pads 18, and the pads 18 are electrically connected to the second sub-pad group P20 through bonding wires 19. Here, the chip C can be a memory, such as a dynamic random access memory (DRAM). The bonding wires 19 are used to conduct signals, and their materials can be metals, for example, gold (Au).

[0068] In one embodiment, the number of chips C disposed on the substrate 10 is multiple, and the side surfaces of the multiple chips C are aligned in a direction perpendicular to the substrate 10, as Figures 1a to 2b shown. However, it is not limited thereto. In other embodiments, two adjacent chips C can be offset from each other by a predetermined distance, as Figures 3a to 3b shown.

[0069] In one embodiment, as Figures 1a to 1bAs shown, among the multiple chips C, there are two stacked chips C1 and C2, and among the multiple second sub-pad groups P20, there are two second sub-pad groups P21 and P22 with different heights. Among them, the upper chip C2 among the two chips C1 and C2 is electrically connected to the upper second sub-pad group P22 among the two second sub-pad groups P21 and P22, and the lower chip C1 among the two chips C1 and C2 is electrically connected to the lower second sub-pad group P21 among the two second sub-pad groups P21 and P22. However, it is not limited to this. In another embodiment, the two stacked chips C1 and C2 can also be respectively electrically connected to two second sub-pad groups P20 with the same height, where the two second sub-pad groups P20 are respectively located on the side surfaces of the two interposer boards 16, as Figures 3a to 3b shown.

[0070] In one embodiment, the chip C further includes an adhesive layer 17, and the adhesive layer 17 is located on the lower surface of the chip C and is used to sequentially bond one or more chips C to the substrate 10. The adhesive layer 17 includes an adhesive film, for example, a direct adhesive film (DAF).

[0071] In one embodiment, the number of the interposer boards 16 is multiple, and the multiple interposer boards 16 are arranged around the one or more chips C. As Figures 1a to 1b shown, in some embodiments, the number of the interposer boards 16 is 2, and the two interposer boards 16 are respectively located on both sides of the one or more chips C. However, it is not limited to this, and the number of the interposer boards 16 can also be more or less, such as 1, 3, or 4.

[0072] In one embodiment, the semiconductor structure further includes: a packaging layer (not shown), and the packaging layer (not shown) at least covers the chip C and the interposer board 16. It can be understood that the packaging layer (not shown) also covers the bonding wires 19 and a part of the surface of the substrate 10.

[0073] In summary, in the embodiment of the present disclosure, the first pad P1 located on the substrate 10 is led out to any surface other than the bottom surface of the interposer board 16 through the connection structure L to form the second pad P2. The interposer board 16 is located above the substrate 10, and its side surface has a large area, so that the arrangement density of the second pads P2 can be smaller than that of the first pads P1, and the possibility of short circuit between adjacent second pads P2 and between adjacent bonding wires 19 can be reduced during wire bonding. Compared with the traditional technology, the semiconductor structure provided by the embodiment of the present disclosure can have a smaller substrate size, more pad numbers, and a lower pad arrangement density. In addition, the presence of the interposer board 16 can also shorten the length of the bonding wires 19, thereby reducing heat generation and signal attenuation.

[0074] An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, as Figure 4 shown, the method comprising the following steps:

[0075] Step 401: Provide a substrate, the surface of the substrate having a first pad;

[0076] Step 402: Form an interposer on the substrate, including: forming a connection structure and a second pad, the second pad being located on any surface of the interposer other than the bottom surface; one end of the connection structure being connected to the first pad, and the other end of the connection structure being connected to the second pad.

[0077] Next, with reference to Figures 5a to 10b a further detailed description of the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure will be given. Among them, Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a are perspective views of the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure in different process steps, Figure 5b , Figure 6b , Figure 7b , Figure 8b , Figure 9b , Figure 10b are respectively schematic cross-sectional structures taken along the lines A-A' of Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a .

[0078] First, perform step 401 to provide a substrate 10, the surface of the substrate 10 having a first pad P1, as Figures 5a to 5b shown.

[0079] The substrate 10 may be a rigid printed circuit board, a flexible printed circuit board, a rigid-flexible printed circuit board, or any combination thereof. In a specific embodiment, the substrate 10 is a multi-layer circuit board internally provided with various circuit elements. In a more specific embodiment, the surface of the substrate 10 includes an insulating layer (not shown), the first pad P1 is located within the insulating layer (not shown), and the upper surface of the first pad P1 is flush with the upper surface of the insulating layer (not shown). The material of the first pad P1 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, conductive carbon, or any combination thereof. The material of the insulating layer (not shown) may be a solder resist.

[0080] In one embodiment, the first pad P1 includes at least one first sub-pad group P10, and the first sub-pad group P10 includes a plurality of first sub-pads 11 arranged and distributed in a first direction.

[0081] Figures 5a - 5b The number of the shown first sub-pad groups P10 is two, and two transfer boards 16 will be respectively formed on the two first sub-pad groups P10 (see Figures 10a to 10b ), that is, each transfer board 16 covers one first sub-pad group P10. However, this is not limited thereto. The number of the first sub-pad groups P10 can also be more, and the number of the first sub-pad groups P10 covered by each transfer board 16 can also be more. As Figures 2a - 2b shown, in one embodiment, the multiple first sub-pad groups P10 covered by the same transfer board 16 are arranged and distributed in a second direction. In a specific embodiment, the second direction is perpendicular to the first direction.

[0082] Next, step 402 is executed. As Figures 6a to 10b shown, forming a transfer board 16 on the substrate 10 includes: forming a connection structure L and a second pad P2, and the second pad P2 is located on any surface of the transfer board 16 except the bottom surface; one end of the connection structure L is connected to the first pad P1, and the other end of the connection structure L is connected to the second pad P2.

[0083] In one embodiment, forming a transfer board 16 on the substrate 10 further includes: forming a sealing layer 15 on the substrate 10, and the sealing layer 15 covers the connection structure L and makes the second pad P2 located on the side surface of the sealing layer 15. However, this is not limited thereto. In other embodiments, the second pad P2 can also be formed on the top surface of the sealing layer 15. Here, the sealing layer 15 can be formed by a molding process, and the material of the sealing layer 15 is an insulating material, for example, epoxy molding compound.

[0084] In one embodiment, forming the connection structure L and the second pad P2 includes:

[0085] forming a sacrificial layer 12 on the substrate 10, and the sacrificial layer 12 covers the first pad P1, as Figures 6a to 6b shown;

[0086] etching the sacrificial layer 12 to form a groove T in the sacrificial layer 12, as Figures 7a to 7b shown;

[0087] filling a conductive material in the groove T to form the connection structure L and the second pad P2, as Figures 8a to 8b shown;

[0088] Remove the sacrificial layer 12, as Figures 9a to 9b shown.

[0089] The forming process of the conductive material can be chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, etc. The conductive material can be the same as or different from the material of the first pad P1. Optionally, the conductive material may include a metal, a metal nitride, a metal silicide, a metal alloy, conductive carbon, or any combination thereof. In one embodiment, the materials of the first pad P1, the connection structure L, and the second pad P2 are the same, for example, copper (Cu).

[0090] Referring again to Figures 7a to 7b , in one embodiment, the groove T includes a plurality of sub-grooves T4 arranged and distributed along a first direction, and each sub-groove T4 includes a first groove sub-part T1, a second groove sub-part T2, and a third groove sub-part T3 that are sequentially connected; etching the sacrificial layer 12 includes:

[0091] Etch downward from the top surface of the sacrificial layer 12 to form the first groove sub-part T1, and the first groove sub-part T1 exposes the first pad P1;

[0092] Etch downward from the top surface of the sacrificial layer 12 to form the second groove sub-part T2, and the depth of the second groove sub-part T2 in the vertical direction is less than the depth of the first groove sub-part T1 in the vertical direction;

[0093] Etch downward from the top surface of the sacrificial layer 12 to form the third groove sub-part T3, and the depth of the third groove sub-part T3 in the vertical direction is greater than the depth of the second groove sub-part T2 in the vertical direction and less than the depth of the first groove sub-part T1 in the vertical direction.

[0094] Optionally, the material of the sacrificial layer 12 can be a photoresist, and the groove T is formed in the sacrificial layer 12 by performing an exposure and development process on the sacrificial layer 12. Moreover, the first groove sub-part T1, the second groove sub-part T2, and the third groove sub-part T3 with different depths can be obtained by adjusting the exposure time, the beam radiation dose, or the development time.

[0095] Referring again to Figures 8a to 8b , in one embodiment, filling the groove T with a conductive material to form the connection structure L and the second pad P2 includes:

[0096] A conductive material is filled in the first groove sub - portion T1 and the second groove sub - portion T2 to form the connection structure L, and a conductive material is filled in the third groove sub - portion T3 to form the second pad P2.

[0097] Specifically, the connection structure L includes a plurality of sub - connection structures 13 arranged uniformly along a first direction. In a specific embodiment, the sub - connection structure 13 includes a first connection sub - portion 131 and a second connection sub - portion 132 that extend in different directions and are connected to each other; wherein, the first connection sub - portion 131 is formed by filling a conductive material in the first groove sub - portion T1, and the second connection sub - portion 132 is formed by filling a conductive material in the second groove sub - portion T2.

[0098] More specifically, the second pad P2 includes a plurality of second sub - pad groups P20 with different heights, and each second sub - pad group P20 includes a plurality of second sub - pads 14 arranged along the first direction.

[0099] It can be understood that the depth of the second groove sub - portion T2 in the vertical direction determines the height of the sub - connection structure 13, and the depth of the second groove sub - portion T2 in the vertical direction and the depth of the third groove sub - portion T3 in the vertical direction determine the height of the second sub - pad 14. In an embodiment, the second groove sub - portions T2 in the adjacent sub - grooves T4 along the first direction have different depths in the vertical direction, and the third groove sub - portions T3 in the adjacent sub - grooves T4 along the first direction have different depths in the vertical direction, so that the adjacent two sub - connection structures 13 finally formed have different heights, and the second sub - pads 14 connected to the adjacent two sub - connection structures 13 also have different heights. The first sub - pads 11 and the second sub - pads 14 are in a one - to - one correspondence relationship, and each first sub - pad group P10 corresponds to a plurality of second sub - pad groups P20 with different heights. Therefore, the distance between the adjacent second sub - pads 14 in the second sub - pad group P20 along the first direction is greater than the distance between the adjacent first sub - pads 11 in each first sub - pad group P10 along the first direction. In other words, in the first direction, the second sub - pads 14 are arranged more sparsely than the first sub - pads 11. In this way, during wire bonding, it is not easy for short - circuits to occur between the adjacent second sub - pads 14 and between the bonding wires connected to the adjacent second sub - pads 14, improving the reliability of the semiconductor structure. Compared with the traditional technology, the semiconductor structure provided by the embodiments of the present disclosure can have a smaller substrate size, a larger number of pads, and a lower pad layout density.

[0100] See again Figure 9a, each of the first sub-pad groups P10 corresponds to two second sub-pad groups P20 with different heights. However, this is not limited thereto. Each of the first sub-pad groups P10 may also correspond to more second sub-pad groups P20 with different heights, such as 3, 4, or 5.

[0101] In one embodiment, the method further includes: fixing at least one chip C on the substrate 10, the surface of the chip C having pads 18; using bonding wires 19 to electrically connect the pads 18 to the second pads P2, forming a Figures 1a to 1b semiconductor structure as shown. The bonding wires 19 are used to conduct signals. In the embodiments of the present disclosure, by using the adapter board 16 to lead the first pads P1 on the substrate 10 to the side surface of the adapter board 16 to form the second pads P2, and directly connecting the bonding wires 19 to the second pads P2, the length of the bonding wires 19 can be effectively shortened, thereby enhancing the signal transmission performance and reducing heat generation and signal attenuation. Here, the chip C may be a memory, such as a dynamic random access memory (DRAM). The material of the bonding wires 19 may be metal, for example, gold (Au).

[0102] In one embodiment, the number of chips C provided on the substrate 10 is multiple, and the side surfaces of the multiple chips C are aligned in a direction perpendicular to the substrate 10, as Figures 1a to 2b shown. However, this is not limited thereto. In other embodiments, two adjacent chips C may be offset from each other by a predetermined distance, as Figures 3a to 3b shown.

[0103] In one embodiment, among the multiple chips C, there are two stacked chips C1 and C2, and among the multiple second sub-pad groups P20, there are two second sub-pad groups P21 and P22 with different heights; wherein, the upper chip C2 among the two chips C1 and C2 is electrically connected to the upper second sub-pad group P22 among the two second sub-pad groups P21 and P22, and the lower chip C1 among the two chips C1 and C2 is electrically connected to the lower second sub-pad group P21 among the two second sub-pad groups P21 and P22, as Figures 1a to 1b shown. However, this is not limited thereto. In another embodiment, the two stacked chips C1 and C2 may also be respectively electrically connected to two second sub-pad groups P20 with the same height, wherein the two second sub-pad groups P20 are respectively located on the side surfaces of the two adapter boards 16, as Figures 3a to 3b shown.

[0104] In one embodiment, the chip C further includes an adhesive layer 17, which is located on the lower surface of the chip C and is used to sequentially bond one or more chips C to the substrate 10. The adhesive layer 17 includes an adhesive film, for example, a direct adhesive film (DAF).

[0105] In one embodiment, the number of the interposer boards 16 is multiple, and the multiple interposer boards 16 are arranged around the one or more chips C. As Figures 1a to 1b shown, in some embodiments, the number of the interposer boards 16 is two, and the two interposer boards 16 are respectively located on both sides of the one or more chips C. However, this is not limited thereto, and the number of the interposer boards 16 can also be more or less, such as one, three, or four.

[0106] In one embodiment, the method further includes: forming a packaging layer (not shown), and the packaging layer (not shown) at least covers the chip C and the interposer board 16. It can be understood that the packaging layer (not shown) also covers the bonding wires 19 and a part of the surface of the substrate 10.

[0107] It should be noted that those skilled in the art can change the above step sequence without departing from the protection scope of the present disclosure. The above are only optional embodiments of the present disclosure and are not used to limit the protection scope of the present disclosure. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate having a first pad; An interposer located on the substrate, the bottom surface of the interposer covering the first pad; wherein, the interposer includes a second pad, a connection structure and a sealing layer; the second pad is located on any surface of the interposer other than the bottom surface; one end of the connection structure is connected to the first pad, and the other end of the connection structure is connected to the second pad; the bottom of the sealing layer covers the first pad, and the second pad is located on the side surface of the sealing layer.

2. The semiconductor structure according to claim 1, wherein, The connection structure is located within the sealing layer.

3. The semiconductor structure according to claim 1, wherein The second pad includes a plurality of second sub-pad groups with different heights, and each of the second sub-pad groups includes a plurality of second sub-pads arranged and distributed in a first direction.

4. The semiconductor structure according to claim 3, wherein The first pad includes one or more first sub-pad groups, and each of the first sub-pad groups includes a plurality of first sub-pads arranged and distributed in a first direction.

5. The semiconductor structure according to claim 4, wherein The distance between two adjacent first sub-pads in the first direction in the first sub-pad group is less than the distance between two adjacent second sub-pads in the first direction in the second sub-pad group.

6. The semiconductor structure according to claim 1, wherein The connection structure includes a plurality of sub-connection structures; wherein, the sub-connection structures have different heights.

7. The semiconductor structure according to claim 1, wherein, The connection structure includes a plurality of sub-connection structures arranged and distributed in a first direction; wherein, two adjacent sub-connection structures have different heights.

8. The semiconductor structure according to claim 6 or 7, wherein The sub-connection structure includes a first connection sub-part and a second connection sub-part that extend in different directions and are connected to each other; the first connection sub-part is connected to the first pad, and the second connection sub-part is connected to the second pad.

9. The semiconductor structure according to claim 8, wherein The extending direction of the first connection sub-part is perpendicular to the substrate, and the extending direction of the second connection sub-part is parallel to the substrate.

10. The semiconductor structure according to claim 3, characterized in that, The semiconductor structure further includes: one or more chips disposed on the substrate, the surface of the chip having pads, and the pads are electrically connected to the second sub-pad group through bonding wires.

11. The semiconductor structure according to claim 10, wherein, Among the plurality of chips, there are two stacked chips, and among the plurality of second sub-pad groups, there are two second sub-pad groups with different heights; wherein, the chip located above among the two chips is electrically connected to the second sub-pad group located above among the two second sub-pad groups, and the chip located below among the two chips is electrically connected to the second sub-pad group located below among the two second sub-pad groups.

12. The semiconductor structure according to claim 10, wherein The semiconductor structure further includes: a packaging layer that at least covers the chip and the interposer.

13. The semiconductor structure according to claim 10, wherein, The number of the interposers is multiple, and the multiple interposers are arranged around the one or more chips.

14. A method for manufacturing a semiconductor structure, characterized in that, The method includes: Providing a substrate, the surface of the substrate having a first pad; Forming an interposer on the substrate, including: forming a connection structure and a second pad, the second pad being located on any surface of the interposer other than the bottom surface; forming a sealing layer on the substrate, the sealing layer covering the connection structure and enabling the second pad to be located on the side surface of the sealing layer; One end of the connection structure is connected to the first pad, and the other end of the connection structure is connected to the second pad.

15. The manufacturing method according to claim 14, characterized in that, Forming the connection structure and the second pad includes: A sacrificial layer is formed on the substrate, and the sacrificial layer covers the first pad; The sacrificial layer is etched to form a groove in the sacrificial layer; A conductive material is filled in the groove to form the connection structure and the second pad; The sacrificial layer is removed.

16. The manufacturing method according to claim 15, characterized in that, The groove includes a plurality of sub-grooves uniformly arranged and distributed in a first direction, and each sub-groove includes a first groove sub-part, a second groove sub-part, and a third groove sub-part that are sequentially connected; Etching the sacrificial layer includes: etching downward from the top surface of the sacrificial layer to form the first groove sub-part, and the first groove sub-part exposes the first pad; Etching downward from the top surface of the sacrificial layer to form the second groove sub-part, and the depth of the second groove sub-part in the vertical direction is less than the depth of the first groove sub-part in the vertical direction; Etching downward from the top surface of the sacrificial layer to form the third groove sub-part, and the depth of the third groove sub-part in the vertical direction is greater than the depth of the second groove sub-part in the vertical direction and less than the depth of the first groove sub-part in the vertical direction.

17. The manufacturing method according to claim 16, characterized in that, The second groove sub-parts in the adjacent sub-grooves in the first direction have different depths in the vertical direction, and the third groove sub-parts in the adjacent sub-grooves in the first direction have different depths in the vertical direction.

18. The manufacturing method according to claim 16, characterized in that, Filling a conductive material in the groove to form the connection structure and the second pad includes: Filling a conductive material in the first groove sub-part and the second groove sub-part to form the connection structure, and filling a conductive material in the third groove sub-part to form the second pad.

19. The manufacturing method according to claim 14, characterized in that, The method further includes: fixing at least one chip on the substrate, and the surface of the chip has pads; electrically connecting the pads to the second pad by bonding wires.

20. The manufacturing method according to claim 14, characterized in that, The sealing layer is formed by a molding process.

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