Integrated circuitry and methods of forming integrated circuits

Abstract

Embodiments of the present application provide integrated circuitry and methods of forming integrated circuits. An exemplary method includes receiving a device layout of a standard cell including a transistor and a multilayer interconnect. The multilayer interconnect includes a power line, a signal line, a source contact connected to the power line and a source of the transistor, and a drain contact connected to one of the signal line and a drain of the transistor. The method includes modifying the device layout of the standard cell. For example, if performance of the standard cell is sensitive to power-related features, then the power line and the source contact are enlarged, and the signal line and the drain contact are reduced. If performance of the standard cell is sensitive to signal-related features, then the power line and the source contact are reduced, and the signal line and the drain contact are enlarged. After modifying the device layout, a cell height of the standard cell is the same.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuit systems and methods for forming integrated circuits. Background Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each generation smaller and more complex than the last. Throughout IC evolution, functional density (the number of interconnects per chip area) has generally increased, while geometry (the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down process typically provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of IC fabrication and manufacturing, requiring similar advancements in IC fabrication and manufacturing to achieve these advancements. For example, as multilayer interconnect (MLI) components become more compact with the continuous shrinking of IC component sizes, MLI interconnects exhibit increased resistance and capacitance, posing challenges to performance, yield, and cost. The performance of logic-based ICs is particularly susceptible to this increase in resistance and / or capacitance. Therefore, improvements to MLI components for logic-based ICs are needed. Summary of the Invention

[0003] According to one aspect of an embodiment of the present invention, a method for forming an integrated circuit is provided, comprising: receiving an integrated circuit layout of standard cells having a cell height, wherein the integrated circuit layout includes power lines, signal lines, a first source / drain via connected to the power lines, and a second source / drain via connected to the signal lines; adjusting the dimensions of the power lines, signal lines, the first source / drain via, and the second source / drain via to generate a modified integrated circuit layout of the standard cells having a cell height. The dimension adjustment is based on desired performance optimization of the standard cells, and the dimension adjustment includes associating power line dimensions with signal line dimensions, associating power line dimensions with the first source / drain via dimensions, and associating signal line dimensions with the second source / drain via dimensions, such that changes in the power line dimensions correspond to changes in the signal line dimensions, the first source / drain via dimensions, and the second source / drain via dimensions. The method further includes manufacturing standard cells based on the modified integrated circuit layout.

[0004] According to another aspect of the present invention, a method for forming an integrated circuit is provided, comprising: receiving an interconnect layout of a standard cell, wherein the interconnect layout includes a metallization layer and a via layer, wherein the metallization layer includes a first conductive line and a second conductive line, the via layer includes a first via and a second via, the first via being connected to the first conductive line and a source of a transistor, and the second via being connected to the second conductive line and a drain of a transistor; and modifying the interconnect layout of the standard cell. The modification of the interconnect layout includes: if the performance of the standard cell is sensitive to a first type of performance characteristic, enlarging the first conductive line and the first via and shrinking the second conductive line and the second via; and if the performance of the standard cell is sensitive to a second type of performance characteristic different from the first type of performance characteristic, shrinking the first conductive line and the first via and enlarging the second conductive line and the second via. The method further includes: manufacturing interconnects of the standard cell using the modified interconnect layout of the standard cell.

[0005] According to another aspect of the present invention, an integrated circuit system is provided, comprising: a processor; a communication module communicatively coupled to the processor and configured to receive a device layout of a standard cell, the device layout including transistors and multilayer interconnects, wherein the multilayer interconnects include power lines, signal lines, source contacts connected to the sources of the power lines and transistors, and drain contacts connected to one of the signal lines and the drain of the transistors; and a non-transitory computer-readable storage, communicatively coupled to the processor and including instructions executable by the processor. The instructions include: instructions for modifying the device layout of the standard cell, wherein the modification of the device layout includes: enlarging the power lines and source contacts and shrinking the signal lines and drain contacts if the performance of the standard cell is sensitive to power-related characteristics, and shrinking the power lines and source contacts and enlarging the signal lines and drain contacts if the performance of the standard cell is sensitive to signal-related characteristics. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 It is a partial schematic plan view of an integrated circuit (IC) chip according to various aspects of this disclosure.

[0008] Figure 2 This is a partial schematic cross-sectional view of some or all of the various layers (levels) of the region that can be fabricated above a semiconductor substrate (wafer) to form an IC chip, according to various aspects of this disclosure.

[0009] Figure 3Aand Figure 3B It is a partial or complete schematic diagram of the layout of standard units according to various aspects of this disclosure.

[0010] Figure 4A , Figure 4B and Figure 4C Based on all aspects of this disclosure Figure 3A and Figure 3B A top view of the partial layout of the standard unit.

[0011] Figure 5A and Figure 5B Based on all aspects of this disclosure Figure 3A and Figure 3B A top view of the partial layout of the standard unit.

[0012] Figure 6A and Figure 6B Based on all aspects of this disclosure Figure 3A and Figure 3B A top view of the partial layout of the standard unit.

[0013] Figure 7 The illustrations depict various aspects of this disclosure. Figure 3A and Figure 3B Power performance optimization of the standard cell layout.

[0014] Figure 8 The illustrations depict various aspects of this disclosure. Figure 3A and Figure 3B Optimize signal performance of the standard cell layout.

[0015] Figure 9 The illustrations depict various aspects of this disclosure. Figure 3A and Figure 3B Signal performance optimization of standard cell layout.

[0016] Figure 10A A top plan view depicts the layout of some or all of the multilayer interconnect MLI of a standard cell before optimization, after power performance optimization, and after signal performance optimization, according to various aspects of this disclosure.

[0017] Figure 10B Partial or complete schematic diagrams of a standard cell manufactured according to various aspects of this disclosure, based on a multilayer interconnect (MLI) layout, are depicted before optimization, after power performance optimization, and after signal performance optimization.

[0018] Figure 11 This is a flowchart illustrating methods that can be implemented for standard design and / or manufacturing according to various aspects of this disclosure.

[0019] Figure 12 The illustration shows a partial or overall IC manufacturing system according to various aspects of this disclosure. Detailed Implementation

[0020] This disclosure generally relates to integrated circuit (IC) devices, and more specifically, to interconnect-driven optimization of IC design layouts.

[0021] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components such that the first and second components are not in direct contact.

[0022] Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not, in itself, prescribe a relationship between the various embodiments and / or configurations discussed. Additionally, in the following disclosure, the formation of components on, connected to, and / or coupled to another component may include embodiments in which these components are formed in direct contact, and may also include embodiments in which components are inserted, or additional components may be formed such that features may not be in direct contact. Furthermore, spatially relative terms, such as “lower,” “upper,” “hierarchical,” “vertical,” “above,” “above,” “below,” “under,” “top,” “bottom,” etc., and their derivatives (e.g., “hierarchical,” “downward,” “upward,” etc.), are used to facilitate understanding of the relationship between one component and another in this disclosure. Spatially relative terms are intended to cover different orientations of the device including the components.

[0023] Integrated circuit (IC) design defines a variety of standard cells with predetermined functions. Each standard cell includes transistors and interconnect (or wiring) structures that combine to provide logic functions (e.g., AND, NAND, OR, NOR, NOT, XOR, and / or XNOR) and / or storage functions (e.g., flip-flops, latches, and / or buffers). Generating an IC design layout typically involves placing (or arranging) an array of standard cells in a given area to implement a specific function, and wiring to connect the standard cells to each other. The IC design layout can then be used to manufacture IC devices.

[0024] As IC technology evolves towards smaller technology nodes, challenges arise in configuring transistors and interconnect structures relative to each other, and / or in configuring various layers of interconnect structures in a way that optimizes PPAC parameters (i.e., performance (e.g., speed), power (e.g., power consumption), area, and cost), efficiency, manufacturing time, manufacturing cost, or combinations thereof). This disclosure addresses these challenges by providing interconnect-driven optimizations for IC design layouts such as standard cell layouts. For example, the dimensions of interconnect structures, components, and / or layers are adjusted relative to each other based on the desired performance of the IC in the IC design layout (e.g., power performance optimization or signal performance optimization). In some embodiments, IC performance optimization is provided by modifying the IC design layout without changing the footprint of the IC design layout (e.g., cell size and / or cell area). Details of the proposed interconnect structures and their design and / or manufacturing methods are described below. Different embodiments may have different advantages, and no particular advantage is required in every embodiment.

[0025] Figure 1 This is a partial schematic plan view of an integrated circuit (IC) chip 10 according to various aspects of this disclosure. The IC chip 10 may include passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other devices, or combinations thereof. Transistors may be planar or non-planar transistors, such as fin FETs (FinFETs) or gate-all-around (GAA) transistors. Microelectronic devices may be configured to provide functionally distinct regions to the IC chip 10, such as core regions (also called logic regions), memory regions (e.g., static random access memory (SRAM) regions or dynamic random access memory (DRAM) regions), analog regions, peripheral regions (also called input / output (I / O) regions), pseudo-regions, other suitable regions, or combinations thereof. For clarity, Figure 1 The invention has been simplified to better understand the inventive concepts of this disclosure. Additional components may be added to the IC chip 10, and some of the components described herein may be replaced, modified, or eliminated in other embodiments of the IC chip 10.

[0026] exist Figure 1In this IC chip 10, a first region 20 is configured to provide a first circuit, and a second region 30 is configured to provide a second circuit. The first and second circuits may perform the same / similar functions and / or operations or different functions and / or operations. In some embodiments, both the first and second circuits are logic circuits. In such embodiments, the first region 20 and the second region 30 include logic cells, which may be standard cells. Each logic cell may include transistors and interconnect structures (also called wiring structures) that combine to provide a corresponding logic device and / or corresponding logic function, such as an inverter, AND gate, NAND gate, OR gate, NOR gate, NOT gate, XOR gate, XNOR gate, other suitable logic devices and / or functions, or combinations thereof. In some embodiments, the first and / or second circuits are memory circuits. In such embodiments, the first region 20, the second region 30, or both include an array of memory cells. Each memory cell may include transistors and interconnect structures that combine to provide a storage device and / or storage function, such as a flip-flop, a latch, other suitable memory devices and / or functions, or combinations thereof. In some embodiments, the memory cell is an SRAM cell, a DRAM cell, a non-volatile random access memory (NVRAM) cell, a flash memory cell, other suitable memory cells, or a combination thereof.

[0027] Figure 2 It is possible to fabricate on a semiconductor substrate (wafer) 50 according to various aspects of this disclosure to form Figure 1 A partial schematic cross-sectional view of various layers (levels) of region 20 and / or region 30 of the IC chip 10. In some embodiments, each layer is partially or entirely formed into a standard cell, which may be a logic cell or a memory cell (e.g., an SRAM cell). For clarity, Figure 2 The invention has been simplified to better understand the inventive concept of this disclosure. Additional components may be added to the various layers, and some of the described components may be replaced, modified, or eliminated in other embodiments.

[0028] exist Figure 2In this embodiment, each layer includes a device layer DL and a multilayer interconnect MLI disposed above the device layer DL. The device layer DL includes devices (e.g., transistors, resistors, capacitors, inductors, other devices, or combinations thereof) and / or device components (e.g., doped wells, gates, source / drains, other device components, or combinations thereof). For example, the device layer DL may include a substrate 50, doped regions 55 (e.g., n-wells and / or p-wells) disposed in the substrate 50, isolation components 60, and transistors T. In the depicted embodiment, the transistor T includes a suspended channel layer 65, a gate structure 70, and source / drains 75. The suspended channel layer 65 and the gate structure 70 are disposed between respective source / drains 75, and the gate structure 70 encloses and / or surrounds each suspended channel layer 65. Each gate structure 70 has a gate stack having a gate electrode 80 and a gate dielectric 82, and a gate spacer 86 disposed along the sidewall of the gate stack.

[0029] Multilayer interconnects (MLIs) electrically couple / connect devices and / or components of devices (DLs) such that the devices and / or components can operate as specified in design requirements. For example, a multilayer interconnect (MLI) may include contact layers (CO level or metal zero (M0) level), via zero layer (V0 level), metal layer one (M1 level), via layer one (V1 level), metal layer two (M2 level), via layer two (V2 level), metal layer three (M3 level), via layer three (V3 level), and metal layer four (M4 level). This disclosure considers multilayer interconnects (MLIs) with more or fewer layers and / or levels. For example, a multilayer interconnect (MLI) may include up to MX levels and V(X-1) levels, where X is the total number of metal layers (layers) of the multilayer interconnect (MLI).

[0030] Each level of a multilayer interconnect (MLI) includes conductive components (e.g., metal lines, metal vias, metal contacts, or combinations thereof) disposed in one or more dielectric layers (e.g., interlayer dielectric (ILD) layers and contact etch stop layers (CESL)). In some embodiments, conductive components are simultaneously formed at the same level of the multilayer interconnect (MLI), such as the M1 level. In some embodiments, the conductive components at the same level of the multilayer interconnect (MLI) have top surfaces that are substantially flat to each other and / or bottom surfaces that are substantially flat to each other.

[0031] The CO layer includes a source / drain contact MD disposed in the dielectric layer 90, wherein the source / drain contact MD is disposed on the source / drain 75. The V0 layer includes a gate via VG, a source / drain via V0, and a mating contact disposed in the dielectric layer 90, wherein the gate via VG is disposed on the gate stack of the gate structure 70, the source / drain via V0 is disposed on the source / drain contact MD, and the mating contact is disposed on the source / drain contact MD and the gate structure 70. The M1 layer includes an M1 metal line disposed in the dielectric layer 90, wherein the gate via VG connects the gate stack (e.g., gate electrode 80) of the gate structure 70 to the M1 metal line, the source / drain via V0 connects the source / drain contact MD to the M1 metal line, and the mating contact connects the gate stack and the source / drain 75 of the gate structure 70 together and further connects to the M1 metal line. The V1 layer includes a V1 via disposed in the dielectric layer 90, wherein the V1 via connects the M1 metal line to the M2 metal line. The M2 layer includes an M2 metal line disposed in the dielectric layer 90. The V2 layer includes a V2 via disposed in the dielectric layer 90, wherein the V2 via connects the M2 line to the M3 line; the M3 layer includes an M3 metal line disposed in the dielectric layer 90. The V3 layer includes a V3 via disposed in the dielectric layer 90, wherein the V3 via connects the M3 line to the M4 line, and so on.

[0032] Figure 3A and Figure 3B This is a partial schematic diagram of a standard unit 100 according to various aspects of this disclosure. Figure 3A This is a top view of standard unit 100. Figure 3A This is a top view of standard unit 100. Figure 3B It is standard unit 100 along Figure 3A A schematic cross-sectional view of line AA. Figures 4A-4C Based on all aspects of this disclosure Figure 3A Top plan views of each layer of the standard unit 100. For example, Figure 4A It is a top plan view of part or all of the device layer DL, contact CO layer and V0 layer of the MLI interconnect (e.g. DL / CO / V0) of the standard cell 100. Figure 4B It is a partial or complete top plan view of the V0, M1, and V1 levels of the MLI interconnects (e.g., V0 / M1 / V1) of the standard unit 100; and Figure 4C This is a partial or complete top plan view of the M1, V1, and M2 levels of the MLI interconnects (e.g., M1 / V1 / M2) of the standard unit 100. For clarity and to better understand the inventive concept of this disclosure, simplified diagrams have been provided. Figure 3A , Figure 3B and Figures 4A-4CAdditional components may be added to standard unit 100, and some of the described components may be replaced, modified, or eliminated in other embodiments of standard unit 100.

[0033] Standard cell 100 has a cell boundary LC, which has a first dimension, such as cell width W, along a first direction (e.g., the X direction), and a second dimension, such as cell height H, along a second direction (e.g., the Y direction). In some embodiments, the cell height H is less than or equal to about 250 nm. The cell width W may be greater than the cell height H (e.g., the ratio of cell width W to cell height H is greater than 1), less than the cell height H (e.g., the ratio of cell width W to cell height H is less than 1), or the same as the cell height H (e.g., the ratio of cell width W to cell height H is equal to 1). When standard cells 100 are repeated and arranged as a standard cell array (which may be a logic cell array or a memory array) in regions 20 and / or 30, the cell width W and cell height H may represent the X pitch and Y pitch of the standard cell array along the X and Y directions, respectively. Standard cells in the standard cell array may have the same cell height and different cell widths, different cell heights and the same cell width, or different cell heights and the same cell width.

[0034] As described above, the standard cell 100 includes a device layer DL and a multilayer interconnect MLI, which can be configured to provide logic circuitry. The device layer DL includes active (OD) regions (lines), such as active region 105, and gate (polysilicon) lines, such as gate lines 110A, 110B, 110C, and 110D. The active regions, such as active region 105, are oriented to be substantially parallel to each other and extend longitudinally along the X direction (i.e., length along the X direction, width along the Y direction, and height along the Z direction). Gate lines 110A-110D are substantially perpendicular to active region 105. For example, gate lines 110A-110D are substantially parallel to each other and extend longitudinally along the Y direction (i.e., length along the Y direction, width along the X direction, and height along the Z direction). Gate lines 110A-110D have a spacing along the X direction and a gate pitch GP along the X direction. Gate pitch GP refers to the lateral distance between the edges of directly adjacent gate lines 110A-110D. Gate pitch GP can be provided by the sum of the width of gate lines 110A-110D (along the X direction) and the spacing between directly adjacent gate lines 110A-110D (e.g., the spacing between gate lines 110A and 110B). In some embodiments, gate pitch GP is less than or equal to about 60 nm. In some embodiments, gate pitch GP is provided by the lateral distance between the centers of directly adjacent gate lines 110A-110D.

[0035] The active region includes the channel region (C), the source region, and the drain region. The source and drain regions are collectively referred to as the source / drain region (S / D). Figure 3B In the device layer DL, the active region 105 has a channel layer 116 (i.e., a channel region) disposed between the epitaxial source / drain 118 (i.e., the source / drain region), and a gate line 110B is disposed on the channel layer 116 and between the epitaxial source / drain 118. The transistor of the device layer DL is formed by the active region 105 (having the channel layer 116 and the epitaxial source / drain 118) and the gate line 110B. The gate line 110B is bonded to the channel layer 116 in a manner that facilitates current flow between the channel 116 and the epitaxial source / drain portion 118. The gate line 110B is similar to the gate structure 70. For example, the gate line 110 includes a gate stack having a gate electrode similar to the gate electrode 80 and a gate dielectric similar to the gate dielectric 82. The gate line 110B also includes a gate spacer similar to the gate spacer 86 along the sidewall of the gate stack. Gate lines 110A, 110C and 110D may also have gate stacks and gate spacers.

[0036] In some embodiments, the transistor is a planar transistor, the active region 105 is a planar active region, and the channel layer 116 and epitaxial source / drain 118 are formed in a portion of the semiconductor substrate. In some embodiments, the transistor is a GAA transistor, the active region 105 is a GAA-based active region, and the channel layer 116 is formed of one or more semiconductor layers suspended above the semiconductor substrate and extending between the epitaxial source / drain 118. In such embodiments, the gate line 110B surrounds the channel region of the suspended semiconductor layer (i.e., the suspended channel layer 116) in the XZ and YZ planes, and the epitaxial source / drain 118 is disposed above the semiconductor and can extend into the semiconductor substrate. In some embodiments, the transistor is a FinFET, the active region 105 is a FinFET-based active region, and the channel layer 116 is formed of one or more semiconductor fins extending from the semiconductor substrate and extending between the epitaxial source / drain 118. In such an embodiment, the gate line 110B wraps the channel region of the semiconductor fin (i.e., the channel layer 116) in the YZ plane, and the epitaxial source / drain 118 is disposed above the semiconductor substrate and can extend into the semiconductor substrate.

[0037] In embodiments where the active region is a FinFET-based active region and / or a GAA-based active region, the active regions may have a spacing along the Y direction and a fin pitch FP along the Y direction. The fin pitch FP refers to the lateral distance between the edges of directly adjacent fins (or suspended semiconductor layers) (i.e., directly adjacent active regions 105), and the fin pitch FP may be provided by the sum of the width of the fin (or suspended semiconductor layer) along the Y direction and the spacing between directly adjacent fins (or suspended semiconductor layers) along the Y direction. In some embodiments, the cell height CH is configured relative to the fin pitch FP. For example, the cell height CH is less than or equal to approximately ten times the fin pitch FP of the standard cell 100 (i.e., cell height CH ≤ 10 × fin pitch FP). In some embodiments, the fin pitch FP is provided by the lateral distance between the centers of directly adjacent fins.

[0038] The multilayer interconnect (MLI) includes a CO layer (with source / drain contacts MD), a V0 layer (with source / drain vias V0 and gate vias VG), an M1 layer (with M1 lines), a V1 layer (with vias V1), and an M2 layer (with M2 lines). The CO layer includes source / drain contacts 120A, 120B, and 120C. The V0 layer includes source / drain vias 125A, 125B, and 125C, and a gate via 130A. The M1 layer includes signal lines (e.g., signal lines 135A, 135B, 135C, 135D, and 135E) and power lines (e.g., power lines 140A and 140B). The V1 layer includes a via 145A, and the M2 layer includes a conductor 150A. The number of signal lines in the standard unit 100 is greater than the number of power lines. In some embodiments, the standard unit 100 has three to eight signal lines and one to two power lines. Signal lines 135A-135E, power lines 140A and 140B can be electrically connected to a voltage via upper wiring layers (e.g., V1 layer, M2 layer, etc.). This voltage can be a positive supply voltage (e.g., V...). DD ), ground voltage (e.g., V) SS (or other suitable voltage).

[0039] The CO layer electrically connects the device layer DL to the V0 layer, the V0 layer electrically connects the CO layer and / or the device layer DL to the M1 layer, and the V1 layer electrically connects the M1 layer to the M2 layer. Source / drain contacts 120A-120C are respectively located between the corresponding epitaxial source / drain 118 and source / drain vias 125A-125C, and physically contact and connect the corresponding epitaxial source / drain 118 and source / drain vias 125A-125C. Source / drain via 125A physically contacts and connects between source / drain contact 120A and signal line 135B. Source / drain via 125B is located between source / drain contact 120B and power line 140A, and physically contacts and connects source / drain contact 120B and power line 140A. A source / drain via 125C is located between the source / drain contact 120C and the power line 140A, and physically contacts and connects the source / drain contact 120C and the power line 140A. A gate via 130 is located between the gate line 110B and the signal line 135C, and physically contacts and connects the gate line 110B and the signal line 135C. A via 145A is located between the signal line 135C and the conductor 150A, and physically contacts the signal line 135C and the conductor 150A, connecting the signal line 135C to the conductor 150A. In some embodiments, the multilayer interconnect MLI electrically connects the transistors of the device layer to one or more voltages (e.g., V). DD and / or V SS This facilitates the biasing of the transistor to achieve the desired operation. In the depicted embodiment, the source of the transistor (e.g., one of the epitaxial source / drain 118) is electrically connected to the power line 140A of the M1 layer via the source / drain via 125B and the source / drain contact 120B, the drain of the transistor (e.g., one of the epitaxial source / drain 118) is electrically connected to the signal line 135B of the M1 layer via the source / drain via 125A and the source / drain contact 120A, and the gate of the transistor (e.g., gate line 110B) is electrically connected to the signal line of the M1 layer, such as one of the signal lines 135A-135E. In some embodiments, the multilayer interconnect MLI electrically connects the transistor to one or more other devices, such as devices in the device layer DL, devices within the multilayer interconnect MLI, devices in other standard cells of the IC, or devices in other regions of the IC.

[0040] The conductive components of the CO layer, M1 layer, and M2 layer are wired along a first wiring direction or a second wiring direction different from the first wiring direction. For example, the first wiring direction is the Y direction (and is substantially parallel to the longitudinal direction of the gate lines 110A-110D), and the second wiring direction is the X direction (and is substantially parallel to the longitudinal direction of the active region 105). In the depicted embodiment, the source / drain contacts 120A-120C have a longitudinal direction substantially along the Y direction (i.e., the first wiring direction), the M1 lines (i.e., signal lines 135A-135E, power lines 140A and 140B) have a length direction substantially along the X direction (i.e., the second wiring direction), and the M2 line (i.e., conductor 150A) has a length direction substantially along the Y direction (i.e., the first wiring direction). In other words, the longest dimension (e.g., length) of the source / drain contacts 120A-120C and the conductor 150 is along the Y direction, and the longest dimension of the signal lines 135A-135E, power lines 140A and 140B is along the X direction. The shortest dimension (e.g., width) of the source / drain contacts 120A-120C and the conductor 150 is along the X direction, and the shortest dimension of the signal lines 135A-135E, power lines 140A and 140B is along the Y direction. For example, signal lines 135A-135E have a width W1 along the Y direction, while power lines 140A and 140B have a width W2 along the Y direction. In the illustrated embodiment, width W2 is greater than width W1. In some embodiments, width W2 is at least 20% larger than width W1. In some embodiments, power lines 140A and 140B have different widths. In some embodiments, signal lines 135A-135E have different widths. In some embodiments, any width difference in signal lines 135A-135E is less than or equal to 20%.

[0041] The source / drain contacts 120A-120C, signal lines 135A-135E, power lines 140A and 140B, and conductor 150A are substantially rectangular (i.e., the length is greater than the width). The source / drain vias 125A-125C and via 145A are substantially square (i.e., the length is approximately equal to the width). The gate via 130 is substantially circular or elliptical. The source / drain contacts 120A-120C, source / drain vias 125A-125C, gate via 130, signal lines 135A-135E, power lines 140A and 140B, via 145A, and conductor 150A have different shapes, different sizes, different combinations of shapes and / or sizes, etc., to optimize and / or improve the performance of the standard cell 100 (e.g., reduce resistance) and / or layout footprint (e.g., reduce density).

[0042] In some embodiments, the dimensions of the source / drain vias 125A-125C are configured to fill and / or span a given amount of overlap between their corresponding M1 lines and the corresponding source / drain contacts MD. For example, turning Figure 5A The source / drain contact 120A and signal line 135B are shown without a source / drain via 125A between them, and the overlapping area OV1 (which is a shaded area) indicates the position where the signal line 135A and the source / drain contact 120A overlap each other. Go to Figure 5B A source / drain via 125A is located between and connects the source / drain contact 120A and the signal line 135B. The dimensions of the source / drain via 125A are configured to substantially cover the overlap region OV1. For example, the area of ​​the source / drain via 125A fills and / or spans approximately 50% to approximately 100% of the overlap region OV1. Figure 5B In this configuration, the area of ​​the source / drain via 125A is close to 100% (e.g., 90%) of the overlap region OV1, thus almost filling the overlap region OV1. The source / drain via 125A is bounded by the interior of the overlap region OV1 and does not extend beyond the overlap of the signal line 135A and the source / drain contact 120A.

[0043] In some embodiments, the dimensions of the V1 vias (such as via 145A) are configured to fill and / or span a given amount of overlap between their corresponding M2 lines and corresponding M1 lines. For example, turning Figure 6A Signal line 135C and conductor 150A are shown without a via 145A between them, and the overlapping area OV2 (which is shaded) indicates where signal line 135C and conductor 150A overlap each other. Go to Figure 6B A via 145A is located between and connects signal line 135C and conductor 150A, and the via 145A is sized to substantially cover the overlap region OV2. For example, the area of ​​via 145A fills and / or spans approximately 50% to approximately 100% of the overlap region OV2. Figure 6B In this configuration, the area of ​​via 145A is approximately 100% (e.g., 90%) of the overlapping region OV2, thus almost completely filling the overlapping region OV2. Via 145A is bounded by the interior of the overlapping region OV2 and does not extend beyond the overlap of signal line 135C and conductor 150A.

[0044] This disclosure proposes modulating the width of the M1 line at the M1 level to optimize the power supply or signal performance of the standard cell 100. For example, the width of the M1 line is associated with the size of the V0 via (e.g., a source / drain via), the size of the V1 via, and the size of the M2 line, such that changing the width of the M1 line results in changing the size of the V0 via, the V1 via, the M2 line, or a combination thereof.

[0045] Figure 7 and Figure 8 Part or all of the adjusted dimensions of the M1 level (and the V0 and V1 levels connected thereto) for optimizing the performance of the standard unit 100 according to various aspects of this disclosure are shown. Figure 7 and Figure 8 These are partial or complete top plan views of the multilayer interconnect MLI layout of the standard cell 100 before and after power performance optimization and signal performance optimization, such as the original (input) CO / V0 / M1 / V1 / M2 layout and the optimized (output) CO / V0 / M1 / V1 / M2 layout. For clarity, Figure 7 and Figure 8 The invention has been simplified to better understand the inventive concept of this disclosure. Additional components may be added to the depicted CO / V0 / M1 / V1 / M2 layout, and some of the described components may be replaced, modified, or eliminated in other embodiments of the CO / V0 / M1 / V1 / M2 layout.

[0046] Turning Figure 7The layout of the multilayer interconnect (MLI) is modified to optimize the power performance of the standard cell 100 without changing its cell height CH. For example, this is achieved by increasing the width of the power lines in the M1 layer, which correspondingly allows for increasing the size / dimension of the interconnects (such as source / drain vias and vias) connected to the power lines. Increasing the power lines and the interconnects connected to them (e.g., source vias and / or source contacts) can reduce the resistance associated with the power lines and correspondingly improve the power performance of the standard cell 100. In some embodiments, the width of the power lines is selected such that the size of the source vias is increased accordingly to reduce resistance and / or increase the speed of electrical signals passing through the power lines, source vias, and source / drain contacts. To maintain the cell height CH, the layout of the multilayer interconnect (MLI) is further modified by reducing the width of the signal lines in the M1 layer to offset the increase in power lines and ensure that the size of the M1 layer remains suitable for the cell height CH. While shrinking signal lines (and corresponding interconnects) may increase their resistance, this increase can be considered negligible when the standard cell 100 is implemented in applications that benefit from standard cells with optimal power performance. Therefore, width adjustments are made at the M1 level to optimize the power performance of the standard cell 100 within the process capabilities of the M1 level (e.g., dimensions that can be manufactured using existing manufacturing techniques for the standard cell 100 and / or dimensions that are not too small or too large) and the cell height CH (avoiding a complete redesign of the layout).

[0047] For example, in a power-performance optimized CO / V0 / M1 / V1 / M2 layout, signal lines 135A-135E have a width W3 that is less than width W1, and power lines 140A and 140B have a width W4 that is greater than width W2. Width W3 is less than width W4. In other words, power performance optimization increases the width of the power lines and decreases the width of the signal lines. To maintain the cell height CH, any increase in width in the power lines is offset by a decrease in width in the signal lines (i.e., signal lines 135A-135E shrink in response to the expansion of power lines 140A and 140B). The width expansion / shrinkage of the power lines and / or signal lines is less than or equal to about 20%. That is, width W4 is no more than about 20% larger than width W2, and width W3 is no more than about 20% smaller than width W1. In some embodiments, the width reduction of signal lines 135A-135E is the same as the width increase of power lines 140A and 140B. For example, if the width of power lines 140A and 140B increases by 10%, the width of signal lines 135A-135E decreases by 10%.

[0048] In some embodiments, the average power line width adjustment (ΔWP) of the M1 layers (here, power lines 140A and 140B) is less than or equal to 20%. That is, the power line width adjustment can be distributed among the power lines. For example, power line 140A can be enlarged by more than 20%, while power line 140B can be enlarged by less than 20%, wherein the width enlargement of power lines 140A and 140B is adjusted to provide an average power line width adjustment of less than or equal to 20%. In some embodiments, after power line width adjustment, the area consumed by the standard cells 100 and / or M1 layers after power performance optimization is larger than the area consumed by the standard cells 100 and / or M1 layers before power performance optimization, by as much as 20%.

[0049] In some embodiments, the average signal line width adjustment (ΔWS) of the M1 layers (here, signal lines 135A-135E) is less than or equal to 20%. That is, the signal line width adjustment can be distributed among the signal lines. For example, some of the signal lines 135A-135E may be reduced by more than 20%, and some of the signal lines 135A-135E may be reduced by less than 20%, wherein the width reduction of the signal lines 135A-135E is adjusted to provide an average signal line width adjustment of less than or equal to 20%. In some embodiments, after the signal line width adjustment, the area of ​​the standard cells 100 and / or the M1 layers consumed by the signal lines after power performance optimization is smaller than the area of ​​the standard cells 100 and / or the M1 layers consumed by the signal lines before power performance optimization, by as much as 20%.

[0050] The dimensions and / or sizes of interconnects (such as interconnects in the V0 and V1 levels) connected to the M1 line can also be adjusted and / or optimized in response to the enlargement / reduction of the M1 line. For example, adjustment / optimization may include enlarging the width and / or length of source vias connected to power lines (e.g., source / drain vias 125B and 125C connected to power line 140A), reducing the width and / or length of source vias connected to signal lines (e.g., via 145A connected to signal line 135C), and reducing the width of the M2 line connected to the signal line (e.g., conductor 150A connected to signal line 135C through via 145A). Figure 7In the original CO / V0 / M1 / V1 / M2 layout, source / drain via 125A has a dimension D1 along the Y direction, source / drain vias 125B and 125C have a dimension D2 along the Y direction, via 145A has a dimension D3 along the Y direction and a dimension D4 along the X direction, and conductor 150A has a width W5 along the X direction. Dimension D1 is smaller than width W1, dimension D2 is smaller than width W2, dimension D3 is smaller than width W1, and dimension D4 is smaller than dimension W5. In various embodiments, dimension D1 may be less than or equal to dimension D2.

[0051] After power performance tuning / optimization, in the optimized CO / V0 / M1 / V1 / M2 layout, source / drain via 120A (e.g., drain via) has a dimension D5 along the Y direction, source / drain vias 125B and 125C (e.g., source via) have a dimension D6 along the Y direction, via 145A has a dimension D7 along the Y direction and a dimension D8 along the X direction, and conductor 150A has a width W6 along the X direction. Dimension D5 is smaller than dimension D1, dimension D6 is larger than dimension D2, dimension D7 is smaller than dimension D3, dimension D8 is smaller than dimension D4, and width W6 is smaller than width W5. Therefore, in response to the increased width of power lines 140A and 140B, the size of the source vias (e.g., source / drain vias 125B and 125C) increases, the size of the drain via (e.g., source / drain via 125A) decreases, and the size of the wiring layer (e.g., via 145A and conductor 150A) directly above the signal lines 135A-135E decreases. In some embodiments, in response to the decrease in the size of the signal lines 135A-135E (due to the increased size of power lines 140A and 140B), the size of the gate via 130 may also decrease. This dimensional change at the CO, M1, and V1 levels increases the contact area between power lines 140A and 140B and their upper / lower interconnects, thereby reducing the resistance of the power line interconnect structure.

[0052] In some embodiments, the size / size adjustment of the source / drain via is configured to ensure that the source / drain via substantially covers the overlapping area between the source / drain contact MD and the M1 line. For example, in a power performance-optimized CO / V0 / M1 / V1 / M2 layout, the area of ​​source / drain via 125A fills and / or spans about 50% to about 100% of the overlapping area between source / drain contact 120A and signal line 135B, the area of ​​source / drain via 125B fills and / or spans about 50% to about 100% of the overlapping area between source / drain contact 120B and power line 140A, and the area of ​​source / drain via 125C fills and / or spans about 50% to about 100% of the overlapping area between source / drain contact 120C and power line 140A. In some embodiments, the size / size adjustment of the V1 via is configured to ensure that the V1 via substantially covers the overlapping area between the M1 and M2 lines. For example, in a power-performance optimized CO / V0 / M1 / V1 / M2 layout, the area of ​​via 145A fills and / or spans approximately 50% to approximately 100% of the overlapping area between signal line 135C and conductor 150A. In some embodiments, source / drain vias 125A-125C and via 145A may be defined by an overlapping area. For example, dimension D5 is smaller than width W3, dimension D6 is smaller than width W4, dimension D7 is smaller than width W3, and dimension D8 is smaller than dimension W6.

[0053] Turning Figure 8The layout of the multilayer interconnect (MLI) is modified to optimize the signal performance of the standard cell 100 without changing its cell height CH. For example, by increasing the width of the M1-level signal lines, this correspondingly allows for increasing the size / dimension of the interconnects (such as source / drain vias, vias, and M2 lines) connected to the signal lines. Increasing the signal lines and the interconnects connected thereto (e.g., drain vias, gate vias, vias, and M2 lines) can reduce the resistance associated with the signal lines and correspondingly improve the signal performance of the standard cell 100. In some embodiments, the width of the signal lines is selected such that the dimensions of the drain vias, gate vias, vias, M2 lines, or combinations thereof are increased accordingly to reduce resistance and / or increase the speed of electrical signal lines passing through the signal lines, drain vias, gate vias, vias, and M2 lines. To maintain the cell height CH, the layout of the multilayer interconnect (MLI) is further modified by reducing the width of the M1-level power lines to offset the increase in signal lines and ensure that the dimensions of the M1 level remain appropriate to maintain the cell height CH. While shrinking the power lines (and corresponding interconnects) may increase their resistance, this increase can be considered negligible when the standard cell 100 is implemented in applications that benefit from the optimal signal performance of the standard cell. Therefore, the width of the M1 level is adjusted to optimize the signal performance of the standard cell within the process capabilities of the M1 level (e.g., dimensions that can be manufactured using existing manufacturing techniques for the standard cell 100 and / or dimensions that are neither too small nor too large) and the cell height CH (which avoids a complete redesign of the layout).

[0054] For example, in a signal performance-optimized CO / V0 / M1 / V1 / M2 layout, signal lines 135A-135E have a width W9 greater than width W1, and power lines 140A and 140B have a width W10 less than width W2. Width W9 is less than width W10. In other words, signal performance optimization increases the width of the signal lines and decreases the width of the power lines. To maintain the cell height CH, any increase in the width of the signal lines is offset by a decrease in the width of the power lines (i.e., power lines 140A and 140B shrink in response to the expansion of signal lines 135A-135E). The expansion / shrinkage of the signal lines and / or power lines is less than or equal to about 20%. That is, width W9 is no more than about 20% larger than width W1, and width W10 is no more than about 20% smaller than width W2. In some embodiments, the increase in the width of signal lines 135A-135E is the same as the decrease in the width of power lines 140A and 140B. For example, if the width of signal lines 135A-135E increases by 10%, the width of power lines 140A and 140B decreases by 10%.

[0055] In some embodiments, the average signal line width adjustment of the M1 layers (here, signal lines 135A-135E) is less than or equal to 20%. That is, the signal line width adjustment can be distributed among the signal lines. For example, some of the signal lines 135A-135E can be increased by more than 20%, while some of the signal lines 135A-135E can be increased by less than 20%, wherein the width increase of the signal lines 135A-135E is adjusted to provide an average signal line width adjustment of less than or equal to 20%. In some embodiments, after the signal line width adjustment, the area of ​​the standard cells 100 and / or M1 layers consumed by the signal lines after signal performance optimization is 20% larger than the area of ​​the standard cells 100 and / or M1 layers consumed by the signal lines before signal performance optimization.

[0056] In some embodiments, the average power line width adjustment of the M1 layers (here, power lines 140A and 140B) is less than or equal to 20%. That is, the power line width adjustment can be distributed throughout the power lines. For example, power line 140A can be reduced by more than 20% and power line 140B can be reduced by less than 20%, wherein the width reduction of power lines 140A and 140B is adjusted to provide an average power line width adjustment of less than or equal to 20%. In some embodiments, after the power line width adjustment, the area of ​​the standard cell 100 and / or M1 layers consumed by the power lines after power performance optimization is smaller than the area of ​​the standard cell 100 and / or M1 layers consumed by the power lines before power performance optimization, by as much as 20%.

[0057] The dimensions and / or sizes of interconnects (such as interconnects in the V0 and V1 levels) connected to the M1 level can also be adjusted and / or optimized in response to the enlargement / reduction of the M1 line. For example, adjustment / optimization may include increasing the width and / or length of drain vias connected to signal lines (e.g., source / drain via 125A connected to signal line 135B), increasing the width and / or length of V1 vias connected to signal lines (e.g., via 145A connected to signal line 135C), and increasing the width of M2 lines connected to signal lines (e.g., conductor 150A connected to signal line 135C through via 145A). Figure 8In the original CO / V0 / M1 / V1 / M2 layout, source / drain via 125A has a dimension D1, source / drain vias 125B and 125C have a dimension D2, via 145A has dimensions D3 and D4, and conductor 150A has a width W5. After signal performance tuning / optimization, in the signal performance optimized CO / V0 / M1 / V1 / M2 layout, source / drain via 125A (e.g., drain via) has a dimension D9 along the Y direction, source / drain vias 125B and 125C (e.g., source via) have a dimension D10 along the Y direction, via 145A has a dimension D11 along the Y direction and a dimension D12 along the X direction, and conductor 150A has a width W7 along the X direction. Dimension D9 is larger than dimension D1, dimension D10 is smaller than dimension D2, dimension D11 is larger than dimension D3, dimension D12 is larger than dimension D4, and width W7 is smaller than width W5. Therefore, in response to the increased width of signal lines 135A-135E, the size of the drain via (e.g., source / drain via 125A) increases, the size of the wiring layer directly above signal lines 135A-135E (e.g., via 145A and conductor 150A) increases, and the size of the source vias (e.g., source / drain via 125B and source / drain via 125C) decreases. In some embodiments, in response to the increased width of signal lines 135A-135E, the size of the gate via 130 along the X and / or Y directions may also be increased. This dimensional change at the CO, M1, and V1 levels increases the contact area between signal lines 135A-135E and their upper / lower interconnects, thereby reducing the resistance of the signal line interconnect structure.

[0058] In some embodiments, the size adjustment of the source / drain via is configured to ensure that the source / drain via substantially covers the overlapping area between the source / drain contact MD and the M1 line. For example, in a signal performance-optimized CO / V0 / M1 / V1 / M2 layout, the area of ​​the source / drain via 125A fills and / or spans approximately 50% to approximately 100% of the overlapping area between the source / drain contact 120A and the signal line 135B. In some embodiments, the size / size adjustment of the V1 via is configured to ensure that the V1 via substantially covers the overlapping area between the M1 and M2 lines. For example, in a signal performance-optimized CO / V0 / M1 / V1 / M2 layout, the area of ​​the via 145A fills and / or spans approximately 50% to approximately 100% of the overlapping area between the signal line 135C and the conductor 150. In embodiments, the source / drain vias and / or the V1 vias are bounded by the overlapping area. For example, dimension D9 is smaller than width W9, and the dimension of source / drain via 125A along the X direction is smaller than the dimension of source / drain contact 120A along the X direction. In another example, dimension D11 is smaller than width W9, and dimension D12 is smaller than width W7.

[0059] This disclosure further envisions reducing the length of the M2 line (such as conductor 150A) during signal performance tuning / optimization. For example, Figure 9 This is a partial or complete top plan view of the multilayer interconnect MLI layout of the standard cell 100 after signal performance optimization. For clarity and to better understand the inventive concept of this disclosure, Figure 9 It has been simplified. Additional components can be added to the depicted CO / V0 / M1 / V1 / M2 layout, and some of the described components can be replaced, modified, or eliminated in other embodiments of the CO / V0 / M1 / V1 / M2 layout.

[0060] Figure 9 Signal performance optimization CO / V0 / M1 / V1 / M2 layout is similar Figure 8 The signal performance is optimized for the CO / V0 / M1 / V1 / M2 layout, except that the via 145A and the conductor 150A have different dimensions. For example, in Figure 9In this embodiment, conductor 150A has a width W8 along the X direction. Width W8 is greater than width W5, and in the illustrated embodiment, greater than width W7. In some embodiments, width W8 is approximately 1 to approximately 3 times larger than width W5. In some embodiments, the ratio of width W8 to width W5 is approximately 2:1 to approximately 4:1. Increasing the width of the M2 line (e.g., conductor 150A) allows for a wider pitch at the M2 level (i.e., the pitch of the M2 line can be larger in a standard cell optimized for signal performance), which can reduce manufacturing complexity and / or manufacturing costs. In some embodiments, increasing the width of the V1 via and / or M2 line can reduce the number of patterning processes required to manufacture the V1 via and / or M2 line. For example, when manufacturing the V1 via and / or M2 line based on a signal-optimized CO / V0 / M1 / V1 / M2 layout, a single patterning can be implemented, whereas dual patterning may be required when manufacturing the V1 via and / or M2 line based on the original CO / V0 / M1 / V1 / M2 layout. In some embodiments, less complex and / or less costly photolithography, etching, deposition, and other processes can be implemented to fabricate larger V1 vias and / or M2 lines, such as those in the signal optimization CO / V0 / M1 / V1 / layout.

[0061] In some embodiments, extending the signal line can allow for a reduction in the length of the M2 line. For example, in the original optimized CO / V0 / M1 / V1 / M2, conductor 150A may have a length L1 along the Y direction, and after signal performance optimization, conductor 150A may have a length L2 along the Y direction, such as in... Figure 9 Signal performance optimization is performed in CO / V0 / M1 / V1 / M2. Length L2 is less than length L1. In some embodiments, length L2 is approximately 1 to approximately 0.3 times the length L1. Figure 9 In this embodiment, because the width of the conductor 150A is relatively large, the dimension D13 of the via 145A along the X direction is larger than the dimension D3, and in the depicted embodiment, it is larger than the dimension D12. In some embodiments, the area of ​​the via 145A after signal performance optimization (e.g., the area of ​​the top contact surface) is approximately 1 to approximately 3.6 times the area of ​​the via 145A before signal performance optimization.

[0062] Figure 10A Partial or overall top plan views depicting the layout of the multilayer interconnect MLI of a standard cell 100 before optimization, after power performance optimization, and after signal performance optimization, according to various aspects of this disclosure. Figure 10A It is evident that by implementing the design techniques described herein, the standard cell 100 can be optimized for different applications (e.g., power-sensitive or signal-sensitive) while maintaining the size of the cell boundary LC. Figure 10BAccording to various aspects of this disclosure, portions of a multilayer interconnect MLI (e.g., portions of CO / V0 / M1) fabricated based on a standard cell multilayer interconnect MLI layout are depicted before optimization, after power performance optimization, and after signal performance optimization. Figure 10A A partial or complete schematic diagram of line BB. In the depicted embodiments, the cell height H and cell width W are the same for both the original and optimized layouts, thereby providing performance optimization within the process capabilities of a given cell size. In some embodiments, performance optimization and / or signal optimization maintain the cell height H while increasing or decreasing the cell width W. For clarity and to better understand the inventive concepts of this disclosure, Figure 10A and Figure 10B It has been simplified. Additional components can be added to the layout of the Multilayer Interconnect (MLI), and some of the described components can be replaced, modified, or eliminated in other embodiments of the MLI layout.

[0063] Figure 11 This is a flowchart of method 200, which can be performed for the design and / or fabrication of a standard cell (such as logic design and / or logic fabrication), according to various aspects of this disclosure. Method 200 implements the concepts described herein to optimize the performance of a standard cell (e.g., standard cell 100). Method 200 begins at block 210, receiving an IC layout of the standard cell. The IC layout includes power lines, signal lines, a first via connected to the power lines, and a second via connected to the signal lines. In some embodiments, the power lines and signal lines are portions of the M1 level (i.e., the bottommost wiring layer) of a multilayer interconnect MLI for the standard cell. In such embodiments, the first and second vias may be source / drain vias (e.g., V0 level vias of a multilayer interconnect MLI) or V1 level vias of a multilayer interconnect MLI. In some embodiments, the standard cell has a cell height.

[0064] At block 215, method 200 includes determining desired performance optimizations for a standard cell. For example, if the standard cell is used in an application that benefits from enhanced power signals, then the desired performance optimization is power optimization. If the standard cell is used in an application that benefits from enhanced signal signals, then the desired performance optimization is signal optimization. In some embodiments, this determination is based on the design specifications of the standard cell. For example, when the power parameters defined by the design specifications of the standard cell are based on a received integrated circuit layout and are difficult to obtain using the processing power required to manufacture the standard cell at its cell size, the desired performance optimization is determined to be power optimization. In another example, when the signal performance parameters defined by the design specifications are based on a received integrated circuit layout and are difficult to obtain using the processing power required to manufacture the standard cell at its cell size, the desired performance optimization is determined to be signal optimization. In another example, when obtaining the design-specified, signal-related parameters using the processing power required to manufacture the standard cell at its cell size is more difficult than obtaining the design-specified, power-related parameters, the desired performance optimization is determined to be signal optimization. In yet another example, when obtaining the design-specified, power-related parameters using the processing power required to manufacture the standard cell at its cell size is more difficult than obtaining the design-specified, signal-related parameters, the desired performance optimization is determined to be power optimization.

[0065] In some embodiments, this determination is based on the material selection of power lines, signal lines, and their associated interconnects (e.g., first and second vias, respectively). For example, it can be observed that power lines and the first via exhibit increased resistance when formed of a first conductive material, while signal lines and the second via exhibit less (or negligible) resistance increase when formed of the first conductive material. In such an example, desired performance optimization is determined to be power optimization to offset the resistance increase that may be caused by the power interconnect structure formed of the first conductive material. In another example, it can be observed that signal lines and the second via exhibit increased resistance when formed of a second conductive material, while power lines and the first via exhibit less (or negligible) resistance increase when formed of the second conductive material. In such an example, desired performance optimization is determined to be signal optimization to offset the resistance increase that may be caused by the signal interconnect structure formed of the second conductive material.

[0066] In some embodiments, process simulation and / or device simulation are performed using integrated circuit layout to obtain information about standard cells manufactured from the integrated circuit layout. If simulation results indicate that the power-related characteristics and / or parameters of the standard cell are more sensitive to the dimensions and / or size of vias, contacts, wiring, etc., of the multilayer interconnects of the standard cell, power optimization is determined to be a desired performance optimization. If simulation results indicate that the signal-related characteristics and / or parameters of the standard cell are more sensitive to the dimensions and / or size of vias, contacts, wiring, etc., of the multilayer interconnects of the standard cell, signal optimization is determined to be a desired performance optimization.

[0067] At block 220, method 200 includes adjusting the dimensions of power lines, signal lines, first vias, and second vias based on desired performance optimization. The power line size is related to the signal line size and the first via size, and the second via size is related to the signal line size. Therefore, a change in the power line size results in a change in the signal line size, the first via size, and the second via size. For example, where the desired performance optimization is power optimization (e.g., the process budget for the M1 level of a multilayer interconnect MLI is allocated to power), method 200 includes increasing the power line size and the first via size and decreasing the signal line size and the second via size, as described herein. In another example, where the desired performance optimization is signal optimization (e.g., the process budget for the M1 level is allocated to signals), method 200 includes decreasing the power line size and the first via size and increasing the signal line size and the via size, as described herein. Adjustment of the first via size (e.g., the size of a source via) and the second via size (e.g., the size of a drain via) may be constrained by the dimensions of the transistors in a standard cell (e.g., the dimensions of the source / drain and gate).

[0068] In some embodiments, a modified integrated circuit layout is generated by adjusting the dimensions of power lines, signal lines, first vias, and second vias based on desired performance optimization. The modified integrated circuit layout provides standard cells with the same cell height as the standard cells provided by the received integrated circuit layout. In some embodiments, at block 225, method 200 includes manufacturing standard cells based on the modified integrated circuit layout. The standard cells can be optimized for power-based or signal-based applications, as described herein. Additional steps may be provided before, during, and after method 200, and for additional embodiments of method 200, some of the described steps may be moved, replaced, or eliminated.

[0069] The various conductive components of the multilayer interconnect (MLI) described herein, such as contacts, vias, and / or metal lines, may include tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, other low-resistivity metals, alloys thereof, or combinations thereof. In some embodiments, the conductive material of the source / drain vias V0 and / or gate vias VG at the V0 level differs from the conductive material of the M1 lines at the M1 level. For example, the M1 lines (e.g., signal lines 135A-135E, power lines 140A and 140B) comprise copper, while the source / drain vias V0 (e.g., source / drain vias 125A-125C) and / or gate vias VG (e.g., gate via 130A) comprise tungsten or ruthenium. In some embodiments, the conductive material of the source / drain vias V0 and / or gate vias VG at the V0 level is the same as the conductive material of the M1 lines at the M1 level. In some embodiments, the various layers of the multilayer interconnect MLI described herein, such as CO, V0, M1, V1, and M2 layers, can be fabricated by the following steps: depositing a dielectric layer (e.g., an ILD layer and / or CESL) on a substrate; performing photolithography and etching processes to form one or more openings in the dielectric layer, the openings exposing one or more conductive components in the underlying layer; filling the one or more openings with a conductive material; and performing a planarization process to remove excess conductive material, such that the conductive components and the dielectric layer have substantially flat surfaces. The conductive material is formed by a deposition process (e.g., PVD, CVD, ALD, etc.) and / or an annealing process. In some embodiments, the conductive component includes a body layer (also referred to as a conductive plug). In some embodiments, the conductive component includes a barrier layer, an adhesive layer, other suitable layers, etc., disposed between the body layer and the dielectric layer. In some embodiments, the barrier layer, adhesive layer, other suitable layers, etc., include titanium, titanium alloys (e.g., TiN), tantalum, tantalum alloys (e.g., TaN), other suitable components, or combinations thereof. In some embodiments, the via layer (e.g., V0 level) and metallization layer (e.g., M1 level) of the multilayer interconnect MLI can be formed by a single damascene or dual damascene process.

[0070] Figure 12 The illustration shows an IC manufacturing system 300 according to various aspects of this disclosure. The IC manufacturing system 300 includes multiple entities 302, 304, 306, 308, 310, 312, 314, 316, ..., N connected by a communication network 318. The communication network 318 may be a single network or various different networks, such as intranets and the Internet, and may include wired and wireless communication channels.

[0071] In some embodiments, entity 302 represents a service system for manufacturing collaboration; entity 304 represents a user, such as a product engineer monitoring IC products; entity 306 represents an engineer, such as a processing engineer controlling IC manufacturing and related formulations, or an equipment engineer monitoring or adjusting the conditions and settings of IC manufacturing tools; entity 308 represents a metrology tool for IC testing and measurement; entity 310 represents a semiconductor and / or IC processing tool; entity 312 represents a virtual metrology module associated with entity 310; entity 314 represents an advanced processing control module associated with entity 310 and other processing tools; and entity 316 represents a sampling module associated with entity 310.

[0072] Each entity can interact with other entities and can provide or receive integrated circuit manufacturing, processing control, computing power, etc., from other entities. Each entity may also include one or more computer systems for performing computations and automation. For example, the advanced processing control module of entity 314 may include multiple computer hardware components in which software instructions are encoded. The computer hardware may include hard disk drives, flash drives, CD-ROMs, RAM memory, display devices (e.g., monitors), and input / output devices (e.g., mice and keyboards). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks, such as those related to optimizing the manufacturing of the aforementioned standard units.

[0073] IC manufacturing system 300 enables interaction between entities for IC design and manufacturing, as well as advanced processing control in IC manufacturing. One capability provided by IC manufacturing system 300 is the ability to enable collaboration and information access in areas such as design, engineering and processing, metrology, and advanced processing control. Another capability provided by IC manufacturing system 300 is the ability to integrate systems between facilities, such as between metrology tools and processing tools. This integration enables facilities to coordinate their activities. IC manufacturing system 300 can be used to perform methods such as method 200 described herein and related layout optimizations. For example, one or more of entities 302-716 can receive IC layout designs from a design company and then modify the received IC layout designs by adjusting the dimensions of the V0, M1, V2, and M2 layers of the multilayer interconnect MLI of standard cells.

[0074] This disclosure provides numerous different embodiments. An exemplary method includes receiving an integrated circuit layout of standard cells having a cell height. The integrated circuit layout includes power lines, signal lines, a first source / drain via connected to the power lines, and a second source / drain via connected to the signal lines. The method further includes adjusting the dimensions of the power lines, signal lines, the first source / drain via, and the second source / drain via to generate a modified integrated circuit layout of the standard cells having a cell height. The dimension adjustment is based on desired performance optimization of the standard cells and includes associating power line dimensions with signal line dimensions, associating power line dimensions with the first source / drain via dimensions, and associating signal line dimensions with the second source / drain via dimensions, such that changes in the power line dimensions correspond to changes in the signal line dimensions, the first source / drain via dimensions, and the second source / drain via dimensions. The method also includes manufacturing the standard cells based on the modified integrated circuit layout.

[0075] In some embodiments, the desired performance optimization is power performance optimization, where the power line size is the power line width and the signal line size is the signal line width. The power line width, signal line width, first source / drain via size, and second source / drain via size are along the same direction, and the size adjustment includes: increasing the power line width and the first source / drain via size, and decreasing the signal line width and the second source / drain via size.

[0076] In some embodiments, the desired performance optimization is signal performance optimization, where the power line size is the power line width and the signal line size is the signal line width. The power line width, signal line width, first source / drain via size, and second source / drain via size are along the same direction, and the size adjustment includes: increasing the signal line width and second source / drain via size, and decreasing the power line width and first source / drain via size.

[0077] In some embodiments, the integrated circuit layout further includes vias and conductors. The vias connect conductors to signal lines. The method may also include adjusting the dimensions of the vias and conductors to generate a modified integrated circuit layout of standard cells with cell heights. The dimensional adjustment includes associating the via dimensions with signal line dimensions and the conductor dimensions with signal line dimensions, such that changes in the via and conductor dimensions correspond to changes in the signal line dimensions.

[0078] In some embodiments, the power line size is the power line width, the signal line size is the signal line width, and the conductor size is the conductor width. The power line width, signal line width, first source / drain via size, second source / drain via size, and via size are along a first direction, and the conductor width is along a second direction. Size adjustments include: when performance optimization is desired for power performance optimization, increasing the power line width and first source / drain via size, and decreasing the signal line width, second source / drain via size, via size, and conductor width. Size adjustments also include: when performance optimization is desired for signal performance optimization, decreasing the power line width and first source / drain via size, and increasing the signal line width, second source / drain via size, via size, and conductor width.

[0079] In some embodiments, the conductors further have a conductor length along a first direction, and the sizing adjustment further includes reducing the conductor length when the desired performance optimization is signal performance optimization. In some embodiments, the via size is a first via size, and the via further has a second via size along a second direction, and the sizing adjustment further includes increasing the second via size when the desired performance optimization is signal performance optimization. In some embodiments, the integrated circuit layout further includes gate lines, and the power line size and signal line size are along the longitudinal direction of the gate lines. In some embodiments, the percentage change in the power line size is the same as the percentage change in the signal line size.

[0080] Another exemplary method includes receiving an interconnect layout of a standard cell. The interconnect layout includes a metallization layer and a via layer. The metallization layer includes a first conductor and a second conductor, and the via layer includes a first via and a second via. The first via is connected to the first conductor and the source of a transistor, and the second via is connected to the second conductor and the drain of a transistor. The method also includes modifying the interconnect layout of the standard cell. Modifications include: if the performance of the standard cell is sensitive to a first type of performance characteristic, enlarging the first conductor and the first via and shrinking the second conductor and the second via. Modifications to the interconnect layout include: if the performance of the standard cell is sensitive to a second type of performance characteristic different from the first type, shrinking the first conductor and the first via and enlarging the second conductor and the second via.

[0081] The method also includes manufacturing interconnects for the standard cells using a modified interconnect layout of the standard cells. In some embodiments, the amount of enlargement is the same as the amount of reduction. In some embodiments, the amount of enlargement and reduction is ≤20%. In some embodiments, the standard cells have a cell size and modifying the interconnect layout of the standard cells does not modify the cell size. In some embodiments, the transistor includes a gate extending longitudinally along a first direction, and a first wire and a second wire extending longitudinally along a second direction different from the first direction.

[0082] In some embodiments, the metallization layer is a first metallization layer and the via layer is a first via layer, and the first metallization layer further includes a third conductor. The first conductor, second conductor, and third conductor of the first metallization layer extend longitudinally along a first direction. The interconnect layout also includes a second metallization layer and a second via layer. The second metallization layer includes a fourth conductor extending longitudinally along a second direction different from the first direction, and the second via layer includes a third via connecting the fourth conductor of the second metallization layer to the third conductor of the first metallization layer. In some embodiments, modifying the interconnect layout of the standard cell further includes reducing the size of the third via and the fourth conductor and enlarging the third conductor if the performance of the standard cell is sensitive to a first type of performance characteristic. In some embodiments, modifying the interconnect layout of the standard cell further includes enlarging the third via and reducing the size of the third conductor if the performance of the standard cell is sensitive to a second type of performance characteristic.

[0083] In some embodiments, modifying the interconnect layout of the standard cell further includes enlarging the fourth conductor if the performance of the standard cell is sensitive to a second type of performance characteristic. In some embodiments, enlarging the fourth conductor includes enlarging the fourth conductor along a first direction. In some embodiments, modifying the interconnect layout of the standard cell further includes shrinking the fourth conductor along a second direction if the performance of the standard cell is sensitive to a second type of performance characteristic.

[0084] An exemplary integrated circuit system includes a processor and a communication module communicatively coupled to the processor and configured to receive a device layout of a standard cell. The device layout of the standard cell includes transistors and multilayer interconnects. The multilayer interconnects include power lines, signal lines, source contacts connected to the sources of the power lines and transistors, and drain contacts connected to one of the signal lines and the drain of the transistors. The integrated circuit (IC) system also includes a non-transitory computer-readable storage device communicatively coupled to the processor and including instructions executable by the processor. These instructions include instructions for modifying the device layout of the standard cell. Modification of the device layout includes enlarging the power lines and source contacts and shrinking the signal lines and drain contacts if the performance of the standard cell is sensitive to power-related characteristics, and shrinking the power lines and source contacts and enlarging the signal lines and drain contacts if the performance of the standard cell is sensitive to signal-related characteristics. In some embodiments, the instructions also include adjusting the amount of enlargement to be the same as the amount of shrinkage.

[0085] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A method for forming an integrated circuit, comprising: An integrated circuit layout for receiving standard cells, the standard cells having a cell height, wherein the integrated circuit layout includes power lines, signal lines, a first source / drain via connected to the power lines, and a second source / drain via connected to the signal lines; Adjusting multiple dimensions of the power lines, signal lines, the first source / drain via, and the second source / drain via to generate a modified integrated circuit layout of the standard cell having the cell height, wherein: the adjustment of the multiple dimensions is based on desired performance optimization of the standard cell, and the adjustment of the multiple dimensions includes associating the power line dimensions with the signal line dimensions, associating the power line dimensions with the first source / drain via dimensions, and associating the signal line dimensions with the second source / drain via dimensions, such that changes in the power line dimensions correspond to changes in the signal line dimensions, the first source / drain via dimensions, and the second source / drain via dimensions; and The standard cell is manufactured based on the modified integrated circuit layout. in: The power line and the signal line extend longitudinally along the first direction; The power line size is the power line width, and the signal line size is the signal line width; The power line width, the signal line width, the size of the first source / drain via, and the size of the second source / drain via are along a second direction intersecting the first direction; and When the desired performance optimization is signal performance optimization, the adjustment of the plurality of dimensions includes: Increase the signal line width and the second source / drain via size, and decrease the power line width and the first source / drain via size.

2. The method according to claim 1, wherein: When the desired performance optimization is power performance optimization... The adjustments to the multiple dimensions include: Increase the width of the power line and the size of the first source / drain via, and decrease the width of the signal line and the size of the second source / drain via.

3. The method according to claim 1, wherein: The increase is the same as the decrease.

4. The method according to claim 1, wherein, The integrated circuit layout further includes vias and conductors, wherein the vias connect the conductors to the signal lines, and the method further includes: The dimensions of the vias and the conductors are adjusted to generate the modified integrated circuit layout of the standard cell having the cell height, wherein: The adjustment of the plurality of dimensions includes associating the via size with the signal line size and associating the conductor size with the signal line size, such that changes in the via size and the conductor size correspond to changes in the signal line size.

5. The method according to claim 4, wherein: The conductor dimension is the conductor width, and the conductor extends longitudinally along the second direction; and The adjustments to the multiple dimensions include: When the desired performance optimization is power performance optimization, the power line width and the first source / drain via size are increased, and the signal line width, the second source / drain via size, the via size, and the conductor width are decreased. When the desired performance optimization is signal performance optimization, the via size and the conductor width are increased.

6. The method according to claim 5, wherein: The conductor also has a conductor length along the first direction; and When the desired performance optimization is signal performance optimization, the adjustment of the plurality of dimensions also includes reducing the length of the conductor.

7. The method according to claim 5, wherein: The through-hole size is a first through-hole size, and the through-hole also has a second through-hole size along the second direction; and The adjustment of the plurality of dimensions also includes increasing the second via size when the desired performance optimization is signal performance optimization.

8. The method according to claim 1, wherein, The integrated circuit layout also includes gate lines, and the power line dimensions and the signal line dimensions are along the longitudinal direction of the gate lines.

9. The method according to claim 1, wherein, The percentage change in the power line size is the same as the percentage change in the signal line size.

10. A method for forming an integrated circuit, comprising: The interconnect layout of the receiving standard cell includes a metallization layer and a via layer. The metallization layer includes a first conductor and a second conductor, and the via layer includes a first via and a second via. The first via is connected to the first conductor and the source of the transistor, and the second via is connected to the second conductor and the drain of the transistor. The first conductor and the second conductor of the metallization layer extend longitudinally along a first direction. Modifying the interconnect layout of the standard cell, wherein the modification of the interconnect layout includes: if the performance of the standard cell is sensitive to a first type of performance characteristic, then enlarging the first conductor and the first via and shrinking the second conductor and the second via; and if the performance of the standard cell is sensitive to a second type of performance characteristic different from the first type, then shrinking the first conductor and the first via and enlarging the second conductor and the second via in a second direction intersecting the first direction; and The interconnects of the standard cell are manufactured using the modified interconnect layout of the standard cell.

11. The method according to claim 10, wherein, The amount of expansion is the same as the amount of contraction.

12. The method according to claim 11, wherein, The amount of expansion and the amount of contraction are ≤20%.

13. The method of claim 10, wherein: The metallization layer is a first metallization layer, and the via layer is a first via layer; The first metallization layer further includes a third conductive line, wherein the third conductive line extends longitudinally along the first direction; The interconnect layout further includes a second metallization layer and a second via layer, wherein the second metallization layer includes a fourth conductor extending longitudinally along a second direction different from the first direction, and the second via layer includes a third via connecting the fourth conductor of the second metallization layer to the third conductor of the first metallization layer; and Modifying the interconnection layout of the standard cell further includes: If the performance of the standard unit is sensitive to the performance characteristics of the first type, then the third via and the fourth conductor are reduced in size and the third conductor is enlarged. If the performance of the standard unit is sensitive to the performance characteristics of the second type, then the third via is enlarged and the third conductor is reduced.

14. The method according to claim 13, wherein, Modifying the interconnect layout of the standard cell further includes enlarging the fourth conductor if the performance of the standard cell is sensitive to the performance characteristics of the second type.

15. The method according to claim 14, wherein, Expanding the fourth conductor includes expanding the fourth conductor along the first direction.

16. The method according to claim 15, wherein, Modifying the interconnect layout of the standard cell further includes: if the performance of the standard cell is sensitive to the performance characteristics of the second type, then reducing the fourth wire along the second direction.

17. The method according to claim 11, wherein, The standard cell has a cell size, and modifying the interconnection layout of the standard cell does not modify the cell size.

18. The method of claim 10, wherein: The transistor includes a gate extending longitudinally along a first direction; and The first conductor and the second conductor extend longitudinally along a second direction different from the first direction.

19. An integrated circuit system, comprising: processor; A communication module, communicatively coupled to the processor and configured to receive a device layout of a standard cell, the device layout including transistors and multilayer interconnects, wherein the multilayer interconnects include power lines, signal lines, source contacts connected to the power lines and the sources of the transistors, and drain contacts connected to one of the signal lines and the drain of the transistor; and A non-transitory computer-readable storage, communicatively coupled to the processor and including instructions executable by the processor, the instructions including: Instructions for modifying the device layout of the standard cell, wherein the modification of the device layout includes: enlarging the power lines and the source contacts and shrinking the signal lines and the drain contacts if the performance of the standard cell is sensitive to power-related characteristics; and shrinking the power lines and the source contacts and enlarging the signal lines and the drain contacts if the performance of the standard cell is sensitive to signal-related characteristics.

20. The integrated circuit system according to claim 19, wherein, The instruction also includes adjusting the amount of expansion to be the same as the amount of reduction.

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