Array substrate, display panel and display device

Abstract

The application provides an array substrate, a display panel and a display device. The array substrate comprises a substrate, a plurality of pixel driving circuits and a plurality of signal lines. The pixel driving circuits and the signal lines are located on the same side of the substrate. The pixel driving circuit comprises a driving transistor and a regulating transistor. The signal line comprises a scanning signal line, a regulating signal line and a power signal line. The scanning signal line comprises a regulating control signal line. The first electrode of the driving transistor is electrically connected with the power signal line. The first electrode of the regulating transistor is electrically connected with the regulating signal line. The second electrode of the regulating transistor is electrically connected with the first electrode of the driving transistor or the second electrode of the driving transistor. The gate electrode of the regulating transistor is electrically connected with the regulating control signal line. The scanning signal line extends along a first direction. The regulating signal line extends along a second direction and is different from the scanning signal line in layers. The first direction intersects with the second direction. The embodiment of the application can reduce the size of the pixel driving circuit along the second direction and improve the display resolution.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] In the prior art display panel technology, there are mainly two mainstream technologies, i.e. liquid crystal display panel and organic self-luminous display panel. The liquid crystal display panel forms an electric field capable of controlling the deflection of liquid crystal molecules by applying a voltage on the pixel electrode and the common electrode in the display panel, thereby controlling the transmission of light to realize the display function of the display panel. The organic self-luminous display panel adopts organic electroluminescent material, which emits light when a current passes through the organic electroluminescent material, thereby realizing the display function of the display panel.

[0003] With the application of display technology in smart wear and other portable electronic devices, the design of electronic products is constantly pursuing the smooth use experience of users, and at the same time, the sensory experience of users is also increasingly pursued. For example, wide viewing angle, high resolution, narrow frame, high screen ratio and other performances have become the selling points of various electronic products. SUMMARY

[0004] The present application provides an array substrate, a display panel and a display device to realize the reduction of the size of the pixel driving circuit along the second direction and the improvement of the display resolution.

[0005] In a first aspect, an array substrate is provided, comprising a substrate, a plurality of pixel driving circuits and a plurality of signal lines, the pixel driving circuits and the signal lines are located on the same side of the substrate.

[0006] The pixel driving circuit comprises a driving transistor and a regulating transistor, and the signal line comprises a scanning signal line, a regulating signal line and a power signal line; the scanning signal line comprises a regulating control signal line.

[0007] The first electrode of the driving transistor is electrically connected with the power signal line.

[0008] The first electrode of the regulating transistor is electrically connected with the regulating signal line, the second electrode of the regulating transistor is electrically connected with the first electrode of the driving transistor or the second electrode of the driving transistor, and the gate electrode of the regulating transistor is electrically connected with the regulating control signal line.

[0009] The scanning signal line extends along a first direction, the regulating signal line extends along a second direction and is in a different layer from the scanning signal line, and the first direction intersects the second direction.

[0010] In a second aspect, an embodiment of the present application provides a display panel, comprising the array substrate of the first aspect, and a plurality of light emitting elements disposed on the array substrate.

[0011] In a third aspect, an embodiment of the present application provides a display device, comprising the display panel of the second aspect.

[0012] In an embodiment of the present application, the extension direction of the scan signal line is different from the extension direction of the adjusting signal line. The scan signal line extends along a first direction, and the adjusting signal line extends along a second direction. It can be understood that for a plurality of signal lines extending along the first direction and arranged along the second direction, a certain spacing is required between two adjacent signal lines along the second direction. The more the signal lines arranged along the second direction, the more space occupied along the second direction. In the embodiment of the present application, the adjusting signal line extends along the second direction, and the adjusting signal line does not extend along the first direction X. The adjusting signal line does not occupy the arrangement space along the second direction, thereby reducing the size of the pixel driving circuit along the second direction. This is beneficial to improve the pixel density (i.e. the number of pixels per inch) and improve the display resolution. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 A top view structural schematic diagram of an array substrate provided by an embodiment of the present application;

[0014] Figure 2 A circuit structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application;

[0015] Figure 3 A top view structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application;

[0016] Figure 4 A sectional view structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application;

[0017] Figure 5 A top view structural schematic diagram of a silicon semiconductor layer provided by an embodiment of the present application;

[0018] Figure 6 A top view structural schematic diagram of a first metal layer provided by an embodiment of the present application;

[0019] Figure 7 A top view structural schematic diagram of a capacitor metal layer provided by an embodiment of the present application;

[0020] Figure 8 A top view structural schematic diagram of a second metal layer provided by an embodiment of the present application;

[0021] Figure 9This is a top view schematic diagram of another array substrate provided in an embodiment of the present invention;

[0022] Figure 10 This is a top view of a third metal layer provided in an embodiment of the present invention;

[0023] Figure 11 A top view schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0024] Figure 12 for Figure 11 A partial structural diagram of the pixel driving circuit shown in the figure;

[0025] Figure 13 A top view schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0026] Figure 14 For along Figure 13 A schematic diagram of the cross-sectional structure of AA';

[0027] Figure 15 for Figure 11 Another partial structural diagram of the pixel driving circuit shown;

[0028] Figure 16 For along Figure 15 A schematic diagram of the cross-sectional structure of BB';

[0029] Figure 17 A top view schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0030] Figure 18 A top view schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0031] Figure 19 For along Figure 18 A schematic diagram of the cross-sectional structure of CC';

[0032] Figure 20 A top view schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0033] Figure 21 For along Figure 20 A schematic diagram of the cross-sectional structure of DD';

[0034] Figure 22 This is a top view of another third metal layer provided in an embodiment of the present invention;

[0035] Figure 23 This is a top view of a fourth metal layer provided in an embodiment of the present invention;

[0036] Figure 24 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application;

[0037] Figure 25 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application; Figure 24 A partial structural schematic diagram of the pixel driving circuit shown in the embodiment of the present application;

[0038] Figure 26 A cross-sectional structural schematic diagram of the EE' in the embodiment of the present application; Figure 25

[0039] Figure 27 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application;

[0040] Figure 28 A cross-sectional structural schematic diagram of the FF' in the embodiment of the present application; Figure 27

[0041] Figure 29 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application;

[0042] Figure 30 A cross-sectional structural schematic diagram of the GG' in the embodiment of the present application; Figure 29

[0043] A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application; Figure 31

[0044] A cross-sectional structural schematic diagram of the HH' in the embodiment of the present application; Figure 32 Figure 31 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application;

[0045] Figure 33 A cross-sectional structural schematic diagram of the II' in the embodiment of the present application;

[0046] Figure 34 Figure 33 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application;

[0047] Figure 35 A top view structural schematic diagram of another silicon semiconductor layer provided by the embodiment of the present application;

[0048] Figure 36 A top view structural schematic diagram of another first metal layer provided by the embodiment of the present application;

[0049] Figure 37 A top view structural schematic diagram of another capacitor metal layer provided by the embodiment of the present application;

[0050] Figure 38 A top view structural schematic diagram of another capacitor metal layer provided by the embodiment of the present application; ​​​​

[0051] Figure 39 Another top view structural schematic diagram of a second metal layer provided by an embodiment of the present application is shown in FIG. 6.

[0052] Figure 40 Another top view structural schematic diagram of a third metal layer provided by an embodiment of the present application is shown in FIG. 7.

[0053] Figure 41 Another top view structural schematic diagram of a fourth metal layer provided by an embodiment of the present application is shown in FIG. 8.

[0054] Figure 42 A cross-sectional structural schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 9.

[0055] Figure 43 A schematic diagram of a display device provided by an embodiment of the present application is shown in FIG. 10. DETAILED DESCRIPTION

[0056] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended to serve only to explain the present application, and not to limit the present application. In addition, it should be noted that only the parts related to the present application are shown in the accompanying drawings for the convenience of description.

[0057] Figure 1 A top view structural schematic diagram of an array substrate provided by an embodiment of the present application is shown in FIG. 1. Figure 2 A circuit structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application is shown in FIG. 2. Figure 3 A top view structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application is shown in FIG. 3. Figure 4 A cross-sectional structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application is shown in FIG. 4. Figures 1-4 The array substrate includes a substrate 10, a plurality of pixel driving circuits 20, and a plurality of signal lines 30. The pixel driving circuits 20 and the signal lines 30 are located on the same side of the substrate 10. The signal lines 30 are configured to provide voltage signals and / or current signals to the pixel driving circuits 20.

[0058] The pixel driving circuit 20 includes a plurality of thin film transistors 200. The plurality of thin film transistors 200 includes a driving transistor T3 and a regulating transistor T8. The signal lines 30 include a scan signal line 31, a regulating signal line DVH, and a power signal line PVDD. The scan signal line 31 is configured to provide a scan signal to the pixel driving circuit 20 for controlling the thin film transistors 200 in the pixel driving circuit 20 to be turned on or turned off. The scan signal line 31 includes a regulating control signal line SP.

[0059] The first electrode of the driving transistor T3 is electrically connected with the power supply signal line PVDD. The first electrode of the driving transistor T3 can be directly electrically connected with the power supply signal line PVDD, or the first electrode of the driving transistor T3 can be indirectly electrically connected with the power supply signal line PVDD via a thin film transistor, a capacitor or the like.

[0060] The first electrode of the adjusting transistor T8 is electrically connected with the adjusting signal line DVH, the second electrode of the adjusting transistor T8 is electrically connected with the first electrode of the driving transistor T3 or the second electrode of the driving transistor T3 (exemplarily, the second electrode of the adjusting transistor T8 is electrically connected with the first electrode of the driving transistor T3), and the gate of the adjusting transistor T8 is electrically connected with the adjusting control signal line SP. The adjusting control signal line SP controls the adjusting transistor T8 to be turned on, so that the adjusting signal transmitted on the adjusting signal line DVH can be transmitted to the first electrode of the driving transistor T3. The second node N2 is reset, the first frame brightness is improved, and the first frame brightness is prevented from being too low. Figure 2

[0061] The scanning signal line 31 extends along the first direction X, and the adjusting signal line DVH extends along the second direction Y. The adjusting signal line DVH is in a different layer from the scanning signal line 31, and the adjusting signal line DVH and the scanning signal line 31 are located in different metal layers. The first direction X and the second direction Y intersect. In an embodiment, the first direction X and the second direction Y are perpendicular. In another embodiment, the first direction X and the second direction Y are not perpendicular, and form an included angle greater than 0 degrees and less than 90 degrees.

[0062] The array substrate provided by the embodiment of the present application has different extension directions of the scanning signal line 31 and the adjusting signal line DVH. The scanning signal line 31 extends along the first direction X, and the adjusting signal line DVH extends along the second direction Y. It can be understood that, for a plurality of signal lines 30 extending along the first direction X and arranged along the second direction Y, a certain spacing needs to be left between two adjacent signal lines 30 along the second direction Y. The more the signal lines 30 arranged along the second direction Y, the more space occupied along the second direction Y. In the embodiment of the present application, the adjusting signal line DVH extends along the second direction Y, and the adjusting signal line DVH does not extend along the first direction X. The adjusting signal line DVH does not occupy the arrangement space along the second direction Y, thereby reducing the size of the pixel driving circuit 20 along the second direction Y. This is beneficial to improving the pixel density (i.e., the number of pixels per inch) and improving the display resolution.

[0063] Exemplarily, with reference to Figure 2 ​The pixel driving circuit 20 includes multiple thin-film transistors 200. The multiple thin-film transistors 200 include a power writing transistor T1, a data writing transistor T2, a driving transistor T3, a compensation transistor T4, a first reset transistor T5, a light emission control transistor T6, a second reset transistor T7, and an adjustment transistor T8. The pixel driving circuit 20 also includes a storage capacitor C. The first terminal of the power writing transistor T1 is electrically connected to the power signal line PVDD, the second terminal of the power writing transistor T1 is electrically connected to the second node N2, and the gate of the power writing transistor T1 is electrically connected to the light emission control scan signal line EM. The first terminal of the data writing transistor T2 is electrically connected to the data line DATA, the second terminal of the data writing transistor T2 is electrically connected to the second node N2, and the gate of the data writing transistor T2 is electrically connected to the second scan signal line S2. The first terminal of the driving transistor T3 is electrically connected to the second node N2, the second terminal of the driving transistor T3 is electrically connected to the third node N3, and the gate of the driving transistor T3 is electrically connected to the first node N1. The first terminal of compensation transistor T4 is electrically connected to the first node N1, the second terminal of compensation transistor T4 is electrically connected to the third node N3, and the gate of compensation transistor T4 is electrically connected to the second scan signal line S2. The first terminal of the first reset transistor T5 is electrically connected to the reset signal line VREF (specifically, the first reset signal line VREF1), the second terminal of the first reset transistor T5 is electrically connected to the first node N1, and the gate of the first reset transistor T5 is electrically connected to the first scan signal line S1. The first terminal of the light-emitting control transistor T6 is electrically connected to the third node N3, the second terminal of the light-emitting control transistor T6 is electrically connected to the fourth node N4, and the gate of the light-emitting control transistor T6 is electrically connected to the light-emitting control scan signal line EM. The first terminal of the second reset transistor T7 is electrically connected to the reset signal line VREF (specifically, the second reset signal line VREF2), the second terminal of the second reset transistor T7 is electrically connected to the fourth node N4, and the gate of the second reset transistor T7 is electrically connected to the adjustment control signal line SP. The first terminal of regulating transistor T8 is electrically connected to the regulating signal line DVH, the second terminal of regulating transistor T8 is electrically connected to the second node N2, and the gate of regulating transistor T8 is electrically connected to the regulating control signal line SP. The first plate C1 of storage capacitor C is electrically connected to the first node N1, and the second plate C2 of storage capacitor C is electrically connected to the power signal line PVDD.

[0064] Among them, the first node N1, the second node N2, the third node N3, and the fourth node N4 can be virtual connection nodes or actual connection nodes.

[0065] It should be noted that, as Figure 2 The circuit diagram shown is merely an example and is not intended to limit the invention. In other embodiments, the pixel driving circuit 20 may have other circuit structures. Figure 3The pixel driving circuit shown in the figure, the first reset signal line VREF1 and the second reset signal line VREF2 transmit the same signal, that is, one reset signal is used to realize the reset of the first node N1 and the reset of the fourth node N4. In other embodiments, the first reset signal line VREF1 and the second reset signal line VREF2 can transmit different signals, and the reset voltage of the first node N1 can not be equal to the reset voltage of the fourth node N4.

[0066] Exemplarily, referring to Figure 2 and Figure 3 , the scan signal line 31 includes a light-emitting control scan signal line EM, a first scan signal line S1, a second scan signal line S2, and an adjustment control signal line SP. The signal line 30 also includes a reset signal line VREF, which includes a first reset signal line VREF1 and / or a second reset signal line VREF2. The reset signal line VREF extends along the first direction X. The power supply signal line PVDD includes a first power supply signal line PVDD1, which extends along the first direction X. The number of signal lines 30 extending along the first direction X is large, so the adjustment signal line DVH is set to extend along the second direction Y, which reduces the size of the pixel driving circuit 20 along the second direction Y and improves the display resolution.

[0067] In the field of display technology, the thin film transistor 200 in the pixel driving circuit 20 and other devices such as the storage capacitor C are all realized by film layer stacking. For the sake of clarity, the pixel driving circuit 20 shown in Figure 3 will be described according to the film layer. Figure 5 A top view structural schematic diagram of a silicon semiconductor layer provided by an embodiment of the present application, Figure 6 A top view structural schematic diagram of a first metal layer provided by an embodiment of the present application, Figure 7 A top view structural schematic diagram of a capacitor metal layer provided by an embodiment of the present application, Figure 8 A top view structural schematic diagram of a second metal layer provided by an embodiment of the present application, referring to Figures 2-8The array substrate includes a silicon semiconductor layer POLY, a first metal layer M1, a capacitor metal layer MC, and a second metal layer M2 which are sequentially stacked. The silicon semiconductor layer POLY is located between the substrate 10 and the first metal layer M1. The silicon semiconductor layer POLY includes silicon. The thin film transistor 200 includes a gate 201, a channel layer 202, a source 203, and a drain 204. The gate 201 is located in the first metal layer M1, the channel layer 202 is located in the silicon semiconductor layer POLY, and the source 203 and the drain 204 are both located in the second metal layer M2. In other embodiments, the channel layer 202 in the thin film transistor 200 can include an oxide semiconductor material. The embodiments of the present application do not limit the type of the thin film transistor 200. The storage capacitor C includes a first plate C1 and a second plate C2. The first plate C1 is located between the second plate C2 and the substrate 10. The first plate C1 is located in the first metal layer M1, and the second plate C2 is located in the capacitor metal layer MC.

[0068] Exemplarily, referring to Figures 1-4 The scan signal line 31 is located in the first metal layer M1. The first power supply signal line PVDD1 is located in the capacitor metal layer MC. The signal line 30 further includes a data line DATA which extends along the second direction Y. The film layer in which the data line DATA is located is located on the side away from the substrate 10 of the film layer in which the scan signal line 31 is located. The film layer in which the adjusting signal line DVH is located is located on the side away from the substrate 10 of the film layer in which the scan signal line 31 is located.

[0069] Figure 9 Another top view structural schematic diagram of an array substrate provided by an embodiment of the present application is shown in Figure 10 A top view structural schematic diagram of a third metal layer provided by an embodiment of the present application is shown in Figure 11 A top view structural schematic diagram of another pixel driving circuit provided by an embodiment of the present application is shown in Figure 11 A top view structural schematic diagram of the pixel driving circuit shown in Figure 3 is shown in Figure 10 . Figure 12 A partial structural schematic diagram of the pixel driving circuit shown in Figure 11 is shown in Figure 13 A top view structural schematic diagram of another pixel driving circuit provided by an embodiment of the present application is shown in Figure 14 A sectional view structural schematic diagram along AA' in Figure 13 is shown in Figures 9-14The array substrate further comprises a connection line 40. The connection line 40 comprises a first connection line 41 and a second connection line 42 electrically connected. The first connection line 41 extends along the first direction X, and the second connection line 42 extends along the second direction Y. The first connection line 41 is connected with the data line DATA and the second connection line 42. The connection line 40 is configured to connect the data line DATA in the display area 101 to the driving chip in the non-display area 102 (specifically, the data line DATA can be connected to the area below the array substrate, which is usually referred to as the step area). The first connection line 41 is in a different layer from the data line DATA and the adjustment signal line DVH, the first connection line 41 is in a different layer from the data line DATA, the first connection line 41 is in a different layer from the adjustment signal line DVH, and the data line DATA and the adjustment signal line DVH can be in the same layer or in different layers. The first connection line 41 and the second connection line 42 are located in the display area 101, without occupying the space of the non-display area 102, so that the frame can be reduced and the screen-to-body ratio can be improved.

[0070] Exemplarily, referring to Figure 9 The display area 101 comprises a non-right-angle corner 51, and the non-display area 102 comprises a chamfered area 510 adjacent to the non-right-angle corner 51. The chamfered area 510 is adjacent to the non-right-angle corner 51 and is located at the periphery of the non-right-angle corner 51. The space of the chamfered area 510 is relatively small. If the connection line 40 is arranged in the chamfered area 510, the connection line 40 occupies the space of the chamfered area 510, and if other elements need to be arranged, a relatively large frame can only be arranged. In the embodiment of the present application, the connection line 40 is arranged by winding into the display area 101, so that the frame can be reduced.

[0071] Optionally, referring to Figures 11-14 The second connection line 42 is in the same layer as the data line DATA. Therefore, the second connection line 42 and the data line DATA can adopt the same material and are formed in the same process, so that the process is saved.

[0072] Exemplarily, referring to Figure 4 And Figures 11-14 The array substrate further comprises a third metal layer M3 located on the side of the second metal layer M2 away from the substrate 10. The second connection line 42 and the data line DATA arranged in the same layer are arranged along the first direction X. The second connection line 42 and the data line DATA are spaced apart by a certain distance to prevent the second connection line 42 and the data line DATA from being electrically connected undesirably. The second connection line 42 and the data line DATA are both located in the third metal layer M3. In other embodiments, the second connection line 42 and the data line DATA can also be located in other metal layers.

[0073] Optionally, referring to Figures 11-14The first connecting line 41 is located in the film layer between the film layer containing the data line DATA and the substrate 10.

[0074] For example, refer to Figure 13 and Figure 14 The first connection line 41 is located in the capacitor metal layer MC, and the data line DATA is located in the third metal layer M3. The film layer containing the first connection line 41 is located between the film layer containing the data line DATA and the substrate 10. The first connection line 41 is electrically connected to the data line DATA through a via 61. The power signal line PVDD includes a second power signal line PVDD2, which extends along the second direction Y and is located in the third metal layer M3.

[0075] Figure 15 for Figure 11 The diagram shows another partial structure of the pixel driving circuit. Figure 16 For along Figure 15 A schematic diagram of the cross-sectional structure of BB' (see reference). Figure 15 and Figure 16 The first connecting line 41 is located in the film layer between the adjustment signal line DVH and the substrate 10.

[0076] For example, refer to Figure 15 and Figure 16 The first connection line 41 is located in the capacitor metal layer MC, and the adjustment signal line DVH is located in the second metal layer M2. The film layer containing the first connection line 41 is located between the film layer containing the adjustment signal line DVH and the substrate 10.

[0077] For example, refer to Figure 15 and Figure 16 In one embodiment, the adjustment signal line DVH is located in a film layer between the data line DATA and the substrate 10. In another embodiment, the adjustment signal line DVH and the data line DATA are in the same layer. In yet another embodiment, the adjustment signal line DVH is located on the side of the data line DATA that is furthest from the substrate 10.

[0078] For example, refer to Figure 9 , Figure 13 and Figure 14The data line DATA extending along the second direction Y is connected to the first connection line 41 extending along the first direction X through the via 61, and the first connection line 41 extending along the first direction X is connected to the second connection line 42 extending along the second direction Y through the via 61, so as to connect the data line DATA to the driving chip in the non-display area 102. It can be understood that the data line DATA and the first connection line 41 are electrically connected only when the data line DATA and the first connection line 41 are connected through the via 61 at the overlapping position of the data line DATA and the first connection line 41. If the via 61 is not arranged at the overlapping position of the data line DATA and the first connection line 41, the data line DATA and the first connection line 41 are not electrically connected. It should be noted that the via 61 in each embodiment of the present application can be a hole arranged in an organic layer or an inorganic layer. When a metal layer is formed above the hole, a metal material is formed in the hole as a connecting part. Therefore, the via 61 can be regarded as a hole and a connecting part in the hole.

[0079] Figure 17 Another top view structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application is shown in Figure 1 、 Figure 2 、 Figure 4 and Figure 17 The pixel driving circuit 20 is configured to drive the light emitting element LD to emit light and display, and control the light emitting brightness of the light emitting element LD. The light emitting element LD is located on the side of the film layer where the pixel driving circuit is located away from the substrate 10 in the direction perpendicular to the substrate 10. The light emitting element LD includes an anode RE, and the anode RE of the light emitting element LD is electrically connected to the source electrode 203 or the drain electrode 204 of the thin film transistor 200.

[0080] Optionally, referring to Figures 11-14 The signal line 30 further includes a reset signal line VREF, and the reset signal line VREF extends along the first direction X. The film layer where the reset signal line VREF is located is between the film layer where the scan signal line 31 is located and the film layer where the adjusting signal line DVH is located. The first connection line 41 is in the same layer as the reset signal line VREF, so that the first connection line 41 and the reset signal line VREF can be formed by using the same material and in the same process, thereby saving the process.

[0081] Exemplarily, referring to Figures 11-16 The scan signal line 31 is located in the first metal layer M1, the first connection line 41 and the reset signal line VREF are both located in the capacitor metal layer MC, and the adjusting signal line DVH is located in the second metal layer M2.

[0082] Exemplarily, referring to Figures 11-16The film layer where the first connection line 41 is located is between the film layer where the data line DATA is located and the substrate 10. The film layer where the first connection line 41 is located is between the film layer where the adjusting signal line DVH is located and the substrate 10. The second connection line 42 and the data line DATA are both located in the third metal layer M3. Thus, in the embodiment of the present application, the first connection line 41, the second connection line 42 and the adjusting signal line DVH do not need to be formed by additionally setting a metal layer, i.e., the fourth metal layer or more metal layers are not needed to form the first connection line 41, the second connection line 42 and the adjusting signal line DVH, thereby reducing the number of metal layers, reducing the thickness of the array substrate, and reducing the process procedure.

[0083] Optionally, referring to Figure 11 The first connection line 41 is in the same layer as the reset signal line VREF. The area where the pixel drive circuit 20 is located is the pixel area P. In the same pixel area P, the first connection line 41 is located between the reset signal line VREF and the light-emitting control scanning signal line EM.

[0084] Optionally, referring to Figure 11 , Figure 11 Four pixel areas P are shown. The four pixel areas P are arranged in a matrix of two rows and two columns along the first direction X and the second direction Y. In order to clearly distinguish the different pixel areas P, in Figure 11 , a horizontal solid line and a vertical solid line are used to represent the boundaries of the adjacent pixel areas P along the first direction X and the second direction Y.

[0085] Optionally, referring to Figure 11 The signal line 30 extending along the first direction X can be electrically connected with the plurality of pixel drive circuits 20 arranged along the first direction X. The signal line 30 extending along the second direction Y can be electrically connected with the plurality of pixel drive circuits 20 arranged along the second direction Y.

[0086] Optionally, referring to Figures 11-14The array substrate also includes a first jumper 321. The first jumper 321 is on a different layer than both the data line DATA and the first connecting line 41. The first end of the first jumper 321 is electrically connected to the data line DATA via a via 61, and the second end of the first jumper 321 is electrically connected to the first connecting line 41 via a via 61. The first jumper 321 is configured to connect the data line DATA and the first connecting line 41. The data line DATA and the second connecting line 42 are on the same layer and are close together. A via 61 is provided at the intersection of the second connecting line 42 and the first connecting line 41. If a via 61 is provided at the intersection of the data line DATA and the first connecting line 41, the via 61 on the data line DATA and the via 61 on the second connecting line 42 will overlap due to insufficient space, resulting in an unwanted electrical connection. In other words, the data line DATA is adjacent to the second connecting line 42, and there is not enough space to set up two adjacent vias 61 that directly connect to the first connecting line 41. In this embodiment of the invention, a first jumper wire 321 is used as an intermediary to connect the data line DATA and the first connecting line 41. The position of the connecting via 61 between the first jumper wire 321 and the first connecting line 41 is relatively free, thereby avoiding the problem of insufficient space for adjacent vias 61.

[0087] Optionally, refer to Figures 11-16 The first jumper wire 321 is on the same layer as the adjustment signal line DVH. Therefore, the first jumper wire 321 and the adjustment signal line DVH can be made of the same material and formed in the same process, saving process steps.

[0088] For example, refer to Figure 16 The first jumper 321 and the adjustment signal line DVH are both located in the second metal layer M2.

[0089] Figure 18 This is a top view schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. Figure 19 For along Figure 18 A schematic diagram of the cross-sectional structure of CC', see reference. Figure 18 and Figure 19 The film layer where the first connecting line 41 is located is on the side of the film layer where the adjustment signal line DVH is located that is far away from the substrate 10.

[0090] For example, refer to Figure 18 and Figure 19 The first connection line 41 is located in the third metal layer M3, and the adjustment signal line DVH is located in the second metal layer M2. The film layer containing the adjustment signal line DVH is located between the film layer containing the first connection line 41 and the substrate 10.

[0091] Optionally, refer toFigure 18 and Figure 19 The film layer where the first connection line 41 is located is between the film layer where the data line DATA is located and the film layer where the adjustment signal line DVH is located.

[0092] Exemplarily, referring to Figure 18 and Figure 19 The array substrate further comprises a fourth metal layer M4, which is located on the side of the third metal layer M3 away from the substrate 10. The data line DATA and the second connection line 42 are both located in the fourth metal layer M4. The first connection line 41 is located in the third metal layer M3, and the adjustment signal line DVH is located in the second metal layer M2. The power supply signal line PVDD comprises a second power supply signal line PVDD2, which extends along the first direction X and is located in the third metal layer M3.

[0093] Figure 20 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in Figure 21 A sectional view structural schematic diagram along DD' in Figure 20 Exemplarily, referring to Figure 20 and Figure 21 The film layer where the first connection line 41 is located is between the film layer where the data line DATA is located and the film layer where the adjustment signal line DVH is located.

[0094] Exemplarily, referring to Figure 20 and Figure 21 The data line DATA and the second connection line 42 are both located in the third metal layer M3. The first connection line 41 is located in the fourth metal layer M4, and the adjustment signal line DVH is located in the second metal layer M2. The power supply signal line PVDD comprises a second power supply signal line PVDD2, which extends along the second direction Y and is located in the third metal layer M3.

[0095] Figure 22 A top view structural schematic diagram of another third metal layer provided by the embodiment of the present application is shown in Figure 23 A top view structural schematic diagram of a fourth metal layer provided by the embodiment of the present application is shown in Figure 24 A top view structural schematic diagram formed after the third metal layer shown in Figure 3 and the fourth metal layer shown in Figure 22 are superimposed on the basis of Figure 23 . Figure 24 A top view structural schematic diagram of another pixel driving circuit provided by the embodiment of the present application is shown in Figure 25 A partial structure schematic diagram of the pixel driving circuit shown in Figure 24 . Figure 26 A sectional view structural schematic diagram along EE' in Figure 25 Exemplarily, referring to Figures 22-26The second connection line 42 is in a layer different from the data line DATA. The layer of the second connection line 42 can be between the layer of the data line DATA and the substrate 10, or the layer of the second connection line 42 can be on the side of the layer of the data line DATA away from the substrate 10.

[0096] Optionally, referring to Figures 24-26 The layer of the second connection line 42 is on the side of the layer of the data line DATA away from the substrate 10.

[0097] Optionally, referring to Figure 25 and Figure 26 The second connection line 42 is in the fourth metal layer M4, the data line DATA is in the third metal layer M3, the adjustment signal line DVH is in the second metal layer M2, and the reset signal line VREF is in the capacitor metal layer MC. The power signal line PVDD includes a second power signal line PVDD2, the second power signal line PVDD2 extends along the second direction Y, and the second power signal line PVDD2 is in the third metal layer M3.

[0098] Optionally, referring to Figures 24-26 The first connection line 41 is in the same layer as the second connection line 42. For example, the first connection line 41 and the second connection line 42 are both in the fourth metal layer M4. It should be noted that, in order to prevent unwanted electrical connection, the first connection line 41 and / or the second connection line 42 can be cut at the cutting position 60.

[0099] Optionally, referring to Figure 14 , Figure 19 and Figure 26 The layer of the adjustment signal line DVH is between the layer of the second connection line 42 and the substrate 10, and the layer of the adjustment signal line DVH is between the layer of the data line DATA and the substrate 10. The adjustment signal line DVH can be formed by using the original metal layer in the array substrate, so that a new metal layer is not needed, the thickness of the array substrate is reduced, and the process is reduced.

[0100] Figure 27 Another top view structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application, Figure 28 is a sectional view structural schematic diagram of FF' in Figure 27 Optionally, referring to Figure 27 and Figure 28 The adjustment signal line DVH, the second connection line 42, and the data line DATA are in the same layer. Thus, the adjustment signal line DVH, the second connection line 42, and the data line DATA can be formed by using the same material and in the same process, thereby saving the process.

[0101] Optionally, referring to Figure 27 and Figure 28The first connection line 41 is located at the third metal layer M3, the adjustment signal line DVH and the second connection line 42 are located at the fourth metal layer M4.

[0102] Figure 29 A top view structural schematic diagram of another pixel driving circuit provided by an embodiment of the present application is shown in FIG. 6. Figure 30 The power supply signal line PVDD includes a second power supply signal line PVDD2, the second power supply signal line PVDD2 extends along the first direction X, and the second power supply signal line PVDD2 is located at the third metal layer M3. Figure 29 The second connection line 42 is located at the third metal layer M3. Figure 29 The adjustment signal line DVH is located at the fourth metal layer M4. Figure 30 The adjustment signal line DVH and the data line DATA are located at the third metal layer M3.

[0103] The first connection line 41 is located at the third metal layer M3, the adjustment signal line DVH and the second connection line 42 are located at the fourth metal layer M4. Figure 29 The second power supply signal line PVDD2 extends along the second direction Y. Figure 30 The second power supply signal line PVDD2 is located at the third metal layer M3.

[0104] Figure 31 A top view structural schematic diagram of another pixel driving circuit provided by an embodiment of the present application is shown in FIG. 6. Figure 32 The second connection line 42 is located at the third metal layer M3. Figure 31 The adjustment signal line DVH is located at the fourth metal layer M4. Figure 31 The adjustment signal line DVH is located at the side of the data line DATA away from the substrate 10. Figure 32 The second connection line 42 is located at the third metal layer M3.

[0105] The first connection line 41 is located at the third metal layer M3, the adjustment signal line DVH and the second connection line 42 are located at the fourth metal layer M4. Figure 31 The second power supply signal line PVDD2 extends along the second direction Y. Figure 32 The second power supply signal line PVDD2 is located at the third metal layer M3.

[0106] Optionally, the first connection line 41 is located at the third metal layer M3. Figure 19 The second connection line 42 is located at the third metal layer M3. Figure 26The signal line 30 further comprises a reset signal line VREF. The reset signal line VREF extends along the first direction X. The reset signal line VREF is located in a film layer between the film layer in which the scan signal line 31 is located and the film layer in which the adjusting signal line DVH is located. The reset signal line VREF is in a different layer from the first connection line 41. In a direction perpendicular to the plane in which the substrate 10 is located, the first connection line 41 at least partially overlaps the reset signal line VREF. This reduces the common light-blocking area of the first connection line 41 and the reset signal line VREF, and increases the light transmittance.

[0107] Exemplarily, reference is made to Figure 19 and Figure 26 The reset signal line VREF is located in the capacitor metal layer MC, and the first connection line 41 is located in the third metal layer M3 or the fourth metal layer M4. In a direction perpendicular to the substrate 10, the distance between the first connection line 41 and the reset signal line VREF is far enough not to affect the signal on the reset signal line VREF. On the other hand, the reset signal line VREF does not overlap the scan signal line 31, so it does not affect the signal on the scan signal line 31, and does not affect the control process of the scan signal line 31 on the thin film transistor 200.

[0108] Figure 33 A top view structural schematic diagram of another pixel driving circuit provided by an embodiment of the present application is shown in Figure 34 A sectional view structural schematic diagram along II’ in Figure 33 Exemplarily, reference is made to Figure 33 and Figure 34 The signal line 30 further comprises an auxiliary reset signal line 70. The auxiliary reset signal line 70 extends along the second direction Y, and the auxiliary reset signal line 70 is in the same layer as the adjusting signal line DVH. Thus, the auxiliary reset signal line 70 and the adjusting signal line DVH can be formed by using the same material and in the same process, thereby saving the process procedure. The second connection line 42 is in a different layer from the auxiliary reset signal line 70. In a direction perpendicular to the plane in which the substrate 10 is located, the second connection line 42 overlaps the auxiliary reset signal line 70. This reduces the common light-blocking area of the second connection line 42 and the auxiliary reset signal line 70, and increases the light transmittance.

[0109] Exemplarily, reference is made to Figure 33 and Figure 34The auxiliary reset signal line 70 includes a first auxiliary reset signal line 71 and a second auxiliary reset signal line 72. The first auxiliary reset signal line 71 is electrically connected to the first reset signal line VREF1 through the via 61. The second auxiliary reset signal line 72 is electrically connected to the second reset signal line VREF2 through the via 61. In the direction perpendicular to the plane where the substrate 10 is located, the second connection line 42 overlaps the first auxiliary reset signal line 71, and the second connection line 42 overlaps the second auxiliary reset signal line 72. In the direction perpendicular to the plane where the substrate 10 is located, the first connection line 41 overlaps the second reset signal line VREF2.

[0110] Optionally, referring to Figure 15 and Figure 16 , the adjustment signal line DVH is in the same layer as the data line DATA. The adjustment signal line DVH includes a first line segment DVH1 extending along the second direction Y. In the direction perpendicular to the plane where the substrate 10 is located, the first line segment DVH1 overlaps the data line DATA. The common light shielding area of the adjustment signal line DVH and the data line DATA is reduced, and the light transmittance is increased.

[0111] Illustratively, referring to Figure 15 and Figure 16 , the adjustment signal line DVH includes a first line segment DVH1 and a second line segment DVH2, and both the first line segment DVH1 and the second line segment DVH2 extend along the second direction Y. The first line segment DVH1 and the second line segment DVH2 are not collinear. The adjustment signal line DVH includes a plurality of broken line segments. In other embodiments, the adjustment signal line DVH can also be a whole straight line segment. Compared with the broken line segment or the curved line segment, the straight line segment has a simple structure and is not prone to over-etching and other problems, thereby reducing the process difficulty.

[0112] Optionally, referring to Figure 12 , Figure 18 and Figure 25 , along the first direction X, one second connection line 42 is included between two adjacent data lines DATA, and one data line DATA is included between two adjacent second connection lines 42. Along the first direction X, the data line DATA and the second connection line 42 are arranged alternately. It should be noted that other signal lines 30 can be included or not included between the data line DATA and the second connection line 42.

[0113] Illustratively, referring to Figure 12 , along the first direction X, a power supply signal line PVDD extending along the second direction Y is included between the data line DATA and the second connection line 42. Referring to Figure 18 , along the first direction X, the power supply signal line PVDD extending along the second direction Y is not included between the data line DATA and the second connection line 42.

[0114] Optionally, referring toFigure 33 and Figure 34 The power signal line PVDD includes a first power signal line PVDD1 and a second power signal line PVDD2 electrically connected. The first power signal line PVDD1 and the second power signal line PVDD2 both extend along the first direction X. The first power signal line PVDD1 and the second power signal line PVDD2 are staggered in a direction perpendicular to the plane on which the substrate 10 lies. The common light shielding area of the first power signal line PVDD1 and the second power signal line PVDD2 is reduced, and the light transmittance is increased.

[0115] Exemplarily, referring to Figure 33 and Figure 34 The first power signal line PVDD1 is in the same layer as the reset signal line VREF. The first power signal line PVDD1 is located in the capacitor metal layer MC. The second power signal line PVDD2 is in the same layer as the first connection line 41. The second power signal line PVDD2 is located in the third metal layer M3. The power signal line PVDD can further include a third power signal line PVDD3. The third power signal line PVDD3 is electrically connected to the first power signal line PVDD1 and the second power signal line PVDD2. The third power signal line PVDD3 is in the same layer as the auxiliary reset signal line 70, and the third power signal line PVDD3 is located in the second metal layer M2.

[0116] Optionally, referring to Figures 11-16 The power signal line PVDD includes a first power signal line PVDD1 and a second power signal line PVDD2 electrically connected. The first power signal line PVDD1 extends along the first direction X. The second power signal line PVDD2 extends along the second direction Y. The second power signal line PVDD2 is in the same layer as the data line DATA and the second connection line 42. The second power signal line PVDD2 is in the same layer as the data line DATA, and the second power signal line PVDD2 is in the same layer as the second connection line 42. The area where the pixel driving circuit 20 is located is the pixel area P. In the same pixel area P, along the first direction X, the second connection line 42 is located on the side of the second power signal line PVDD2 away from the via 61 (specifically, the fourth node N4). The via 61 at the fourth node N4 occupies a certain space, so it is not easy to arrange the second connection line 42 between the via 61 at the fourth node N4 and the data line DATA. In the embodiment of the application, the second connection line 42 is arranged on the side of the second power signal line PVDD2 away from the via 61 at the fourth node N4, thereby avoiding the unwanted electrical connection between the second connection line 42 and the fourth node N4.

[0117] Optionally, referring to Figures 24-26The power signal line PVDD includes a first power signal line PVDD1 and a second power signal line PVDD2 electrically connected. The first power signal line PVDD1 extends along the first direction X. The second power signal line PVDD2 extends along the second direction Y and is in the same layer as the data line DATA. The second connection line 42 is in a different layer from the second power signal line PVDD2. In a direction perpendicular to the plane in which the substrate 10 lies, the second connection line 42 overlaps the second power signal line PVDD2. The common light shielding area of the second connection line 42 and the second power signal line PVDD2 is reduced, and the light transmittance is increased.

[0118] Optionally, referring to Figures 11-14 The second power signal line PVDD2 includes a second power signal line main body portion 81 and a second power signal line extension portion 82. The extension direction of the second power signal line main body portion 81 intersects the extension direction of the second power signal line extension portion 82. Along the second direction Y, the semiconductor layer between the first scan signal line S1 and the second scan signal line S2 is denoted as a first node semiconductor layer 2021. The first node semiconductor layer 2021 is the semiconductor layer at the position of the first node N1. The second power signal line extension portion 82 is in a different layer from the first node semiconductor layer 2021. In a direction perpendicular to the plane in which the substrate 10 lies, the second power signal line extension portion 82 overlaps the first node semiconductor layer 2021. The second power signal line extension portion 82 transmits a constant voltage, and the second power signal line extension portion 82 overlaps the first node semiconductor layer 2021, so that the second power signal line extension portion 82 can act as a shielding layer to shield electromagnetic interference generated by other film layers on the first node semiconductor layer 2021, thereby reducing voltage disturbance of the first node N1.

[0119] Exemplarily, referring to Figures 11-14 The extension direction of the second power signal line PVDD2 is the same as the extension direction of the second power signal line main body portion 81. The second power signal line PVDD2 extends along the second direction Y, the second power signal line main body portion 81 extends along the second direction Y, and the second power signal line extension portion 82 extends along the first direction X. The second power signal line extension portion 82 is a protruding portion of the second power signal line PVDD2 in the XY plane.

[0120] Exemplarily, referring to Figure 18 and Figure 19 The extension direction of the second power signal line PVDD2 is the same as the extension direction of the second power signal line main body portion 81. The second power signal line PVDD2 extends along the first direction X, the second power signal line main body portion 81 extends along the first direction X, and the second power signal line extension portion 82 extends along the second direction Y.

[0121] Optionally, referring toFigures 11-14 The first connection line 41 is electrically connected to the data line DATA through a via 61. The array substrate also includes a dummy via 62, which is located at the intersection of the first connection line 41 and the data line DATA. That is, at the intersection of the first connection line 41 and the data line DATA, the first connection line 41 and the data line DATA do not need to be electrically connected, and a via 61 is not provided; instead, a dummy via 62 is provided. Unlike a via 61, the dummy via 62 only includes the corresponding metal layer and does not form a hole on the organic or inorganic layer. Therefore, the film thickness at the location of the dummy via 62 is consistent with the film thickness at the location of the via 61, improving the thickness uniformity of the array substrate at various locations.

[0122] It should be noted that, in some implementations, the adjustment signal line DVH may also extend along the first direction X. Figure 35 This is a top view schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. Figure 36 This is a top view schematic diagram of another silicon semiconductor layer provided in an embodiment of the present invention. Figure 37 This is a top view schematic diagram of another first metal layer provided in an embodiment of the present invention. Figure 38 This is a top view schematic diagram of another capacitor metal layer structure provided in an embodiment of the present invention. Figure 39 This is a top view schematic diagram of another second metal layer provided in an embodiment of the present invention. Figure 40 This is a top view schematic diagram of another third metal layer provided in an embodiment of the present invention. Figure 41 This is a top view schematic diagram of another fourth metal layer provided in an embodiment of the present invention. Figure 35 For the reason Figures 36-41 A top view of the pixel driving circuit formed by layer stacking, with the adjustment signal line DVH extending along the first direction X. The adjustment signal line DVH is located in the capacitor metal layer MC. The adjustment signal line DVH and the reset signal line VREF are in the same layer. In other embodiments, the adjustment signal line DVH extending along the first direction X may also be located in other film layers, and this embodiment of the invention does not limit this. It should be noted that when the adjustment signal line DVH extends along the first direction X, the above-mentioned settings of each signal line 30, power signal line PVDD, first connecting line 41 and second connecting line 42 are also applicable, and will not be repeated here.

[0123] Figure 42 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention, with reference to... Figure 1 , Figure 2 and Figure 42 The display panel includes the array substrate of any of the above embodiments and a plurality of light-emitting elements (LDs) disposed on the array substrate. Figure 42An exemplary light-emitting element (LD) is illustrated. The light-emitting element LD is electrically connected to the pixel driving circuit 20, and the light-emitting element LD is configured to emit light under the drive of the pixel driving circuit 20.

[0124] For example, refer to Figure 1 , Figure 2 and Figure 42 The light-emitting element (LD) includes an anode (RE), a light-emitting functional layer (83), and a cathode (84), with the light-emitting functional layer (83) located between the anode (RE) and the cathode (84). The light-emitting functional layer (83) may include organic light-emitting materials and / or inorganic light-emitting materials. The cathode (84) is electrically connected to the power supply line (PVEE).

[0125] Figure 43 This is a schematic diagram of a display device provided in an embodiment of the present invention, with reference to... Figure 43 The display device includes the display panel in the above embodiments. The display device provided in the embodiments of the present invention can be a mobile phone or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on these.

[0126] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. An array substrate, characterized by, The display panel comprises a substrate, a plurality of pixel driving circuits and a plurality of signal lines, the pixel driving circuits and the signal lines are located on the same side of the substrate; The pixel driving circuit comprises a driving transistor and a regulating transistor, the signal line comprises a scanning signal line, a regulating signal line and a power signal line, and the scanning signal line comprises a regulating control signal line; The first electrode of the driving transistor is electrically connected with the power signal line; The first electrode of the regulating transistor is electrically connected with the regulating signal line, the second electrode of the regulating transistor is electrically connected with the first electrode or the second electrode of the driving transistor, and the gate electrode of the regulating transistor is electrically connected with the regulating control signal line; The scanning signal line extends along a first direction, the regulating signal line extends along a second direction and is different from the scanning signal line in layer, and the first direction intersects with the second direction.

2. The array substrate of claim 1, wherein, Further comprising a connecting line, the connecting line comprises a first connecting line and a second connecting line which are electrically connected, the first connecting line extends along the first direction, and the second connecting line extends along the second direction; The signal line further comprises a data line, and the data line extends along the second direction; The first connecting line connects the data line and the second connecting line and is different from the data line and the regulating signal line in layer.

3. The array substrate of claim 2, wherein, The second connecting line is in the same layer as the data line.

4. The array substrate of claim 3, wherein, The film layer where the first connecting line is located is between the film layer where the data line is located and the substrate.

5. The array substrate of claim 4, wherein, The film layer where the first connecting line is located is between the film layer where the regulating signal line is located and the substrate.

6. The array substrate of claim 5, wherein, The signal line further comprises a reset signal line, the reset signal line extends along the first direction, and the film layer where the reset signal line is located is between the film layer where the scanning signal line is located and the film layer where the regulating signal line is located; The first connecting line is in the same layer as the reset signal line.

7. The array substrate of claim 6, wherein, The scanning signal line further comprises a light-emitting control scanning signal line; The pixel driving circuit further comprises a power supply writing transistor; The first electrode of the power supply writing transistor is electrically connected with the power signal line, the second electrode of the power supply writing transistor is electrically connected with the first electrode of the driving transistor, and the gate electrode of the power supply writing transistor is electrically connected with the light-emitting control scanning signal line; The area where the pixel driving circuit is located is a pixel area, in the same pixel area, the first connecting line is located between the reset signal line and the light-emitting control scanning signal line.

8. The array substrate of claim 5, wherein, Further comprising a first bridging line, the first bridging line is different from the data line and the first connecting line in layer, the first end of the first bridging line is electrically connected with the data line through a via, and the second end of the first bridging line is electrically connected with the first connecting line through the via.

9. The array substrate of claim 8, wherein, The first bridging line is in the same layer as the regulating signal line.

10. The array substrate of claim 4, wherein, The film layer where the first connecting line is located is on the side away from the substrate of the film layer where the regulating signal line is located.

11. The array substrate of claim 10, wherein, The film layer where the first connecting line is located is between the film layer where the regulating signal line is located and the film layer where the data line is located.

12. The array substrate of claim 3, wherein, The film layer where the first connecting line is located is on the side away from the substrate of the film layer where the data line is located.

13. The array substrate of claim 2, wherein, The second connecting line is different from the data line in layer.

14. The array substrate of claim 13, wherein, The film layer where the second connection line is located is away from the substrate on a side of the film layer where the data line is located.

15. The array substrate of claim 13, wherein, The first connection line and the second connection line are in the same layer.

16. The array substrate of claim 2, wherein, The film layer where the adjustment signal line is located is between the film layer where the second connection line is located and the substrate, and between the film layer where the data line is located and the substrate.

17. The array substrate of claim 2, wherein, The adjustment signal line, the second connection line, and the data line are in the same layer.

18. The array substrate of claim 2, wherein, The adjustment signal line and the data line are in the same layer, and the film layer where the adjustment signal line is located is between the film layer where the second connection line is located and the substrate.

19. The array substrate of claim 2, wherein, The adjustment signal line is located on a side of the data line away from the substrate, and the second connection line is in the same layer as the data line.

20. The array substrate of claim 2, wherein, The signal line further includes a reset signal line extending along the first direction, and the film layer where the reset signal line is located is between the film layer where the scan signal line is located and the film layer where the adjustment signal line is located. In a direction perpendicular to the plane where the substrate is located, the first connection line and the reset signal line are in different layers and at least partially overlap.

21. The array substrate of claim 2, wherein, The signal line further includes an auxiliary reset signal line extending along the second direction and in the same layer as the adjustment signal line. In a direction perpendicular to the plane where the substrate is located, the second connection line and the auxiliary reset signal line are in different layers and overlap.

22. The array substrate of claim 2, wherein, The adjustment signal line includes a first segment extending along the second direction, and in a direction perpendicular to the plane where the substrate is located, the first segment overlaps the data line.

23. The array substrate of claim 2, wherein, In the first direction, between two adjacent data lines, there is a second connection line, and between two adjacent second connection lines, there is a data line.

24. The array substrate of claim 1, wherein, The power signal line includes electrically connected first and second power signal lines, and the first and second power signal lines both extend along the first direction. In a direction perpendicular to the plane where the substrate is located, the first power signal line and the second power signal line are in different layers and overlap.

25. The array substrate of claim 3, wherein, The power signal line includes electrically connected first and second power signal lines, the first power signal line extends along the first direction, and the second power signal line extends along the second direction and is in the same layer as the data line and the second connection line. The scan signal line further includes a light-emitting control scan signal line, the pixel driving circuit further includes a light-emitting control transistor, the first electrode of the light-emitting control transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the light-emitting control transistor is electrically connected to a light-emitting element through a via, and the gate of the light-emitting control transistor is electrically connected to the light-emitting control scan signal line. The area where the pixel driving circuit is located is a pixel area, and in the same pixel area, in the first direction, the second connection line is located on a side of the second power signal line away from the via.

26. The array substrate of claim 13, wherein, The power signal line includes electrically connected first and second power signal lines, the first power signal line extends along the first direction, and the second power signal line extends along the second direction and is in the same layer as the data line. The second connection line overlaps the second power signal line in a direction perpendicular to a plane in which the substrate is located.

27. The array substrate of claim 1, wherein, The power signal line comprises a first power signal line and a second power signal line electrically connected, the first power signal line extending in the first direction, and a film layer in which the first power signal line is located being between a film layer in which the second power signal line is located and the substrate; The second power signal line comprises a second power signal line main body portion and a second power signal line extension portion, and an extension direction of the second power signal line main body portion intersects an extension direction of the second power signal line extension portion; The signal line further comprises a data line and a reset signal line, and the scan signal line further comprises a first scan signal line and a second scan signal line; and the pixel driving circuit further comprises a first reset transistor and a data write transistor; A first electrode of the first reset transistor is electrically connected to the reset signal line, a second electrode of the first reset transistor is electrically connected to a gate electrode of the driving transistor, and a gate electrode of the first reset transistor is electrically connected to the first scan signal line; A first electrode of the data write transistor is electrically connected to the data line, a second electrode of the data write transistor is electrically connected to a first electrode of the driving transistor, and a gate electrode of the data write transistor is electrically connected to the second scan signal line; In the second direction, a semiconductor layer located between the first scan signal line and the second scan signal line is a first node semiconductor layer; and in a direction perpendicular to a plane in which the substrate is located, the second power signal line extension portion overlaps the first node semiconductor layer.

28. The array substrate of claim 2, wherein, The first connection line is electrically connected to the data line through a via hole; The array substrate further comprises a dummy via hole, and the dummy via hole is located at an intersection position of the first connection line and the data line.

29. A display panel, comprising: An array substrate comprising any one of claims 1-28, and a plurality of light emitting elements disposed on the array substrate.

30. A display device comprising: A display panel comprising the display panel of claim 29. A display panel comprising the display panel of claim 29.

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