A vertical cavity surface emitting laser with on-chip vector beam generation and manufacturing method

Abstract

The present invention discloses a vertical cavity surface emitting laser (VCSEL) capable of generating vector beams on-chip and a method for its fabrication. The method relates to the fields of micro-nanostructures and semiconductor laser technology. The structure primarily comprises an ohmic contact protection electrode, a periodically alternating upper distributed Bragg reflector, a current-limiting oxide hole, and an oxide-limiting layer; an active region, a periodically alternating lower distributed Bragg reflector, a GaAs substrate layer, a P-type metal electrode layer, a passivation layer, a BCB cured insulating layer, an N-type metal electrode layer, a light-emitting hole, and a metasurface. The present invention utilizes conventional semiconductor processing techniques to easily integrate a birefringent square nanocolumn structure on the light-emitting end face of a vertical cavity surface emitting laser (VCSEL), enabling the generation and manipulation of vector beams at the chip level. The developed method paves the way for VCSEL platforms to achieve customized vector beams, resolving the issues of traditional vector beam generation devices, such as complex structure, large size, low efficiency, and difficulty in operation.

Description

Technical Field

[0001] The present invention relates to the technical field of micro-nano structures and semiconductor lasers, and in particular to a vertical cavity surface emitting laser for generating a vector light beam on a chip and a manufacturing method thereof. Background Art

[0002] Structured light refers to the use of light fields with spatially varying properties, such as amplitude, phase, and polarization state. Over the past two or three decades, it has promoted the development of modern optical technology and generated great interest in both basic science and technology. Vector beams, as a typical type of structured light, have spatially non-uniform polarization states and have many interesting properties compared to traditional uniformly polarized scalar beams. For example, using high-value lenses, radially polarized cylindrical vector beams can be tightly focused at the focal plane with a strong and non-propagating longitudinal electric field, less than the diffraction limit, while focused azimuthally polarized beams can generate an axial magnetic field component in the absence of any electric field at their center. This unique polarization property of vector beams makes them a powerful tool for a variety of applications, including optical trapping and manipulation, polarization spectroscopy, laser processing, and high-resolution imaging.

[0003] Because the full potential of developing vector beams depends on the research of efficient vector beam sources, the study of vector beam sources has naturally become a hot topic, including free-space, fiber-optic, and integrated devices. Among them, vertical-cavity surface-emitting lasers (VCSELs) are an ideal light source. They have advantages such as circular beam profile distribution, low power consumption and manufacturing cost, high modulation speed, and ease of two-dimensional array fabrication and optical integration, making them suitable for the development of vector beam sources. In this context, significant progress has been made by coupling additional polarization or phase modulation components to VCSELs, such as frequency-selective volume Bragg gratings, birefringent external cavities, and liquid crystal spatial light modulators. However, these solutions are contrary to the current trend of miniaturization of photonic systems.

[0004] Metasurfaces, as subwavelength-scale artificial optical structures, are typically composed of densely packed, strongly scattering metal or dielectric nanostructures. Under the influence of external light sources or stimuli, these flat micro-nanostructures can rapidly manipulate light field properties over a wide range, altering the amplitude, phase, and polarization of light waves, thus providing new avenues for beam manipulation. The key to generating vector beams on a chip is to control the phase and polarization of VCSELs using a single integrated metasurface, but this remains elusive. Summary of the Invention

[0005] The purpose of the present invention is to provide a vertical cavity surface emitting laser (VCSEL) for on-chip vector beam generation and a manufacturing method. By integrating a birefringent square nanorod structure on a flip-chip VCSEL, the wavefront phase polarization is regulated, thereby realizing the generation and manipulation of vector beams at the chip level, thereby solving the problems of traditional vector beam generation devices such as complex structure, large size, low reliability, and difficulty in operation.

[0006] The present invention adopts the following technical solutions:

[0007] The present invention provides a vertical cavity surface emitting laser for generating a vector beam on a chip, comprising a lower distributed Bragg reflector and an upper distributed Bragg reflector that are periodically and alternately grown, wherein the upper distributed Bragg reflector and the lower distributed Bragg reflector form a convex frustum structure;

[0008] The bottom surface of the lower distributed Bragg reflector is provided with a substrate layer, the bottom surface of the substrate layer is provided with a metasurface and an N-type metal electrode layer, and the N-type metal electrode layer is located on the periphery of the metasurface; the top surface of the lower distributed Bragg reflector is covered with an active area, an oxidation restriction layer is provided between the active area and the upper distributed Bragg reflector, and a current-limiting oxidation hole is provided in the middle of the oxidation restriction layer;

[0009] The top surface of the upper distributed Bragg reflector is provided with a GaAs heavily doped layer and an ohmic contact protection electrode in sequence from bottom to top; the top surface of the ohmic contact protection electrode, the side surface of the upper distributed Bragg reflector, and the top surface of the active area are all covered with a passivation layer, the outer side of the passivation layer is provided with a cured insulating layer, the passivation layer is provided with an electrode hole above the ohmic contact protection electrode, a P-type metal electrode layer is provided in the electrode hole, and the outer edge of the P-type metal electrode layer covers the top of the passivation layer;

[0010] The center of the P-type metal electrode layer is aligned with the center of the metasurface.

[0011] Preferably, the substrate layer is GaAs; the oxidation restriction layer is Al 0.98 Ga 0.02 As; the passivation layer is SiO2; and the cured insulating layer is benzocyclobutene.

[0012] Preferably, the current limiting oxidation pore has a pore diameter of 2.5 to 3 μm.

[0013] Preferably, the structure of the metasurface is arranged by FDTD unit parameter scanning and light field distribution function combined with MATLAB calculation to obtain the phase information of each position in the layout, and square nanopillars of different sizes are selected to generate a photolithography mask. The designed square nanopillar period is 360nm, and the four different nanopillar sizes are:

[0014] #1: Du=128nm, Dv=252nm;

[0015] #2: Du=150nm, Dv=282nm;

[0016] #3: Du=252nm, Dv=131nm;

[0017] #4: Du=287nm, Dv=151nm.

[0018] Preferably, the unit height of the metasurface is fixed at 700 nm.

[0019] Preferably, the upper distributed Bragg reflector is composed of 30.5 pairs of P-type Al 0.9 Ga 0.1 As and Al 0.12 Ga 0.88 As layers grow alternately;

[0020] The lower distributed Bragg reflector consists of 28 pairs of n-type Al 0.9 Ga 0.1 As and Al 0.12 Ga 0.88 As layers grow alternately.

[0021] The present invention also provides a method for manufacturing a vertical cavity surface emitting laser that generates a vector beam on a chip, comprising the following steps:

[0022] Step 1: fabricating an epitaxial wafer, using a metal organic compound chemical vapor deposition process to epitaxially grow a vertical cavity surface emitting laser epitaxial wafer;

[0023] The structure of the vertical cavity surface emitting laser epitaxial wafer includes a GaAs heavily doped layer, an upper distributed Bragg reflector, an oxidized confinement layer, an active region, a lower distributed Bragg reflector and a substrate layer;

[0024] The upper distributed Bragg reflector is composed of 30.5 pairs of P-type Al 0.9 Ga 0.1 As and Al 0.12 Ga 0.88 As layers are grown alternately; the lower distributed Bragg reflector is composed of 28 pairs of n-type Al 0.9 Ga 0.1 As and Al 0.12 Ga 0.88 As layers grow alternately;

[0025] Step 2: Making an ohmic contact protection electrode, using reverse photolithography and sputtering stripping process to sequentially sputter a certain thickness of Ti and Au on the top surface of the heavily doped GaAs layer as an ohmic contact protection electrode;

[0026] Step 3: Making a SiO2 hard mask, using a plasma enhanced chemical vapor deposition process to deposit a SiO2 layer of a certain thickness as a hard mask, wherein the hard mask completely covers the ohmic contact protection electrode and the GaAs heavily doped layer;

[0027] Step 4: etching to form a frustum, using positive resist photolithography and inductively coupled plasma reactive ion etching to etch the upper distributed Bragg reflector and GaAs heavily doped layer around the ohmic contact protection electrode until the active area is exposed;

[0028] Using a buffered oxide etchant to remove the hard mask on top of the ohmic contact protection electrode by chemical etching;

[0029] Step 5: forming a current-limiting oxidation hole by controlling the oxidation temperature and time using a wet oxidation method to obtain a current-limiting oxidation hole on the oxidation-limiting layer;

[0030] Step 6: Making a passivation layer by using a plasma enhanced chemical vapor deposition process to deposit a SiO2 layer of a certain thickness as a passivation layer, wherein the passivation layer covers the ohmic contact protection electrode and the active area;

[0031] Step 7: forming a solidified insulating layer, spin-coating benzocyclobutene on the outside of the passivation layer, flattening the surface of the spin-coated benzocyclobutene at a set rotation speed, then gradually heating the benzocyclobutene and solidifying it to finally form a solidified insulating layer; after the solidified insulating layer is completely cooled, using reactive ion etching to remove the solidified benzocyclobutene above the ohmic contact protection electrode;

[0032] Step eight, making an electrode hole, using negative resist photolithography and buffered oxide etching solution to etch the middle portion of the passivation layer located above the ohmic contact protection electrode, thereby forming an electrode hole;

[0033] Step nine, forming a P-type metal electrode layer, using reverse photolithography and sputtering lift-off process to sequentially sputter a certain thickness of Ti and Au in the electrode hole as the P-type metal electrode layer, and the outer edge of the P-type metal electrode layer covers the surrounding passivation layer;

[0034] Step 10: Forming an N-type metal electrode layer, by using a reverse photoresist double-sided photolithography and sputtering lift-off process to sequentially sputter a certain thickness of AuGeNi and Au on the periphery of the bottom surface of the substrate layer as the N-type metal electrode layer;

[0035] Step 11, fabricating a metasurface by integrating a metasurface structure in the middle of the bottom surface of the substrate layer using electron beam lithography and ICP-RIE etching processes;

[0036] Preferably, in the step 11, a 180 nm thick hydrogen siloxane layer is spin-coated onto the substrate layer, and then the accelerating voltage is 100 kV and the dose is 5000 μC / cm 2 The electron beam lithography system is used to expose the metasurface pattern, and finally the etching depth of the GaAs nanocolumns is controlled to 700nm by reactive ion etching and inductively coupled plasma etching processes, controlling the etching time and gas ratio.

[0037] Compared with the prior art, the present invention has the following beneficial technical effects:

[0038] The vertical cavity surface emitting laser of the present invention can provide an output beam with a near-Gaussian distribution and TM mode dominance; and the metasurface can effectively control the phase and polarization of the light field at the subwavelength scale. The present invention combines the advantages of both and utilizes the characteristics of its planar structure. Through conventional semiconductor processing technology, it can easily integrate a birefringent square nanocolumn structure on the light-emitting end face of the vertical cavity surface emitting laser, thereby realizing the generation and manipulation of vector beams at the chip level; the developed method paves the way for the VCSEL platform to realize customized vector beams, and solves the problems of traditional vector beam generation devices such as complex structure, large size, low efficiency, and difficult operation; this will likely promote the development of ultra-compact, lightweight and scalable vector beams, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The present invention will be further described below with reference to the accompanying drawings.

[0040] Figure 1 A schematic diagram of the longitudinal cross-section structure of a vertical cavity surface emitting laser for generating vector beams on a chip according to the present invention;

[0041] Figure 2 Schematic diagram of the structure of a VCSEL epitaxial wafer obtained by MOCVD epitaxial growth in step 1 of the present invention;

[0042] Figure 3 Schematic diagram of the ohmic contact protection electrode structure of Ti / Au after photolithography and sputtering in the reverse photoresist process in step 2 of the present invention;

[0043] Figure 4 Schematic diagram of the SiO2 mask deposited by PECVD in step three of the present invention;

[0044] Figure 5 A schematic diagram of defining a circular mesa using positive photolithography and inductively coupled plasma reactive ion etching (ICP-RIE) in step four of the present invention;

[0045] Figure 6 This is a schematic diagram of the structure after silicon dioxide is wet-etched by BOE in step 4 of the present invention;

[0046] Figure 7 Schematic diagram of the formation of current-limited oxidation pores by selective wet oxidation in step five of the present invention;

[0047] Figure 8 Schematic diagram of PECVD deposition of SiO2 passivation layer in step six of the present invention;

[0048] Figure 9 Schematic diagram of spin coating BCB to solidify the insulating layer in step seven of the present invention;

[0049] Figure 10 Schematic diagram of negative photolithography and etching to produce electrode holes in step eight of the present invention;

[0050] Figure 11 Schematic diagram of reverse photolithography and sputtering and stripping Ti / Au to produce a P-type metal electrode layer in step nine of the present invention;

[0051] Figure 12 Schematic diagram of the double-sided alignment photolithography of the reverse photoresist and the sputtering and stripping of AuGeNi / Au to produce the N-type metal electrode layer in step 10 of the present invention;

[0052] Figure 13 Schematic diagram of integrating the metasurface structure on the back side of the substrate by electron beam lithography (EBL) and ICP-RIE etching process in step eleven of the present invention.

[0053] Figure 14 Schematic diagram of the vector beam structure designed for the present invention.

[0054] Explanation of the accompanying symbols: 1. P-type metal electrode layer; 2. Ohmic contact protection electrode; 3. GaAs heavily doped layer; 4. Periodically alternatingly grown upper distributed Bragg reflector; 5. Current-limiting oxide hole; 6. Oxide limiting layer; 7. Passivation layer; 701, electrode hole; 8. Cured insulating layer; 9. Active area; 10. Lower distributed Bragg reflector; 11. GaAs substrate layer; 12. N-type metal electrode layer; 13. Metasurface; 14. Hard mask. DETAILED DESCRIPTION

[0055] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0056] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0057] In the description of the present invention, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0058] like Figure 1 As shown, this embodiment discloses a vertical cavity surface emitting laser for generating vector beams on a chip, comprising a lower distributed Bragg reflector 10 and an upper distributed Bragg reflector 4 that are grown periodically and alternately. The upper distributed Bragg reflector 4 and the lower distributed Bragg reflector 10 form a convex truncated cone structure. The upper distributed Bragg reflector 4 is composed of 30.5 pairs of P-type Al 0.9 Ga 0.1 As and Al 0.12 Ga 0.88 As layers are grown alternately; the lower distributed Bragg reflector 10 consists of 28 pairs of n-type Al 0.9 Ga 0.1 As and Al 0.12 Ga 0.88 As layers grow alternately.

[0059] The bottom surface of the lower DBR 10 is provided with a substrate layer 11. The bottom surface of the substrate layer 11 is provided with a metasurface 13 and an N-type metal electrode layer 12. The N-type metal electrode layer 12 is located on the periphery of the metasurface 13. The top surface of the lower DBR 10 is covered with an active area 9. An oxidation confinement layer 6 is provided between the active area 9 and the upper DBR 4. A current-limiting oxidation aperture 5 is provided in the middle of the oxidation confinement layer 6. The aperture of the current-limiting oxidation aperture 5 is controlled to be 2.5 to 3 μm.

[0060] The top surface of the upper distributed Bragg reflector 4 is provided with a GaAs heavily doped layer 3 and an ohmic contact protection electrode 2 in sequence from bottom to top; the top surface of the ohmic contact protection electrode 2, the side surface of the upper distributed Bragg reflector 4, and the top surface of the active area 9 are all covered with a passivation layer 7, and a cured insulating layer 8 is provided on the outside of the passivation layer 7. The passivation layer 7 is provided with an electrode hole 701 above the ohmic contact protection electrode 2, and a P-type metal electrode layer 1 is provided in the electrode hole 701. The outer edge of the P-type metal electrode layer 1 covers the top of the passivation layer 7.

[0061] In order to ensure that the outgoing beam of the prepared vertical cavity surface emitting laser can be incident from the center of the integrated metasurface structure and realize effective phase and polarization control, it is necessary to align the center of the laser P-side electrode with the center of the N-side electrode of the metasurface structure through a double-sided photolithography process. Therefore, the center of the P-type metal electrode layer 1 in this embodiment needs to be aligned with the center of the metasurface 13.

[0062] In this embodiment, the substrate layer 11 is GaAs; the oxidation restriction layer 6 is Al 0.98 Ga 0.02 As; the passivation layer 7 is SiO2; and the cured insulating layer 8 is benzocyclobutene.

[0063] In this embodiment, the cell height of the metasurface 13 is fixed at 700 nm. The structural arrangement of the metasurface 13 is calculated by FDTD cell parameter scanning and light field distribution function combined with MATLAB to obtain the phase information of each position in the layout. Square nanopillars of different sizes are selected to generate the photolithography mask. The designed square nanopillar period is 360 nm, and the four different nanopillar sizes are:

[0064] #1: Du=128nm, Dv=252nm; #2: Du=150nm, Dv=282nm;

[0065] #3: Du=252nm, Dv=131nm; #4: Du=287nm, Dv=151nm.

[0066] like Figures 2 to 14 As shown, this embodiment also discloses a method for manufacturing a vertical cavity surface emitting laser that generates a vector beam on a chip, comprising the following steps:

[0067] Step 1: make epitaxial wafers, such as Figure 2 As shown in FIG, a vertical cavity surface emitting laser (VCSEL) epitaxial wafer is obtained by epitaxial growth using a metal organic chemical vapor deposition process (MOCVD).

[0068] The structure of the vertical cavity surface emitting laser (VCSEL) epitaxial wafer includes a GaAs heavily doped layer 3, an upper distributed Bragg reflector 4, an oxide confinement layer 6, an active region 9, a lower distributed Bragg reflector 10 and a substrate layer 11. The upper distributed Bragg reflector 4 is composed of 30.5 pairs of P-type Al 0.9 Ga 0.1 As and Al 0.12 Ga 0.88 As layers are grown alternately; the lower distributed Bragg reflector 10 consists of 28 pairs of n-type Al 0.9 Ga 0.1 As and Al 0.12 Ga 0.88 As layers grow alternately;

[0069] In this embodiment, the lasing wavelength of the vertical cavity surface emitting laser epitaxial wafer (VCSEL for short) is 980 nm.

[0070] Step 2: Make an ohmic contact protection electrode, such as Figure 3 As shown, a certain thickness of Ti and Au are sequentially sputtered on the top surface of the GaAs heavily doped layer 3 using reverse photolithography and sputtering lift-off processes as the ohmic contact protection electrode 2. In this embodiment, the thickness of Ti is 150Å and the thickness of Au is 1500Å.

[0071] Step 3: Make a SiO2 hard mask, such as Figure 4 As shown, a SiO2 layer of a certain thickness is deposited as a hard mask 14 using a plasma enhanced chemical vapor deposition process (PECVD for short). The hard mask 14 completely covers the ohmic contact protection electrode 2 and the GaAs heavily doped layer 3.

[0072] In this embodiment, the thickness of the hard mask 14 is 400 nm. The functions of the hard mask 14 are, firstly, to protect the ohmic contact electrode 2 in step 2, and secondly, to provide a circular mesa mask for etching in the following step 4.

[0073] Step 4: Etch to make a frustum, as shown in the figure Figure 5 and 6 As shown, positive photolithography and inductively coupled plasma reactive ion etching (ICP-RIE) are used to form the upper distributed Bragg reflector 4 and the GaAs heavily doped layer 3 around the ohmic contact protection electrode 2 until the active region 9 is exposed.

[0074] The hard mask 14 on the top of the ohmic contact protection electrode 2 is removed by chemical etching using a buffered oxide etchant (BOE solution for short).

[0075] In this embodiment, the diameter of the etched frustum is 50 μm and the height is 5.5 μm.

[0076] Step five, make a current limiting oxide hole, such as Figure 7 As shown, a wet oxidation method is used to control the oxidation temperature and time to obtain a current limiting oxidation hole 5 on the oxidation limiting layer 6. In this embodiment, the current limiting oxidation hole 5 has a pore diameter of 2.5 to 3 μm.

[0077] Step six, make a passivation layer, such as Figure 8 As shown, a SiO 2 layer of a certain thickness is deposited as a passivation layer 7 by using a plasma enhanced chemical vapor deposition process (PECVD for short). The passivation layer 7 covers the ohmic contact protection electrode 2 and the active area 9 .

[0078] In this embodiment, the thickness of the passivation layer 7 is 400 nm.

[0079] Step seven, making a solidified insulating layer, such as Figure 9 As shown, benzocyclobutene (BCB) is spin-coated on the outside of the passivation layer 7, and the surface of the spin-coated benzocyclobutene (BCB) is flattened at a set rotation speed. Then, the benzocyclobutene (BCB) is gradually heated and solidified to finally form a solidified insulating layer 8. After the solidified insulating layer 8 is completely cooled, reactive ion etching (RIE) is used to remove the solidified benzocyclobutene (BCB) above the ohmic contact protection electrode 2.

[0080] Step 8: Make electrode holes, such as Figure 10 As shown, negative resist photolithography and buffered oxide etchant (BOE solution for short) are used to etch the middle portion of the passivation layer 7 located above the ohmic contact protection electrode 2 , thereby forming an electrode hole 701 .

[0081] Step nine, making a P-type metal electrode layer, such as Figure 11 As shown, a reverse photolithography and sputtering stripping process are used to sequentially deposit Ti and Au of a certain thickness in the electrode hole (701) as a P-type metal electrode layer 1, and the outer edge of the P-type metal electrode layer 1 is covered with a surrounding passivation layer 7.

[0082] In this embodiment, the thickness of Ti is 150 Å, and the thickness of Au is 3000 Å.

[0083] Step 10: Make an N-type metal electrode layer, such as Figure 12 As described above, AuGeNi and Au of a certain thickness are sequentially sputtered on the periphery of the bottom surface of the substrate layer 11 by reverse photoresist double-sided lithography and sputtering stripping process as the N-type metal electrode layer 12;

[0084] In this embodiment, the thickness of AuGeNi is 500 Å, and the thickness of Au is 3000 Å. After the N-type metal electrode layer 12 is fabricated, it is annealed at a temperature of 320° C. for 35 seconds.

[0085] Step 11: Make a metasurface, such as Figure 13As shown, the metasurface 13 structure is integrated in the middle of the bottom surface of the substrate layer 11 using electron beam lithography (EBL) and ICP-RIE etching processes.

[0086] Specifically, a 180 nm thick hydrogen silane (HSQ) layer was spin-coated onto the substrate layer, and then the HSQ layer was deposited using an accelerating voltage of 100 kV and a dose of 5000 μC / cm 2 The metasurface pattern is formed by exposure using an electron beam lithography (EBL) system. Finally, reactive ion etching (RIE) and inductively coupled plasma etching (ICP) processes are used to control the etching time and gas ratio so that the GaAs nanocolumn etching depth is controlled at 700nm.

[0087] The embodiments described above are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by persons skilled in the art should fall within the scope of protection defined by the claims of the present invention.

Claims

1. A vertical cavity surface emitting laser (VCSEL) capable of generating a vector beam on-chip, characterized in that: It comprises a lower distributed Bragg reflector (10) and an upper distributed Bragg reflector (4) that are grown alternately and periodically, wherein the upper distributed Bragg reflector (4) and the lower distributed Bragg reflector (10) form a convex truncated cone structure; The bottom surface of the lower distributed Bragg reflector (10) is provided with a substrate layer (11), the bottom surface of the substrate layer (11) is provided with a metasurface (13) and an N-type metal electrode layer (12), and the N-type metal electrode layer (12) is located on the periphery of the metasurface (13); the top surface of the lower distributed Bragg reflector (10) is covered with an active area (9), an oxidation restriction layer (6) is provided between the active area (9) and the upper distributed Bragg reflector (4), and a current-limiting oxidation hole (5) is provided in the middle of the oxidation restriction layer (6); The top surface of the upper distributed Bragg reflector (4) is provided with a GaAs heavily doped layer (3) and an ohmic contact protection electrode (2) in sequence from bottom to top; the top surface of the ohmic contact protection electrode (2), the side surface of the upper distributed Bragg reflector (4), and the top surface of the active area (9) are all covered with a passivation layer (7), a solidified insulating layer (8) is provided on the outer side of the passivation layer (7), an electrode hole (701) is provided on the passivation layer (7) above the ohmic contact protection electrode (2), a P-type metal electrode layer (1) is provided in the electrode hole (701), and the outer edge of the P-type metal electrode layer (1) covers the top of the passivation layer (7); The center of the P-type metal electrode layer (1) is aligned with the center of the metasurface (13).

2. The on-chip vector beam generating vertical cavity surface emitting laser according to claim 1, characterized in that: The substrate layer (11) is GaAs; the oxidation restriction layer (6) is Al 0.98 Ga 0.02 As; the passivation layer (7) is SiO2; and the cured insulating layer (8) is benzocyclobutene.

3. The on-chip vector beam generating vertical cavity surface emitting laser according to claim 1, characterized in that: The current limiting oxidation pore (5) has a pore diameter of 2.5 to 3 μm.

4. The on-chip vector beam generating vertical cavity surface emitting laser according to claim 1, characterized in that: The structure of the metasurface (13) is arranged by FDTD unit parameter scanning and light field distribution function combined with MATLAB calculation to obtain the phase information of each position of the layout, and square nanocolumns of different sizes are selected to generate a photolithography mask. The designed square nanocolumn period is 360nm, and the four different nanocolumn sizes are: #1: Du=128nm, Dv=252nm; #2: Du=150nm, Dv=282nm; #3: Du=252nm, Dv=131nm; #4: Du=287nm, Dv=151nm.

5. The on-chip vector beam generating vertical cavity surface emitting laser according to claim 1, characterized in that: The unit height of the metasurface (13) is fixed at 700 nm.

6. The on-chip vector beam generating vertical cavity surface emitting laser according to claim 1, characterized in that: The upper distributed Bragg reflector (4) is composed of 30.5 pairs of P-type Al 0.9 Ga 0.1 As and Al 0.12 Ga 0.88 As layers grow alternately; The lower distributed Bragg reflector (10) is composed of 28 pairs of n-type Al 0.9 Ga 0.1 As and Al 0.12 Ga 0.88 As layers grow alternately.

7. A method for manufacturing a vertical cavity surface emitting laser capable of generating a vector beam on a chip, characterized in that: The following steps are involved: Step 1: fabricating an epitaxial wafer, using a metal organic compound chemical vapor deposition process to epitaxially grow a vertical cavity surface emitting laser epitaxial wafer; The structure of the vertical cavity surface emitting laser epitaxial wafer includes a GaAs heavily doped layer (3), an upper distributed Bragg reflector (4), an oxidized confinement layer (6), an active region (9), a lower distributed Bragg reflector (10) and a substrate layer (11); The upper distributed Bragg reflector (4) is composed of 30.5 pairs of P-type Al 0.9 Ga 0.1 As and Al 0.12 Ga 0.88 As layers are grown alternately; the lower distributed Bragg reflector (10) is composed of 28 pairs of n-type Al 0.9 Ga 0.1 As and Al 0.12 Ga 0.88 As layers grow alternately; Step 2: fabricating an ohmic contact protection electrode, using a reverse photolithography and sputtering stripping process to sequentially sputter a certain thickness of Ti and Au on the top surface of the heavily doped GaAs layer (3) as an ohmic contact protection electrode (2); Step 3: fabricating a SiO2 hard mask, using a plasma enhanced chemical vapor deposition process to deposit a SiO2 layer of a certain thickness as a hard mask (14), wherein the hard mask (14) completely covers the ohmic contact protection electrode (2) and the GaAs heavily doped layer (3); Step 4: etching to produce a truncated cone, using positive photolithography and inductively coupled plasma reactive ion etching to etch the upper distributed Bragg reflector (4) and the GaAs heavily doped layer (3) around the ohmic contact protection electrode (2) until the active area (9) is exposed; Using a buffered oxide etching solution to remove the hard mask (14) on the top of the ohmic contact protection electrode (2) by chemical etching; Step 5: preparing a current-limiting oxidation hole by controlling the oxidation temperature and time using a wet oxidation method to obtain a current-limiting oxidation hole (5) on the oxidation-limiting layer (6); Step six, making a passivation layer, using a plasma enhanced chemical vapor deposition process to deposit a SiO2 layer of a certain thickness as a passivation layer (7), wherein the passivation layer (7) covers the ohmic contact protection electrode (2) and the active area (9); Step seven, making a solidified insulating layer, spin-coating benzocyclobutene on the outside of the passivation layer (7), flattening the surface of the spin-coated benzocyclobutene at a set rotation speed, then gradually heating the benzocyclobutene and solidifying it, finally forming a solidified insulating layer (8); after the solidified insulating layer (8) is completely cooled, using reactive ion etching to remove the solidified benzocyclobutene above the ohmic contact protection electrode (2); Step eight, making an electrode hole, using negative resist photolithography and buffered oxide etching solution to etch the middle portion of the passivation layer (7) located above the ohmic contact protection electrode (2), thereby forming an electrode hole (701); Step nine, manufacturing a P-type metal electrode layer, using reverse photolithography and sputtering stripping process to sequentially sputter a certain thickness of Ti and Au in the electrode hole (701) as a P-type metal electrode layer (1), wherein the outer edge of the P-type metal electrode layer (1) covers the surrounding passivation layer (7); Step 10, manufacturing an N-type metal electrode layer, by using a reverse photoresist double-sided photolithography and sputtering stripping process to sequentially sputter a certain thickness of AuGeNi and Au on the periphery of the bottom surface of the substrate layer (11) as the N-type metal electrode layer (12); Step eleven: fabricating a metasurface by integrating a metasurface (13) structure in the middle of the bottom surface of the substrate layer (11) using electron beam lithography and ICP-RIE etching processes.

8. The method for manufacturing an on-chip vector beam generating vertical cavity surface emitting laser according to claim 7, characterized in that: In the step 11, a 180 nm thick hydrogen siloxane layer is spin-coated onto the substrate layer, and then the catalyst is heated to 100 kV with a dose of 5000 μC / cm 2 The electron beam lithography system is used to expose the metasurface pattern, and finally the etching depth of the GaAs nanocolumns is controlled to 700nm by reactive ion etching and inductively coupled plasma etching processes, controlling the etching time and gas ratio.

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