A DC / DC control circuit for reducing the conduction loss of the body diode

Abstract

The present invention discloses a DC / DC control circuit for reducing the conduction loss of the body diode. By adopting a digital successive approximation method, the dead time of the next cycle is calculated based on the information of the current switching cycle, so as to successively approximate to the minimum body diode conduction time, which can generally be controlled within 1 to 2 nanoseconds, maximizing the reduction of the conduction loss and improving the efficiency of the DC / DC converter.

Description

Technical Field

[0001] The present invention belongs to the technical field of switching power supply DC / DC converter control, and particularly relates to a DC / DC control circuit for reducing the conduction loss of body diodes. Background Art

[0002] In switching power converters, especially synchronous buck DC / DC converters, two power NMOS transistors are usually used as switching transistors to achieve voltage conversion, as Figure 1 shown. The drain of the high-side power NMOS switching transistor N1 is connected to the power supply VCC, the source is interconnected with the drain of the low-side power NMOS switching transistor N2, and is connected to the first input terminal of the inductor L1. The source of the low-side power NMOS switching transistor N2 is grounded. The second input terminal of the inductor L1 is connected to the first input terminal of the capacitor C1, serving as the output of the DC / DC converter, and the second input terminal of the capacitor C1 is grounded. The gate control signals of the high-side power NMOS switching transistor N1 and the low-side power NMOS switching transistor N2 both come from the output of the previous-stage control chip. Diode D1 is the source-drain parasitic body diode of the high-side power NMOS switching transistor N1, and diode D2 is the source-drain parasitic body diode of the low-side power NMOS switching transistor N2. When N1 is conducting and N2 is off, the power supply stores energy in the load capacitor C1 through N1 and L1; when N1 is off and N2 is conducting, the inductor discharges through N2. To prevent N1 and N2 from conducting simultaneously and generating a large current to damage the DC / DC converter, the common practice is to introduce a dead-time delay unit, and prevent the high-side power NMOS switching transistor and the low-side power NMOS switching transistor from conducting through dead-time delay technology. During the dead-time delay, since both the high-side power NMOS switching transistor and the low-side power NMOS switching transistor are in the off state, the inductor current discharges through the body diode D2, generating body diode conduction loss, resulting in significant power loss of the DC / DC converter.

[0003] In order to reduce the body diode conduction loss and improve the converter efficiency, the industry usually adopts two technologies: fixed-time dead-time control and adaptive dead-time control. Figure 2 Shown is a commonly used adaptive dead-time control circuit. When the PWM signal changes from low to high, after passing through the INV1, NAND1, and U1 units, the high-side power NMOS switching transistor N1 turns off. At this time, after sampling the SW port voltage and the inductor current, through the adaptive dead-time generator, a dead-time related to the inductor current is obtained. After the dead-time, the low-side power NMOS switching transistor N2 turns on. The disadvantage of this structure is that the time for sampling and processing the inductor current is superimposed on the dead-time, usually between a dozen nanoseconds and dozens of nanoseconds, and the dead-time varies greatly under different process conditions and different temperatures. This control method cannot minimize the body diode conduction loss. Summary of the Invention

[0004] To overcome the deficiencies of the prior art, the present invention provides a DC / DC control circuit for reducing the conduction loss of the body diode. It adopts a digital successive approximation method to calculate the dead time of the next cycle based on the information of the current switching cycle, thereby successively approaching the minimum conduction time of the body diode, which can generally be controlled within 1 to 2 nanoseconds, maximizing the reduction of conduction loss and improving the efficiency of the DC / DC converter.

[0005] The technical solution adopted by the present invention to solve its technical problems is as follows:

[0006] A DC / DC control circuit for reducing the conduction loss of the body diode, comprising a high-side power NMOS switch N1, a low-side power NMOS switch N2, a fixed-delay unit U11, a high-side driver U12, an N-bit variable-delay unit U13, a low-side driver N14, a first comparator N15, a second comparator N16, a NOR gate U17, an RS flip-flop U18, a first counter U19, and a second counter U20;

[0007] The drain of the high-side power NMOS switch N1 is connected to the power supply VCC, and the source is interconnected with the drain of the low-side power NMOS switch N2 to form a SW signal. The gate HD of the high-side power NMOS switch N1 is connected to the output of the high-side driver U12;

[0008] The source of the low-side power NMOS switch N2 is grounded, and the gate LD is simultaneously interconnected with the output of the low-side driver U14 and the positive input terminal of the comparator U15;

[0009] The input terminal of the fixed-delay unit U11 is connected to the PWM signal, and the output terminal is connected to the input terminal of the high-side driver U12;

[0010] The input terminal of the N-bit variable-delay unit U13 is connected to the PWM signal, and the N-bit address selection bits are simultaneously connected to the outputs of the counter U19 and the counter U20; the first output terminal of the N-bit variable-delay unit U13 is connected to the first input terminal of the low-side driver U14, and the second output terminal is connected to the second input terminal of the low-side driver U14;

[0011] The negative input terminal of the first comparator U15 is a fixed 2V bias voltage, and the output terminal is connected to the first input terminal of the NOR gate U17;

[0012] The positive input terminal of the second comparator U16 is the SW signal, the negative input terminal is a fixed -0.3V bias voltage, and the output terminal is connected to the second input terminal of the NOR gate U17;

[0013] The output terminal of the NOR gate U17 is connected to the S input terminal of the RS flip-flop U18;

[0014] The R input terminal of the RS flip-flop U18 is the CLK signal, and the output terminal Q is connected to the +1 input terminal of the first counter U19 and the -1 input terminal of the second counter U20;

[0015] The -1 input port of the first counter U19 is the CLK / A signal, and the input enable port is connected to the EN1 signal;

[0016] The +1 input port of the second counter U20 is the CLK / A signal, and the input enable port is connected to the EN2 signal.

[0017] Preferably, the signals of the -1 port of the first counter U19 and the +1 port of the second counter U20 come from 1 / A of the oscillator frequency, that is, every A clock frequencies, the counters U19 and U20 will perform a reverse operation once.

[0018] Preferably, the N unit delay units of the N-bit variable delay unit U13 are cascaded, and the output of each bit is connected to a transmission gate. The transmission gate is controlled by a control signal to switch. In the same switching cycle, only one transmission gate is opened to transmit the k-bit delay time to the OUT terminal.

[0019] The beneficial effects of the present invention are as follows:

[0020] By sampling the gate and drain signals of the low-side power NMOS switch tube, processing through a comparator and changing the output delay time of the N-bit variable delay unit through a counter, the present invention finally realizes the minimum body diode conduction time in a digital successive approximation manner, which can generally be controlled within 1 to 2 nanoseconds, maximally reducing the conduction loss and improving the efficiency of the DC / DC converter. Description of the Drawings

[0021] Figure 1 It is a schematic structural diagram of a buck DC / DC converter in the background technology of the present invention.

[0022] Figure 2 It is a schematic structural diagram of a traditional adaptive dead-time generation circuit in the background technology of the present invention.

[0023] Figure 3 It is the circuit diagram of the present invention.

[0024] Figure 4 It is a schematic diagram of the working waveforms of the SW port and the LD port of a DC / DC control technology circuit structure for reducing the conduction loss of the body diode provided by the present invention.

[0025] Figure 5 It is a schematic structural diagram of an N-bit variable delay unit circuit structure provided by the present invention. Detailed Embodiments

[0026] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0027] The object of the present invention is to propose a DC / DC control technology for reducing the conduction loss of the body diode, so as to solve the problems of the long conduction time of the body diode and the low efficiency of the converter in the traditional technology.

[0028] The present invention proposes a DC / DC control circuit for reducing the conduction loss of the body diode, including power NMOS switch tubes N1 and N2, a fixed delay unit U11, a high-side driver U12, an N-bit variable delay unit U13, a low-side driver N14, comparators N15 and N16, a NOR gate U17, an RS flip-flop U18, and counters U19 and U20. Among them,

[0029] The drain of the high-side power NMOS switch tube N1 is connected to the power supply VCC, the source is interconnected with the drain of the low-side power NMOS switch tube N2 to form a SW signal, and the gate HD is connected to the output of the high-side driver U12.

[0030] The source of the low-side power NMOS switch tube N2 is grounded, and the gate LD is interconnected with the output of the low-side driver U14 and the positive input terminal of the comparator U15.

[0031] The input terminal of the fixed delay unit U11 is connected to the PWM signal, and the output terminal is connected to the input terminal of the high-side driver U12.

[0032] The input terminal of the variable delay unit U13 is connected to the PWM signal, the N-bit address selection bit is connected to the outputs of the counters U19 and U20, and the first output terminal and the second output terminal are connected to the first input terminal and the second input terminal of the low-side driver U14.

[0033] The negative input terminal of the comparator U15 is a fixed 2V bias voltage, and the output terminal is connected to the first input terminal of the NOR gate U17.

[0034] The positive input terminal of the comparator U16 is the SW signal, the negative input terminal is a fixed -0.3V bias voltage, and the output terminal is connected to the second input terminal of the NOR gate U17.

[0035] The output terminal of the NOR gate U17 is connected to the S input terminal of the RS flip-flop U18.

[0036] The R input terminal of the RS flip-flop U18 is the CLK signal, and the output terminal Q is connected to the +1 input terminal of the counter U19 and the -1 input terminal of the U20.

[0037] The -1 input port of the counter U19 is the CLK / A signal, and the input enable port is the EN1 signal.

[0038] The +1 input port of the counter U20 is the CLK / A signal, and the input enable port is the EN2 signal. Specific embodiments:

[0040] A DC / DC control ground circuit for reducing the conduction loss of the body diode proposed by the present invention has a circuit structure as Figure 3 shown. It includes power NMOS switch tubes N1 and N2, a fixed delay unit U11, a high-side driver U12, an N-bit variable delay unit U13, a low-side driver N14, comparators N15 and N16, a NOR gate U17, an RS flip-flop U18, and counters U19 and U20. Among them, the drain of the high-side power NMOS switch tube N1 is connected to the power supply VCC, the source is interconnected with the drain of the low-side power NMOS switch tube N2 to form a SW signal, and the gate HD is connected to the output of the high-side driver U12. The source of the low-side power NMOS switch tube N2 is grounded, and the gate LD is interconnected with the output of the low-side driver U14 and the positive input terminal of the comparator U15. The input terminal of the fixed delay unit U11 is connected to the PWM signal, and the output terminal is connected to the input terminal of the high-side driver U12. The input terminal of the variable delay unit U13 is connected to the PWM signal, the N-bit address selection bits are connected to the outputs of the counters U19 and U20, and the first output terminal and the second output terminal are connected to the first input terminal and the second input terminal of the low-side driver U14. The negative input terminal of the comparator U15 is a fixed 2V bias voltage, and the output terminal is connected to the first input terminal of the NOR gate U17. The positive input terminal of the comparator U16 is the SW signal, the negative input terminal is a fixed -0.3V bias voltage, and the output terminal is connected to the second input terminal of the NOR gate U17. The output terminal of the NOR gate U17 is connected to the S input terminal of the RS flip-flop U18. The R input terminal of the RS flip-flop U18 is the CLK signal, and the output terminal Q is connected to the +1 input terminal of the counter U19 and the -1 input terminal of the U20. The -1 input port of the counter U19 is the CLK / A signal, and the input enable port is the EN1 signal. The +1 input port of the counter U20 is the CLK / A signal, and the input enable port is the EN2 signal.

[0041] When the first PWM signal in the system changes from low to high, that is, when EN1 is in the rising edge state, the counter U19 works. The initial counter U19 output controls the delay time of the m-th bit of the N-bit variable delay unit. If the unit variable delay time is 2 nanoseconds, then in the initial state, when the first PWM signal in the system changes from low to high, the N-bit variable delay unit outputs a delay time of 2m nanoseconds. It is set that 2m nanoseconds should be less than the delay time of the fixed delay unit. At this time, the LD signal first becomes low level, the N2 transistor turns off, and due to the existence of the dead time, the HD signal is still low level, the N2 transistor is in the off state, and the parasitic body diode of the N2 transistor causes the SW signal to become about -0.6V. After the dead time ends, the HD signal becomes high to turn on the N1 transistor, the SW signal becomes high, and the changes of the SW signal and the LD signal are as Figure 4(as shown in (a)). As mentioned above, due to the existence of the dead time, the SW signal and the LD signal are both low for a period of time. The comparators U15 and U16 both output low levels, U17 outputs a high level, controlling the RS flip-flop U18 to output high, the counter U19 performs an increment operation, controlling the N-bit variable delay unit to output a delay time of 2(m + 1) nanoseconds, that is, the upper transistor N1 turns on further in advance, shortening the conduction time of the body diode. It realizes calculating the dead time of the next cycle through the information of the current switching cycle, thereby gradually approaching the minimum conduction time of the body diode. After several cycles, finally, the NOR gate U17 will not output a high level, as Figure 4 (b) shows, achieving a body diode conduction time less than 2 nanoseconds.

[0042] When the first PWM signal of the system changes from high to low, that is, in the falling edge state of EN2, the counter U20 works. The initial counter U20 outputs to control the nth bit delay time of the N-bit variable delay unit. If the unit variable delay time is 2 nanoseconds, then in the initial state, when the first PWM signal of the system changes from high to low, the N-bit variable delay unit outputs a delay time of 2n nanoseconds. It is set that 2n nanoseconds should be greater than the delay time of the fixed delay unit. At this time, the HD signal first becomes low, the N1 transistor turns off, and due to the existence of the dead time, the LD signal is still low, the N2 transistor is in the off state, and the parasitic body diode of the N2 transistor causes the SW signal to become about -0.6V. After the dead time ends, the LD signal becomes high to turn on the N2 transistor, and the SW signal becomes high. The changes of the SW signal and the LD signal are as Figure 4 (c) shows. As mentioned above, due to the existence of the dead time, the SW signal and the LD signal are both low for a period of time. The comparators U15 and U16 both output low levels, U17 outputs a high level, controlling the RS flip-flop U18 to output high, the counter U20 performs a decrement operation, controlling the N-bit variable delay unit to output a delay time of 2(n - 1) nanoseconds, that is, the lower transistor N2 turns on further in advance, shortening the conduction time of the body diode. It realizes calculating the dead time of the next cycle through the information of the current switching cycle, thereby gradually approaching the minimum conduction time of the body diode. After several cycles, finally, the NOR gate U17 will not output a high level, as Figure 4 (d) shows, achieving a body diode conduction time less than 2 nanoseconds.

[0043] The signals of the -1 port of the counter U19 and the +1 port of the counter U20 come from 1 / A of the oscillator frequency, that is, every A clock frequencies, the counters U19 and U20 will perform a reverse operation once. This is to prevent the high-side power NMOS switches N1 and N2 from conducting through when the input voltage, output voltage, and load current states change.

[0044] Figure 5It is one of the circuit structures of the N-bit variable delay unit. N unit delay units are cascaded, and the output of each bit is connected to a transmission gate. The transmission gate is controlled by a control signal to switch. In the same switching cycle, only one transmission gate is turned on to transmit the k-bit delay time to the OUT terminal.

[0045] It can be seen that by sampling the gate and drain signals of the low-side power NMOS switch tube in the current switching cycle, processing through a comparator and changing the output delay time of the N-bit variable delay unit through a counter, the minimum body diode conduction time can be finally achieved in a digital successive approximation manner, which can generally be controlled within 1 to 2 nanoseconds, maximizing the reduction of conduction loss and improving the efficiency of the DC / DC converter.

Claims

1. A DC / DC control circuit for reducing the conduction loss of the body diode, characterized in that, it includes a high-side power NMOS switch N1, a low-side power NMOS switch N2, a fixed delay unit U11, a high-side driver U12, an N-bit variable delay unit U13, a low-side driver N14, a first comparator N15, a second comparator N16, a NOR gate U17, an RS flip-flop U18, a first counter U19 and a second counter U20; The drain of the high-side power NMOS switch N1 is connected to the power supply VCC, and the source is interconnected with the drain of the low-side power NMOS switch N2 to form a SW signal. The gate HD of the high-side power NMOS switch N1 is connected to the output of the high-side driver U12; The source of the low-side power NMOS switch N2 is grounded, and the gate LD is interconnected with the output of the low-side driver U14 and the positive input terminal of the comparator U15 at the same time; The input terminal of the fixed delay unit U11 is connected to the PWM signal, and the output terminal is connected to the input terminal of the high-side driver U12; The input terminal of the N-bit variable delay unit U13 is connected to the PWM signal, and the N-bit address selection bits are connected to the outputs of the counter U19 and the counter U20 at the same time; The first output terminal of the N-bit variable delay unit U13 is connected to the first input terminal of the low-side driver U14, and the second output terminal is connected to the second input terminal of the low-side driver U14; The negative input terminal of the first comparator U15 is a fixed 2V bias voltage, and the output terminal is connected to the first input terminal of the NOR gate U17; The positive input terminal of the second comparator U16 is the SW signal, the negative input terminal is a fixed -0.3V bias voltage, and the output terminal is connected to the second input terminal of the NOR gate U17; The output terminal of the NOR gate U17 is connected to the S input terminal of the RS flip-flop U18; The R input terminal of the RS flip-flop U18 is the CLK signal, and the output terminal Q is connected to the +1 input terminal of the first counter U19 and the -1 input terminal of the second counter U20; The -1 input port of the first counter U19 is the CLK / A signal, and the input enable port is connected to the EN1 signal; The +1 input port of the second counter U20 is the CLK / A signal, and the input enable port is connected to the EN2 signal.

2. The DC / DC control circuit for reducing the conduction loss of the body diode according to claim 1, characterized in that, The signals of the -1 port of the first counter U19 and the +1 port of the second counter U20 come from 1 / A of the oscillator frequency, that is, every A clock frequencies, the counters U19 and U20 will perform a reverse operation once.

3. The DC / DC control circuit for reducing the conduction loss of the body diode according to claim 1, characterized in that, The N unit delay units of the N-bit variable delay unit U13 are cascaded, and the output of each bit is connected to a transmission gate. The transmission gate is controlled by a control signal to switch. In the same switching cycle, only one transmission gate is opened to transmit the k-bit delay time to the OUT terminal.

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