Parallel inverter system and impedance compression method thereof

Abstract

The parallel inverter system and impedance compression method of the present invention relate to a high-frequency inverter impedance compression circuit and modulation method thereof. The purpose is to overcome the problem that when the existing megahertz inverter adopts a passive network for impedance adjustment, it can only limit the changing resistive load, and when the load contains a changing capacitive or inductive component, the input impedance range shows a divergent trend. The parallel inverter system includes: a first impedance compression branch, which is used to compress the load impedance to the first impedance compression branch impedance interval; the value of the center point of the first impedance compression branch impedance interval is recorded as zGoalU; a second impedance compression branch, which is used to compress the changing load impedance to the second impedance compression branch impedance interval; the value of the center point of the second impedance compression branch impedance interval is recorded as zGoalL; a first impedance matching network, which is used to match zGoalU to the ideal impedance point of the first inverter unit; and a second impedance matching network, which is used to match zGoalL to the ideal impedance point of the second inverter unit.

Description

Technical Field

[0001] The invention relates to a high-frequency inverse impedance compression circuit and a modulation method thereof. Background Art

[0002] In recent years, multi-megahertz inverters have been widely used in RF plasma acceleration, wireless power transmission and magnetic resonance imaging systems. In these systems, the inverter needs to work under dynamically changing loads, but the commonly used Class D, E, Φn and other resonant inverters are very sensitive to the load and can only maintain a soft switching state under the rated load. In addition, due to the high switching frequency, multi-megahertz inverters are often difficult to achieve single-cycle closed-loop control by adjusting the frequency or duty cycle. In order to provide an ideal equivalent load for the inverter under a dynamic load environment, the current commonly used solution is to add a first-level impedance modulation network between the inverter and the load.

[0003] The existing impedance matching network is usually composed of multiple vacuum capacitors with adjustable capacitance and fixed inductors. When the load impedance changes, the matching network adjusts the vacuum capacitor in a closed loop according to the measured reflected power through the stepper motor driven vacuum capacitor adjustment method. However, the stepper motor driven adjustment method causes the impedance matching network to respond very slowly, and the vacuum capacitor is expensive and large in size, which restricts the improvement of the overall power density of the inverter system.

[0004] Therefore, in addition to dynamically modulating impedance, passive networks are often used to compress widely varying load impedance into a narrower range to statically adjust the impedance variation range. However, the existing passive network has limited regulation capabilities and can only limit the varying resistive load. When the load contains varying capacitive or inductive components, the input impedance range cannot be controlled and may even show a divergent trend. Summary of the invention

[0005] The purpose of the present invention is to overcome the problem that when the existing megahertz inverter adopts a passive network for impedance adjustment, it can only limit the changing resistive load. When the load contains a changing capacitive or inductive component, the input impedance range tends to diverge. A parallel inverter system and an impedance compression method thereof are provided.

[0006] The present invention provides a parallel inverter system, comprising a first inverter unit, a second inverter unit, a first impedance matching network and a second impedance matching network;

[0007] The voltage input end of the first inverter unit is used to be electrically connected to the voltage output end of the first adjustable DC power supply; the voltage output end of the first inverter unit is electrically connected to the voltage input end of the first impedance matching network to form a first impedance compression branch;

[0008] The voltage input end of the second inverter unit is used to be electrically connected to the voltage output end of the second adjustable DC power supply; the voltage output end of the second inverter unit is electrically connected to the voltage input end of the second impedance matching network to form a second impedance compression branch;

[0009] The current output end of the first impedance compression branch and the current output end of the second impedance compression branch are both used to be electrically connected to the current input end of the load; the load contains a variable capacitive and / or inductive component;

[0010] The first impedance compression branch is used to convert the changing load impedance z Load Compress to the first impedance compression branch impedance interval z U ; The first impedance compression branch impedance interval z U The coordinates on the impedance rectangular coordinate system are (R, X), R∈[0,10], X∈[8,16]; and the impedance interval z of the first impedance compression branch U The value of the center point is recorded as z GoalU ;

[0011] The second impedance compression branch is used to change the load impedance z Load Compress to the second impedance compression branch impedance interval z L ; The second impedance compression branch impedance interval z L The coordinates on the impedance rectangular coordinate system are (R', X'), R'∈[0,10], X'∈[-8,-16]; and the impedance interval z of the second impedance compression branch L The value of the center point is recorded as z GoalL ;

[0012] The first impedance matching network is used to GoalU Matching to the ideal impedance point of the first inverter unit;

[0013] The second impedance matching network is used to GoalL Matching to the ideal impedance point of the second inverter unit;

[0014] And the ideal impedance point of the first inverter unit is the same as the ideal impedance point of the second inverter unit.

[0015] The present invention also provides an impedance compression method for a parallel inverter system. Based on the above-mentioned parallel inverter system, the specific steps are as follows:

[0016] Step 1: Change the load impedance z Load Compression to the first impedance compression branch impedance interval z U and the second impedance compression branch impedance interval z L ;;

[0017] Step 2: z GoalU and zGoalL The impedances of the first inverter unit and the second inverter unit are matched to their ideal impedance points respectively.

[0018] The beneficial effects of the present invention are:

[0019] 1. The variation range of impedance of each branch of the inverter system can be limited to a limited area centered on a specific point;

[0020] 2. Widely varying loads can be compressed to a small range of input impedance centered around the ideal value;

[0021] 3. Under a wide range of loads, the resonant inverter can operate under an ideal load environment, and the voltage across the switch can always maintain soft switching. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the circuit topology of the parallel inverter system of the present invention;

[0023] Figure 2 The impedance z of the first impedance compression branch that compresses the load impedance in the present invention is U ; Compress the load impedance to the impedance z of the second impedance compression branch L Schematic diagram of the principle;

[0024] Figure 3 In the present invention, the first impedance center z GoalU and the second impedance center z GoalL The ideal impedance points z matched to the first inverter voltage source and the second inverter voltage source are respectively Inv Schematic diagram of the principle.

[0025] Figure 4 It is a schematic diagram of the simulation results of the impedance variation range of the first impedance compression branch and the second impedance compression branch in the parallel inverter system and the impedance compression method thereof of the present invention;

[0026] Figure 5 It is a schematic diagram of the simulation results of the input terminal impedance variation range of the parallel inverter system and the impedance compression method thereof of the present invention;

[0027] Figure 6 It is a schematic diagram of the simulation results of the switch drain-source voltage waveform under the parallel inverter system and the impedance compression method of the present invention. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0030] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention. Specific implementation method 1

[0032] The parallel inverter system of this embodiment includes a first inverter unit 1, a second inverter unit 2, a first impedance matching network 3 and a second impedance matching network 4;

[0033] The voltage input end of the first inverter unit 1 is used to be electrically connected to the voltage output end of the first adjustable DC power supply; the voltage output end of the first inverter unit 1 is electrically connected to the voltage input end of the first impedance matching network 3 to form a first impedance compression branch;

[0034] The voltage input end of the second inverter unit 2 is used to be electrically connected to the voltage output end of the second adjustable DC power supply; the voltage output end of the second inverter unit 2 is electrically connected to the voltage input end of the second impedance matching network 4 to form a second impedance compression branch;

[0035] The current output end of the first impedance compression branch and the current output end of the second impedance compression branch are both used to be electrically connected to the current input end of the load 5; the load 5 contains a variable capacitive and / or inductive component;

[0036] The first impedance compression branch is used to convert the changing load impedance z Load Compress to the first impedance compression branch impedance interval z U ; The first impedance compression branch impedance interval z U The coordinates on the impedance rectangular coordinate system are (R, X), R∈[0,10], X∈[8,16]; and the impedance interval z of the first impedance compression branch U The value of the center point is recorded as z GoalU ;

[0037] The second impedance compression branch is used to change the load impedance z Load Compress to the second impedance compression branch impedance interval z L ; The second impedance compression branch impedance interval z LThe coordinates on the impedance rectangular coordinate system are (R', X'), R'∈[0,10], X'∈[-8,-16]; and the impedance interval z of the second impedance compression branch L The value of the center point is recorded as z GoalL ;

[0038] The first impedance matching network 3 is used to GoalU Matching to the ideal impedance point of the first inverter unit 1;

[0039] The second impedance matching network 4 is used to GoalL Matching to the ideal impedance point of the second inverter unit 2;

[0040] Furthermore, the ideal impedance point of the first inverter unit 1 is the same as the ideal impedance point of the second inverter unit 2 . Specific implementation method 2

[0042] This embodiment is a further description of the first embodiment. In this embodiment, the first inverter unit 1 includes a capacitor C INU 、Inductance L FU , Switching device S U , capacitor C FU 、Inductance L RU and capacitor C RU ;

[0043] The positive electrode of the first adjustable DC power supply is connected to the capacitor C INU One end and the inductor L FU One end of the electrical connection;

[0044] Inductance L FU The other end is connected to the switch device S U The source, capacitor C FU One end and the inductor L RU One end of the inductor is electrically connected; RU The other end of the capacitor C RU One end of the capacitor C is electrically connected RU The other end of is used as the voltage output end of the first inverter unit 1;

[0045] The negative electrode of the first adjustable DC power supply, capacitor C INU The other end of the switch device S U The drain and capacitor C FU The other end of is grounded;

[0046] The second inverter unit 2 includes a capacitor C INL 、Inductance L FL , Switching device S L , capacitor C FL 、Inductance L RL and capacitor C RL ;

[0047] The positive electrode of the second adjustable DC power supply is connected to the capacitor C INL One end and the inductor L FL One end of the electrical connection;

[0048] Inductance L FL The other end is connected to the switch device S L The source, capacitor C FL One end and the inductor L RL One end of the inductor is electrically connected; RL The other end of the capacitor C RL One end of the capacitor is electrically connected to RL The other end of is used as the voltage output end of the second inverter unit 2;

[0049] The negative electrode of the second adjustable DC power supply, capacitor C INL The other end of the switch device S L The drain and capacitor C FL The other ends are grounded.

[0050] The other technical features of this embodiment are exactly the same as those of the second embodiment. Specific implementation method three

[0052] This embodiment is a further description of the second embodiment. In this embodiment, the first impedance matching network 3 and the second impedance matching network 4 are both T-type impedance matching networks;

[0053] The first impedance matching network 3 includes an inductor L U1 , capacitor C U2 and inductor L U3 ;

[0054] Inductance L U1 One end of the capacitor C RU The other end is electrically connected;

[0055] Inductance L U1 The other end is connected to the capacitor C U2 One end and the inductor L U3 One end of the electrical connection;

[0056] Capacitor C U2 The other end of the inductor is electrically connected to the load 5; U3 The other end is grounded;

[0057] The second impedance matching network 4 includes an inductor L L1 、Inductance L L2 and inductor L L3 ;

[0058] Inductance L L1 One end of the capacitor CRL The other end is electrically connected;

[0059] Inductance L L1 The other end is connected to the inductor L L2 One end and the inductor L L3 One end of the electrical connection;

[0060] Inductance L L2 The other end of the inductor is electrically connected to the load 5; L3 The other end is grounded.

[0061] The other technical features of this embodiment are exactly the same as those of the third embodiment. Specific implementation method four

[0063] The impedance compression method of the parallel inverter system of this embodiment is a further description of the parallel inverter system of the first, second or third embodiment. In this embodiment, the specific steps are as follows:

[0064] Step 1: Change the load impedance z Load Compression to the first impedance compression branch impedance interval z U and the second impedance compression branch impedance interval z L ;;

[0065] Step 2: z GoalU and z GoalL Matched to the ideal impedance points of the first inverter unit 1 and the second inverter unit 2 respectively.

[0066] The other technical features of this embodiment are exactly the same as those of embodiments one, two or three. Specific implementation method five

[0068] This implementation is a further description of the fourth implementation. In this implementation, step one is as follows:

[0069] Step 1: Get z by simulation in the impedance rectangular coordinate system GoalU and z GoalL , so that the first impedance compression branch impedance interval z U In z GoalU In the region (R, X) with the center point, the impedance interval of the second impedance compression branch is z L In z GoalL The center is in the (R', X') region, and the impedance interval z of the second impedance compression branch is obtained. L The impedance interval z of the first impedance compression branch U The corresponding relationship;

[0070] Step 1 and 2: By adjusting the current amplitude and current phase of the first impedance compression branch and the second impedance compression branch, the load impedance zLoad Match to the first impedance compression branch impedance interval z U and the second impedance compression branch impedance interval z L Place.

[0071] The other technical features of this embodiment are exactly the same as those of embodiment 4. Specific implementation method 6

[0073] This embodiment is a further explanation of the fifth embodiment. In this embodiment, in step 11, the impedance z of the second impedance compression branch is obtained by the following formula: L The impedance interval z of the first impedance compression branch U The corresponding relationship:

[0074]

[0075] Among them, z Load is the load impedance, z L is the impedance of the second impedance compression branch, Z Load is the magnitude of the load impedance, is the phase of the load impedance, k is the scaling factor of the impedance range, k=0.4~0.5; i is the imaginary unit.

[0076] The other technical features of this embodiment are exactly the same as those of embodiment five. Specific implementation method seven

[0078] This embodiment is a further explanation of the sixth embodiment. In this embodiment, steps one and two are as follows:

[0079]

[0080] Among them, I U is the current amplitude of the output current of the first impedance compression branch, I L is the current amplitude of the output current of the second impedance compression branch; is the current phase of the output current of the first impedance compression branch, The second impedance compresses the current phase of the branch output current.

[0081] The other technical features of this embodiment are exactly the same as those of embodiment six. Specific implementation method eight

[0083] This implementation is a further explanation of the seventh implementation. In this implementation, step 2 is specifically as follows:

[0084] Step 21: According to z GoalU 、z GoalL and the ideal impedance value z Inv, obtain the impedance parameters of the first impedance matching network 3 and the second impedance matching network 4;

[0085] Step 22: Calculate the input DC voltage V of the first inverter unit 1 INU and the phase of the switch drive signal The input DC voltage V of the second inverter unit 2 INL and the phase of the switch drive signal And the input voltage v of the first impedance matching network 3 U and the input voltage v of the second impedance matching network 4 L ;

[0086] And through the input DC voltage V of the first inverter unit 1 INU and the phase of the switch drive signal Control the first impedance matching network 3 to GoalU Matches to the ideal impedance point of the first inverter unit 1, and the input DC voltage V through the second inverter unit 2 INL and the phase of the switch drive signal Control the second impedance matching network 4 to GoalL Matched to the ideal impedance point of the second inverter unit 2.

[0087] The other technical features of this embodiment are exactly the same as those of embodiment seven. Specific implementation method nine

[0089] This embodiment is a further description of the eighth embodiment. In this embodiment, in step 21, the impedance parameters of the first impedance matching network 3 and the second impedance matching network 4 are obtained by the following formula:

[0090]

[0091] Among them, R GoalU , X GoalU They are z GoalU The resistance and reactance components of GoalL , X GoalL They are z GoalL The resistance and reactance components of inv , X inv are the values ​​of the ideal impedance point z Inv The resistance and reactance components of CU1 ,z CU2 ,z CU3 ,z CL1 ,z CL2 ,z CL3 They are inductance L U1 , capacitor C U2 、Inductance L U3 、Inductance LL1 、Inductance L L2 and inductor L L3 Impedance value.

[0092] The other technical features of this embodiment are exactly the same as those of embodiment eight. Specific implementation method ten

[0094] This embodiment is a further explanation of the ninth embodiment. In this embodiment, in step 22, the input DC voltage V of the first inverter unit 1 is obtained by the following formula: INU and the phase of the switch drive signal and the input DC voltage V of the second inverter unit 2 INL and the phase of the switch drive signal

[0095]

[0096] Among them, P Load is the desired output power, R Load is the load resistance component;

[0097] The input voltage v of the first impedance matching network 3 is obtained by the following formula: U and the input voltage v of the second impedance matching network 4 L :

[0098]

[0099] The other technical features of this embodiment are exactly the same as those of embodiment nine.

[0100] Example

[0101] The present invention is directed to an equivalent circuit of an ultra-high frequency inverter system such as Figure 1 The inverter system consists of two sets of ultra-high frequency resonant Class E voltage sources with adjustable amplitude and phase in parallel, where the amplitude of the voltage source is determined by the input DC voltage V INU ,V INL Control, the voltage source phase is controlled by the switch drive signal phase Each branch is connected with an additional set of T-type matching networks.

[0102] The impedance compression method includes two steps. First, the amplitude and phase of the current in the impedance compression branch are controlled to change the load impedance z load Compressed to a narrower range, z U ,z L , and then further z through the T-type network in the branch U and z L Match to the ideal impedance point z Inv .

[0103] Load impedance z load to z U , z L The compression method is as follows Figure 2 As shown. Figure 1 For the parallel inverter system circuit, the upper and lower branch impedance z U ,z L There is a corresponding relationship, so for any load impedance z Load Next, first you need to get the z U ,z L Both are in z GoalU , z GoalL z in a limited area centered at L Value. GoalU , z GoalL It can be obtained through simulation, provided that z U ,z L The range is the smallest and is located in the positive half of the x-axis.

[0104]

[0105] Among them, z Load ,z L is the load impedance and the lower branch impedance, Z Load , are the magnitude and phase of the load impedance respectively. k is the scaling factor of the impedance range. When k = 0, only the lower branch impedance z L is compressed. When k = 1, only the upper branch impedance z U is compressed. Usually k can be selected between 0.4 and 0.5 to make z U and z L Varies within the same range.

[0106] When the target impedance z L After being determined, the load impedance z can be adjusted by adjusting the current amplitude and phase as shown in the figure. Load Match to z U '(New z U ) and z L Place.

[0107]

[0108] Compressed to z GoalU ,z GoalL The branch impedance z is the center U ,z L Need to further match to the ideal impedance point of the inverter: z Inv Therefore, the T-type network in each branch can be designed to GoalU ,z GoalL Match to zInv .

[0109]

[0110] In the formula, R GoalU ,X GoalU ,R GoalL ,X GoalL The impedance center z GoalU ,z GoalL The resistance and reactance components of R inv ,X inv The target impedance z Inv The resistance and reactance components of CU1 ,z CU2 ,z CU3 ,z CL1 ,z CL2 ,z CL3 is the impedance value of the component in the T-type impedance network. CU1 ,z CU2 ,z CU1 ,z CU2 determines the impedance center position, and z CU3 , z CL3 The value of z determines Inv The impedance variation range is centered. Usually, z CU3 , z CL3 Should be greater than z U and z L .

[0111] After the relevant parameters of the T-type network are determined, the current amplitude and phase distribution relationship in can be indirectly controlled by the input voltage amplitude and phase. Then the input voltage v of the proposed impedance compression network is U , v L Can be obtained by seeking.

[0112]

[0113] Where P Load is the desired output power, R Load is the load resistance component. The inverter system input DC voltage V INU ,V INL Phase with switch drive signal It can be finally obtained by solving .

[0114]

[0115] Effect:

[0116] 1. If Figure 4 As shown, based on the proposed parallel inverter system, the variation range of the impedance of each branch of the inverter system can be limited to a limited area centered at a specific point.

[0117] 2. If Figure 5 As shown, based on the proposed parallel inverter system and its impedance compression method, the load with a wide range of variations can be compressed to a small range of input impedance centered on the ideal value.

[0118] 3. If Figure 6 As shown, based on the proposed parallel inverter system, under a wide range of loads, the resonant inverter can operate under an ideal load environment, and the voltage across the switch can always maintain soft switching.

[0119] The designed parallel Class E inverter system and impedance compression method are oriented to plasma generators and wireless power transmission systems. The output power is 50W, the operating frequency is 13.56MHz, the rated duty cycle is 50%, and the load range is 20±50jΩ~80±50jΩ. Through reasonable parameter design, the wide range of impedance can be mapped to the ideal area. The passive components in the system are all RF inductors and capacitors. The inductors are wound by 3x0.15mm copper tape, which can significantly improve the quality factor of the inductor at megahertz frequencies and improve the overall efficiency of the inverter. The component parameters of the main circuit can be determined by the rated working conditions. The specific parameters are shown in Table 1.

[0120] Table 1 High frequency inverter system parameters

[0121]

[0122] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the features of the various dependent claims and herein may be combined in a manner different from that described in the original claims. It should also be understood that the features described in conjunction with the individual embodiments may be used in other embodiments.

Claims

1. Parallel inverter system, characterized in that: It comprises a first inverter unit (1), a second inverter unit (2), a first impedance matching network (3) and a second impedance matching network (4); The voltage input end of the first inverter unit (1) is used to be electrically connected to the voltage output end of the first adjustable DC power supply; the voltage output end of the first inverter unit (1) is electrically connected to the voltage input end of the first impedance matching network (3) to form a first impedance compression branch; The voltage input end of the second inverter unit (2) is used to be electrically connected to the voltage output end of the second adjustable DC power supply; the voltage output end of the second inverter unit (2) is electrically connected to the voltage input end of the second impedance matching network (4) to form a second impedance compression branch; The current output end of the first impedance compression branch and the current output end of the second impedance compression branch are both used to be electrically connected to the current input end of a load (5); the load (5) contains a variable capacitive and / or inductive component; The first impedance compression branch is used to convert the changing load impedance z Load Compress to the first impedance compression branch impedance interval z U ; The first impedance compression branch impedance interval z U The coordinates on the impedance rectangular coordinate system are (R, X), R∈[0,10], X∈[8,16]; and the impedance interval z of the first impedance compression branch U The value of the center point is recorded as z GoalU ; The second impedance compression branch is used to change the load impedance z Load Compress to the second impedance compression branch impedance interval z L The second impedance compression branch impedance interval z L The coordinates on the impedance rectangular coordinate system are (R', X'), R'∈[0,10], X'∈[-8,-16]; and the second impedance compression branch impedance interval z L The value of the center point is recorded as z GoalL ; The first impedance matching network (3) is used to GoalU Matching to the ideal impedance point of the first inverter unit (1); The second impedance matching network (4) is used to GoalL Matching to the ideal impedance point of the second inverter unit (2); Furthermore, the ideal impedance point of the first inverter unit (1) is the same as the ideal impedance point of the second inverter unit (2).

2. The parallel inverter system according to claim 1, characterized in that: The first inverter unit (1) comprises a capacitor C INU 、Inductance L FU , Switching device S U , capacitor C FU 、Inductance L RU and capacitor C RU ; The positive electrode of the first adjustable DC power supply is connected to the capacitor C INU One end and the inductor L FU One end of the electrical connection; Inductance L FU The other end is connected to the switch device S U The source, capacitor C FU One end and the inductor L RU One end of the inductor is electrically connected; RU The other end of the capacitor C RU One end of the capacitor is electrically connected to RU The other end of the first inverter unit (1) serves as a voltage output end; The negative electrode of the first adjustable DC power supply, capacitor C INU The other end of the switch device S U The drain and capacitor C FU The other end of is grounded; The second inverter unit (2) includes a capacitor C INL 、Inductance L FL , Switching device S L , capacitor C FL 、Inductance L RL and capacitor C RL ; The positive electrode of the second adjustable DC power supply is connected to the capacitor C INL One end and the inductor L FL One end of the electrical connection; Inductance L FL The other end is connected to the switch device S L The source, capacitor C FL One end and the inductor L RL One end of the inductor is electrically connected; RL The other end of the capacitor C RL One end of the capacitor is electrically connected to RL The other end of the inverter unit (2) serves as a voltage output end of the second inverter unit (2); The negative electrode of the second adjustable DC power supply, capacitor C INL The other end of the switch device S L The drain and capacitor C FL The other ends are grounded.

3. The parallel inverter system according to claim 2, characterized in that: The first impedance matching network (3) and the second impedance matching network (4) are both T-type impedance matching networks; The first impedance matching network (3) includes an inductor L U1 , capacitor C U2 and inductor L U3 ; Inductance L U1 One end of the capacitor C RU The other end is electrically connected; Inductance L U1 The other end is connected to the capacitor C U2 One end and the inductor L U3 One end of the electrical connection; Capacitor C U2 The other end of the inductor is electrically connected to the load (5); U3 The other end is grounded; The second impedance matching network (4) includes an inductor L L1 、Inductance L L2 and inductor L L3 ; Inductance L L1 One end of the capacitor C RL The other end is electrically connected; Inductance L L1 The other end is connected to the inductor L L2 One end and the inductor L L3 One end of the electrical connection; Inductance L L2 The other end of the inductor is electrically connected to the load (5); L3 The other end is grounded.

4. The impedance compression method of the parallel inverter system is characterized in that: Based on the parallel inverter system according to any one of claims 1 to 3, the specific steps are as follows: Step 1: Change the load impedance z Load Compression to the first impedance compression branch impedance interval z U and the second impedance compression branch impedance interval z L ; Step 2: z GoalU and z GoalL The impedance points are matched to the ideal impedance points of the first inverter unit (1) and the second inverter unit (2) respectively.

5. The impedance compression method of the parallel inverter system according to claim 4, characterized in that: Step 1 is as follows: Step 1: Get z by simulation in the impedance rectangular coordinate system GoalU and z GoalL , so that the first impedance compresses the branch impedance interval z U In z GoalU In the region (R, X) with the center point, the impedance interval of the second impedance compression branch is z L In z GoalL The center is in the (R', X') region, and the impedance interval z of the second impedance compression branch is obtained. L The impedance interval z of the first impedance compression branch U The corresponding relationship; Step 1 and 2: By adjusting the current amplitude and current phase of the first impedance compression branch and the second impedance compression branch, the load impedance z Load Match to the first impedance compression branch impedance interval z U and the second impedance compression branch impedance interval z L Place.

6. The impedance compression method of the parallel inverter system according to claim 5, characterized in that: In step 1, the impedance z of the second impedance compression branch is obtained by the following formula: L The impedance interval z of the first impedance compression branch U The corresponding relationship: Among them, z Load is the load impedance, z L is the impedance of the second impedance compression branch, Z Load is the magnitude of the load impedance, is the phase of the load impedance, k is the scaling factor of the impedance range, k=0.4~0.5; i is the imaginary unit.

7. The impedance compression method of the parallel inverter system according to claim 6, characterized in that: In steps one and two, the details are as follows: Among them, I U is the current amplitude of the output current of the first impedance compression branch, I L is the current amplitude of the output current of the second impedance compression branch; is the current phase of the output current of the first impedance compression branch, The second impedance compresses the current phase of the branch output current.

8. The impedance compression method of the parallel inverter system according to claim 7, characterized in that: Step 2 is as follows: Step 21: According to z GoalU 、z GoalL and the ideal impedance value z Inv , obtaining impedance parameters of the first impedance matching network (3) and the second impedance matching network (4); Step 22: Calculate the input DC voltage V of the first inverter unit (1) INU and the phase of the switch drive signal The input DC voltage V of the second inverter unit (2) INL and the phase of the switch drive signal and the input voltage v of the first impedance matching network (3) U and the input voltage v of the second impedance matching network (4) L ; And through the input DC voltage V of the first inverter unit (1) INU and the phase of the switch drive signal Control the first impedance matching network (3) to GoalU Matched to the ideal impedance point of the first inverter unit (1), and the input DC voltage V through the second inverter unit (2) INL and the phase of the switch drive signal Control the second impedance matching network (4) to set z GoalL Matched to the ideal impedance point of the second inverter unit (2).

9. The impedance compression method of the parallel inverter system according to claim 8, characterized in that: In step 21, the impedance parameters of the first impedance matching network (3) and the second impedance matching network (4) are obtained by the following formula: Among them, R GoalU , X GoalU They are z GoalU The resistance and reactance components of GoalL , X GoalL They are z GoalL The resistance and reactance components of inv , X inv are the values ​​of the ideal impedance point z Inv The resistance and reactance components of CU1 ,z CU2 ,z CU3 ,z CL1 ,z CL2 ,z CL3 They are inductance L U1 , capacitor C U2 、Inductance L U3 、Inductance L L1 、Inductance L L2 and inductor L L3 Impedance value.

10. The impedance compression method of the parallel inverter system according to claim 9, characterized in that: In step 22, the input DC voltage V of the first inverter unit (1) is obtained by the following formula: INU and the phase of the switch drive signal and the input DC voltage V of the second inverter unit (2) INL and the phase of the switch drive signal Among them, P Load is the desired output power, R Load is the load resistance component; The input voltage v of the first impedance matching network (3) is obtained by the following formula: U and the input voltage v of the second impedance matching network (4) L :

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