Pulse modulation method and related equipment based on nine-segment three-level converter

Abstract

The present application discloses a pulse modulation method, apparatus, and computing device based on a nine-segment three-level converter. The method includes: normalizing the vector space to generate a normalized sector; converting the target vector into a vector within the normalized sector, recorded as a normalized vector; selecting a reference vector with the same angle as the normalized vector, and calculating the action time of the basic vector synthesizing the reference vector to obtain the switching timing of the reference vector; superimposing a preset PWM wave on the switching timing of the reference vector to generate an equivalent switching timing of the normalized vector; and obtaining a nine-segment switching state timing diagram of the target vector based on the corresponding relationship between the target vector and the first vector. This method greatly reduces the computational complexity of the three-level converter space vector modulation algorithm and ensures that the system harmonic distortion (THD) is within an acceptable range.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a pulse modulation method, a transmission control device, and a computing device based on a nine-segment three-level converter. Background Art

[0002] Multilevel converters are widely used in high-power, high-voltage applications. Compared to two-level converters, multilevel converters are favored due to their low output current and voltage harmonics, high voltage resistance of switching devices, good output waveform quality, and lower common-mode voltage.

[0003] Traditional modulation strategies for three-phase, three-level converters include SPWM and SVPWM. SVPWM modulation strategies are widely used due to their higher voltage efficiency and lower harmonics. The three-level SVPWM algorithm divides the entire three-level vector into six large sectors, each of which is further divided into four smaller sub-sectors: A, B, C, and D. It then determines the numbers of the 24 specific small triangles in the reference voltage vector space and calculates the action time of each effective vector and the switching angle between each small triangle within each sector. This modulation method is computationally intensive, requiring the calculation of the vector synthesis time within each of the 24 small sectors. The solution is complex and requires the storage of a large number of fixed tables, limiting its applicability. To simplify the calculation, two main approaches exist: 1. Converting the three-level vector to a two-level vector through coordinate translation. However, to obtain the target vector in the entire vector space, the solution must be performed for each small triangle within the large sector, which is still computationally intensive. 2. Using a non-orthogonal coordinate system, it can be divided into the gh coordinate system, kl coordinate system, α-β coordinate system and imaginary coordinate system, but it is still necessary to solve the situation of each small triangle in the large sector, and the amount of calculation is still very large.

[0004] Therefore, in the prior art, especially in the FPGA-based scenario, three-level modulation cannot quickly realize the on-off of the switching device. Summary of the Invention

[0005] The embodiments of the present application provide a pulse modulation method and related equipment based on a nine-segment three-level converter, which reduces the response time of a multi-level converter and improves the on-off efficiency of a control switch device.

[0006] A pulse modulation method based on a nine-segment three-level converter, comprising:

[0007] Normalize the vector space to generate a normalized sector;

[0008] Convert the target vector into the corresponding vector in the normalized sector, recorded as the normalized vector;

[0009] Selecting a reference vector with the same angle as the first vector, and calculating the action time of a basic vector synthesizing the reference vector to obtain a switching timing sequence;

[0010] Superimposing a preset PWM wave on the switching timing of the reference vector to generate an equivalent switching timing of the first vector;

[0011] According to the corresponding relationship between the target vector and the first vector, a nine-segment switching state timing diagram of the target vector is obtained.

[0012] Preferably, the normalized sector is specifically a 30° sector, which is specifically implemented as follows:

[0013] Starting from 0° and at intervals of 30°, the entire vector space can be divided into 12 sectors.

[0014] Preferably, the method further comprises: selecting a basic vector to synthesize the reference vector, including:

[0015] In the normalized sector, basic vectors are selected and synthesized according to seven-segment vectors to obtain the reference vector.

[0016] Preferably, the selecting of basic vectors to synthesize the reference vector is specifically implemented as follows:

[0017] The inscribed circle of the vector space is taken as the reference circle, and the vector whose end point is on the reference circle is taken as the reference vector;

[0018] According to the volt-second balance theorem, the action time of the basic vector corresponding to the reference vector is obtained, and the basic vector is recorded as; The action time is recorded as: T 01 , T 12 and T1.

[0019] Preferably, the method further comprises:

[0020] Establishing a correspondence between the target vector and the first vector includes:

[0021] Construct a one-to-one correspondence between the modules of the components on the abc axis;

[0022] The relationship between the intermediate level time corresponding to the first vector and the intermediate level time of the target vector is obtained according to the corresponding relationship.

[0023] A pulse modulation control device based on a nine-segment three-level converter, comprising:

[0024] A normalization unit, used to normalize the vector space and generate a normalized sector;

[0025] A vector conversion unit is used to convert the target vector into a corresponding vector in the normalized sector, which is recorded as a normalized vector;

[0026] A reference vector acquisition unit is configured to acquire a reference vector having the same angle as the normalized vector, and calculate the action time of a basic vector synthesizing the reference vector to obtain a switching timing sequence;

[0027] an equivalent switching timing generation unit, configured to superimpose a preset PWM wave on the switching timing of the reference vector to generate an equivalent switching timing of the first vector;

[0028] The nine-segment switch state timing generation unit is configured to obtain a nine-segment switch state timing diagram of the target vector according to a corresponding relationship between the target vector and the first vector.

[0029] Preferably, the corresponding relationship building unit is specifically implemented as follows:

[0030] Construct a one-to-one correspondence between the modules of the components on the abc axis;

[0031] The relationship between the intermediate level time corresponding to the first vector and the intermediate level time of the target vector is obtained according to the corresponding relationship.

[0032] Preferably, the device further includes: a reference vector synthesis unit, which selects a basic vector to synthesize the reference vector, which is specifically implemented as follows:

[0033] In the normalized sector, basic vectors are selected and synthesized according to the seven-segment vector to obtain the reference vector, which is specifically implemented as follows: an inscribed circle in the vector space is used as the reference circle, and a vector whose end point is on the reference circle is used as the reference vector;

[0034] According to the volt-second balance theorem, the action time of the basic vector corresponding to the reference vector is obtained, and the basic vector is recorded as; The action time is recorded as: T 01 , T 12 and T1.

[0035] A computing device comprising:

[0036] at least one processor; and a memory communicatively coupled to the at least one processor;

[0037] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the above method.

[0038] The present invention is based on a pulse modulation method for a nine-segment three-level converter. The algorithm provided by the present invention is based on a conventional seven-segment vector synthesis method to obtain the switching timing and intermediate level time of the reference vector in the 0-30° sector. Based on the concept of "DC chopping voltage regulation", a "PWM wave" is added to the switching timing of the reference vector to convert the seven-segment into a nine-segment, thereby obtaining a target vector with any modulus smaller than the reference vector in the sector and expanding it to the entire vector space. This greatly reduces the computational complexity of conventional modulation algorithms, reduces the time consumption of space vector modulation of multi-level converters, and ensures that the system harmonic distortion (THD) is within an acceptable range. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0040] Figure 1 A schematic diagram of a pulse modulation scenario based on a nine-segment three-level converter in the prior art;

[0041] Figure 2 Schematic diagram of a normalized sector of a pulse modulation method based on a nine-segment three-level converter in an embodiment of the present application;

[0042] Figure 3 Schematic diagram of the flow of a pulse modulation method based on a nine-segment three-level converter in an embodiment of the present application;

[0043] Figure 4 Schematic diagram of a nine-segment switch state timing diagram of a pulse modulation method based on a nine-segment three-level converter in an embodiment of the present application;

[0044] Figure 5 Schematic diagram of the corresponding relationship of the pulse modulation method based on the nine-segment three-level converter in the embodiment of the present application;

[0045] Figure 6 Schematic diagram of the relationship between the angle of the reference vector and the sequence diagram of the corresponding basic vector in the pulse modulation control method based on the nine-segment three-level converter in the embodiment of the present application;

[0046] Figure 7 Schematic diagram of a pulse modulation control device based on a nine-segment three-level converter in an embodiment of the present application

[0047] Figure 8 A schematic diagram of the structure of a computing device based on an embodiment of the present application in an embodiment of the present application;

[0048] Figure 9This is a structural diagram of the computer-readable medium in the embodiment of the present application. DETAILED DESCRIPTION

[0049] The embodiments of the present application provide a pulse modulation method and related equipment based on a nine-segment three-level converter, which reduces the response time of the multi-level converter and improves the on-off efficiency of the control switching device.

[0050] To address the shortcomings of existing algorithms, this patent aims to reduce the response time of multi-level converters. By normalizing the entire vector space into 30° sectors and leveraging the concept of DC chopping voltage regulation, a space vector pulse width modulation (SVPWM) algorithm for three-level converters is proposed. By using symmetry and rotation concepts to extend the algorithm to the entire vector space, the algorithm significantly reduces the computational complexity of the traditional seven-segment modulation algorithm. This algorithm is particularly suitable for accelerating the switching control of three-level converters controlled by FPGAs.

[0051] Figure 1 A pulse modulation method based on a nine-segment three-level converter is shown, comprising:

[0052] S11: Normalize the vector space to generate a normalized sector;

[0053] As a preferred method, the normalization step is to divide the vector space into 12 sectors with an interval of 30°. The vector space is normalized into a standardized 30° sector, i.e., sector 0. That is, starting from 0°, with an interval of 30°, the entire vector space can be divided into 12 sectors, such as Figure 2 shown.

[0054] S12: Convert the target vector into a corresponding vector in the normalized sector to generate a target vector in the normalized sector, which is recorded as a first vector;

[0055] For the entire space vector, the vector of any angle (Target vector) can be converted into a vector within the 0-30° sector by the following formula (first vector):

[0056] θ=30°-|30°-mod(α / 60°)|, where α is the target vector in the space vector diagram , θ is the angle normalized to the 0-30° sector, and mod() is the remainder function;

[0057] S13: Select a reference vector having the same angle as the first vector, and calculate the action time of a basic vector synthesizing the reference vector to obtain a switching timing of the reference vector;

[0058] Preferably, selecting a basic vector to synthesize the reference vector includes:

[0059] In the normalized sector, basic vectors are selected and synthesized according to a seven-segment vector to obtain the reference vector.

[0060] Obtaining the basic vector closest to the first vector and the corresponding action time, where the basic vector is recorded as; The action time is recorded as: T 01 , T 12 and T1;

[0061] Determine the optimal switching sequence, and obtain the three switching timing diagram types and the action time of the intermediate level based on the optimal switching sequence, which is recorded as T ar , T br and T cr , as an example, the calculation method is shown in the figure:

[0062] The order of their effect is: (1,0,0)→(1,0,-1)→(1,-1,-1)→(0,-1,-1)→(1,-1,-1)→(1,0,-1)→(1,0,0)

[0063] S14: superimposing a preset PWM wave on the switching timing of the reference vector to generate an equivalent switching timing of the first vector;

[0064] Based on the concept of “DC chopping voltage regulation”, a duty cycle of The "PWM wave" of the target vector Required equivalent switching state timing diagram.

[0065] By combining the time periods of the same potential state, a nine-segment switching state vector diagram is obtained, and the new intermediate level time is obtained as follows:

[0066] Where m is The action time of the zero vector is (1-m)*T, and the first vector The order of basic vector action is: (0,0,0)→(1,0,0)→(1,0,-1)→(1,-1,-1)→(0,-1,-1)→(1,-1,-1)→(1,0,-1)→(1,0,0)→(0,0,0)

[0067] When the PWM wave is high, the target vector With reference vector The switching states of the three phases are the same; when the PWM wave is low, the switching states of the three phases are all 0, which is equivalent to zero vector The time of action. From this we can understand that the target vector is through the basic vector To synthesize, V0 is the starting vector.

[0068] S15: According to the corresponding relationship between the target vector and the first vector, a nine-segment switching state timing diagram of the target vector is obtained.

[0069] refer to Figure 3 , constructing a correspondence between the target vector and the first vector, including:

[0070] S31: Construct a one-to-one correspondence between the modules of the components on the abc axis;

[0071] S32: Obtaining a relationship between an intermediate level time corresponding to the first vector and an intermediate level time of the target vector according to the corresponding relationship.

[0072] The shape of the seven-segment switch state timing diagram can be divided into 4 categories. The shape of the nine-segment timing diagram can also be divided into 4 categories. After determining the shape of the three-phase timing diagram in sector 0, you can use and The corresponding relationship between the components on the abc axis gives the shape of the three-phase timing diagram of other sectors, such as Figure 4 shown.

[0073] Through the above analysis, for the target vector that is not in the 0-30° sector It can be converted into the 0-30° sector through symmetry and rotation. The corresponding switching timing diagram of the three-phase switch is the intermediate level time T A 、T B 、T C With T a 、T b 、T c The corresponding relationship is shown in the following table:

[0074] Sector number <![CDATA[T A ]]> <![CDATA[T B ]]> <![CDATA[T C ]]> 0，6 <![CDATA[T a ]]> <![CDATA[T b ]]> <![CDATA[T c ]]> 1，7 <![CDATA[T c ]]> <![CDATA[T b ]]> <![CDATA[T a ]]> 2，8 <![CDATA[T b ]]> <![CDATA[T c ]]> <![CDATA[T a ]]> 3，9 <![CDATA[T b ]]> <![CDATA[T a ]]> <![CDATA[T c ]]> 4，10 <![CDATA[T c ]]> <![CDATA[T a ]]> <![CDATA[T b ]]> 5，11 <![CDATA[T a ]]> <![CDATA[T c ]]> <![CDATA[T b ]]>

[0075] First Vector With target vector There is a one-to-one correspondence between the moduli of the components on the abc axis, from which we can get The corresponding intermediate level time (T a 、T b 、T c )and The corresponding intermediate level time (T A 、T B 、T C ) between them.

[0076] refer to Figure 5, select the basic vector to synthesize the reference vector, which is specifically implemented as follows:

[0077] S51: taking the inscribed circle of the three-level converter vector space as a reference circle, and the vector whose end point is on the reference circle as a reference vector;

[0078] S52: According to the volt-second balance theorem, obtain the action time of the basic vector corresponding to the reference vector, and the basic vector is recorded as; The action time is recorded as: T 01 , T 12 and T1.

[0079] refer to Figure 6 , the relationship between the angle of the reference vector and the sequence diagram of the corresponding basic vector can be used to determine the relationship between the type of switching sequence diagram and the angle: taking phase A as an example, when the target vector is located in units 11 and 0, the switching sequence diagram belongs to category (b); when the target vector is located in units 1, 2, 9, and 10, it belongs to category (a); when the target vector is in units 3, 4, 7, and 8, it belongs to category (d); when the target vector is in units 5 and 6, it belongs to category (c).

[0080] Since phase B and phase C lead and lag phase A by 120°, respectively, the switching timing diagrams of phases B and C can be obtained by simply replacing θ with θ-120° and θ+120°, respectively.

[0081] S54: Calculate T corresponding to each basic vector 01 , T 12 and T1, obtain the action time T ar , T br and T cr ;

[0082] S55: The T corresponding to the three basic vectors ar , T br and T cr They are composed of three arrays, recorded as U, V, and W;

[0083] This T a , T b and T c The value of can be obtained by the following formula:

[0084] Where int() is the rounding function.

[0085] To verify the above examples, experiments were conducted on a 10kVA three-level T-type converter solution, with FPGA-based control implemented. The DC input voltage was 150V, and the AC side was a Y-connected resistive load (50Ω). A relatively high 20kHz frequency was used to reduce current ripple amplitude and provide improved control accuracy and dynamic performance.

[0086] Figure 7 A pulse modulation control device based on a nine-segment three-level converter is shown, comprising:

[0087] A normalization unit 71 is used to normalize the vector space to generate a normalized sector;

[0088] A vector conversion unit 72 is used to convert the target vector into a corresponding vector in the normalized sector, which is recorded as a normalized vector;

[0089] A reference vector acquisition unit selects a reference vector with the same angle as the normalized vector, calculates the action time of the basic vector synthesizing the reference vector, and obtains the switching timing of the reference vector;

[0090] an equivalent switching timing generation unit 74, configured to superimpose a preset PWM wave on the switching timing of the reference vector to generate an equivalent switching timing of the normalized vector;

[0091] The nine-segment switch state timing diagram generating unit 75 is configured to obtain a nine-segment switch state timing diagram of the target vector according to the corresponding relationship between the target vector and the first vector.

[0092] refer to Figure 7 The figure also shows a corresponding relationship building unit 76, which is specifically implemented as follows:

[0093] Construct a one-to-one correspondence between the modules of the components on the abc axis;

[0094] The relationship between the intermediate level time corresponding to the first vector and the intermediate level time of the target vector is obtained according to the corresponding relationship.

[0095] The invention also includes: a reference vector synthesis unit 77, which selects a basic vector to synthesize the reference vector, which is specifically implemented as follows:

[0096] In the normalized sector, a basic vector is selected and synthesized according to the seven-segment vector to obtain the reference vector, which is specifically implemented as follows:

[0097] The inscribed circle of the three-level converter vector space is used as a reference circle, and the vector whose end point is on the reference circle is used as a reference vector;

[0098] According to the volt-second balance theorem, the action time of the basic vector corresponding to the reference vector is obtained, and the basic vector is recorded as; The action time is recorded as: T 01 , T 12 and T1.

[0099] The present invention also discloses a computing device, which is described below with reference to Figure 8 80 according to this embodiment of the present application. Figure 8 The computing device 80 shown is only an example and should not limit the functionality and scope of use of the embodiments of the present application.

[0100] like Figure 8 As shown, the computing device 80 is a general-purpose computing device. Components of the computing device 80 may include, but are not limited to, at least one processor 81, at least one memory 82, and a bus 83 connecting different system components (including the memory 82 and the processor 81).

[0101] Bus 83 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, and a processor or local bus using any of a variety of bus architectures.

[0102] The memory 82 may include a readable medium in the form of a volatile memory, such as a random access memory (RAM) 821 and / or a cache memory 822 , and may further include a read-only memory (ROM) 823 .

[0103] The memory 82 may also include a program / utility 825 having a set (at least one) of program modules 824, such program modules 824 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0104] Computing device 80 may also communicate with one or more external devices 84 (e.g., a keyboard, pointing device, etc.), one or more devices that enable a user to interact with computing device 80, and / or any device that enables computing device 80 to communicate with one or more other computing devices (e.g., a router, a modem, etc.). Such communication may occur via input / output (I / O) interface 85. Furthermore, computing device 80 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) via network adapter 86. As shown, network adapter 86 communicates with other modules of computing device 80 via bus 83. It should be understood that, although not shown, other hardware and / or software modules may be used in conjunction with computing device 80, including but not limited to microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0105] The method of the present invention can also be implemented by computer readable medium 91, referring to Figure 9 , stores computer executable instructions, namely, program instructions corresponding to the method of the present invention, and the computer executable instructions are used to execute the method described in the above embodiment.

[0106] A readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0107] Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0108] The program code for performing the operations of the present application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, using an Internet service provider to connect via the Internet).

[0109] In summary:

[0110] The present invention is based on a pulse modulation method for a nine-segment three-level converter. The algorithm provided by the present invention is based on a conventional seven-segment vector synthesis method to obtain the switching timing and intermediate level time of the reference vector in the 0-30° sector. Based on the concept of "DC chopping voltage regulation", a "PWM wave" is added to the switching timing of the reference vector to convert the seven-segment scheme into a nine-segment scheme. A target vector with the same angle as the reference vector and a smaller modulus than the reference vector is obtained at any angle in the sector, and the target vector is expanded to the entire vector space. This greatly reduces the computational complexity of the conventional seven-segment modulation algorithm, reduces the response time of the multi-level converter, improves the on-off efficiency of the control switching device, and ensures that the system harmonic distortion (THD) is within an acceptable range.

[0111] In some possible implementations, various aspects of the pulse modulation method based on the nine-segment three-level converter provided in the present application may also be implemented in the form of a program product, which includes program code. When the program product is run on a computer device, the program code is used to enable the computer device to execute the steps of the encryption method for information to be verified and / or the verification method for information to be verified according to various exemplary embodiments of the present application described above in this specification. For example, the computer device may execute the following steps: Figure 1 Steps S11-S14 shown in .

[0112] In some possible implementations, a computing device according to the present application may include at least one processor and at least one memory (such as the aforementioned first server). The memory stores program code, and when the program code is executed by the processor, the processor executes the steps of the system permission activation method according to various exemplary embodiments of the present application described above in this specification.

[0113] The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0114] The program product for system permission opening of the embodiment of the present application can be a portable compact disc read-only memory (CD-ROM) and include program code, and can be run on a computing device. However, the program product of the present application is not limited thereto. In this document, a readable storage medium can be any tangible medium containing or storing a program, which can be used by or in combination with an instruction execution system, apparatus, or device.

[0115] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0116] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0117] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0118] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0119] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A pulse modulation method based on a nine-segment three-level converter, characterized in that: include: Normalize the vector space to generate a normalized sector; Convert the target vector into the corresponding vector in the normalized sector, recorded as the normalized vector; Selecting a reference vector with the same angle as the normalized vector, and calculating the action time of a basic vector synthesizing the reference vector to obtain a switching timing of the reference vector; Superimposing a preset PWM wave on the switching timing of the reference vector to generate an equivalent switching timing of the normalized vector; According to the corresponding relationship between the target vector and the normalized vector, a nine-segment switch state timing diagram of the target vector is obtained; The normalized vector is obtained by the following expression: θ=30°-|30°-mod(α / 60°)| Where: α is the target vector in the space vector diagram Angle; θ is normalized to the 0-30° sector Angle; mod() is the remainder function; Select basic vectors to synthesize reference vectors, including: In the normalized sector, a basic vector is selected and synthesized according to a seven-segment vector to obtain the reference vector; Get the basic vector closest to the normalized vector and the corresponding action time, the basic vector is recorded as The action time is recorded as: T 01 , T 12 and T1; Determine the optimal switching sequence, and obtain the three switching timing diagram types and the action time of the intermediate level based on the optimal switching sequence, which is recorded as T ar , T br and T cr : The order of action is: (1,0,0)→(1,0,-1)→(1,-1,-1)→(0,-1,-1)→(1,-1,-1)→(1,0,-1)→(1,0,0).

2. The method according to claim 1, characterized in that The normalized sector is specifically a 30° sector, which is specifically implemented as follows: Starting from 0° and at intervals of 30°, the entire vector space can be divided into 12 sectors.

3. The method according to any one of claims 1 or 2, characterized in that The selection of basic vectors to synthesize the reference vector is specifically implemented as follows: The inscribed circle of the vector space is taken as the reference circle, and the vector whose end point is on the reference circle is taken as the reference vector; According to the volt-second balance theorem, the action time of the basic vector corresponding to the reference vector is obtained, and the basic vector is recorded as The action time is recorded as: T 01 , T 12 and T1.

4. The method according to any one of claims 1 or 2, characterized in that Also includes: Constructing a correspondence between the target vector and the normalized vector includes: Construct a one-to-one correspondence between the modules of the components on the abc axis; A relationship between the normalized vector and the switching state timing diagram of the target vector is obtained according to the corresponding relationship.

5. A pulse modulation control device based on a nine-segment three-level converter, executing the method according to any one of claims 1 to 4, characterized in that: include: A normalization unit, used to normalize the vector space and generate a normalized sector; A vector conversion unit, used to convert the target vector into a corresponding vector in the normalized sector, recorded as a normalized vector; A reference vector acquisition unit selects a reference vector with the same angle as the normalized vector, calculates the action time of the basic vector synthesizing the reference vector, and obtains the switching timing of the reference vector; an equivalent switching timing generation unit, configured to superimpose a preset PWM wave on the switching timing of the reference vector to generate an equivalent switching timing of the normalized vector; The nine-segment switch state timing diagram generating unit is configured to obtain the nine-segment switch state timing diagram of the target vector according to the corresponding relationship between the target vector and the normalized vector.

6. The device according to claim 5, characterized in that The corresponding relationship construction unit is specifically implemented as follows: Construct a one-to-one correspondence on the modulus of the components on the abc axis; The relationship between the switching state timing diagrams of the target vector and the normalized vector is obtained according to the corresponding relationship.

7. The device according to claim 5, characterized in that Also includes: The reference vector synthesis unit selects the basic vector to synthesize the reference vector, which is specifically implemented as follows: In the normalized sector, a basic vector is selected and synthesized according to a seven-segment vector to obtain the reference vector, which is specifically implemented as follows: an inscribed circle of the three-level converter vector space is used as a reference circle, and a vector whose end point is on the reference circle is used as a reference vector; According to the volt-second balance theorem, the action time of the basic vector corresponding to the reference vector is obtained, and the basic vector is recorded as The action time is recorded as: T 01 , T 12 and T1.

8. A computing device, characterized in that include: at least one processor; and a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 4.

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