amplifier circuit

Abstract

An amplifier circuit includes a continuous-time linear equalizer, a variable gain circuit, and a filter circuit. The continuous-time linear equalizer includes a first high-pass path, a first low-pass path, a second high-pass path, and a second low-pass path. The first high-pass path is configured to amplify a gain for a high frequency portion of a first signal source, and the second high-pass path is configured to amplify a gain for a high frequency portion of a second signal source. The filter circuit is configured to amplify and filter the first signal source and the second signal source, and includes a fully differential operational amplifier, a first filter network, and a second filter network.

Description

Technical Field

[0001] This invention application relates to an amplifier circuit, and more particularly to an amplifier circuit used in long-distance broadband network communication systems to compensate for high-frequency signal attenuation. Background Technology

[0002] For reference Figure 1 , Figure 1 This is a schematic diagram illustrating high-frequency signal attenuation using an existing amplifier. Figure 1 As shown, in a communication system, the longer the communication distance, the faster the high-frequency signal attenuates. If a common amplifier circuit is used, the high-frequency signal noise is relatively small due to the attenuation of the high-frequency signal, resulting in poor overall communication system connection quality.

[0003] Furthermore, in existing communication systems, receiver amplifiers are a mainstream circuit used to amplify electronic signals or perform various operations on them. However, existing first-order filter circuits do not have the function of amplifying high-frequency signals. If the required connection distance for the communication system is long, it will cause high-frequency signals to attenuate and degrade their noise ratio, resulting in poor connection quality for long-distance communication. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide an amplifier circuit for compensating for high-frequency signal attenuation in long-distance broadband network communication systems, in order to overcome the shortcomings of the prior art.

[0005] To solve the above-mentioned technical problems, one of the technical solutions adopted by the present invention is to provide an amplifier circuit, which includes a continuous-time linear equalizer, a variable gain circuit, and a filter circuit.

[0006] In some embodiments, the continuous-time linear equalizer includes a first high-pass path, a first low-pass path, a second high-pass path, and a second low-pass path. The first high-pass path is connected between a first signal input terminal and a first node, and includes a first resistor and a first capacitor, for amplifying the gain of a high-frequency portion of a first input signal provided by a first signal source to the first signal input terminal. The first low-pass path is connected between the first signal input terminal and a second node, and includes a second resistor. The second low-pass path is connected between a second signal input terminal and a third node, and includes a third resistor. The second high-pass path is connected between the second signal input terminal and a fourth node, and includes a fourth resistor and a second capacitor, for amplifying the gain of the high-frequency portion of a second input signal provided by a second signal source to the second signal input terminal.

[0007] In some embodiments, the variable gain circuit includes a first variable resistor, a second variable resistor, and a third variable resistor. The first variable resistor is connected between the second node and the third node, the second variable resistor is connected between the first node and the second node, and the third variable resistor is connected between the third node and the fourth node.

[0008] In some embodiments, the filter circuit is used to amplify and filter the first signal source and the second signal source, and includes a fully differential operational amplifier, a first filter network, and a second filter network. The fully differential operational amplifier has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first filter network is connected to the first input terminal, the first output terminal, and the first node. The second filter network is connected to the second input terminal, the second output terminal, and the fourth node.

[0009] One of the advantages of the present application is that the amplifier circuit can be applied to a long distance broadband communication system to compensate for high frequency signal attenuation and reduce the attenuation caused by long online distance, and improve the online quality of long distance broadband communication.

[0010] In particular, the amplifier circuit can amplify the attenuated high frequency signal to achieve better online quality, and only a single operational amplifier is used in the circuit to achieve variable gain, second order filter, echo cancellation, and high frequency signal amplification. In addition, the use of a small area capacitor to achieve high frequency signal amplification can further save circuit area and reduce costs.

[0011] For a further understanding of the features and technical content of the present application, please refer to the following detailed description of the present application and the accompanying drawings, however, the provided drawings are only used for reference and illustration, and are not used to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 A high frequency signal attenuation diagram using a prior art amplifier circuit.

[0013] Figure 2 A circuit diagram of an amplifier circuit according to an embodiment of the present application.

[0014] Figure 3 A circuit diagram of an amplifier circuit according to another embodiment of the present application applied to a communication system.

[0015] Figure 4 A high frequency signal amplification diagram using the amplifier circuit provided by the present application.

[0016] SYMBOL DESCRIPTION

[0017] 1: amplifier circuit

[0018] 10: continuous-time linear equalizer

[0019] 12: variable gain circuit

[0020] 14: filter circuit

[0021] 30: transmitting end device

[0022] 32: voltage dividing circuit

[0023] 34: communication interface

[0024] 140: fully differential operational amplifier

[0025] 142: first filter network

[0026] 144: second filter network

[0027] Tx+Rx: first divided voltage signal

[0028] -(Tx+Rx): second divided voltage signal

[0029] 2Tx: first transmission signal

[0030] -2Tx: second transmission signal

[0031] ADC: analog-to-digital converter

[0032] C1, C2, C3, C4, C5: capacitors

[0033] Cac1, Cac2: coupling capacitors

[0034] HP1: first high-pass path

[0035] HP2: second high-pass path

[0036] In1: first signal input

[0037] In2: second signal input

[0038] LD: linear driver

[0039] DAC: digital-to-analog converter

[0040] LP1: first low-pass path

[0041] LP2: second low-pass path

[0042] N1, N2, N3, N4, N5, N6, N7, N8, N9, N10: nodes

[0043] P1, P2: pads

[0044] R1, R2, R3, R4, R5, R6, R7, R8: resistors

[0045] Rc1, Rc2, Rc3, Rc4: cancellation resistors

[0046] Rd1, Rd2: voltage division resistors

[0047] RL: load

[0048] Rv1, Rv2, Rv3: variable resistors

[0049] Sin1: first signal source

[0050] Sin2: second signal source

[0051] Tin1: first transmission end

[0052] Tin2: second transmission end

[0053] Vout: output voltage DETAILED DESCRIPTION

[0054] The following is a detailed description of the implementation of the disclosed amplifier circuit according to specific embodiments. Those skilled in the art will appreciate the advantages and superiorities of the present application upon reading the detailed description of the present application. The present application can be implemented or applied in other different embodiments, and the details in the present specification can be modified and changed in various ways based on different viewpoints and applications without departing from the spirit and scope of the present application. In addition, it is declared in advance that the drawings of the present application are only simple schematic illustrations and are not actual size depictions. The following embodiments will further illustrate the technical contents of the present application in detail, but the disclosed contents are not intended to limit the scope of protection of the present application. In addition, the term "or" used herein can include any one or a combination of the associated listed items as the case can be.

[0055] Figure 2 A circuit diagram of an amplifier circuit according to an embodiment of the present application is shown. Referring to Figure 2 As shown, an embodiment of the present application provides an amplifier circuit 1 including a continuous-time linear equalizer (CTLE) 10, a variable gain circuit 12, and a filter circuit 14. In some applications, the amplifier circuit 1 can be part of a receiver for amplifying an input signal and transmitting to an analog-to-digital converter, but the present application does not limit the use of the amplifier circuit.

[0056] As shown, an embodiment of the present application provides an amplifier circuit 1 including a continuous-time linear equalizer (CTLE) 10, a variable gain circuit 12, and a filter circuit 14. In some applications, the amplifier circuit 1 can be part of a receiver for amplifying an input signal and transmitting to an analog-to-digital converter, but the present application does not limit the use of the amplifier circuit. Figure 2As shown, CTLE 10 includes a first high-pass path HP1, a first low-pass path LP1, a second high-pass path HP2, and a second low-pass path LP2. Amplifier circuit 1 has a first signal input terminal In1 and a second signal input terminal In2 for receiving a first signal source Sin1 and a second signal source Sin2. Due to the use of a differential signal scheme, the first signal source Sin1 and the second signal source Sin2 can be differential pair signal sources.

[0057] The first high-pass path HP1 is connected between the first signal input terminal In1 and node N1, and includes a resistor R1 and a capacitor C1. The first low-pass path LP is connected between the first signal input terminal In1 and node N2, and includes a resistor R2.

[0058] For the first signal source Sin1, if it is in a high-frequency state, the capacitive impedance is relatively small, which is equivalent to the high-frequency signal seeing a small impedance and a large gain, thus achieving a high-frequency amplification effect. Therefore, since the first high-pass path HP1 is equipped with capacitor C1 and resistor R1, the first high-pass path HP1 is similar to a small high-pass filter, which can amplify the high-frequency part of the first input signal provided by the first signal source Sin1 to the first signal input terminal In1.

[0059] On the other hand, the second high-pass path HP1 is connected between the second signal input terminal In2 and node N4, and includes a resistor R4 and a capacitor C2. The second low-pass path LP2 is connected between the second signal input terminal In2 and node N3, and includes a resistor R3. Similarly, since the second high-pass path HP2 is equipped with a capacitor C2 and a resistor R4, it is similar to a small high-pass filter, which can amplify the gain of the high-frequency portion of the second input signal provided by the second signal source Sin2 to the second signal input terminal In2.

[0060] exist Figure 2 In some embodiments, the variable gain circuit 12 may include variable resistors Rv1, Rv2, and Rv3. Variable resistor Rv1 is connected between nodes N2 and N3, variable resistor Rv2 is connected between nodes N1 and N2, and variable resistor Rv3 is connected between nodes N3 and N4. In some embodiments, variable resistors Rv1, Rv2, and Rv3 are like... Figure 2 The arrows in the diagram indicate that the resistors are adjustable. For example, the variable resistors Rv1, Rv2, and Rv3 can be adjusted by hardware (e.g., fuses, registers, etc.) or firmware (e.g., software, operating system, etc.).

[0061] The variable gain circuit 12 can adjust the proportion of the two variable resistors Rv1, Rv2 to adjust the current shunt, and the adjusted current can be converted into an output voltage Vout via the feedback resistor of the subsequent filter circuit 14, thereby realizing variable gain.

[0062] The variable gain circuit 12 further comprises alternating current (AC) coupling capacitors Cac1, Cac2. The AC coupling capacitor Cac1 is connected between the variable resistor Rv2 and the node N2, and the AC coupling capacitor Cac2 is connected between the variable resistor Rv3 and the node N3. Here, as shown in Figure 2 , the AC coupling capacitors Cac1, Cac2 and the variable resistors Rv1, Rv2 can be used to provide a common-mode voltage at the input of the filter circuit 14. Using the AC coupling topology can solve many problems of using the DC coupling scheme, such as power consumption, crosstalk, etc.

[0063] In the above embodiment, the overall equivalent impedance RCTLE of the CTLE 10 plus the variable gain circuit 12 can be represented by the following formula (1):

[0064] RCTLE = (R1 + 1 / sC1) / / (R2 + (0.5Rv2 / / Rv1)) … Formula (1);

[0065] Wherein, R1, R2, Rv1, Rv2 respectively represent the resistance values of the resistors R1, R2 and the variable resistors Rv1, Rv2, and s is a complex frequency σ + jω.

[0066] In some embodiments, the filter circuit 14 comprises a fully differential operational amplifier 140, a first filter network 142 and a second filter network 144. The fully differential operational amplifier has a first input end (left side - end), a second input end (left side + end), a first output end (right side + end) and a second output end (right side - end). The first filter network 142 is connected to the first input end, the first output end and the node N1. The second filter network 144 is connected to the second input end, the second output end and the node N4.

[0067] In the present embodiment, the filter circuit 144 is a second-order filter circuit, for example, a second-order active filter circuit such as Butterworth, Chebyshev, Bessel or Sallen-Key. As shown in Figure 2 , a fully differential second-order Butterworth low-pass filter with multiple feedback (MFB) topology is used, but the present application is not limited thereto. The Butterworth filter realizes its flatness at the cost of a relatively wide transition zone from the passband to the stopband, and has an average transient characteristic.

[0068] As shown in Figure 2As shown, the first filter network 142 includes a capacitor C3 and resistors R5, R6, and the second filter network 144 includes a capacitor C3 and resistors R5, R6. The first filter network 142 and the second filter network 144 form a symmetrical architecture, the capacitor C3 is connected between the first input terminal and the first output terminal, the resistor R5 is connected between the first input terminal and the node Nl, and the resistor R6 is connected between the first output terminal and the node Nl. Similarly, the capacitor C4 is connected between the second input terminal and the second output terminal, the resistor R7 is connected between the second input terminal and the node N4, and the resistor R8 is connected between the second output terminal and the node N4. The filter circuit 14 further includes a capacitor C5 connected between the node Nl and the node N4.

[0069] In addition, the filter circuit 144 substantially shares the variable resistors Rvl, Rv2 with the variable gain circuit 12, and thus, the proportion of the two sets of variable resistors Rvl, Rv2 is adjusted to adjust the current shunt, and the adjusted current is converted into the output voltage Vout via the feedback resistors R6, R8 to achieve the variable gain, and the two capacitors C3, C4 are connected in parallel to complete the architecture of the filter circuit 144.

[0070] Therefore, the amplifier circuit according to the present application can amplify the attenuated high-frequency signal to achieve better online quality, and only a single operational amplifier is used in the circuit to achieve the functions of variable gain, second-order filter, and high-frequency signal amplification. In addition, since a smaller area capacitor is used to achieve the effect of high-frequency signal amplification, the circuit area can be further saved, and the cost is reduced.

[0071] Reference is made to Figure 3 , Figure 3 The amplifier circuit according to another embodiment of the present application is applied to a circuit diagram of a communication system. In Figure 3 the circuit architecture, the amplifier circuit 1 of Figure 2 is used, and thus repeated descriptions will be omitted.

[0072] In Figure 3 , the amplifier circuit 1 further includes an echo cancellation circuit 18 including cancellation resistors Rcl, Rc2, Rc3, Rc4. The cancellation resistor Rcl is connected between the node N5 and the first signal input terminal Inl, the cancellation resistor Rc2 is connected between the node N6 and the first signal input terminal Inl, the cancellation resistor Rc3 is connected between the node N7 and the second signal input terminal In2, and the cancellation resistor Rc4 is connected between the node N8 and the second signal input terminal In2.

[0073] In some specific communication systems, amplifier circuit 1 is connected to transmitting device 30 (including linear driver LD and digital-to-analog converter DAC), receiving device (e.g. analog-to-digital converter ADC), voltage divider circuit 32 and communication interface 34, and amplifier circuit 1 shares communication interface 32 with transmitting device 30.

[0074] However, in such a system, when the amplifier circuit 1 tries to acquire the received signal through the communication interface 34, it is affected by the transmitted signal Tx that is simultaneously transmitted on the same channel, making it difficult to determine the true nature of the received signal. This phenomenon is generally referred to as echo interference. In order to minimize the echo interference effect, the amplifier circuit 1 of the present invention also uses an echo cancellation circuit 18 to remove the transmitted signal component from the received signal.

[0075] like Figure 3 As shown, the transmitting end device 30 has a first transmitting end Tin1 and a second transmitting end Tin2. The communication interface includes a load RL, a pad P1, and a pad P2. The voltage divider circuit 32 has a voltage divider resistor Rd1 connected to the pad P1 and the first transmitting end Tin1, and a voltage divider resistor Rd2 connected to the pad P2 and the second transmitting end Tin2. Here, the voltage divider circuit 32 is used to design multiple voltages input to the echo cancellation circuit 18 under a differential signal architecture, but the invention is not limited thereto.

[0076] When the above architecture is combined with the aforementioned echo cancellation circuit 18, node N8 is connected to node N9 between pad P1 and voltage divider resistor Rd1, node N6 is connected to the first transmission terminal Tin1, node N7 is connected to the second transmission terminal Tin2, and node N5 is connected to node N10 between pad P2 and voltage divider resistor Rd2.

[0077] Therefore, in this architecture, when the transmitting end device 30 provides a first transmitting signal, for example, +2Tx, to the first transmitting end Tin1 and a second transmitting signal, for example, -2Tx, to the second transmitting end Tin2, simultaneously, the communication interface 32 provides a first receiving signal, for example, +Rx, to the contact pad P1 and a second receiving signal, for example, -Rx, to the contact pad P2. Here, the amplifier circuit 1, the transmitting end device 30, and the receiving end device are implemented using a differential signal scheme. A voltage signal may include two voltages represented by "+" and "-", respectively, and the value of the voltage signal is defined by the difference between the two voltages represented by "+" and "-".

[0078] Therefore, the first transmission signal +2Tx is divided by the dividing resistor Rd1 to form a first divided signal at node N9 by superimposing the first reception signal +Rx, i.e., 2Tx*d1+Rx, where d1 is the dividing ratio of the dividing resistor Rd1, and the second transmission signal -2Tx is divided by the dividing resistor Rd2 to form a second divided signal at node N10 by superimposing the second reception signal -Rx, i.e., -2Tx*d2-Rx.

[0079] It should be noted that the first proportionality between the cancellation resistors Rc1 and Rc2 is eliminated so that the second divided signal (-2Tx*d2-Rx) received at node N5 and the first transmission signal +2Tx received at node N6 superimposed at the first signal input terminal In1 only leaves the second reception signal -Rx.

[0080] Similarly, the second proportionality between the cancellation resistors Rc3 and Rc4 is eliminated so that the second transmission signal (-2Tx) received at node N7 and the first divided signal (2Tx*d1+Rx) received at node N8 superimposed at the second signal input terminal In2 only leaves the first reception signal +Rx.

[0081] Furthermore, since the differential signal scheme is adopted, the first proportionality should be the same as the second proportionality, and will correspond to a third proportionality between the dividing resistor Rd1 and the load RL.

[0082] Therefore, taking the present embodiment as an example, the resistance values of the dividing resistors Rd1 and Rd2 in the dividing circuit 34 are set to be one half of the equivalent resistance value of the load RL of the communication interface 32, for example, Rd1 and Rd2 are 50 ohms, and RL is 100 ohms, then according to the dividing law, d1=d2=0.5, the second divided signal received at node N5 is -(Tx+Rx), and the first divided signal received at node N8 is Tx+Rx.

[0083] Then, according to the dividing law, it can be known that when the cancellation resistor Rc2 is twice the resistance value of the cancellation resistor Rc1, the second reception signal -Rx can be left after superimposing at the first signal input terminal In1 according to the second divided signal -(Tx+Rx) received at node N5 and the first transmission signal 2Tx received at node N6. Therefore, the first proportionality can be obtained in this way.

[0084] Similarly, according to the first voltage division signal received by node N8 as (Tx+Rx) and the second transmission signal -2Tx received by node N7, when the cancellation resistance Rc3 is twice the resistance value of the cancellation resistance Rc4, only the first received signal +Rx is left after superposition at the second signal input terminal In2. Therefore, the first proportional relationship can be obtained in this way, and the first proportional relationship and the second proportional relationship actually correspond to the third proportional relationship. In addition, the resistance value of the cancellation resistance Rc2 can be set to be equal to the input impedance (hereinafter referred to as Rin), and the resistance value of the cancellation resistance Rc1 can be set to be equal to half of the input impedance (Rin / 2), and Rin is equal to the equivalent impedance (hereinafter referred to as RTX) of the transmission end device 30, so as to achieve impedance matching.

[0085] Therefore, through this architecture, since there is no component of the transmission signal in the signals received at the first signal input terminal In1 and the second signal input terminal In2, the effect of echo cancellation can be achieved.

[0086] Furthermore, the gain Gain of the amplifier circuit 1 can be calculated as follows: Figure 3

[0087] Gain=-R6*(Vin / ((Rin / 2)+RCTLE / / RTX)*RTX / (RTX+RCTLE))*(((0.5Rv2 / (0.5Rv2+Rv1))*(R1+1 / sC1) / RCTLE)+(R1+0.5Rv2 / / Rv1) / RCTLE).

[0088] wherein Vin is the input voltage (the difference between +Rx and -Rx), RCTLE is the overall equivalent impedance of the CTLE 10 and the variable gain circuit 12, RTX is the equivalent impedance of the transmission end device 30, R1, R6, Rv1, Rv2 respectively represent the resistance values of the resistances R1, R6 and the variable resistances Rv1, Rv2, and s is the complex frequency σ+jω.

[0089] Please refer to Figure 4 , which is a high-frequency signal amplification schematic diagram using the amplifier circuit provided by the present application. As shown in Figure 4 , using the amplifier circuit provided by the present application, high-frequency signals can be amplified without increasing noise, so the overall signal-to-noise ratio from low frequency to high frequency can be increased, and the overall online quality and stability of the communication system can be greatly improved.

[0090] [Advantages of the embodiment]

[0091] One of the advantages of the present application is that the amplifier circuit provided by the present application can be applied to a long-distance broadband network communication system to compensate for high-frequency signal attenuation and reduce attenuation caused by long online distance, while improving the online quality of long-distance broadband communication.​

[0092] In particular, the amplifier circuit can amplify the high-frequency signal with attenuation to achieve better online quality, and can realize variable gain, a second-order filter, echo cancellation and high-frequency signal amplification by using only a single operational amplifier in the circuit. In addition, since a small-area capacitor is used to achieve the effect of high-frequency signal amplification, the circuit area can be further saved, and the cost is reduced.

[0093] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application, and those skilled in the art can make changes to the technical features of the present application according to the explicit or implicit contents of the present application. Any such changes can be within the scope of the patent protection sought by the present application. In other words, the scope of the patent protection of the present application shall be subject to the scope defined by the claims of the present application.

Claims

1. An amplifier circuit, characterized by The amplifier circuit comprises: a continuous-time linear equalizer comprising: a first high-pass path connected between a first signal input and a first node and comprising a first resistance and a first capacitance for amplifying a high frequency portion of a first input signal provided to the first signal input by a first signal source; a first low-pass path connected between the first signal input and a second node and comprising a second resistance; a second low-pass path connected between a second signal input and a third node and comprising a third resistance; and a second high-pass path connected between the second signal input and a fourth node and comprising a fourth resistance and a second capacitance for amplifying a high frequency portion of a second input signal provided to the second signal input by a second signal source; a variable gain circuit comprising: a first variable resistance connected between the second node and the third node; a second variable resistance connected between the first node and the second node; and a third variable resistance connected between the third node and the fourth node; and a filter circuit for amplifying and filtering the first and second signal sources and comprising: a fully differential operational amplifier having a first input, a second input, a first output, and a second output; a first filter network connected between the first input, the first output, and the first node; and a second filter network connected between the second input, the second output, and the fourth node.

2. The amplifier circuit of claim 1, wherein, The first and second signal sources are a differential pair signal source.

3. The amplifier circuit of claim 1, wherein, The variable gain circuit further comprises: a first AC coupling capacitance connected between the second variable resistance and the second node; and a second AC coupling capacitance connected between the third variable resistance and the third node.

4. The amplifier circuit of claim 1, wherein, The filter circuit is a second order filter circuit and the first filter network comprises: a third capacitance connected between the first input and the first output; a fifth resistance connected between the first input and the first node; and a sixth resistance connected between the first output and the first node; wherein the second filter network comprises: a fourth capacitance connected between the second input and the second output; a seventh resistance connected between the second input and the fourth node; and an eighth resistance connected between the second output and the fourth node; wherein the filter circuit further comprises: a fifth capacitance connected between the first node and the fourth node.

5. The amplifier circuit of claim 1, wherein, The amplifier circuit further comprises an echo cancellation circuit comprising: a first cancellation resistance connected between a fifth node and the first signal input; a second cancellation resistance connected between a sixth node and the first signal input; a third cancellation resistance connected between a seventh node and the second signal input; and a fourth cancellation resistance connected between an eighth node and the second signal input.

6. The amplifier circuit of claim 5, wherein, The amplifier circuit is connected to a transmitting end device, a receiving end device, a voltage dividing circuit and a communication interface, the transmitting end device has a first transmitting end and a second transmitting end, the communication interface includes a load, a first contact pad and a second contact pad, the voltage dividing circuit has a first voltage dividing resistor connected between the first contact pad and the first transmitting end and a second voltage dividing resistor connected between the second contact pad and the second transmitting end, wherein the eighth node is connected to a ninth node between the first contact pad and the first voltage dividing resistor, the sixth node is connected to the first transmitting end, the seventh node is connected to the second transmitting end, and the fifth node is connected to a tenth node between the second contact pad and the second voltage dividing resistor.

7. The amplifier circuit of claim 6, wherein, The transmitting end device provides a first transmitting signal to the first transmitting end and a second transmitting signal to the second transmitting end, and the communication interface provides a first receiving signal to the first contact pad and a second receiving signal to the second contact pad, wherein the first transmitting signal is divided by the first voltage dividing resistor to generate a first divided voltage signal at the ninth node and superimposed with the first receiving signal to generate a first divided voltage signal, and the second transmitting signal is divided by the second voltage dividing resistor to generate a second divided voltage signal at the tenth node and superimposed with the second receiving signal to generate a second divided voltage signal.

8. The amplifier circuit of claim 7, wherein, The first cancellation resistor and the second cancellation resistor have a first proportional relationship, so that the second divided voltage signal received by the fifth node and the first transmitting signal received by the sixth node only leave the second receiving signal after superimposed at the first signal input end.

9. The amplifier circuit of claim 8, wherein, The third cancellation resistor and the fourth cancellation resistor have a second proportional relationship, so that the second transmitting signal received by the seventh node and the first divided voltage signal received by the eighth node only leave the first receiving signal after superimposed at the second signal input end.

10. The amplifier circuit of claim 9, wherein, The first proportional relationship is the same as the second proportional relationship, and corresponds to a third proportional relationship between the first voltage dividing resistor and the load.

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