TIADC sampling time mismatch error extraction and calibration method and calibration device

Abstract

The present application relates to high-speed analog-to-digital conversion technical field, specifically relates to the extraction and calibration method for TIADC sampling time mismatch error, the calibration device using the mismatch error extraction and calibration method.The present application can accurately and quickly extract the sampling time mismatch data caused by various reasons in TIADC system, so as to significantly improve the size of TIADC SNDR, SFDR and other technical indexes.The present application is a background calibration method, which can adaptively extract compensation values according to different external conditions, without spending additional time to complete the calibration work, at the same time, the present application method structure is simple and clear, without complex derivative operation or matrix operation, which reduces the hardware complexity, is easy to realize, in addition, the present application method is not limited by the number of channels, has good adaptability and great flexibility.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of high-speed analog-to-digital conversion, and in particular to a TIADC sampling time mismatch error extraction and calibration method and a calibration device using the same. BACKGROUND

[0002] With the rapid development of the integrated circuit industry, the rise of the field of automatic driving and 5G communication, the demand for the number of external signals of the data processing system is increasingly large, and the requirement for precision is also higher and higher. The analog-to-digital converter (ADC) can convert analog signals into digital signals, and is a bridge between the real world and the digital world. For a system of high-speed sampling and signal processing, the performance of a single-channel ADC has gradually failed to meet the performance requirements of the rapidly increasing data throughput and high precision. The conversion speed of the ADC almost reaches a bottleneck under the current process node. Speed and precision are two important indicators to measure the performance of the ADC, but these two indicators are mutually restrictive, and a single-channel ADC cannot meet the requirements of high speed and high precision at the same time. Therefore, how to improve the performance of the ADC under the existing technology has very important practical significance.

[0003] Changing the ADC from a single-channel structure to a multi-channel structure is a very good solution to this problem, that is, the Time-Interleaved Analog To Digital Converter (TIADC) technology. This technology uses several low-speed sub-ADCs, which are alternately operated at the same clock frequency, and then the outputs of the sub-ADCs are fused in the digital domain, so that the overall ADC system can achieve higher sampling speed without losing precision. In this way, the performance requirements of the sampling system on a single ADC can be greatly reduced. In addition, the sub-ADCs can be selected according to the actual application scene and requirements, so the flexibility of this structure is very strong and is not restricted by the type of sub-ADC. For a system with M sub-ADCs, the speed of the entire ADC system is M times higher than that of a single ADC. In theory, as long as the number of stacked ADCs is infinite, a super-high-speed ADC can be realized, and the TIADC system can maintain the same sampling rate as the sub-ADC.

[0004] Ideally, the sub-ADC parameters between channels are the same, and the time of the sampling clock reaching the sub-ADC is also the same, and the system performance can reach the theoretical effect, however, the reality is not the case. In actual conditions, due to the current CMOS process fluctuation and the influence of unstable internal and external factors such as temperature, device aging, voltage fluctuation and the like, the multi-channel structure will appear the mismatch phenomenon of the signals between channels in the process of fusing the sub-ADC outputs, thereby causing the distortion of the output signals. The mismatch between channels mainly includes three aspects: offset mismatch, gain mismatch and time-skew mismatch. The three kinds of mismatches will reduce the conversion precision and signal-to-noise ratio of the system, and limit the performance of the TIADC.

[0005] Among the three kinds of mismatches, the research on the offset mismatch and the gain mismatch is relatively mature, and the solution can obtain good correction results with relatively small cost. Because the clock signal of the high-speed sampling ADC system changes in a short period and has a very fast frequency, the mismatch of the sampling clock offset has a great influence on the TIADC system and is also the most difficult to eliminate, which is the problem that needs to be solved urgently to improve the performance of the TIADC.

[0006] The calibration of the time mismatch is divided into foreground calibration and background calibration. The foreground calibration method is simple, but needs to input a specific signal, the accuracy requirement for the input signal is very high, and the normal work of the TIADC needs to be interrupted. The traditional foreground calibration method is the pre-sampling and holding (SHA) structure. The structure can effectively improve the time mismatch problem, but when the sampling rate reaches GHz, the pre-sampling and holding circuit will greatly limit the performance of the TIADC. In addition, the pre-sampling and holding circuit will also generate high power consumption problem when working at high frequency, which is not conducive to integration. The background calibration method can automatically calibrate when the TIADC works, however, the analog background calibration method is greatly affected by the external conditions such as temperature and pressure; the digital background calibration often needs to consume a large amount of hardware and power consumption to achieve good performance, at the same time, most of the calibration methods of this type need multiple rounds of calibration to affect the convergence speed, which greatly increases the chip power consumption and complexity. SUMMARY

[0007] Based on this, it is necessary to provide a TIADC sampling time mismatch error extraction and calibration method and a calibration device in view of the problem of large operation load of the existing digital background calibration method.

[0008] The application adopts the following technical solutions:

[0009] The first aspect discloses a TIADC sampling time mismatch error extraction and calibration method, which is used for background correction of a TIADC system with sampling time mismatch.

[0010] The TIADC sampling time mismatch error extraction and calibration method comprises the following steps:

[0011] Step one, periodically acquire a sampling signal, and obtain digital output signals of N sub-ADCs each time;

[0012] Step two, calculate a difference between a digital output signal of a (k+1)th sub-ADC acquired in a current time and a digital output signal of a kth sub-ADC acquired in the current time, to obtain an adjacent difference signal D k,k+1 ; k∈[1,N-1]

[0013] Step three, calculate a difference between a digital output signal of a first sub-ADC acquired in a previous time and a digital output signal of an Nth sub-ADC acquired in the current time, to obtain an adjacent difference signal D N,1 .

[0014] Step four, perform a first-order Taylor expansion on the adjacent difference signals D k,k+1 , D N,1 at an ideal sampling time of each channel, to obtain a digital signal approximation value

[0015] Step five, take an absolute value of the digital signal approximation value , and then calculate an expectation, to obtain expectation values A k,k+1 , A N,1 .

[0016] Step six, perform an operation on the expectation values A k,k+1 , A N,1 , to obtain a digital signal Δτ K containing a sampling time absolute error Δt K ; K∈[1,N]

[0017] Step seven, perform an iteration on a sampling time relative error τ K according to the digital signal Δτ K containing the sampling time absolute error Δt K , and correspondingly compensate the sampling time relative error τ K into digital output signals of the N sub-ADCs acquired in a next time.

[0018] Step eight, repeat the steps one to seven until the sampling time relative error τ K converges, to obtain an output signal with eliminated time mismatch.

[0019] The implementation of the TIADC sampling time mismatch error extraction and calibration method is according to the method or process of the embodiment of the present disclosure.

[0020] In a second aspect, the present disclosure discloses a TIADC sampling time mismatch calibration device which uses the TIADC sampling time mismatch error extraction and calibration method disclosed in the first aspect.

[0021] The implementation of the TIADC sampling time mismatch calibration device is according to the method or process of the embodiment of the present disclosure.

[0022] In a third aspect, the present disclosure discloses a readable storage medium, which stores computer program instructions, and when the computer program instructions are read and run by a processor, the TIADC sampling time mismatch error extraction and calibration method disclosed in the first aspect is executed.

[0023] Compared with the prior art, the present disclosure has the following beneficial effects:

[0024] The present disclosure can accurately and quickly extract the sampling time mismatch data caused by various reasons in the TIADC system, thereby significantly improving the size of the SNDR, SFDR and other technical indicators of the TIADC; the present disclosure is a background calibration method, which can extract and compensate values according to different external conditions, without spending a large amount of additional time to complete the calibration work; at the same time, the method of the present disclosure is simple in structure and easy to understand, without complex derivative operation or matrix operation, which reduces the hardware complexity and is easy to implement; in addition, the method of the present disclosure is not limited by the number of channels, and has good adaptability and great flexibility. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0026] Figure 1 The TIADC sampling time mismatch error extraction and calibration method for the embodiment 1 of the present disclosure is shown in the following flowchart.

[0027] Figure 2 The principle diagram of steps 1 to 4 in the TIADC sampling time mismatch error extraction and calibration method for the embodiment 1 of the present disclosure is shown in the following.

[0028] Figure 3 The principle diagram of the TIADC sampling time mismatch error extraction and calibration method for the embodiment 1 of the present disclosure is shown in the following. Figure 1 The principle diagram of the TIADC sampling time mismatch error extraction and calibration method for the embodiment 1 of the present disclosure is shown in the following.

[0029] Figure 4 Convergence of the TIADC system with uncalibrated sampling time mismatch for the case of μ = 2 for the simulation of embodiment 1 of the present application. -16

[0030] Figure 5 Convergence of the TIADC system with uncalibrated sampling time mismatch for the case of μ = 2 for the simulation of embodiment 1 of the present application. -21

[0031] Figure 6 TIADC system spectrum for the case of uncalibrated sampling time mismatch for the simulation of embodiment 2 of the present application.

[0032] Figure 7 TIADC system spectrum for the case of calibrated sampling time mismatch for the simulation of embodiment 2 of the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0034] It should be noted that when a component is referred to as being "mounted on" another component, it can be directly on the other component or there can be a middle component. When a component is referred to as being "disposed on" another component, it can be directly disposed on the other component or there can be a middle component. When a component is referred to as being "fixed on" another component, it can be directly fixed on the other component or there can be a middle component.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0036] Embodiment 1

[0037] Please refer to Figure 1 , Figure 1 The flow chart of the method for extracting and calibrating the sampling time mismatch error of the TIADC for embodiment 1. The method is used for background correction of the TIADC system with sampling time mismatch.

[0038] ​​It should be noted that this method assumes that the offset and gain mismatches have been calibrated. If the offset and gain mismatches are not calibrated, they should be calibrated first or simultaneously.

[0039] In summary, this method can be summarized as follows: first, subtract the outputs of adjacent channels, then take the absolute value and the expected value; add the average value obtained from the calculation to the calculation to obtain the time error value of each channel; and use the obtained error value for compensation to obtain the improved output of the sub-channel.

[0040] For details, please refer to Figure 2 , Figure 3 The TIADC system comprises N sub-ADCs, each corresponding to one of the N sub-channels. The TIADC input signal is x(t), which passes through the N sub-ADCs (Sub-ADC1 to Sub-ADC2). N The output signal before compensation is Y1~Y1. N The compensated output signal is Y1′~Y N ′.

[0041] The TIADC sampling time mismatch error extraction and calibration method includes the following steps:

[0042] Step one: Periodically acquire the sampling signal, obtaining the digital output signals of N sub-ADCs each time. It should be noted that the period of signal acquisition should be the same as the sampling period, that is, the outputs of all N sub-ADCs are acquired each time.

[0043] Specifically, the digital output signal of the m-th sample and the K-th sub-ADC is Y. K [m]. K∈[1,N].

[0044] That is, we have formula (1): Y K [m]=y((N·m+K)·T s +Δt K ).

[0045] Among them, T s Δt represents the period of the sub-channel sampling clock. K This represents the absolute error of the sampling time for the Kth channel.

[0046] Step 2: Calculate the difference between the (k+1)th sub-ADC's digital output signal acquired in the current iteration and the kth sub-ADC's digital output signal acquired in the current iteration to obtain the adjacent differential signal D. k,k+1 ;k∈[1,N-1];Calculate the difference between the digital output signal of the first sub-ADC acquired in the last acquisition and the digital output signal of the Nth sub-ADC acquired in the current acquisition to obtain the adjacent differential signal D. N,1 .

[0047] Let the current time be represented by the mth time, and the next time be represented by the m+1th time, represents the difference between the X2th channel and the X1th channel.

[0048] Then we have:

[0049] D k,k+1 = Y k+1 [m] - Y k [m] = y((N·m+k+1)·T s + Δt k+1 ) - y((N·m+k)·T s + Δt k ).

[0050] D N,1 = Y1[m+1] - Y N [m] = y((N·(m+1)+1)·T s + Δt1) - y((N·m+N)·T s + Δt N ).

[0051] Then, for N sub-ADCs, we have the following equation (2):

[0052]

[0053]

[0054] Step three, at the ideal sampling time of each channel, first-order Taylor expansion is performed on the adjacent difference signals D k,k+1 , D N,1 to obtain the digital signal approximation value at the expansion point

[0055] This step uses the Taylor expansion formula to expand the adjacent difference signal D k,k+1 at k obtained in step two to obtain the adjacent difference signal D N,1 expanded at N. It should be noted that first-order Taylor expansion is sufficient, and higher-order expansion will increase hardware complexity, increase circuit calculation difficulty and convergence speed, but the effect of improving accuracy is small. At the same time, due to subsequent algorithm factors, there is no need to take higher-order terms.

[0056] The first-order Taylor expansion formula is: y(x+Δx)≈y(x)+y′(x)·Δx;

[0057] Using the above expansion formula, equation (2) is transformed to obtain equation (3):

[0058]

[0059] Step 4: Approximate the digital signal at the expansion point. First, take the absolute value, then calculate the expectation to obtain the expected value A of the numerical signal approximation. k,k+1 A N,1 .

[0060] Take the absolute value of both sides of formula (3), and then calculate the expectation of the signal after taking the absolute value.

[0061] It should be noted that for a band-limited signal with zero mean, when the number of samples is sufficiently large, the expectation of the signal and its absolute value is constant and does not change with time. Furthermore, T... s Ratio Δt K The order of magnitude is large, therefore, T s +Δt k+1 -Δt k It is a positive value.

[0062] Therefore, we have formula (5):

[0063] E(|y1′[m]|)=E(|y2′[m]|)=...=E(|y k ′[m]|)=...=E(|y N-1 ′[m]|)=E(|y N ′[m]|)=α;

[0064] in, α is a constant.

[0065] Therefore, we have formula (6):

[0066]

[0067] Step 5: Calculate the expected value A of the numerical signal approximation. k,k+1 A N,1 The calculation is performed to obtain the absolute error Δt of the sampling time. K digital signal Δτ K ;K∈[1,N].

[0068] Choose the first channel as the reference channel, that is, when k=1, Δτ1=Δt1=0.

[0069] and then:

[0070]

[0071] That is, the absolute error Δt of the sampling time is obtained. K digital signal Δτ K .

[0072] Step 6, based on the absolute error Δt of the sampling time. K digital signal ΔτK , the relative error of sampling time τ K is compensated into the digital output signal of the N sub-ADCs acquired in the next iteration.

[0073] , the relative error of sampling time τ K is compensated into the digital output signal of the N sub-ADCs acquired in the next iteration.

[0074]

[0075] , the relative error of sampling time τ K is compensated into the digital output signal of the N sub-ADCs acquired in the next iteration. K is the parameter of iteration convergence, μ∈(0, 1); τ K is the initial value of 0.

[0076] More specifically:

[0077] After the m+1 sampling, the digital signal Δτ K containing the absolute error of sampling time Δt K corresponding to the m sampling can be obtained through steps 1-5; wherein Δt K is expressed as Δτ K is expressed as

[0078] The relative error of sampling time τ K is iterated once again:

[0079] , the relative error of sampling time τ is expressed as τ K is expressed as

[0080] Therefore, the iteration formula can be written as:

[0081] μ is the parameter value, between 0 and 1, representing the convergence step of the time error value. When μ is larger, the convergence speed is faster, but the convergence accuracy is smaller. Conversely, when μ is smaller, the convergence speed is slower, but the convergence accuracy is larger. Referring to Figure 4 , Figure 5 , the influence of μ on the convergence is verified through simulation: Figure 4 In the simulation, μ is taken as 2 -16 , and converges at about 1200 times, but the fluctuation amplitude after convergence is large; μ is taken as 2 -21 , and converges at about 2500 times, and the fluctuation amplitude after convergence is small.

[0082] So according to the demand, a suitable value can be obtained through simulation experiment, so that the TIADC system converges fast and can achieve certain accuracy.

[0083] The iteration value is obtained Then, the N error values of the first channel to the Nth channel are compensated one by one into the digital output signals of the N sub-ADCs obtained in the m+1th sampling: the error value of the first channel is compensated into the digital output signal of the first sub-ADC; the error value of the second channel is compensated into the digital output signal of the second sub-ADC; and so on; and the error value of the Nth channel is compensated into the digital output signal of the Nth sub-ADC.

[0084] After the above process, the compensated digital output signals of the N sub-ADCs obtained in the last sampling (denoted as Y K [m+1]) are obtained, and the compensated digital output signals of the N sub-ADCs obtained in the last sampling (denoted as Y K [m+1]) are replaced by the compensated digital output signals of the N sub-ADCs obtained in the last sampling.

[0085] In the above process, since the first channel is used as the reference channel, the error value of the first channel is 0, which is equivalent to not compensating the digital output signal of the first sub-ADC, and therefore the first channel signal before and after compensation is unchanged.

[0086] Step seven, repeat steps one to six until the relative error τ K converges, and the output signal eliminating time mismatch is obtained.

[0087] The above steps form a feedback loop, and after a certain number of iterations, a stable signal output eliminating time mismatch can be obtained.

[0088] The embodiment 1 also discloses a TIADC sampling time mismatch calibration device, which uses the TIADC sampling time mismatch error extraction and calibration method.

[0089] The TIADC sampling time mismatch calibration device includes a signal acquisition module, a signal difference processing module, a signal approximation processing module, a signal expectation processing module, a signal absolute error processing module, a signal relative error module, and a signal compensation module.

[0090] The signal acquisition module is used to periodically acquire sampling signals, and each acquisition obtains digital output signals of N sub-ADCs. The signal difference processing module is used to subtract the digital output signal of the k+1th sub-ADC obtained in the current sampling from the digital output signal of the kth sub-ADC obtained in the current sampling to obtain adjacent difference signals D k,k+1; k e [1, N-1]; the difference between the digital output signal of the first sub-ADC obtained in the previous time and the digital output signal of the Nth sub-ADC obtained in the current time is obtained to obtain an adjacent difference signal D N,1 The signal approximation processing module is configured to perform first-order Taylor expansion on the adjacent difference signal D k,k+1 , D N,1 at the ideal sampling time of each channel to obtain a digital signal approximation value at the expansion point The signal expectation processing module is configured to take the absolute value of the digital signal approximation value at the expansion point , and then take the expectation to obtain an expected value A k,k+1 , A N,1 of the numerical signal approximation value. The signal absolute error processing module is configured to perform operations on the expected value A k,k+1 , A N,1 of the numerical signal approximation value to obtain a digital signal Δτ K containing the sampling time absolute error Δt K . The signal relative error module is configured to perform one iteration on the sampling time relative error τ K according to the digital signal Δτ K containing the sampling time absolute error Δt K . The signal compensation module is configured to compensate the sampling time relative error τ K obtained after the iteration into the digital output signals of the N sub-ADCs obtained in the previous time.

[0091] Wherein, referring to Figure 3 , the signal difference processing module, the signal approximation processing module, the signal expectation processing module, and the signal error processing module form a time skew estimation module (i.e., Time skew estimation). The signal relative error module is Adaptation. The signal compensation module is a derivative filter (Time skew digital correction). Of course, the signal compensation function can also be realized by adjusting the digital control delay clock line.

[0092] In addition, the TIADC sampling time mismatch calibration device further includes an iterative adjustment module configured to adjust a parameter μ affecting the iterative convergence condition, so as to adapt to different output signals.

[0093] Embodiment 2

[0094] The TIADC sampling time mismatch error extraction and calibration method proposed in Embodiment 1 is simulated and verified in this embodiment 2.

[0095] In this embodiment 2, MATLAB software is used to model the TIADC, and parameters such as sampling frequency, input frequency, and time mismatch are set externally.

[0096] Referring to Figure 6 , Figure 6 is the spectrum diagram without correction. It can be seen that in addition to the main signal (near the abscissa 0.17), there is a large noise signal (near the abscissas 0.07, 0.33, 0.43), and the SNDR, SFDR indicators are not high.

[0097] Referring to Figure 7 , Figure 7 is the spectrum diagram after correction by the method. It can be seen that the large noise signal has been filtered out, leaving only the main signal, and the SNDR, SFDR indicators have been significantly improved, indicating that the correction is successful.

[0098] Embodiment 3

[0099] Embodiment 3 also discloses a readable storage medium, which stores computer program instructions, and the computer program instructions are read and run by a processor to execute the TIADC sampling time mismatch error extraction and correction method disclosed in Embodiment 1.

[0100] The method of Embodiment 1 can be applied in the form of software when applied, such as designed as a program that can be independently run on a computer readable storage medium, and the computer readable storage medium can be a U disk, designed as a U disk, and the program is designed to start the whole method through external triggering by the U disk.

[0101] The technical features of the above embodiments can be combined in any way. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0102] The above embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A method for extracting and calibrating TIADC sampling time mismatch error, used for background correction of a TIADC system with sampling time mismatch; the TIADC system comprises N sub-ADCs corresponding to N sub-channels, characterized in that, The method comprises the following steps: Step one, periodically acquiring sampling signals, and obtaining digital output signals of N sub-ADCs each time; Step two, difference between the digital output signal of the k+1th sub-ADC in the current acquisition and the digital output signal of the kth sub-ADC in the current acquisition is obtained to obtain an adjacent difference signal D k,k+1 ; k ∈ [1, N-1] Difference between the digital output signal of the first sub-ADC of the previous acquisition and the digital output signal of the Nth sub-ADC of the current acquisition is obtained, to obtain adjacent difference signal D N,1 ; Step three, at the ideal sampling time for each channel, perform a first order Taylor expansion of the adjacent difference signal D k,k+1 , D N,1 to obtain a digital signal approximation at the expansion point Step four, approximating the digital signal at the point of expansion Taking the absolute value first and then the expectation, the expectation value A of the numerical signal approximation is obtained k,k+1 , A N,1 ; Step five, the expectation value A of the numerical signal approximation value k,k+1 , N,1 Operation is performed to obtain a digital signal Δτ K containing the absolute error Δt K of the sampling time; K ∈ [1, N] wherein the time mismatch value AT for the kth channel is k given by: Δτ k = N · a · Δt k = (N - k + 1)(A 1,2 +... + A k-1,k ) - (k - 1)(A k,k+1 +... + A N,1 ); Alpha is a constant value; when k=1, Delta tau 1=Delta t1=0; The time mismatch value Δτ of the Nth channel N is: Δτ N = N - a - Δt N = (A 1,2 +... + A N-1,N ) - (N - 1)A N,1 ; Step 6, based on the absolute error Δt of the sampling time. K digital signal Δτ K The relative error τ of the sampling time K Perform one iteration and compensate accordingly for the digital output signals of the N sub-ADCs acquired in the next iteration; where the relative error of the sampling time τ K The formula for iteration is: for τ K the iteration value after one iteration; μ is the relative error of the sampling time τ K a parameter for the convergence of the iteration, μ ∈ (0, 1), τ K initial value 0; Step seven, repeat steps one through six until the sampling time relative error τ K converges, resulting in an output signal that is free of time mismatch.

2. The TIADC sampling time mismatch error extraction and calibration method of claim 1, wherein, In step one, the digital output signal of the mth sampling, the Kth sub-ADC is Y K [m], Y K [m] = y ((N · m + K) · T s + Δt K ); Wherein, T s represents the period of the sub-channel sampling clock, Δt K represents the absolute error of the sampling time of the Kth channel.

3. The TIADC sampling time mismatch error extraction and calibration method of claim 2, wherein, In step two, the adjacent difference signal Dmof the mthsample is k,k+1 is: D k,k+1 = Y k+1 [m] - Y k [m]; The adjacent difference signal D of the (m+1)th sample and the mth sample N,1 is: D N,1 = Y1[m+1] - Y N [m].

4. The TIADC sampling time mismatch error extraction and calibration method of claim 3, wherein, In step three, where Δt k+1 represents the absolute error of the sampling time of the k+1th channel, Δt k represents the absolute error of the sampling time of the kth channel, y′ k [m] represents the first derivative of y k [m]; Δt1 represents the absolute error of the sampling time of the 1st channel, Δt N represents the absolute error of the sampling time of the Nth channel, y′ N [m] represents the first derivative of y N [m].

5. The TIADC sampling time mismatch error extraction and calibration method of claim 4, wherein, In step four, 6. The TIADC sampling time mismatch error extraction and calibration method of claim 5, wherein, The larger the mu is, the faster the convergence speed is, and the smaller the convergence precision is; the smaller the mu is, the slower the convergence speed is, and the larger the convergence precision is.

7. A TIADC sampling time mismatch calibration apparatus, characterized in that, The TIADC sampling time mismatch error extraction and calibration method of any one of claims 1-6 is used, The TIADC sampling time mismatch calibration device comprises: A signal acquisition module is configured to periodically acquire sampling signals, and obtain digital output signals of N sub-ADCs each time; a signal difference processing module, configured to obtain adjacent difference signals D by subtracting the digital output signal of the k+1th sub-ADC in the current acquisition from the digital output signal of the kth sub-ADC in the current acquisition k,k+1 ; k∈[1,N-1]; and obtain adjacent difference signals D by subtracting the digital output signal of the first sub-ADC in the previous acquisition from the digital output signal of the Nth sub-ADC in the current acquisition N,1 ; a signal approximation processing module for performing a first order Taylor expansion of the adjacent difference signal D k,k+1 , D N,1 at the ideal sampling time of each channel to obtain a digital signal approximation value at the expansion point a signal expectation processing module which approximates the digital signal at the unwinding point taking the absolute value first and then the expectation to obtain the expectation value A of the numerical signal approximation k,k+1 , A N,1 ; a signal absolute error processing module for processing the expected value A of the numerical signal approximation k,k+1 , N,1 to obtain a digital signal Δτ containing the sampling time absolute error Δt K ; and K ; a signal relative error module for performing one iteration of a sampling time relative error τ K in terms of a digital signal Δτ K containing a sampling time absolute error Δt K ; and a signal compensation module for compensating the digital output signals of the N sub-ADCs of the last acquisition with the iterated sampling time relative error τ K corresponding to the last acquisition.

8. The TIADC sampling time mismatch calibration device according to claim 7, wherein, The signal difference processing module, the signal approximation processing module, the signal expectation processing module, and the signal error processing module constitute a time deviation estimation module group. The signal compensation module is a derivative filter.

9. The TIADC sampling time mismatch calibration apparatus of claim 7, wherein, The TIADC sampling time mismatch calibration device further comprises: An iterative adjustment module is configured to adjust a parameter mu affecting the iterative convergence.

10. A readable storage medium, characterized by, The readable storage medium stores computer program instructions, and when the computer program instructions are read and run by a processor, the TIADC sampling time mismatch error extraction and calibration method of any one of claims 1-7 is executed.

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