Adaptive equalizer, electronic device and data processing method

Abstract

The present application discloses an adaptive equalizer, an electronic device, and a data processing method, which are used to improve the working efficiency of the adaptive equalizer, enhance the performance of the adaptive equalizer, reduce the circuit structure area, and save space resources. The adaptive equalizer includes: a pipeline equalization module, an error calculation module, and a parameter update module; wherein the pipeline equalization module includes a cascaded multi-order equalizer for receiving input data of a channel and calculating the equalization result of the input data; the error calculation module is used to determine and output the output data of the adaptive equalizer based on the equalization result output by the pipeline equalization module, and calculate the error between the equalization result and the preset ideal expected data; the parameter update module is used to update the parameters of the pipeline equalization module based on the error output by the error calculation module.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an adaptive equalizer, an electronic device, and a data processing method. Background Art

[0002] In high-speed channel transmission applications, when data rates reach 50 Gb / s, the symbol period for non-return-to-zero (NRZ) signals will be less than 20 ps, ​​and link loss will also be high. Therefore, the 200G / 400G Ethernet standards have adopted four-level pulse amplitude modulation (PAM-4) as the mainstream modulation method. Intersymbol interference (ISI) in PAM-4 signals is a major factor limiting signal quality. To effectively improve the transmission quality of PAM-4 signals and reduce bit error rates, the current common practice is to use various equalization technologies at the transmitter and receiver of serial links to enhance signal integrity.

[0003] As data rates increase, channel characteristics are increasingly affected by environmental factors such as temperature and humidity. Adaptive equalizers dynamically adjust their weights based on their algorithms, adapting to changing channel conditions and maintaining optimal performance. Therefore, existing adaptive equalizers based on the least mean square (LMS) algorithm can effectively address the ISI issue in PAM-4 signals, and higher-order adaptive equalization circuits can achieve even better equalization results.

[0004] However, the operating delay and convergence time of the adaptive equalizer based on the LMS algorithm will increase significantly with the increase of the order, which will lead to the performance degradation of the high-order adaptive equalizer and restrict the application of high-order adaptive equalizer in high-speed channel transmission. Summary of the Invention

[0005] The embodiments of the present application provide an adaptive equalizer, an electronic device, and a data processing method to improve the working efficiency of the adaptive equalizer, enhance the performance of the adaptive equalizer, reduce the circuit structure area, and save space resources.

[0006] An adaptive equalizer provided by an embodiment of the present application includes: a pipeline equalization module, an error calculation module and a parameter update module; wherein,

[0007] The pipeline equalization module includes a cascaded multi-stage equalizer, which is used to receive input data of the channel and calculate the equalization result of the input data;

[0008] The error calculation module is used to determine and output the output data of the adaptive equalizer according to the equalization result output by the pipeline equalization module, and calculate the error between the equalization result and the preset ideal expected data;

[0009] The parameter updating module is used to update the parameters of the pipeline equalization module according to the error output by the error calculation module.

[0010] The embodiment of the present application sets a pipeline equalization module with a pipeline structure in the adaptive equalizer, that is, it includes a cascade of multi-order equalizers, so that the calculation process of the maximum sum of products of the multi-order equalizer can be distributed to the equalizers of each order in the pipeline, reducing the circuit delay of obtaining the equalization result and improving the efficiency of calculating the equalization result of the input data; and each order equalizer only needs to store an intermediate result value calculated by the equalizer of the current order, thereby reducing the area of ​​the pipeline structure, that is, reducing the circuit structure area. Therefore, the embodiment of the present application can not only improve the equalization efficiency of the adaptive equalizer and enhance the performance of the adaptive equalizer, but also reduce the circuit structure area and save space resources.

[0011] In some embodiments, the first-order equalizer in the multi-order equalizer multiplies the input data by the weight coefficient of the first-order equalizer and outputs the result to the second-order equalizer;

[0012] The second-order equalizer and each subsequent cascaded order equalizer except the last-order equalizer respectively multiply the input data by the weight coefficient of the order equalizer, add the obtained result to the output result of the previous order equalizer, and output the result to the next-order equalizer;

[0013] The last-order equalizer multiplies the input data by the weight coefficient of the last-order equalizer, adds the obtained result to the result output by the previous-order equalizer, and finally obtains the equalization result of the input data and outputs it to the error calculation module.

[0014] In some embodiments, the parameter updating module is configured to update the parameters of the pipeline equalization module according to the error output by the error calculation module, specifically including:

[0015] The parameter updating module is used to iteratively update the parameters of the pipeline equalization module based on the input data group, including: according to the error output by the error calculation module, based on the least mean square algorithm, using each valid input data in the input data group to obtain a weight coefficient iteration value, and statistically summing the obtained weight coefficient iteration values, and updating the parameters of the pipeline equalization module based on the obtained sum value.

[0016] In some embodiments, the input data group includes a preset number of input data, and the preset number is greater than or equal to the order of the equalizer included in the pipeline equalization module.

[0017] In some embodiments, obtaining a weight coefficient iteration value using each valid input data in the input data set and summing the obtained weight coefficient iteration values ​​may specifically include:

[0018] A weight coefficient iteration value is obtained using each valid input data in the input data group. When Bv_num weight coefficient iteration values ​​are accumulated, the sum of the Bv_num weight coefficient iteration values ​​is counted, where Bv_num satisfies the following formula:

[0019] Bv_num=B_num-D_num;

[0020] Wherein, B_num is the preset number;

[0021] D_num is the number of input data delayed by the delay circuit in the error calculation module.

[0022] In some embodiments, the parameter updating module updates the parameters of the pipeline balancing module using the following formula:

[0023]

[0024] Wherein, n_block represents the number of the input data group; h i (n_block) represents the weight coefficient of the i-th order equalizer determined by the n_th block group of input data, h i (n_block-1) represents the weight coefficient of the i-th order equalizer determined using the n_block-1-th set of input data;

[0025] j represents the number of valid input data in each set of input data;

[0026] μ represents the iteration factor;

[0027] e(n+D_num-j) represents the error determined by the error calculation module using the input data at the n+D_num-jth moment; x(n+D_num-ji) represents the input data on the i-th order equalizer at the n+D_num-jth moment; wherein n represents the input moment of the first input data in each set of input data;

[0028] The iteration factor μ is calculated by the following formula:

[0029] μ=2 -lr+(B_num / N) ;

[0030] Wherein, lr represents a preset training learning rate, which is a preset constant, and N represents the total number of orders of equalizers included in the pipeline equalization module.

[0031] An electronic device provided in an embodiment of the present application includes any of the above-mentioned adaptive equalizers.

[0032] An embodiment of the present application provides a data processing method, including:

[0033] Receive input data from a channel and calculate an equalization result of the input data through a cascaded multi-stage equalizer;

[0034] Determining output data based on the equalization result and outputting the output data; and calculating an error between the equalization result and a preset ideal expected data;

[0035] The parameters of the multi-tap equalizer are updated according to the error.

[0036] In some embodiments, updating the parameters of the multi-tap equalizer according to the error includes:

[0037] The parameters of the multi-order equalizer are iteratively updated in units of input data groups, including: according to the error, based on the least mean square algorithm, using each valid input data in the input data group to obtain a weight coefficient iteration value, and statistically summing the obtained weight coefficient iteration values, and updating the parameters of the multi-order equalizer based on the obtained sum value.

[0038] An electronic device provided in an embodiment of the present application includes:

[0039] a memory for storing program instructions;

[0040] The processor is configured to call the program instructions stored in the memory and execute any one of the methods described in accordance with the obtained program.

[0041] Furthermore, according to an embodiment, a computer program product for a computer is provided, for example, comprising software code portions for executing the steps of the method defined above when the product is executed on the computer. The computer program product may include a computer-readable medium having the software code portions stored thereon. Furthermore, the computer program product may be directly loaded into the internal memory of the computer and / or transmitted via a network through at least one of an upload process, a download process, and a push process.

[0042] Another embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable the computer to execute any of the above methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] Figure 1 A schematic diagram of the overall structure of the adaptive equalizer provided in an embodiment of the present application;

[0045] Figure 2 A schematic diagram of the signal flow of each module in the adaptive equalizer provided in an embodiment of the present application;

[0046] Figure 3 A schematic diagram of a specific circuit structure of an adaptive equalizer provided in an embodiment of the present application;

[0047] Figure 4 A schematic diagram of the specific circuit structure and functional module division of the adaptive equalizer provided in an embodiment of the present application;

[0048] Figure 5 Schematic diagram of input channel data distribution of a 64-tap adaptive equalizer provided in an embodiment of the present application;

[0049] Figure 6 Schematic diagram of the output data distribution after processing by a 64-tap adaptive equalizer provided in an embodiment of the present application;

[0050] Figure 7 Schematic diagram of the convergence process of the error e(n) during the equalization process of the 64-tap adaptive equalizer provided in an embodiment of the present application;

[0051] Figure 8 A schematic diagram of the overall flow of a data processing method provided in an embodiment of the present application;

[0052] Figure 9 A flow chart of a data processing method for a 64-tap adaptive equalizer provided in an embodiment of the present application;

[0053] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0055] Embodiments of the present application provide an adaptive equalizer, an electronic device, and a data processing method to improve the operating efficiency and convergence performance of the adaptive equalizer, thereby enhancing the equalization performance of the entire adaptive equalizer, and also reducing the circuit structure area and saving space resources.

[0056] Among them, the adaptive equalizer, electronic device and data processing method are based on the same application concept and have similar principles for solving problems. Therefore, the specific embodiments can refer to each other and the repeated parts will not be repeated.

[0057] The terms "first", "second", etc. (if any) in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0058] The following examples and embodiments are to be understood as illustrative examples only. Although this specification may refer to "one," "an," or "some" examples or embodiments at several places, this does not mean that each such reference relates to the same example or embodiment, nor does it mean that the feature applies only to a single example or embodiment. Individual features of different embodiments may also be combined to provide further embodiments. Furthermore, terms such as "comprises" and "comprising" should be understood as not limiting the described embodiments to consisting only of those features already mentioned; such examples and embodiments may also include features, structures, units, modules, etc. that are not specifically mentioned.

[0059] The following describes in detail the various embodiments of the present application in conjunction with the accompanying drawings. It should be noted that the order in which the embodiments of the present application are presented only represents the order of the embodiments, and does not represent the advantages or disadvantages of the technical solutions provided by the embodiments.

[0060] In high-speed channel transmission, the data transmitter utilizes units such as an encoder, a parallel-to-serial converter, an equalizer, an output buffer, and a phase-locked loop (PLL). After being encoded by the encoder, the input data is converted into a serial data stream by the parallel-to-serial converter. Before being transmitted to the channel, an equalizer compensates for channel losses caused by bandwidth limitations. Equalization techniques typically used on the transmitter side include pre-emphasis / de-emphasis and FIR filters. Pre-emphasis compensates for channel attenuation by boosting high-frequency components, while de-emphasis attenuates low-frequency components to relatively enhance high-frequency components. FIR filters reshape the symbol signal in the time domain, restoring the signal after it has been damaged by the channel.

[0061] Accordingly, the data receiver primarily includes units such as a variable gain amplifier, equalizer, clock recovery, serial-to-parallel converter, and decoder. Equalizers are typically categorized as feedforward equalizers (FFE), continuous-time linear equalizers (CTLE), and decision feedback equalizers (DFE). FFE and CTLE can eliminate forward intersymbol interference (i.e., pre-cursor) and backward intersymbol interference (i.e., post-cursor). DFE can effectively eliminate post-cursor interference without amplifying crosstalk and noise, but it cannot eliminate pre-cursor interference. The serial-to-parallel converter module converts high-speed serial data into low-speed parallel data.

[0062] In the embodiment of the present application, a least mean square (LMS) algorithm is used in a high-order adaptive equalizer to adjust the weight coefficients of each order equalizer. The principle of the equalizer is as follows:

[0063]

[0064] In the above formula, n represents the time, y(n) is the equalization result of the equalizer output for the input data at the nth time, and h i (n_block) is the weight coefficient of the i-th order equalizer tap obtained by updating the n_block-th group input data (i can also be understood as the time offset caused by the N-th order adaptive equalizer), and x(ni) is the input data of the equalizer at the ni-th moment.

[0065] Among them, about h i (n_block), for example, the orders of the high-order adaptive equalizer described in the embodiment of the present application can be numbered starting from 0. For example, if the high-order adaptive equalizer includes a 64-order equalizer, that is, the value range of i is [0,63], then these equalizers can be numbered in sequence from order 0 to order 63, respectively referred to as the 0th order equalizer, the 1st order equalizer...the 63rd order equalizer.

[0066] It should be noted that n_block described in the embodiments of the present application represents the nth block, and the block is a group consisting of a preset number of input data (UI). The n in n_block represents number, that is, the number of blocks. Similar to the above order, the UI groups can also be numbered starting from 0. For example, if it is the first block, that is, the first group of UI, then n_block is 0_block, and the value of n_block is equal to 0. For example, h0(n_block) can represent the weight coefficient of the 0th order equalizer tap obtained using the n_block group of UI. Specifically, for different UI groups, there are the weight coefficient h0(0_block) of the 0th order equalizer tap calculated using the 0th group of UI, the weight coefficient h0(1_block) of the 0th order equalizer tap calculated using the 1st group of UI, and so on.

[0067] Regarding x(ni), for example, if the input data of the equalizer at the 0th moment is x(0), then the input data of the equalizer at the previous moment is x(-1), and the input data of the equalizer at the previous moment is x(-2), and so on.

[0068] The adaptive equalizer determines the iteration direction by the difference between the current output and the expected value. The error equation is as follows:

[0069] e(n)=d(n)-y(n)

[0070] According to the steepest descent method, the iterative formula (i.e., update formula) of the weight coefficient is as follows:

[0071] h i (n+1)=h i (n)+2μe(n)x i (n)

[0072] Where μ is the step size factor for weight coefficient iteration, which determines the convergence speed and error of the adaptive equalizer. If μ is too small, the convergence will be too slow, while if μ is too large, the training will not converge and the steady-state error will be large.

[0073] To address the issues of excessive delay and long convergence time in high-order adaptive equalizers, an embodiment of the present application provides a high-order adaptive equalizer for a high-speed Ethernet interface. In the adaptive equalizer, a pipelined delay and block-by-block LMS (DBLMS) adaptive equalization technology is proposed. The high-order adaptive equalizer adopts a transposed pipeline structure for adaptive equalization processing, which can effectively reduce the circuit delay of the high-order adaptive equalizer. Furthermore, combined with a block-by-block iterative update method for equalizer parameters, the convergence time is shortened, thereby ultimately improving the performance of the high-order adaptive equalizer.

[0074] See also Figure 1 The adaptive equalizer provided in the embodiment of the present application includes: a pipeline equalization module 101, an error calculation module 102, and a parameter update module 103, wherein the data direction of each module is as follows: Figure 2 shown.

[0075] The pipeline equalization module 101 includes a cascaded multi-stage equalizer, which is used to receive and equalize the input data of the channel to obtain the equalization result y(n) of the input data;

[0076] The cascaded multi-stage equalizer, i.e., the multi-stage equalizer included in the pipeline equalization module, adopts a pipeline structure, i.e., a multi-stage equalizer with a transposed and reconstructed pipeline structure in the embodiment of the present application, which calculates the equalization result of the input data step by step. This structure can improve the efficiency of calculating the equalization result of the input data and reduce the circuit structure area. For example:

[0077] The maximum sum-of-products calculation process for a 64-tap adaptive equalizer (the longest delay path for a 64-tap equalizer is y = Σx * h, representing the "maximum sum-of-products calculation") is distributed across each stage of the pipeline (i.e., each equalizer stage), thereby reducing the circuit latency required to obtain the equalization result. Furthermore, each pipeline stage only needs to store a single intermediate result value, reducing the area of ​​the pipeline circuit structure.

[0078] The error calculation module 102 determines and outputs the output data of the adaptive equalizer based on the equalization result output by the pipeline equalization module 101, and calculates the error between the equalization result and a preset ideal expected data (i.e., a preset value, the specific value of which can be determined according to actual needs);

[0079] For example, the error calculation module 102 compares the equalization result y(n) output by the pipeline equalization module 101 with four preset values ​​and outputs the value closest to the equalization result y(n) as the output data. Furthermore, the error calculation module 102 is further configured to calculate the error e(n) between the equalization result y(n) and the ideal expected data d(n).

[0080] The parameter updating module 103 is configured to update the parameters of the pipeline equalization module 101 (eg, weight coefficients of taps of equalizers of various orders, referred to as weight coefficients) according to the error output by the error calculation module 102 .

[0081] The latency of a high-order adaptive equalizer increases with the order, and higher orders are significantly effective in addressing the effects of high-noise environments. The embodiments of this application utilize a pipelined equalization module to address these effects while also reducing the latency of the high-order adaptive equalizer. Furthermore, when using a pipelined equalization module, the convergence performance of the adaptive equalizer degrades, and this deteriorates with higher orders. Therefore, the embodiments of this application utilize a DBLMS design in the parameter update module (i.e., the aforementioned block-by-block iterative update of the equalizer parameters) to address this issue.

[0082] Therefore, in some embodiments, the parameter updating module 103 obtains a weight coefficient using each UI based on the error e(n) output by the error calculation module 102 and based on the least mean square algorithm, and calculates the sum of a preset number of weight coefficients, that is, the cumulative weight coefficient iteration value, and updates the weight coefficient once each time a cumulative result is obtained. That is, the parameter updating module in the embodiment of the present application updates the weight coefficient by group according to each specified number of UIs, rather than updating the weight coefficient each time a weight coefficient is obtained using one UI.

[0083] The specific circuit structure of the adaptive equalizer provided in the embodiment of the present application is as follows: Figure 3 As shown, the corresponding relationship between the above modules and the circuit structure is as follows: Figure 4 As shown below. Figure 4 Give specific examples for each of the above modules.

[0084] The pipeline equalization module 101 is specifically used to receive and store the input data x(n) of the channel, and reconstruct the pipeline equalization structure after transposition (ie Figure 4 The circuit structure of the pipeline equalization module 101 shown in FIG is used to calculate the sum of the products of the weight coefficients step by step. In other words:

[0085] A first-order equalizer in the multi-order equalizer included in the pipeline equalization module multiplies the input data by the weight coefficient of the first-order equalizer and outputs the result to the second-order equalizer;

[0086] The second-order equalizer and each subsequent cascaded order equalizer except the last-order equalizer respectively multiply the input data by the weight coefficient of the order equalizer, add the obtained result to the output result of the previous order equalizer, and output the result to the next-order equalizer;

[0087] The last-order equalizer multiplies the input data by the weight coefficient of the last-order equalizer, adds the obtained result to the result output by the previous-order equalizer, and finally obtains the equalization result of the input data and outputs it to the error calculation module.

[0088] Taking a 64-tap equalizer as an example, each tap has a weight coefficient. 64 signals are sequentially input into the 64-tap equalizer and multiplied by each of the 64 weight coefficients. The sum of these 64 products is the calculated output of the pipeline equalization module (i.e., the equalization result). The weight coefficients are the weights of each tap equalizer.

[0089] The pipeline balancing structure after transposition and reconstruction described in the embodiment of the present application is to transform the original y=Σx*h into Figure 3 、 Figure 4 The pipeline structure shown is similar to a matrix transposition operation, so the structure of the cascaded multi-stage equalizer in the pipeline equalization module described in the embodiment of the present application is called a pipeline equalization structure after transposition reconstruction.

[0090] The error calculation module 102 is configured to perform hard decision based on the equalization result y(n) output by the pipeline equalization module to obtain a four-level output value (i.e., the aforementioned output data), and calculate the error e(n) between y(n) and the ideal expected signal d(n). The four-level output values ​​are, for example, 0, 1, 2, and 3, respectively.

[0091] The hard decision is to make a decision directly based on the relationship between the equalization result output by the pipeline equalization module and the size of the four-level output value. For example, if the equalization result output by the pipeline equalization module is 0.85, then the hard decision believes that 0.85 is closest to 1, so the output data after the decision is 1.

[0092] The parameter updating module 103 calculates the error e(n) and updates the weight coefficients based on the cumulative weight coefficient iteration values ​​using the least mean square (LMS) algorithm, with a specified number of UI (input data) as the unit. The error e(n) is the difference between the equalization result y(n) and the preset ideal expected value d(n).

[0093] The weight coefficients are updated in units of a specified number of UIs (input data), where each block is a block. For example, if the specified number is set to 50, the weight coefficients are updated every 50 UIs. The specific value of the specified number can be determined based on actual needs and is not limited in the present embodiment.

[0094] That is, in some embodiments, the parameter updating module 103 is used to iteratively update the parameters of the pipeline equalization module based on the input data group, including: according to the error output by the error calculation module 102, based on the least mean square algorithm, using each valid input data in the input data group to obtain a weight coefficient iteration value (for example, expressed as Δh), and statistically summing the obtained weight coefficient iteration values, and updating the parameters of the pipeline equalization module based on the obtained sum value.

[0095] The parameters of the pipeline equalization module are updated based on the obtained sum value. For example, the sum value can be directly used as the latest weight coefficient, or it can be updated iteratively, that is, the old weight coefficient is also added and then the weight coefficient is updated.

[0096] Among them, each set of input data can be fully valid or partially valid, depending on the structure of the delay circuit in the error calculation module. For example, if the number of delayed input data is 2, there will be two fewer valid input data in each set of input data.

[0097] In some embodiments, the input data group includes a preset number of input data, and the preset number is greater than or equal to the order of the equalizer included in the pipeline equalization module.

[0098] Regarding the iterative value of the weight coefficient (expressed as Δh), the weight coefficient h can be updated once a Δh is calculated, but this method is not applicable to the pipeline equalization module structure. Therefore, in some embodiments, for a 64-order adaptive equalizer, the specified number can be set to 64, that is, the weight coefficient is updated once every 64 UIs. Specifically, each UI corresponds to one Δh, and every 64 Δhs are added up (each order equalizer corresponds to one UI and one Δh, and the 64-order equalizer has a total of 64 Δhs). The weight coefficient is updated once using the sum value obtained by using 64 Δhs. In this way, the direction of the weight coefficient iteration is more accurate and the convergence effect is better.

[0099] Among them, when the parameter update module updates the weight coefficient of each tap based on the least mean square algorithm (the "tap" here actually means "each tap". The 64-tap equalizer has 64 taps, and each tap corresponds to a weight coefficient (understood as "weight")), it iterates the weight coefficient block by block, with each B_num UI as a group, where the relationship of B_num is as follows:

[0100] B_num≥N

[0101] The above formula indicates that the value of B_num cannot be less than the order N of the adaptive equalizer.

[0102] In some embodiments, the following formula is a relational expression of each valid UI number Bv_num:

[0103] Bv_num=B_num-D_num

[0104] B_num is the number of UIs per group (e.g., N, where the number of UIs per group = the number of UIs per block);

[0105] Bv_num is the number of valid UIs per group;

[0106] N is the order of the high-order adaptive equalizer;

[0107] D_num is the delay beat number of the delay circuit in the error calculation module 102, that is, the number of delayed input data (that is, invalid input data for updating the weight coefficient). For example, if it is delayed by 2 beats, see Figure 4 , the delay circuit in error calculation module 102 includes two D flip-flops, namely first D flip-flop 21 and first D flip-flop 22, so D_num is 2. Since the cumulative result Δh of each group of weight coefficients corresponds to the equalization result calculated using the old weight coefficients from the beginning of the weight coefficient accumulation, it cannot be used for the next round of weight coefficient iteration. During the block-by-block iterative update, the output of the delay circuit at the beginning of each group cannot be included. Therefore, the valid UI number for each group is obtained by subtracting D_num from B_num. Therefore, if the delay circuit in error calculation module 102 includes two D flip-flops, then D_num is 2. Then, the first two input data of each B_num input data are invalid for updating the weight coefficients, and the subsequent input data are considered valid input data for updating the weight coefficients.

[0108] In some embodiments, the iteration factor μ is calculated by the following formula:

[0109] μ=2 -lr+(B_num / N)

[0110] In the above formula, lr is the training learning rate set according to the specific channel harshness. It is a preset constant and its specific value can be determined according to actual needs.

[0111] Therefore, in some embodiments, the parameter updating module 103 updates the parameters of the pipeline balancing module 101 using the following formula:

[0112]

[0113] Wherein, n_block represents the number of the input data group; h i (n_block) represents the weight coefficient of the i-th order equalizer determined by the n_th block group of input data (i.e., the updated weight coefficient), h i (n_block-1) represents the weight coefficient of the i-th order equalizer determined using the n_block-1-th set of input data (i.e., the weight coefficient before update);

[0114] j represents the number of valid input data in each set of input data;

[0115] μ represents the iteration factor;

[0116] e(n+D_num-j) represents the error determined by the error calculation module using the input data at the n+D_num-jth moment; x(n+D_num-ji) represents the input data on the i-th order equalizer at the n+D_num-jth moment; wherein n represents the input moment of the first input data in each set of input data;

[0117] The iteration factor μ is calculated by the following formula:

[0118] μ=2 -lr+(B_num / N) ;

[0119] Wherein, lr represents a preset training learning rate, which is a preset constant, and N represents the total number of orders of equalizers included in the pipeline equalization module.

[0120] The following is a specific example of the 64-tap adaptive equalizer provided in the embodiment of the present application.

[0121] This embodiment of the invention is a 64-tap adaptive equalizer for a high-speed Ethernet interface, comprising a pipeline equalization module, an error calculation module, and a parameter update module. The pipeline equalization module receives input data and transposes and reconstructs the equalization process into a pipeline structure, calculating the sum y(n) of the product of the input data x(n) and the weight coefficient h step by step. The error calculation module uses hard decision to obtain a standard four-level output value based on y(n) and calculates the error e(n). The parameter update module iterates the weight coefficients block by block, with a specified number of UIs as a group. Specifically:

[0122] About the pipeline balancing module:

[0123] In a high-order adaptive equalizer, the performance of the pipeline equalization module determines the operating speed of the entire circuit. The pipeline equalization module, as the name implies, includes multiple stages of pipelines, that is, multiple stages of circuits, and each stage of the circuit acts as a first-stage pipeline, which is equivalent to a first-order equalizer, and obtains an intermediate calculation result. In the embodiment of the present application, the equalization calculation process is transposed and reconstructed into a pipeline structure, which improves the circuit operating speed while reducing the circuit area. The pipeline structure is equivalent to dividing a large multiplication and addition operation into many steps, and each step calculates an intermediate result. When it reaches the last stage of the pipeline, the final complete equalization result is output. Therefore, the circuits of each stage before the last stage of the pipeline (that is, each stage of the equalizer except the last stage equalizer) store the intermediate results that have not been calculated, leaving the next stage of the circuit to continue the calculation. Therefore, see Figure 4 The intermediate result expression stored in each circuit (a total of 64 stages) in the 64-stage pipeline equalization module provided in the embodiment of the present application is For example:

[0124] stage_00:x(n)·h0(n_block)

[0125] stage_01:x(n)·h1(n_block)+x(n-1)·h0(n_block)

[0126] stage_02:x(n)·h2(n_block)+x(n-1)·h1(n_block)+x(n-2)·h0(n_block)

[0127] stage_03:x(n)·h3(n_block)+x(n-1)·h2(n_block)+x(n-2)·h1(n_block)

[0128] +x(n-3)·h0(n_block)

[0129] stage_04:x(n)·h4(n_block)+x(n-1)·h3(n_block)+x(n-2)·h2(n_block)

[0130] +x(n-3)·h1(n_block)+x(n-4)·h0(n_block)

[0131] stage_05:x(n)·h5(n_block)+x(n-1)·h4(n_block)+x(n-2)·h3(n_block)

[0132] +x(n-3)·h2(n_block)+x(n-4)·h1(n_block)+x(n-5)·h0(n_block)

[0133] …

[0134] In the above expression, x(n) represents input data and n represents time.

[0135] The subscript of h indicates which order of the 64-order equalizer is the weight coefficient. For example, the weight coefficient of the 0th order equalizer, then the subscript is 0, that is, h0, then h 63 It is the weight coefficient of the 63rd order equalizer.

[0136] The number after Stage represents the circuit level of the pipeline, that is, the order of the equalizer. The 0th stage circuit is stage_00, and the 63rd stage circuit is stage_63.

[0137] For example, stage_00:x(n)·h0(n_block) means that the output result of the 0th-order equalizer is x(n)·h0(n_block), where x(n) represents the input data at time n, and h0(n_block) represents the weight coefficient of the 0th-order equalizer calculated using the n_block-th group of UIs.

[0138] For example, stage_01:x(n)·h1(n_block)+x(n-1)·h0(n_block) means that the output result of the first-order equalizer is x(n)·h1(n_block)+x(n-1)·h0(n_block), where x(n) represents the input data at time n, h1(n_block) represents the weight coefficient of the first-order equalizer calculated using the n_block group of UIs, x(n-1) represents the input data at time n-1, and h0(n_block) represents the weight coefficient of the 0th-order equalizer calculated using the n_block group of UIs.

[0139] For example, stage_02:x(n)·h2(n_block)+x(n-1)·h1(n_block)+x(n-2)·h0(n_block), which means that the output result of the second-order equalizer is x(n)·h2(n_block)+x(n-1)·h1(n_block)+x(n-2)·h0(n_block), where x(n) represents the input data at time n, h2(n_block) represents the weight coefficient of the second-order equalizer calculated using the n_block group of UIs, x(n-1) represents the input data at time n-1, h1(n_block) represents the weight coefficient of the first-order equalizer calculated using the n_block group of UIs, x(n-2) represents the input data at time n-2, and h0(n_block) represents the weight coefficient of the 0th-order equalizer calculated using the n_block group of UIs.

[0140] The output results of other stages of circuits are similar and will not be described in detail.

[0141] During the calculation process of the pipeline equalization module, the initial value of the internal storage register is 0, and the input data is stored in the register one by one. At the same time, the register is shifted row by row, and the most recent 64 input data are taken as x(n) and the weight coefficient h of each equalizer tap is used. i (n) and sum them to obtain the equilibrium calculation result y(n).

[0142] The pipeline equalization module in this embodiment distributes the maximum sum-of-products calculation process of the 64-tap adaptive equalizer across each stage of the pipeline, thereby reducing the circuit delay in obtaining the equalization result. Furthermore, each stage of the pipeline only stores one intermediate value, reducing the area of ​​the pipeline circuit structure.

[0143] For example, suppose the sum of 64 numbers is calculated at once. If the calculation is divided into two stages, the sum of each 8 numbers is calculated first, and 8 intermediate values ​​are obtained and stored for the next stage. The next stage then sums these 8 intermediate values ​​to obtain the total sum of 64 numbers. In this case, 8 intermediate values ​​need to be stored, which requires a lot of storage circuits. However, in the embodiment of the present application, only one intermediate value needs to be stored. The calculation of each stage of the pipeline equalization module is based on the calculation result of the previous stage circuit, thus saving the area of ​​the storage circuit.

[0144] The following describes how to preset the circuit parameters in the parameter update module.

[0145] The circuit parameters include: B_num, Bv_num, D_num, iteration factor μ, etc.

[0146] Among them, B_num is the number of UIs in each group. If B_num is set too small, it cannot offset the problem of asynchronous update of the weight coefficients of the pipeline balancing module. If B_num is set too large, the weight coefficient update frequency is too low and the convergence time is too long.

[0147] D_num is the UI number of the delay circuit. The delay circuit can reduce the delay of the error calculation circuit, fully utilizing the low-latency characteristics of the pipeline equalization module. If D_num is too small, the circuit delay cannot be reduced. If D_num is too large, the effective UI number Bv_num is too small, reducing convergence efficiency.

[0148] In some embodiments, the value of B_num is set to meet the following conditions:

[0149] B_num≥N;

[0150] As shown in the above formula, B_num cannot be less than the order N of the adaptive equalizer.

[0151] In some embodiments, the relationship between Bv_num, B_num, and D_num is as follows:

[0152] Bv_num=B_num-D_num;

[0153] In the above formula, B_num is the number of UIs in each group, Bv_num is the effective number of UIs in each group, and D_num is the number of UIs delayed by the delay circuit in the error calculation module. For example, if D_num = 2, it means that the delay circuit in the error calculation module delays 2 UIs.

[0154] In some embodiments, a 64-tap adaptive equalizer uses a value of D_num set to 2, a value of B_num set to 64, and a value of Bv_num set to 62. This achieves the highest efficiency for the block-by-block equalization algorithm. During the parameter update module's execution, the equalization results for the first two UIs of every 64 UIs are discarded, and the error e(n) between the equalization results for the last 62 UIs is calculated to obtain the iterative value of the weight coefficients, which is then accumulated and summed.

[0155] In some embodiments, see Figure 4 The parameter update module 103 includes a counter (cnt), namely counter cnt64, which counts cyclically from 0 to 63. When the count value cnt<2, the parameter update module 103 ignores the obtained error e(n); when the count value cnt≥2 and ≤63, the parameter update module 103 multiplies the error e(n) with the input data (x(n) in the cache Rx_buffer) to obtain the weight coefficient iteration value Δh, and accumulates the obtained block-by-block iteration value Δh, for example, Δh=2μe(n)x(n).

[0156] In the least mean square algorithm, the iteration factor μ determines the convergence time of the adaptive equalizer. If the iteration factor is too large, the training process is prone to non-convergence and the steady-state error is too large; if the iteration factor is too small, the iteration step size is too small and the convergence speed is too slow.

[0157] In some embodiments, the iteration factor μ is calculated as follows:

[0158] μ=2 -lr+(B_num / N) ;

[0159] In the above formula, lr is the training learning rate pre-set according to the specific channel harshness. It is a preset constant and its specific value can be determined according to actual needs.

[0160] In some embodiments, for a 64-tap adaptive equalizer, the optimal lr is set to 7 and B_num is set to 64, so the calculated optimal iteration factor μ is equal to 2 -6 In digital circuit implementation, a register can be shifted right by 6 bits instead of multiplying by 2. -6 .

[0161] In summary, about Figure 4 The various modules in the circuit structure of the adaptive equalizer shown:

[0162] Pipeline balancing module: The input data x(n) at the nth moment is Figure 4 The signal line shown in the figure is input to the pipeline equalization module, and x(n) is multiplied by the i-th order weight coefficient h on the 64-stage pipeline from stage_00 to stage_63. i(n_block) and adds it to the result of the previous pipeline stage. Finally, the equalization result is output in stage_63. Due to the presence of the first D flip-flop 21 connected to the last stage of the stage_63 pipeline, the output at time n is the equalization result y(n-1) of the previous moment.

[0163] Error calculation module: compares the equalization result y(n) output by the pipeline equalization module 101 with four preset values ​​through a decision device, and outputs the value closest to the equalization result y(n) among the four values ​​as output data; and calculates the error e(n-1) at the n-1th moment, wherein e(n-1) requires the difference between the ideal data d(n-1) at the n-1th moment and the equalization result y(n-1), so see Figure 4 , it is necessary to add a D flip-flop 23 to the ideal data d(n) to achieve a delay of 1 beat, that is, a delay of 1 UI time.

[0164] In some embodiments, to reduce the circuit delay from pipeline equalization module 101 to parameter update module 103, a D flip-flop is inserted at the output of stage_63 of pipeline equalization module 101 and the output of error calculation module 102, respectively. These two D flip-flops represent circuit parameter D_num = 2 (the D in D_num stands for Delay).

[0165] Parameter updating module 103:

[0166] The parameter update module 103 includes a cache (for example, 64 caches: Rx_buffer(1) to Rx_buffer(64)) for caching X(n) data. According to the weight coefficient iteration value calculation formula Δh(n_block)=2μe(n-1)x(n-1), the error e(n-1) is multiplied by x(n-1) in the cache and multiplied by the iteration factor μ to calculate the weight coefficient iteration value Δh.

[0167] cnt64 is a 64-bit counter. In this embodiment, B_num = 64, so the maximum range of the counter is 0 to 63. Since Bv_num = 62, when the counter is less than 2, the calculated Δh is not included in the weight coefficient update array. When the counter is greater than or equal to 2 and less than or equal to 63, the calculated Δh is included in the weight coefficient update array. By summing these 62 Δh, the obtained sum is used to update the weight coefficient of the equalizer. That is, for each order of equalizer, the current weight coefficient of the order equalizer is added to the sum value to obtain the updated weight coefficient of the order equalizer.

[0168] In the embodiment of the present application, the weight coefficients used on equalizers of different orders may be different, but the weight coefficients of equalizers of each order may be updated simultaneously each time an update is performed.

[0169] In this embodiment, the input end inputs 0.7Gb / s channel data, and after being equalized by a 64-order high-order adaptive equalizer, a standard PAM4 level signal is output. The input data x(n) of this embodiment enters the circuits of each stage in the pipeline equalization module in sequence, and is multiplied by the weight coefficients of each stage of the pipeline circuit respectively. At the same time, the pipeline transmits the calculation results of each stage step by step. When it is transmitted to the stage_63 pipeline, the complete equalization result is output. However, due to the existence of the D flip-flop of the stage_63 pipeline, the output equalization result is y(n-1) corresponding to the previous moment. After judgment, the equalization result y(n-1) is subtracted from the ideal expected signal d(n). This process inserts two levels of delay, that is, D_num=2, thereby further reducing the path delay. The calculated error e(n-1) is multiplied by the iteration factor μ and x(n) to obtain the weight coefficient iteration value Δh. After counting by the counter, after accumulating 64 Δh, the last 62 Δh are accumulated and the weight coefficient h is updated once. The input channel data distribution of the 64-order adaptive equalizer is as follows: Figure 5 As shown, the output data distribution after 64-order adaptive equalizer processing is as follows Figure 6 As shown in the figure, it can be seen that after being processed by the 64-order high-order adaptive equalizer, the voltage values ​​of the output data are well separated, which meets the standard of the PAM4 four-level modulation signal and effectively eliminates inter-symbol interference. Figure 7 FIG. 3 shows the convergence process of the error e(n) during the equalization process of the 64-tap adaptive equalizer. It can be seen that after about 8000 UI of adaptive iterations, the 64-tap adaptive equalizer reaches stability, and the error after stabilization is less than 70 mV.

[0170] In summary, in order to solve the problems of large circuit delay, slow operating speed and long convergence time of traditional high-order adaptive equalizers. The embodiment of the present application provides a 64-order adaptive equalizer for a high-speed Ethernet interface, proposes a pipelined DBLMS adaptive equalization technology, adopts a transposed reconstructed pipeline structure to build an equalization module, adopts a block-by-block iterative method to update the weight coefficient, and proposes a relationship expression of B_num, Bv_num and D_num applicable to the pipelined DBLMS adaptive equalization technology of the present invention, as well as a corresponding iteration factor μ setting expression. The improved high-order adaptive equalizer proposed in the embodiment of the present application includes a pipelined DBLMS adaptive equalization technology, which can effectively reduce the circuit delay of the high-order adaptive equalizer, improve the operating speed of the high-order adaptive equalizer, and reduce the convergence time, thereby improving the performance of the high-order adaptive equalizer and can be applied to the field of high-speed Ethernet communications.

[0171] Accordingly, an embodiment of the present application further provides an electronic device, which may be, for example, a data transmitter or a data receiver, or may include both of them. The electronic device includes the adaptive equalizer provided in the embodiment of the present application.

[0172] Accordingly, see Figure 8 , a data processing method provided in an embodiment of the present application includes:

[0173] S801, receiving input data from a channel, and calculating an equalization result of the input data through a cascaded multi-stage equalizer;

[0174] S802: Determine output data according to the equalization result and output the output data; and calculate the error between the equalization result and preset ideal expected data;

[0175] S803: Update parameters of the multi-tap equalizer according to the error.

[0176] In some embodiments, updating the parameters of the multi-tap equalizer according to the error includes:

[0177] The parameters of the multi-order equalizer are iteratively updated in units of input data groups, including: according to the error, based on the least mean square algorithm, using each valid input data in the input data group to obtain a weight coefficient iteration value Δh, and statistically summing the obtained weight coefficient iteration values, and updating the parameters of the multi-order equalizer based on the obtained sum value. For example, for the above-mentioned 64-order equalizer, 64 input data are preset as a group (i.e., B_num=64), and the number of valid data in each group is 62 (i.e., Bv_num=62), then 62 sum values ​​of Δh are obtained. For each order equalizer, the current weight coefficient of the order equalizer is added to the sum value to obtain the updated weight coefficient of the order equalizer.

[0178] In some embodiments, the input data group includes a preset number of input data, and the preset number is greater than or equal to the order of the equalizer included in the pipeline equalization module.

[0179] In some embodiments, obtaining a weight coefficient iteration value using each valid input data in the input data set and summing the obtained weight coefficient iteration values ​​may specifically include:

[0180] A weight coefficient iteration value is obtained using each valid input data in the input data group. When Bv_num weight coefficient iteration values ​​are accumulated, the sum of the Bv_num weight coefficient iteration values ​​is counted, where Bv_num satisfies the following formula:

[0181] Bv_num=B_num-D_num;

[0182] Wherein, B_num is the preset number;

[0183] D_num is the number of input data delayed by the delay circuit in the error calculation module.

[0184] In some embodiments, the parameters of the multi-tap equalizer are updated using the following formula:

[0185]

[0186] Wherein, n_block represents the number of the input data group; h i (n_block) represents the weight coefficient of the i-th order equalizer determined by the n_th block group of input data, h i (n_block-1) represents the weight coefficient of the i-th order equalizer determined using the n_block-1-th set of input data;

[0187] j represents the number of valid input data in each set of input data;

[0188] μ represents the iteration factor;

[0189] e(n+D_num-j) represents the error determined by the error calculation module using the input data at the n+D_num-jth moment; x(n+D_num-ji) represents the input data on the i-th order equalizer at the n+D_num-jth moment; wherein n represents the input moment of the first input data in each set of input data;

[0190] The iteration factor μ is calculated by the following formula:

[0191] μ=2 -lr+(B_num / N) ;

[0192] Wherein, lr represents a preset training learning rate, is a preset constant, and N represents the total number of orders of the multi-order equalizer.

[0193] The data processing flow using a 64-tap equalizer as an example is shown in Figure 9 , for example:

[0194] S901, the pipeline equalization module receives input data;

[0195] S902, each order equalizer in the pipeline equalization module multiplies the input data by the corresponding weight coefficient;

[0196] S903, the pipeline equalization module calculates the equalization result and outputs it to the error calculation module, and then executes step S908;

[0197] S904, the error calculation module calculates the error and outputs it to the parameter update module;

[0198] S905, the parameter updating module calculates the iterative value of the weight coefficient;

[0199] S906: The parameter updating module determines whether the weight coefficient iteration value has accumulated 64 entries. If so, step S907 is executed; otherwise, the module returns to step S902.

[0200] S907, the parameter updating module outputs the updated weight coefficient to the pipeline balancing module;

[0201] S908. The pipeline equalization module outputs the judgment result.

[0202] The following is an introduction to the electronic device provided in an embodiment of the present application, in which the explanations or examples of technical features that are the same as or corresponding to those described in the above-mentioned data processing method are not repeated hereafter.

[0203] The present application provides an electronic device, see Figure 10 ,include:

[0204] The processor 500 is configured to read the program in the memory 520 and execute the following process:

[0205] Receive input data from a channel and calculate an equalization result of the input data through a cascaded multi-stage equalizer;

[0206] Determining output data based on the equalization result and outputting the output data; and calculating an error between the equalization result and a preset ideal expected data;

[0207] The parameters of the multi-tap equalizer are updated according to the error.

[0208] In some embodiments, updating the parameters of the multi-tap equalizer according to the error includes:

[0209] The parameters of the multi-order equalizer are iteratively updated in units of input data groups, including: according to the error, based on the least mean square algorithm, using each valid input data in the input data group to obtain a weight coefficient iteration value, and statistically summing the obtained weight coefficient iteration values, and updating the parameters of the multi-order equalizer based on the obtained sum value.

[0210] In some embodiments, the input data group includes a preset number of input data, and the preset number is greater than or equal to the order of the equalizer included in the pipeline equalization module.

[0211] In some embodiments, obtaining a weight coefficient iteration value using each valid input data in the input data set and summing the obtained weight coefficient iteration values ​​may specifically include:

[0212] A weight coefficient iteration value is obtained using each valid input data in the input data group. When Bv_num weight coefficient iteration values ​​are accumulated, the sum of the Bv_num weight coefficient iteration values ​​is counted, where Bv_num satisfies the following formula:

[0213] Bv_num=B_num-D_num;

[0214] Wherein, B_num is the preset number;

[0215] D_num is the number of input data delayed by the delay circuit in the error calculation module.

[0216] In some embodiments, the parameters of the multi-tap equalizer are updated using the following formula:

[0217]

[0218] Wherein, n_block represents the number of the input data group; h i (n_block) represents the weight coefficient of the i-th order equalizer determined by the n_th block group of input data, h i (n_block-1) represents the weight coefficient of the i-th order equalizer determined using the n_block-1-th set of input data;

[0219] j represents the number of valid input data in each set of input data;

[0220] μ represents the iteration factor;

[0221] e(n+D_num-j) represents the error determined by the error calculation module using the input data at the n+D_num-jth moment; x(n+D_num-ji) represents the input data on the i-th order equalizer at the n+D_num-jth moment; wherein n represents the input moment of the first input data in each set of input data;

[0222] The iteration factor μ is calculated by the following formula:

[0223] μ=2 -lr+(B_num / N) ;

[0224] Wherein, lr represents a preset training learning rate, is a preset constant, and N represents the total number of orders of the multi-order equalizer.

[0225] In some embodiments, the electronic device provided by the embodiments of the present application further includes: a transceiver 510 for receiving and sending data under the control of the processor 500.

[0226] Among them, Figure 10 In the embodiment, the bus architecture may include any number of interconnected buses and bridges, specifically linking together various circuits of one or more processors represented by processor 500 and memory represented by memory 520. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are all well known in the art and, therefore, will not be described further herein. The bus interface provides an interface. The transceiver 510 may be a plurality of components, i.e., a transmitter and a receiver, providing a unit for communicating with various other devices on a transmission medium, such as a wireless channel, a wired channel, an optical cable, and the like. The processor 500 is responsible for managing the bus architecture and general processing, and the memory 520 may store data used by the processor 500 when performing operations.

[0227] The processor 500 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or a complex programmable logic device (CPLD). The processor may also adopt a multi-core architecture.

[0228] It should be noted that the division of modules in the various devices described in the embodiments of the present application is schematic and is only a logical functional division. In actual implementation, there may be other division methods. In addition, the functional units in the various embodiments of the present application may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The above-mentioned integrated units may be implemented in the form of hardware or in the form of software functional units.

[0229] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to perform all or part of the steps of the method described in each embodiment of the present application.

[0230] The present application also provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform any of the methods described in the above embodiments. The program product may utilize any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium.

[0231] The present invention provides a computer-readable storage medium for storing computer program instructions used by the apparatus provided in the above embodiments of the present invention, which includes a program for executing any of the methods provided in the above embodiments of the present invention. The computer-readable storage medium may be a non-transitory computer-readable medium.

[0232] The computer-readable storage medium can be any available medium or data storage device that can be accessed by a computer, including but not limited to magnetic storage (such as floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO), etc.), optical storage (such as CDs, DVDs, BDs, HVDs, etc.), and semiconductor storage (such as ROMs, EPROMs, EEPROMs, non-volatile memories (NANDFLASH), solid-state drives (SSDs)), etc.

[0233] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. An adaptive equalizer, characterized in that: The high-order adaptive equalization application scenario applied to the high-speed Ethernet interface includes: a pipeline equalization module, an error calculation module and a parameter update module; wherein, The pipeline equalization module includes a multi-stage equalizer with a transposed and reconstructed pipeline structure, which is used to receive input data of the channel and calculate the equalization result of the input data; wherein each stage equalizer stores an intermediate result value calculated by the current stage equalizer; The error calculation module is used to determine and output the output data of the adaptive equalizer according to the equalization result output by the pipeline equalization module, and calculate the error between the equalization result and the preset ideal expected data; The parameter updating module is used to iteratively update the parameters of the pipeline equalization module based on the error output by the error calculation module and in units of input data groups.

2. The adaptive equalizer according to claim 1, wherein A first-order equalizer in the multi-order equalizer multiplies the input data by a weight coefficient of the first-order equalizer, and outputs the result to a second-order equalizer; The second-order equalizer and each subsequent cascaded order equalizer except the last-order equalizer respectively multiply the input data by the weight coefficient of the order equalizer, add the obtained result to the output result of the previous order equalizer, and output the result to the next-order equalizer; The last-order equalizer multiplies the input data by the weight coefficient of the last-order equalizer, adds the obtained result to the result output by the previous-order equalizer, and finally obtains the equalization result of the input data and outputs it to the error calculation module.

3. The adaptive equalizer according to claim 1, wherein The parameter updating module is configured to iteratively update the parameters of the pipeline equalization module based on the error output by the error calculation module and in units of input data groups, specifically comprising: The parameter updating module is used to obtain a weight coefficient iteration value based on the error output by the error calculation module and the least mean square algorithm using each valid input data in the input data group, and to calculate the sum of the obtained weight coefficient iteration values, and to update the parameters of the pipeline equalization module based on the obtained sum value.

4. The adaptive equalizer according to claim 3, wherein: The input data group includes a preset number of input data, and the preset number is greater than or equal to the order of the equalizer included in the pipeline equalization module.

5. The adaptive equalizer according to claim 4, wherein: The method of obtaining a weight coefficient iteration value by using each valid input data in the input data group and summing the obtained weight coefficient iteration values ​​is as follows: A weight coefficient iteration value is obtained using each valid input data in the input data group. When Bv_num weight coefficient iteration values ​​are accumulated, the sum of the Bv_num weight coefficient iteration values ​​is counted, where Bv_num satisfies the following formula: Bv_num=B_num-D_num; Wherein, B_num is the preset number; D_num is the number of input data delayed by the delay circuit in the error calculation module.

6. The adaptive equalizer according to claim 5, wherein: The parameter updating module updates the parameters of the pipeline balancing module using the following formula: Wherein, n_block represents the number of the input data group; h i (n_block) represents the weight coefficient of the i-th order equalizer determined by the n_th block group of input data, h i (n_block-1) represents the weight coefficient of the i-th order equalizer determined using the n_block-1-th set of input data; j represents the number of valid input data in each set of input data; μ represents the iteration factor; e(n+D_num-j) represents the error determined by the error calculation module using the input data at the n+D_num-jth moment; x(n+D_num-ji) represents the input data on the i-th order equalizer at the n+D_num-jth moment; wherein n represents the input moment of the first input data in each set of input data; The iteration factor μ is calculated by the following formula: μ=2 -lr+(B_num / N) ; Wherein, lr represents a preset training learning rate, which is a preset constant, and N represents the total number of orders of equalizers included in the pipeline equalization module.

7. An electronic device, characterized in that: The electronic device comprises the adaptive equalizer according to any one of claims 1 to 6.

8. A data processing method, characterized in that: The method comprises: Receive input data from a channel and calculate an equalization result of the input data through a transposed and reconstructed pipeline multi-stage equalizer; wherein each stage equalizer stores an intermediate result value; Determining output data based on the equalization result and outputting the output data; and calculating an error between the equalization result and a preset ideal expected data; According to the error, the parameters of the multi-step equalizer are iteratively updated in units of input data groups.

9. The method according to claim 8, characterized in that The iterative updating of the parameters of the multi-step equalizer based on the error and taking the input data group as a unit comprises: According to the error, based on the least mean square algorithm, a weight coefficient iteration value is obtained using each valid input data in the input data group, and the sum of the obtained weight coefficient iteration values ​​is statistically calculated, and the parameters of the multi-order equalizer are updated based on the obtained sum value.

10. An electronic device, characterized in that: The electronic device comprises: a memory for storing program instructions; A processor is configured to call the program instructions stored in the memory and execute the method according to claim 8 or 9 according to the obtained program.

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