System and method for driving word lines using set-reset latches

Abstract

A memory device includes: a first core of memory bit cells; a second core of memory bit cells; a pre-decoding circuit system shared by the first core and the second core; and a row decoder coupled to the pre-decoding circuit system, the first core and the second core, the row decoder including a first set-reset (SR) latch and a second SR latch, the first set-reset (SR) latch being coupled to a first word line of the first core and the second SR latch being coupled to a second word line of the second core.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Patent Application No. 17 / 089,534, filed on November 4, 2020, the disclosure of which is incorporated herein by reference in its entirety as if fully set forth below and for all applicable purposes. Technical Field

[0003] The present application relates generally to row decoders and, more particularly, to a row decoder with a set-reset latch. Background Art

[0004] Conventional computing devices (e.g., smart phones, tablet computers, etc.) may include a system on a chip (SOC) having a processor and other operating circuits. The SOC may also include random access memory (RAM) implemented as static RAM (SRAM), dynamic RAM (DRAM), and various read-only memories (ROM). RAM may be implemented inside a processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU)) or outside a processor.

[0005] An example of a RAM includes a system with two single-sided memories that share an address predecoder and a set of row decoders. The address predecoder receives the addresses of the two single-sided memories and predecodes them. The predecoded signal is then applied to the row decoder to turn on the appropriate word line. This is true for both reading and writing. Relative to a system in which each memory has its own address predecoder and row decoder, a system is designed so that physical space on the semiconductor die can be saved by reducing the number of transistors so that the two single-sided memories share an address predecoder and a set of row decoders. However, sharing address predecoders and row decoders between memories may have disadvantages.

[0006] One disadvantage found in some systems is that each row decoder may be coupled to a transistor stack via a floating node. The transistor stack may include a pull-down stack that receives a pre-decoded signal. Assuming the row decoder has the ability to latch the word line, the stability of the circuit may depend on the relative strength of the row decoder latch relative to the transistor stack. Specifically, if the row decoder latch is weaker than the transistor stack, then in some cases it may be necessary to allow for an undesired discharge of one or both of the row decoders.

[0007] Therefore, there is a need in the art for a RAM row decoder with higher stability while maintaining the space saving advantage by sharing address pre-decoding and row decoding among multiple single-sided memories. Summary of the invention

[0008] Various embodiments provide systems and methods for driving word lines using set-reset (SR) latches. One embodiment includes a row decoder in a larger memory device having a first memory core and a second memory core that share pre-decoding circuitry. Each row decoder may include cross-coupled NOR gates for the SR latches. A further improvement of one embodiment includes using a more compact configuration of transistors for the SR latches, rather than cross-coupled NOR gates.

[0009] According to one embodiment, a memory device includes: a first core of memory bit cells; a second core of memory bit cells; a pre-decoding circuit system shared by the first core and the second core; and a row decoder coupled to the pre-decoding circuit system, the first core and the second core, the row decoder including a first set-reset (SR) latch and a second SR latch, the first SR latch being coupled to a first word line of the first core and the second SR latch being coupled to a second word line of the second core.

[0010] According to one embodiment, a method performed in a time-sharing memory architecture includes: driving a first word line in a first core of a memory bit cell, including setting a first set-reset (SR) latch by using a first set signal; maintaining a voltage of the first word line in an on state, including applying the voltage of the first word line to a first transistor in the first SR latch; driving a second word line in a second core of the memory bit cell, including setting a second SR latch using a second set signal; maintaining a voltage of the second word line in an on state, including applying the voltage of the second word line to a second transistor in the second SR latch; and after driving the first word line, turning off the first word line by changing a first reset signal of the first SR latch.

[0011] According to one embodiment, a system on a chip (SOC) includes: a time-sharing memory device, including a first core of memory bit cells and a second core of memory bit cells; a component for converting address bits into a pre-decoded signal; and a component for receiving the pre-decoded signal and for accessing data in the time-sharing memory device according to the pre-decoded signal, the receiving component including a row decoder array, each row decoder in the array including a first set-reset (SR) latch and a second SR latch, the first SR latch having a first SR latch coupled to the first core and the second SR latch coupled to the second core.

[0012] According to one embodiment, a system on chip (SOC) includes: a first core of a memory bit cell; a second core of a memory bit cell; and a plurality of row decoders shared by the first core and the second core, wherein a first row decoder of the plurality of row decoders includes a first set-reset (SR) latch and a second SR latch, the first SR latch being coupled to a first word line of the first core, and the second SR latch being coupled to a second word line of the second core. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a simplified diagram illustrating an example memory device having two memory cores according to one embodiment.

[0014] Figure 2 According to one embodiment, Figure 1 Illustration of an example row decoder applied in a memory device of .

[0015] Figure 3 is based on Figure 2 A timing diagram of an embodiment of an example row decoder operation.

[0016] Figure 4 is used for Figure 1 In the implementation mode, control is performed as follows Figure 2 , Figure 6 and a diagram of an example global block controller (GBC) for a row decoder illustrated in FIG. 8 .

[0017] Figure 5 is a diagram of an example address predecoder adapted in accordance with one embodiment.

[0018] Figure 6 According to one embodiment Figure 2 An exemplary scaled-up illustration of a row decoder of FIG. 1 such that multiple row decoders are included in the same memory device (eg, Figure 1 within an exemplary memory device).

[0019] Figure 7 is an exemplary timing diagram of an exemplary scaled-up memory device having multiple row decoders according to one embodiment.

[0020] Fig. 8A and 8B According to one embodiment, two SR latches are used and can be used Figure 1 A diagram and timing diagram of a row decoder in an embodiment of a memory device.

[0021] Fig. 9 is a diagram of an exemplary system on a chip (SOC) according to one embodiment, in which a row decoder (e.g. Figure 2 , Figure 6 and a memory device having a row decoder as illustrated in FIG8 ).

[0022] Fig.10 is a diagram of a method of driving a plurality of word lines according to one embodiment. DETAILED DESCRIPTION

[0023] Various embodiments provided herein include systems and methods for driving word lines in a memory device, wherein the memory cores share a pre-decoding circuit system. In one embodiment, the memory device includes a first core of memory bit cells and a second core of memory bit cells. The first core and the second core share the pre-decoding circuit system. The memory device also includes a row decoder group or array, which is coupled to the pre-decoding circuit system and the first core and the second core. Referring to a row decoder in the row decoder, a first set-reset (SR) latch and a second SR latch may be included, the first SR latch being coupled to a first word line of the first core and the second SR latch being coupled to a second word line of the second core.

[0024] The SR latch can allow the word line to remain in the on state for a desired time. For example, after a read or write operation in the first core and during a read or write operation in the second core, the word line in the first core can be held in the on state, allowing the first core and the second core to operate in the same clock cycle while sharing the pre-decoding circuit system.

[0025] Continuing with this example, in some implementations, the SR latch may include cross-coupled NOR gates, such as Fig. 8A As shown. Referring to an SR latch, a first of the NOR gates is used for input of a reset signal, and a second of the NOR gates may have an input for an inverted set signal. In this embodiment, the reset signal may cause the latch to hold the corresponding word line in an off position, while the set signal may cause the latch to hold the corresponding word line in an on position. A set of cross-coupled NOR gates may be implemented using sixteen transistors. In some embodiments, sixteen transistors for an SR latch may be suitable, although other embodiments may be well served by using a smaller number of transistors for each SR latch.

[0026] Thus, another embodiment includes implementing each SR latch with as few as eight transistors, although the scope of the embodiments is not limited to any particular number of transistors. Figure 2An example is shown in , where the reset input may include a pull-up transistor 210 of the SR latch, which is coupled to the first word line through a first inverter 215 and is gate-coupled to the reset signal. Thus, if the reset signal is active low, and if the pull-up transistor is a positive channel metal oxide semiconductor (PMOS) device, a low reset signal may be used to hold the input of the inverter so that the output of the inverter on the word line is low, thereby holding the word line in an off state. When the memory core is selected for a read or write operation, the reset signal is shifted to a logic high level so that the appropriate word line can be asserted based on the address input.

[0027] Continuing with this example, the SR latch may also include a pull-down transistor (eg, Figure 2 213). If the set signal is active high, and if the pull-down transistor is a negative channel metal oxide semiconductor (NMOS) device, the set signal can be used to pull down the input of the inverter to turn the word line on. In one embodiment, the set signal is pulsed so that it is high for a short time relative to the clock cycle. Figure 2 Examples of initial states including pre-decoded signals and pause signals are discussed in more detail.

[0028] In addition, exemplary embodiments may include another transistor 211 gate coupled to the word line. When the word line is asserted, the transistor may be turned on and the input of the inverter may be pulled down, thereby maintaining the word line in the on state. The word line may be returned to the off state by asserting an active low reset signal.

[0029] Of course, the above example describes only one SR latch. Various implementations include an SR latch for each word line in each memory core. For example, one embodiment may include two memory cores each with 512 word lines, such that each row decoder will have 512 SR latches driving its word line for one core, and another 512 SR latches driving its word line for the other core. These numbers are examples only, and the scope of the implementation may be scaled to any appropriate number of word lines.

[0030] Various embodiments may also include methods. An example method includes: driving a first word line in a first core of a memory bit cell, including setting a first SR latch. The method may also include maintaining a voltage of the first word line in an on state, including applying the voltage of the first word line to a transistor in the first SR latch. The method may also include driving a second word line in a second core of the memory bit cell, such as by setting a second SR latch. After driving the word line, the method may also include turning off the first word line by changing a first reset signal in the first SR latch. Other actions may include turning off the second word line by changing a second reset signal of the second SR latch.

[0031] Various embodiments may include advantages over other systems. Compared to previous embodiments using a floating node between an NMOS transistor stack and a latch, one advantage includes additional stability. For example, various embodiments have complementary pull-up and pull-down portions to avoid charge sharing. Complementary pull-ups and pull-downs can avoid accidental selection of word lines. In addition, using the voltage of the word line to maintain the state of the latch when the voltage of the word line is high can also further help improve the stability of the word line by avoiding accidental shutdowns.

[0032] In addition, various embodiments also reduce the number of transistors by implementing the SR latch using as few as eight transistors. Reducing the number of transistors can reduce silicon area, thereby obtaining cost and size advantages compared to larger-sized row decoders. Reducing the number of transistors can also reduce leakage power and dynamic power, thereby obtaining power saving advantages compared to larger-sized row decoders.

[0033] Another advantage may include using a reset signal that defaults to zero. Such a reset signal may prevent power loss by having the reset signal at zero (lower voltage) for a longer time than at one (higher voltage).

[0034] Figure 1 1 is a simplified diagram illustrating an exemplary memory device 100 according to one embodiment. The memory device 100 includes two memory cores 101, 102. The memory cores 101, 102 include a plurality of memory bit cells arranged in rows (words) and columns (bits). The scope of the embodiments is not limited to any size of the memory cores 101, 102, as any appropriately sized memory cores may be modified according to the principles described herein.

[0035] The memory device 100 also includes global input outputs (GIOs) 121, 122. The global input outputs 121, 122 provide data paths into and out of the memory device 100 for both read and write operations. In this example, each of the memory cores 101, 102 is shown as having 32 input data paths and 32 output data paths, but the scope of the embodiment may include multiple data paths that are appropriately scaled.

[0036] The global block controller (GBC) 120 receives control instructions and addresses, pre-decodes those addresses, and controls the array of row decoders 110 to access specific word lines within the memory cores 101, 102 for read and write access. In the example shown, addr_m0 and addr_m1 are both address signals indexed by the specific core (m0 or m1) to which they apply. In this example, each address signal is 12 bits, but the scope of implementation can include any number of address bits. Signal clk is the master clock of the memory device 100. Signals cs_n_m0 and cs_n_m1 are used as core select signals and determine whether the corresponding core 101, 102 is to read from or write to it or not to work at all.

[0037] The row decoder group 110 includes a plurality of individual row decoders that are selected by a pre-decoded signal (not shown) output from the GBC 120. Various embodiments include a row decoder that includes an SR latch for increased stability, as described in more detail below. In an embodiment herein, the memory device 100 includes a time-shared memory architecture in which cores 101, 102 are read from or written to during the same cycle of the clock signal clk. As described below with respect to Figure 7 Explained in more detail, row decoder group 110 includes a plurality of selectable row decoders, wherein a word line having a first index may be selected within core 101 , and a word line having a second (same or different) index may be selected within core 102 .

[0038] Reference now Figure 2 , Figure 2 is a simplified diagram of a single row decoder 200 according to one embodiment. The embodiment row decoder 200 may be included in Figure 1 In other words, row decoder 200 is an example of a row decoder that can be implemented as one row decoder among many row decoders within row decoder group 110 to select from a plurality of word lines in both cores 101 and 102.

[0039] The row decoder 200 includes two SR latches 220, 221. The SR latches 220, 221 are coupled to a NOR gate 201, which outputs a digital 1 when the pre-decoded signals ra, rb, rc are all zero. The pre-decoded signals are explained in more detail below and are used to select and turn on the row decoder 200 so that the word line w1_m0 can be turned on. <0> and w1_m1 <0> Any one or both of for read or write operation. In this embodiment, the pre-decoded signal is active low, so when all three pre-decoded signals ra, rb, rc are digital 0, the row decoder 200 is selected.

[0040] The following embodiment looks at SR latch 220, which corresponds to a single word line within core 101. It should be understood that SR latch 221 corresponding to a single word line within core 102 is constructed in the same manner, operates in the same manner, and can be independently selected using its own set and reset signals. SR latch 220 in this embodiment is implemented using eight transistors, which is half of a similarly implemented SR latch composed of cross-coupled NOR gates. SR latch 220 presents a digital 0 output in response to a reset signal (rst_n_m0) and a digital 0 output in response to a set signal (clkd_m0). <0> ) presents a digital 1 output, and in this example uses the set-reset functionality to turn word line w1_m0 on and off <0> .

[0041] If all inputs (pre-decoded signals ra, rb, rc) are zero, then NOR gate 201 outputs a digital 1. Otherwise, the output or NOR gate 201 is a digital 0. When all inputs are zero, transistors 217 and 218, which are gate-coupled to NOR gate 201, receive a digital 1 at their gates. Transistor 218 is a negative channel metal oxide semiconductor (NMOS) device, and it is turned on. Transistor 217 is a positive channel metal oxide semiconductor (PMOS) device, and it is turned off. Both transistors 217 and 218 are source-coupled or drain-coupled to the input of inverter 215.

[0042] In this embodiment, transistor 210 is a PMOS device used as a pull-up transistor. Transistor 210 is gate-coupled to a reset signal rst_n_m0, which is an active low reset signal. Thus, when the reset signal is low, transistor 210 turns on and applies the power rail voltage to the input of inverter 215. When receiving a high voltage, inverter 215 turns word line w1_m0 on. <0> Off. Off is the default state when a word line is not reading or writing a value in the memory core 101.

[0043] A read or write operation is initiated by bringing the reset signal high, which turns transistor 210 off so that a low voltage or digital zero can be applied to the input of inverter 215. Signal clkd_m0 <0> is used as a set signal, and it can be pulsed to cause a low voltage to appear at the input of inverter 215 by turning on NMOS device 213 and turning off PMOS device 216. In addition, when the reset signal is high, it turns on transistor 212, which couples pull-down transistor 213 to ground. Once the word line is turned on, its value is applied to the gates of transistors 211 and 214. The digital 1 value of the word line turns transistor 214 off and turns on transistor 211, which acts as a pull-down transistor to maintain a low voltage at the input of inverter 215. The word line can be turned off by changing the value of the reset signal back to digital 0, thereby turning on transistor 210 and turning off transistor 212.

[0044] A read or write operation from the perspective of SR latches 220 and 221 is Figure 3 The timing diagram of Figure 3 , times T1-T13 are provided to illustrate signal transitions. The pre-decoded signals ra, rb, rc start high and then go low at time T1 to select the row decoder 200 by causing the NOR gate 201 to output a digital 1. The reset signals rst_n_m0 and rst_n_m1 both start off low, and the reset signal (rst_n_m0) corresponding to the memory core 101 goes high for the first time at time T2, decoupling the input of the inverter 215 from the power rail by turning off the transistor 210. Thereafter, the set signal clkd_m0 is pulsed at time T3, turning on the transistor 213 and coupling the input of the inverter 215 to ground, causing the word line w1_m0 in the memory core 101 to be turned on. <0> The transistor 211 is turned on at time T4. The gate of the transistor 211 is coupled to the word line, and even the set signal clkd_m0 is removed at time T6. <0> The word line is then kept in the on state until the reset signal rst_n_m0 is changed at time T10.

[0045] In the same clock cycle of clk, the reset signal rst_n_m1 corresponding to the memory core 102 goes high at time T5, and the set signal clkd_m1 is pulsed from time T7 to time T9, thereby causing the word line w1_m1 in the memory core 102 to be high. <0> Goes high at time T8. Turns on word line w1_m1 corresponding to memory core 102 and SR latch 221 <0> Similar to the above given conductive word line w1_m0 <0> Specifically, SR latch 221 has the same structure as SR latch 220 , and components corresponding to 210 - 218 are turned on or off in the same manner as at SR latch 221 .

[0046] At this time, word line w1_m0 <0> and w1_m1 <0> Both SR latches 220 and 221 are turned on, thereby allowing the bit cells to be read or written in both memory cores 101 and 102. Before the end of the clock cycle, both SR latches 220 and 221 are reset to enable word line w1_m0 <0> and w1_m1 <0> SR latches 220 and 221 are reset by changing the values ​​of reset signals rst_n_m0 and rst_n_m1 from 1 back to 0 at times T10 and T12. Figure 2 , when the reset signal returns to zero, this turns transistor 210 on and turns transistor 212 off. <0> and w1_m1 <0> Both are turned off at time T11 and T13 respectively.

[0047] Figure 3 The example of is a simplified example, in which the SR latches 220, 221 are set and reset in the same clock cycle, assuming that a read or write operation is performed at the corresponding word line index in the memory core 101 and the memory core 102. However, various implementations allow the memory cores 101, 102 to be addressed independently, thereby selecting word lines of different indices (and therefore row decoders of different indices) in the same clock cycle. This is referred to below Figure 7 Explain in more detail.

[0048] Go to Figure 4 , which is a diagram of an example GBC 120 according to one implementation. In this example, the GBC 120 receives address signals addr_m0 and addr_m1 for each of the memory cores 101, 102, respectively. In this embodiment, the address signals are shown as both including nine bits, but the scope of implementations may include any suitable number of address bits to implement an addressing scheme depending on the number of bit cells and word lines of a given memory core.

[0049] Each of the memory cores 101, 102 can be individually selected and multiplexed by the multiplexer 401. For a given address signal that is multiplexed, it is received by the address pre-decoder 402, which converts the address signal into a set of pre-decoded signals, which are used to turn on specific SR latches corresponding to specific word lines in the corresponding memory core. In other words, the pre-decoding converts the address signal from the address domain used by the CPU or GPU into an identifiable word line in the memory core. For example, ra, rb, rc are fanned out to multiple different NOR gates, such as Figure 2NOR gate 201. In this example, each of the signals ra, rb, rc includes four parallel bits, indexed as <0:3>. As described above, when the three inputs of a given NOR gate are low, it turns on the corresponding (multiple) row decoders. Each of the set signals clkd_m0 and clkd_m1 includes 8 parallel bits, indexed as <0:7>.

[0050] The address predecoder 402 also generates set signals clkd_m0 and clkd_m1. In an example use case, the address signal (addr_m0) of the memory core 101 is first sent by the multiplexer 401 to the address predecoder 402. Then, the address predecoder 402 generates ra, rb, rc signals and the set signal clkd_m0 to turn on a specific word line at the memory core 101. Thereafter, the address signal (addr_m1) for the memory core 102 is sent by the multiplexer 401 to the address predecoder 402, and the address predecoder 402 generates new ra, rb, rc signals and the set signal clkd_m1 to turn on a specific word line at the memory core 102. This process can be repeated every time there is a read or write operation, possibly even at every clock cycle.

[0051] Although not in Figure 4 As shown in FIG. 1 , GBC 120 may also include logic and circuitry to generate any appropriate signals to control the read and write operations of cores 101, 102. For example, GBC 120 may also include logic and circuitry to generate the various reset signals described herein.

[0052] Figure 5 4 is a diagram of an example address predecoder 402 according to one embodiment. In this example, the address predecoder 402 includes four separate predecoders 501-504. A given address is converted from a 9-bit address signal into 4 ra bits, 4 rb bits, 4 rc bits, and 8 group (clkd) bits. However, the scope of implementation is not limited to any specific number of predecode bits or address bits. In one embodiment, the predecoders 501-504 include hardware logic to provide faster operation than what is expected from software logic.

[0053] Figure 6 is a diagram of an example set 600 of row decoders according to one embodiment. Looking first at row decoder 610, it complies with the above description of Figure 2The described architecture, the SR latches are each configured using eight transistors. Row decoder 620 is substantially similar to row decoder 610, but omits transistors 601, 602 and instead couples to cm_rst_m0 and cm_rst_m1 in common. The omission of transistors 601, 602 allows for space savings compared to implementations that otherwise include transistors 601, 602.

[0054] Row decoder 630 is a combination of six different row decoders with indexes {2:7}, while row decoder 610 includes index 0 and row decoder 620 includes index 1. For ease of illustration, six different row decoders are represented by row decoder 630, and it should be understood that when drawn, each subsequent row decoder with a subsequent index will be arranged to move in the vertical direction to have a total of eight row decoders. In this example, a total of eight row decoders 610-630 share the same ra, rb, rc space so that when the group of ra, rb, rc is all zero, they are all turned on by the common NOR gate 603. In this group of a total of eight row decoders, individual word lines can be indexed to memory core 101 (m0) or memory core 102 (m1) and sub-index The corresponding set signal clkd is used to turn on or off a single word line, where Having a value in the range of {0:7}.

[0055] continue Figure 6 , which illustrates only a portion of a row decoder group, such as Figure 1 A row decoder group 110 may have as many row decoders as word lines. Thus, for example, if a row decoder group supports 512 word lines, then according to one embodiment, it would include 512 separate row decoders. Additional row decoders (not shown) may be located using different ra, rb, rc spaces. For example, Figure 6 The ra, rb, rc space corresponds to ra <0> ,rb <0> rc <0> , and the next ra, rb, rc can correspond to ra <0> , rb <0> rc <1> and on and until ra <3> ,rb <3> rc <3> In other words, there can be as many RA, RB, and RC spaces as there are bit arrangements for RA, RB, and RC signals. Figures 4 to 5 The pre-decoded signals described are used to access individual word lines.

[0056] Figure 7 According to one embodiment, the use Figure 6 An example timing diagram of the row decoder group 600 in FIG. Figure 7 The action is usually applicable to Figure 1 The memory device 100 is shown. Figure 7 In an embodiment of the present invention, two different row decoders are used to turn on two different word lines with different indexes for the first memory core and the second memory core. Figure 7 Times T1-T16 are labeled to illustrate signal transitions.

[0057] Figure 7 The operation starts by accessing the word line w1_m0 in the first memory core m0 (eg, memory core 101). <0> . Word line w1_m0 <0> exist Figure 6 6 is shown as coupled to the row decoder 610. The reset signal (rst_n_m0) corresponding to the first memory core changes from digital 0 to digital 1 at time T1, and then the set signal (clkd_m0) corresponding to the row decoder 610 and the first memory core is reset. <0> ) is pulse modulated from time T2 to time T4. During this period, the signal ra <0> , rb <0> , rc <0> are all 0, and they are all set to 1 at time T5 after the set signal pulse until time T13 after the reset signal changes back to 0 at time T11.

[0058] The set signal is pulse modulated so that word line w1_m0 <0> It turns on at time T3 and is held on by being gate coupled to the pull-down transistor, as described above with respect to Figure 2 In the same clock cycle, the word line in the second memory core, such as memory core 102, is also turned on. Different bits of ra, rb, rc and a set signal with an appropriate index are used to locate the second memory core (w1_m1 <511> ) in the word line. The word line in the second memory core is not Figure 6 , but it should be understood that the memory structure can be scaled. Specifically, in this example, the pre-decoded signal ra is used at time T6 and T8. <3> ,rb <3> rc <3> and clkd_m1 <7> Similar to the action of the first word line, at time T7 the appropriate reset signal (rst_n_m1) is changed from digital 0 to digital 1, and then the appropriate set signal (clkd_m1) is <7> ) from time T8 to time T10, which makes word line w1_m1 <511> The first memory core is turned on at time T9. During this period, the word line in the first memory core remains on until time T12. The word line in the second memory core remains on until time T16. After these read / write actions in the first memory core and the second memory core, the two reset signals are then changed from digital 1 back to digital 0 at times T11 and T14 (respectively), turning off the two word lines. The pre-decoded signals ra, rb, rc of the first core and the second core are transitioned at times T13 and T15, respectively.

[0059] As mentioned above about Figure 1 As discussed, a given row decoder includes two different SR latches, each configured using eight different transistors. However, the scope of the embodiments is not limited to any particular arrangement of transistors as shown in FIG. 8 .

[0060] Fig. 8A 8 is a diagram of an example row decoder 800 adapted according to one embodiment. The row decoder 800 is configured using an SR latch having multiple sets of cross-coupled NOR gates 801, 802. Looking at the cross-coupled NOR gates 801, a first NOR gate 820 receives a reset signal (rst_m0), while a second NOR gate 821 receives a set signal (clkd_m0). <0> ) derived signal. Specifically, the reset signal is received by NAND gate 805, where the other input of NAND gate 805 is the output of NOR gate 803. The operation of NOR gate 803 is similar to Figure 6 The output of NAND gate 805 is applied to the input of inverter 810, and the output of inverter 810 is applied as input to NOR gate 821.

[0061] Now let's look at the cross-coupled NOR gate 802, which is similar to the cross-coupled NOR gate 801. The first NOR gate 822 receives the reset signal (rst_m1), and the second NOR gate 823 receives the slave set signal (clkd_m1). <0> ) derived signal. In this example, the reset signal is received by NAND gate 806, where the other input of NAND gate 806 is the output of NOR gate 803. The output of NAND gate 806 is applied to the input of inverter 812, and the output of inverter 812 is applied as input to NOR gate 823.

[0062] Figure 8B A timing diagram 830 is included, which illustrates Fig. 8A How can an embodiment of the invention operate to select word line w1_m0 in a single clock cycle? <0> and w1_m1 <0> Of course, it should be understood that row decoder 800 may be one of many row decoders that are replicated within a set of row decoders to access two different memory cores. For example, row decoder 800 may be replicated, as described above with respect to Figure 6 and 7 In this example, word lines with the same index are selected in timing diagram 830, and in the example of replica row decoder 800, word lines with different indexes may be selected in the same clock cycle, for example, Figure 7 In the example.

[0063] The pre-decoded signal <0> , rb <0> , rc <0> After time T1, both are low, which causes the row decoder 800 to be selected. In addition, each of the word lines starts in an off state at the beginning of the clock cycle, which is caused by the input of each of the inverters 825, 826 being high. The reset signal remains low until the word line is to be reset at the end of the clock cycle.

[0064] When the setting signal (clkd_m0 <0> ) is pulse modulated from time T2 to T4, which makes word line w1_m0 <0> It turns on at time T3 because the input of inverter 825 is low. <0> The on state of word line w1_m0 is maintained by the SR latch having the cross-coupled NOR gate 801 until time T9. <0> During the conduction interval, another set signal clkd_m1 <0> The word line w1_m1 is pulsed from time T5 to time T7, which causes the word line w1_m1 to be high by providing a low signal to the input of inverter 826. <0> At time T6, word line w1_m0 is turned on. From time T6 to time T9, word line w1_m0 <0> and w1_m1 <0> are in the on state.

[0065] Towards the end of the clock cycle, rst_m0 is pulsed from time T8 to time T10, causing word line w1_m0 to <0> The word line w1_m1 returns to the off state at time T9. The reset signal rst_m1 is then pulse-modulated from time T11 to time T13, so that the word line w1_m1 also returns to the off state at time T12.

[0066] Various embodiments may include one or more advantages over other systems. For example, when a word line is in an off state or in an on state, Figure 2 and Fig. 8A The row decoders shown in are all stable. Figure 2 An embodiment of the invention has a transistor arrangement with complementary pull-up and pull-down portions that do not share charge, thereby avoiding the risk of one transistor over-powering another transistor during the off state, possibly inadvertently selecting a word line. In addition, Figure 2 The configuration shown in uses the voltage on the word line to hold the SR latch when the word line is turned on, thereby providing stability during the on-state of the word line.

[0067] In addition, although Figure 2 and 8A The implementation methods are all stable, but due to the reduction of the number of transistors in the SR latch, Figure 2 The implementation method can be compared to Fig. 8A The implementation is more efficient. The reduced number of transistors may provide the benefit of reducing the amount of silicon area occupied by the SR latch as well as reducing leakage and dynamic power compared to implementations using a large number of transistors.

[0068] Various implementations described herein may be applicable to a system on a chip (SOC). An embodiment of a SOC includes a semiconductor chip having a plurality of processing devices therein, including a graphics processing unit (GPU), a central processing unit (CPU), a modem unit, a camera unit, etc. In some embodiments, the SOC may be included in a chip package, mounted on a printed circuit board, and arranged in a portable device (e.g., a smart phone or a tablet computer). However, the scope of the implementation is not limited to chips implemented in a tablet computer or a smart phone, as other applications are possible.

[0069] Fig. 9 900 is a diagram of an example SOC 900 according to one embodiment. In this example, the SOC 900 is implemented on a semiconductor die, and it includes multiple system components 910-990. Specifically, in this example, the SOC 900 includes a CPU 910, which is a multi-core general-purpose processor with four processor cores, core 0-core 3. Of course, the scope of the implementation is not limited to any particular number of cores, as it can include two cores, eight cores, or any other suitable number of cores in the CPU 910. The SOC 900 also includes other system components, such as a first digital signal processor (DSP) 940, a second DSP 950, a modem 930, a GPU 920, a video subsystem 960, a wireless local area network (WLAN) transceiver 970, and a video front end (VFE) subsystem 980.

[0070] SOC 900 also includes a RAM storage unit 990. In this example, RAM storage unit 990 may include corresponding to the above Figure 1 The implementations described herein may be applicable to any RAM storage unit or read-only memory (ROM) storage unit. For example, in this SOC embodiment, a cache RAM (not shown) within CPU cores 0-3 may be applicable to include the row decoders described herein. In addition, the example SOC may include a separate RAM memory unit 990 or ROM component and / or a RAM or ROM component in other processing units such as GPU 920, modem unit 130, DSP 140, 150, etc. These RAM or ROM units may also be applicable to use the row decoders described herein.

[0071] As described above, the SOC 900 may include a CPU 910 having a plurality of cores 0-3, and one or more of these cores may execute computer readable code that provides the functionality of an operating system core. In addition, the example operating system core may include memory management software that may perform read and write operations on various memory units, wherein these memory units may include row decoders as described herein. Therefore, the above reference to Figure 1-8B and Fig.10 The described principles may be implemented in SOC 900, more specifically, Figure 1-8B and Fig.10 The circuits and methods shown in can be implemented in SOC 900 or other chips to provide memory read and write functions.

[0072] Fig.10 A flow chart of an example method 1000 of operating one or more row decoders is shown. In one example, the method 1000 comprises Figure 1 , Figure 2 , Figure 4 and Figure 6-7 In some embodiments, a memory management unit inside or outside the CPU or GPU includes a processing circuit system that executes computer-readable instructions to control the GBC (e.g., Figure 1 and Figure 4 GBC 120) performs a read or write operation on a RAM memory cell or a ROM memory cell. For example, logic in a CPU or GPU can send an address and control signal to the GBC to cause the GBC to read or write data.

[0073] At act 1010, the method includes driving a first word line in a first core of memory bit cells. For example, the first word line in the first core of memory bit cells may include a core of the memory bit cell (eg, Figure 1 Action 1010 also includes setting a first SR latch. Figure 3 An example is shown in FIG. 1 , where the set signal clkd_m0 <0> is pulse modulated so that word line w1_m0 <0> On. Figure 7 Another example is shown in FIG. 1 , in which the set signal clkd_m0 <0> is pulse modulated so that word line w1_m0 <0> Conductivity.

[0074] At act 1020, the voltage of the word line is maintained in an on state. For example, the voltage of the word line can be maintained in an on state for the remainder of the read or write operation, or even continue the read or write operation on a time-sharing core of the same memory device. Act 1020 can include applying the voltage of the word line to a transistor in the first SR latch. Figure 2 An example is shown in , where transistor 211 is gate coupled to a word line and is turned on when the word line is at a high voltage, thereby pulling down the input of the inverter.

[0075] At act 1030, the method includes driving a second word line in a second core of memory bit cells. Figure 1 In the example of , it may be a word line with the same or different index as the first word line, and it may be present in other memory cores, such as memory core 102. Action 1030 may also include setting a second SR latch. Figure 3 An example is shown in FIG. 1 , where the set signal clkd_m1 <0> is pulse modulated so that word line w1_m1 <0> Conductivity. Figure 7 Another example is shown in FIG. 5 , where the set signal clkd_m17 is pulse modulated to turn on the word line w1_m1511 . Figure 2 The example shows that word lines with the same index are turned on, while Figure 7 The example shows that word lines with different indexes are turned on.

[0076] At act 1040, the second word line may be held in an on state by applying the voltage of the second word line to the transistor in the second SR latch. Act 1040 is similar to act 1020, but occurs at the second word line and the second SR latch.

[0077] At action 1050, the first word line is turned off by changing the first reset signal of the first SR latch. Figure 2 In the embodiment of , the reset signal rst_m0 is an active low signal provided to the gate of the PMOS transistor. In this case, action 1050 can include changing the reset signal from high to low, thereby turning on the pull-up transistor 210. Of course, while this example discusses the use of PMOS transistors and active low signals, other implementations can use active high signals and NMOS transistors.

[0078] Action 1060 is similar to action 1050. The second word line is turned off by changing the second reset signal of the second SR latch. Figure 2 In an embodiment of the present invention, the active low reset signal changes from a high value to a low value to turn on the PMOS pull-down transistor. Figure 7 In the embodiment of the present invention, the reset signal rst_n_m1 changes from a high value to a low value to turn on the PMOS pull-down transistor.

[0079] Looking at actions 1050 and 1060, they together turn off two different word lines in two different memory cores driven in the same clock cycle. In other words, the two different word lines are turned on in overlapping cycles and then turned off (i.e., the word line in the first core is turned on first, and the word line and the second core are turned on while the word line in the first core is still turned on, and the word line in the first core is turned off first while the word line in the second core is still turned on).

[0080] The scope of implementation is not limited to Fig.10 Specific actions shown. In contrast, other implementations may add, omit, rearrange, or modify one or more actions. In one example, an implementation may repeat actions 1010-1060 in each clock cycle or at least in subsequent non-continuous cycles. Actions 1010-1060 may be performed multiple times as appropriate to read or write the requested data. When a word line is driven, it allows a data byte to be read from a memory, where the data byte is written to or read from a physical location in a memory device corresponding to a logical location known to a CPU, GPU, or other processing device. Multiple clock cycles may be used to read or write multiple bytes of data, where the clock cycle used is adapted to the size of the read or write request.

[0081] As those skilled in the art will now appreciate and depending on the particular application at hand, many modifications, substitutions and variations may be made in the materials, apparatus, configurations and methods of use of the apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the scope of the specific implementations shown and described herein, as they are merely by way of some examples thereof, but should be fully commensurate with the scope of the claims appended hereto and their functional equivalents.

Claims

1. A memory device, comprising: a first core of a memory bit cell; a second core of a memory bit cell; a pre-decoding circuit system, shared by the first core and the second core; as well as a row decoder coupled to the pre-decoding circuitry, the first core, and the second core, the row decoder comprising a first set-reset SR latch and a second SR latch, the first SR latch being coupled to a first word line of the first core via a first inverter, the second SR latch being coupled to a second word line of the second core via a second inverter, Wherein the first SR latch comprises: a first transistor coupled to a power rail and to an input of the first inverter via a second transistor, the gate of the first transistor being coupled to the first word line, and A third transistor is coupled to the input of the first inverter and to ground via a fourth transistor, a gate of the third transistor being coupled to the first word line.

2. The memory device of claim 1, wherein: The third transistor is drain coupled to the input of the first inverter.

3. The memory device of claim 2, wherein: A fifth transistor in the second SR latch is gate coupled to the second word line and drain coupled to an input of the second inverter via a sixth transistor. 4 . The memory device of claim 1 , wherein the third transistor comprises a negative channel metal oxide semiconductor (NMOS) device.

5. The memory device of claim 1 , wherein the first SR latch comprises: A first pull-up transistor is coupled to the first word line through the first inverter, wherein the first pull-up transistor is gate-coupled to a first reset signal. 6 . The memory device of claim 5 , wherein the first pull-up transistor comprises a positive-channel metal oxide semiconductor (PMOS) device.

7. The memory device of claim 1 , wherein the first SR latch comprises: The first pull-down transistor has a gate coupled to the first set signal. 8 . The memory device of claim 7 , wherein the first pull-down transistor comprises a negative channel metal oxide semiconductor (NMOS) device.

9. The memory device of claim 1, wherein the first transistor comprises a positive channel metal oxide semiconductor (PMOS) device.

10. The memory device of claim 1, wherein the first SR latch comprises: A first positive channel metal oxide semiconductor (PMOS) transistor is gate-coupled to the output of the NOR gate and further coupled to the first word line through the first inverter.

11. The memory device of claim 1 , wherein the first SR latch comprises: A first negative channel metal oxide semiconductor (NMOS) transistor is gate-coupled to the output of the NOR gate and further coupled to the first word line through the first inverter and further coupled to the third transistor by a drain.

12. The memory device of claim 1, wherein the second transistor comprises: A first positive channel metal oxide semiconductor (PMOS) transistor is gate-coupled to a first set signal and further coupled to the first word line through the first inverter and source-coupled to the first transistor.

13. The memory device of claim 1 , wherein the fourth transistor comprises: A first negative channel metal oxide semiconductor (NMOS) transistor is gate-coupled to the first reset signal and further coupled to ground and drain-coupled to the third transistor.

14. The memory device of claim 1, wherein the first SR latch comprises a first plurality of cross-coupled NOR gates.

15. A method performed in a time-sharing memory architecture, the method comprising: driving a first word line in a first core of memory bit cells, including setting a first set-reset SR latch using a first set signal; maintaining a voltage of the first word line in a conducting state, comprising applying the voltage of the first word line to a gate of a first transistor in the first SR latch, wherein the first transistor is drain coupled to an input of a first inverter, and wherein the first SR latch is coupled to the first word line through the first inverter; driving a second word line in a second core of memory bit cells, including setting a second SR latch using a second set signal; maintaining the voltage of the second word line in the on-state, comprising applying the voltage of the second word line to a gate of a third transistor in the second SR latch, wherein the third transistor is drain coupled to an input of a second inverter, and wherein the second SR latch is coupled to the second word line through the second inverter; as well as After driving the first word line, the first word line is turned off by changing a first reset signal of the first SR latch.

16. The method according to claim 15, further comprising: After driving the second word line, the second word line is turned off by changing a second reset signal of a second SR latch.

17. The method according to claim 15, further comprising: After the first word line reaches the on state, the first set signal is removed.

18. The method according to claim 15, further comprising: After the second word line reaches the on state, the second set signal is removed. The method of claim 15 , wherein the first reset signal comprises an active low signal.

20. A system on chip (SOC), comprising: A time-sharing memory device having a first core of memory bit cells and a second core of memory bit cells; means for converting address bits into a pre-decoded signal; as well as means for receiving the pre-decoded signal and for accessing data in the time-sharing memory device according to the pre-decoded signal, the receiving means comprising a row decoder array, each row decoder in the array having a first set-reset SR latch and a second SR latch, the first SR latch being coupled to the first core, the second SR latch being coupled to the second core, wherein a first row decoder in the array comprises: an inverter coupled to a word line, and wherein a corresponding first SR latch comprises: a first transistor coupled to the power rail and to the input of the inverter via a second transistor, the gate of the first transistor being coupled to the word line, and A third transistor is coupled to the input of the inverter and to ground via a fourth transistor, the gate of the third transistor being coupled to the word line.

21. The SOC of claim 20, wherein the receiving component comprises a plurality of NOR gates, each of the plurality of NOR gates being disposed at a corresponding SR latch input and coupled to the converting component.

22. The SOC of claim 20, wherein the first row decoder in the array comprises: a first pull-up transistor and the third transistor, the first pull-up transistor being coupled to the input of the inverter and the power rail.

23. The SOC of claim 20, wherein the first row decoder in the array comprises an arrangement of cross-coupled NOR gates.

24. A system on chip (SOC), comprising: a first core of a memory bit cell; a second core of a memory bit cell; as well as a plurality of row decoders shared by the first core and the second core, wherein a first row decoder of the plurality of row decoders comprises a first set-reset SR latch and a second SR latch, the first SR latch being coupled to a first word line of the first core via a first inverter, the second SR latch being coupled to a second word line of the second core via a second inverter, Wherein the first SR latch comprises: a first transistor coupled to a power rail and to an input of the first inverter via a second transistor, the gate of the first transistor being coupled to the first word line, and A third transistor is coupled to the input of the first inverter and to ground via a fourth transistor, a gate of the third transistor being coupled to the first word line.

25. The SOC of claim 24, wherein the first row decoder comprises: a first pull-up transistor coupled to the input of the first inverter and to a power rail, and wherein a second row decoder of the plurality of row decoders comprises a second pull-up transistor coupled to an input of the second inverter and the power rail and a fifth transistor coupled to the power rail and to the input of the second inverter via a sixth transistor, a gate of the fifth transistor coupled to the second word line.

26. The SOC of claim 25, wherein the third transistor comprises a negative channel metal oxide semiconductor (NMOS) device that couples the input of the first inverter to ground.

27. The SOC of claim 25, wherein the first pull-up transistor is gate coupled to a first reset signal.

28. The SOC of claim 27, wherein the first pull-up transistor comprises a positive channel metal oxide semiconductor (PMOS) device.

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