An on-chip self-test circuit architecture and method applied to a phased array radio frequency chip

Abstract

This invention discloses an on-chip self-test circuit architecture and on-chip self-test method for phased array RF chips. It includes a test signal source generation circuit for generating a signal to be injected into the main signal chain of the phased array RF chip and providing an input signal to the local oscillator circuit; a local oscillator circuit for generating a quadrature local oscillator for use with the input signal provided by the test signal source generation circuit; and a signal processing circuit for adjusting the gain of the signal from the main signal chain of the phased array RF chip, and performing quadrature mixing of the gain-adjusted signal and the quadrature local oscillator to obtain a processed signal. Gain and phase information of the main signal chain of the phased array RF chip are obtained from the processed signal. Based on the gain and phase information of the main signal chain of the phased array RF chip, the gain switching performance, phase shifter performance, channel mismatch performance, and absolute gain performance of the main signal chain of the phased array RF chip are tested.

Description

Technical Field

[0001] This invention belongs to the field of circuit design technology. It relates to an on-chip self-test circuit architecture and on-chip self-test method for phased array radio frequency chips. Background Technology

[0002] A phased array (PAA) RF chip is a type of RF chip that connects to an array of antennas. By controlling the phase and power of the RF channels connected to each antenna in the array, it can quickly control the direction and intensity of signals, thereby achieving rapid scanning and efficient data transmission.

[0003] Testing phased array RF chips is a core step in their mass production. Traditional testing methods utilize automated test benches and RF testing instruments, which incurs extremely high hardware costs, significantly increasing the mass production cost of phased array RF chips. Furthermore, because high-frequency pin testing is highly sensitive to stress during crimping, it is difficult to achieve the required testing accuracy. Summary of the Invention

[0004] Purpose of the invention: To address the problems of high hardware cost and low testing accuracy in existing testing schemes, this invention proposes an on-chip self-test circuit architecture and on-chip self-test method for phased array RF chips.

[0005] Technical solution: An on-chip self-test circuit architecture for a phased array RF chip, comprising: an on-chip self-test circuit and a signal coupling network; the on-chip self-test circuit injects a signal Signal_In into the main signal chain of the phased array RF chip through the signal coupling network, and the on-chip self-test circuit receives a signal Signal_Out from the main signal chain of the phased array RF chip through the signal coupling network;

[0006] The on-chip self-test circuit includes:

[0007] The test signal source generation circuit is used to generate the signal Signal_In, which is injected into the main signal chain of the phased array RF chip, and to provide the input signal for the local oscillator circuit.

[0008] The local oscillator circuit is used to generate an orthogonal local oscillator for the signal processing circuit based on the input signal provided by the test signal source generation circuit.

[0009] The signal processing circuit is used to adjust the gain of the signal Signal_Out from the main signal chain of the phased array RF chip, and to perform quadrature mixing between the gain-adjusted signal Signal_Out and the quadrature local oscillator to obtain the processed signal. The processed signal contains the gain information and phase information of the main signal chain of the phased array RF chip.

[0010] Furthermore, the test signal source generation circuit consists of a signal source and a frequency multiplier connected in sequence.

[0011] Furthermore, the local oscillator circuit is composed of a phase shifter and a quadrature generation circuit connected in sequence.

[0012] Furthermore, the signal processing circuit consists of a variable gain amplifier and a quadrature mixer connected in sequence. The quadrature mixer receives the quadrature local oscillator from the local oscillator circuit and performs quadrature mixing on the gain-adjusted signal Signal_Out.

[0013] Furthermore, the on-chip self-test circuit also includes a receive link switch network and a transmit link switch network;

[0014] When the main signal chain of the phased array RF chip is in receive mode, the test signal source generation circuit injects the signal Signal_In into the main signal chain of the phased array RF chip through the receive link switch network and the signal coupling network, and the mixer / sampling signal processing circuit receives the signal Signal_Out from the main signal chain of the phased array RF chip through the signal coupling network and the receive link switch network.

[0015] When the main signal chain of the phased array RF chip is in transmit mode, the test signal source generation circuit injects the signal Signal_In into the main signal chain of the phased array RF chip through the transmit link switch network and the signal coupling network. The mixer / sampling signal processing circuit receives the signal Signal_Out from the main signal chain of the phased array RF chip through the signal coupling network and the transmit link switch network.

[0016] This invention also discloses an on-chip self-test method for a phased array radio frequency chip, comprising the following steps:

[0017] Step 1: Inject the signal Signal_In into the main signal chain of the phased array RF chip;

[0018] Step 2: Obtain the Signal_Out signal from the main signal chain of the phased array RF chip;

[0019] Step 3: Perform gain adjustment and quadrature mixing on the Signal_Out signal sequentially to obtain the processed signal, which contains the gain information and phase information of the main signal chain of the phased array RF chip;

[0020] Step 4: Obtain the gain and phase information of the main signal chain of the phased array RF chip from the processed signal. Based on the gain and phase information of the main signal chain of the phased array RF chip, complete the tests on the gain switching performance, phase shifter performance, channel mismatch performance, and absolute gain performance of the main signal chain of the phased array RF chip.

[0021] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0022] (1) The on-chip self-test circuit architecture of the present invention can realize the testing of phased array RF chips without the need for external test equipment, which has the advantage of low cost;

[0023] (2) The on-chip self-test circuit architecture of the present invention can be built into the phased array RF chip, so the phased array RF chip of the present invention has the advantages of easy miniaturization and easy integration.

[0024] (3) The on-chip self-test circuit architecture of the present invention can complete the test based on the test resources inside the phased array RF chip, which can effectively avoid the problem of high frequency pin test being sensitive to force during crimping. Therefore, the phased array RF chip of the present invention has high test accuracy. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of an on-chip self-test circuit architecture applied to a phased array RF chip;

[0026] Figure 2 This is a block diagram of the on-chip self-test circuit architecture of the present invention;

[0027] Figure 3 This is a block diagram of the switching network when the main signal chain of the phased array RF chip is in receive mode and transmit mode; where... Figure 3 (a) is a block diagram of the switching network when the main signal chain of the phased array RF chip is in receive mode. Figure 3 (b) is a block diagram of the switching network when the main signal chain of the phased array RF chip is in transmit mode;

[0028] Figure 4 This is a schematic diagram illustrating the basic principle of the signal processing circuit of the present invention. Figure 4 (a) in the diagram is a schematic diagram of the signal input and signal output of the signal processing circuit. Figure 4 In the diagram, (b) represents the polar coordinates of the output signal of the signal processing circuit. Detailed Implementation

[0029] The technical solution of the present invention will now be further described in conjunction with the accompanying drawings and embodiments.

[0030] Example 1:

[0031] like Figure 1As shown, this embodiment discloses an on-chip self-test circuit architecture for a phased array RF chip, which mainly includes an on-chip self-test circuit 1 and a signal coupling network 2. Since the on-chip self-test circuit 1 and the signal coupling network 2 are implemented inside the chip, they can be referred to as internal chip test resources. Therefore, this embodiment proposes an on-chip self-test circuit architecture that completes testing based on the internal test resources of the phased array RF chip. When the on-chip self-test circuit architecture of this embodiment is used to test the phased array RF chip, the on-chip self-test circuit 1 injects the signal Signal_In into the main signal chain 3 of the phased array RF chip through the signal coupling network 2, and the on-chip self-test circuit 1 receives the signal Signal_Out from the main signal chain 3 of the phased array RF chip through the signal coupling network 2. The on-chip self-test circuit 1 performs signal processing on the injected signal Signal_In and signal Signal_Out, ultimately realizing the RF performance test of the main signal chain 3 of the phased array chip.

[0032] Specifically, such as Figure 2 As shown, the on-chip self-test circuit 1 of this embodiment includes a test signal source generation circuit 11, a local oscillator circuit 12, a switching network 13, and a signal processing circuit 14.

[0033] The test signal source generation circuit 11 is used to generate the signal Signal_In, which is injected into the main signal chain of the phased array RF chip, and to provide an input signal for the local oscillator circuit. The test signal source generation circuit in this embodiment includes, but is not limited to, the following: Figure 2 The structure shown may include a signal source and a frequency multiplier. The signal source can be implemented using an on-chip clock source, or a pin can be provided for external signal source input. The purpose of using a frequency multiplier is to reduce the frequency requirements of the clock source / external signal source. For example, when applied to the 5G millimeter wave 24.25-29.5GHz band, the test signal source generation circuit of this embodiment can use a frequency multiplier circuit, in which case the signal source requirement is 12.125GHz-14.75GHz; when applied to the automotive radar 76-79GHz band, the test signal source generation circuit of this embodiment can use a frequency multiplier circuit, in which case the signal source requirement is 19-19.75GHz.

[0034] The local oscillator circuit 12 is used to generate a quadrature local oscillator for the signal processing circuit based on the input signal provided by the test signal source generation circuit. The local oscillator circuit in this embodiment includes, but is not limited to, the following: Figure 2 The structure shown may include a phase shifter and a quadrature generation circuit.

[0035] Since the main signal chain of the phased array RF chip has two operating states, receiving mode and transmitting mode, this embodiment uses a switch network 13 to achieve link switching. Specifically, the switch network 13 in this embodiment is implemented by several single-pole double-throw switches, which are used to switch the position of the injected signal Signal_In and the position of the received signal Signal_Out to meet the measurement requirements of the two modes of the main signal chain of the phased array chip. Figure 3 The diagram illustrates the switching network in both the receive and transmit modes of the phased array chip's main signal chain. When the phased array chip's main signal chain is in receive mode, the switching network introduces the signal Signal_In to the input of the receive link and obtains the signal Signal_Out from the output of the receive link. Conversely, when the phased array chip's main signal chain is in transmit mode, the switching network introduces the signal Signal_In to the input of the transmit link and obtains the signal Signal_Out from the output of the transmit link.

[0036] The signal processing circuit 14 is used to adjust the gain of the signal Signal_Out from the main signal chain of the phased array RF chip, perform quadrature mixing between the gain-adjusted Signal_Out and the quadrature local oscillator, and finally convert the signal into a digital signal to obtain the processed signal. This processed signal contains gain and phase information of the main signal chain of the phased array RF chip. The signal processing circuit 14 in this embodiment includes, but is not limited to, the following: Figure 2 The structure shown may include a variable gain amplifier 141, a quadrature mixer 142, and an analog-to-digital converter 143; the input signal is sequentially adjusted for gain, quadrature mixed, and converted into a digital signal. The purpose of using an analog-to-digital converter in this embodiment is to facilitate the processing of digital signals.

[0037] Specifically, when the main signal chain of the phased array RF chip is in receive mode, the test signal source generation circuit injects the signal Signal_In into the main signal chain of the phased array RF chip through a switching network and a signal coupling network, and the signal processing circuit receives the signal Signal_Out from the main signal chain of the phased array RF chip through the signal coupling network and the switching network; when the main signal chain of the phased array RF chip is in transmit mode, the test signal source generation circuit injects the signal Signal_In into the main signal chain of the phased array RF chip through a switching network and a signal coupling network, and the signal processing circuit receives the signal Signal_Out from the main signal chain of the phased array RF chip through the signal coupling network and the switching network.

[0038] Figure 4 The basic principle of the signal processing circuit is illustrated. Assume the signal Signal_Out from the main signal chain of the phased array RF chip is... Among them, Asig The signal amplitude of the main signal chain of the phased array chip. This refers to the signal phase of the main signal chain of the phased array chip. The quadrature local oscillator is: A lo ·cos(ω lo t+θ lo A) lo ·cos(ω lo t+θ lo +90°). Where, ω lo It is the angular frequency of the local oscillator signal, A. lo It is the amplitude of the local oscillator signal, θ lo It is the phase of the local oscillator signal.

[0039] The output of the signal processing circuit is:

[0040]

[0041]

[0042] That is:

[0043]

[0044]

[0045] In the formula, Vout_I represents I-channel output signal, and A mixer Vout_Q represents the total gain of the variable gain amplifier and quadrature mixer, and Vout_Q represents the Q-channel output signal.

[0046] from Figure 4 (b) can yield the gain information of the main signal chain of the phased array chip. and includes phase information of the main signal chain of the phased array chip.

[0047] Equations (3) and (4) represent the I-path and Q-path outputs of the BIST circuit, which can be expressed as follows: Figure 4 The vector signal b in the signal chain, which is output by A from the signal link. sig and Therefore, the gain and phase change information of the signal link can be obtained through the I and Q outputs of the BIST circuit. Thus, information such as the gain / phase difference of the variable gain amplifier, phase shifter, and channels can all be obtained through the BIST circuit. After calibrating the BIST output voltage and the output power of the signal link, the absolute power and gain can be obtained. In other words, during testing, the link gain can be adjusted through the variable gain amplifier, the link phase through the phase shifter, or a specific channel of the phased array chip can be selected to make that channel operational. The gain and phase information of the phased array chip's main signal chain can then be measured using the on-chip self-test circuit. This allows for the determination of the phased array chip's gain switching performance, phase shifter performance, and channel mismatch performance. Under the condition of power calibration of the phased array chip, the on-chip self-test circuit can also measure the absolute power and gain of the phased array chip's main signal chain.

[0048] Example 2:

[0049] This embodiment discloses an on-chip self-test method for a phased array radio frequency chip, including the following steps:

[0050] Step 1: Inject the signal Signal_In into the main signal chain of the phased array RF chip;

[0051] Step 2: Obtain the Signal_Out signal from the main signal chain of the phased array RF chip;

[0052] Step 3: Perform gain adjustment and quadrature mixing on the Signal_Out signal sequentially to obtain the processed signal, which contains the gain information and phase information of the main signal chain of the phased array RF chip;

[0053] Step 4: Obtain the gain and phase information of the main signal chain of the phased array RF chip from the processed signal. Based on the gain and phase information of the main signal chain of the phased array RF chip, complete the tests on the gain switching performance, phase shifter performance, channel mismatch performance, and absolute gain performance of the main signal chain of the phased array RF chip.

Claims

1. An on-chip self-test circuit architecture applied to a phased array radio frequency chip, characterized in that: The chip-on self-test circuit and a signal coupling network; the chip-on self-test circuit injects a signal Signal_In into a main signal chain of the phased array radio frequency chip through the signal coupling network, and the chip-on self-test circuit receives a signal Signal_Out from the main signal chain of the phased array radio frequency chip through the signal coupling network; The chip-on self-test circuit comprises: a test signal source generation circuit for generating the signal Signal_In injected into the main signal chain of the phased array radio frequency chip and providing an input signal for a local oscillator circuit; a local oscillator circuit for generating a quadrature local oscillator provided to a signal processing circuit according to the input signal provided by the test signal source generation circuit; a signal processing circuit for gain adjusting the signal Signal_Out from the main signal chain of the phased array radio frequency chip and quadrature mixing the gain-adjusted signal Signal_Out and the quadrature local oscillator to obtain a processed signal, wherein the processed signal contains gain information and phase information of the main signal chain of the phased array radio frequency chip; The signal processing circuit is composed of a variable gain amplifier and a quadrature mixer connected in sequence, and the quadrature mixer receives the quadrature local oscillator from the local oscillator circuit to quadrature mix the gain-adjusted signal Signal_Out; The chip-on self-test circuit further comprises a receive chain switch network and a transmit chain switch network; When the main signal chain of the phased array radio frequency chip is in a receive mode, the test signal source generation circuit injects the signal Signal_In into the main signal chain of the phased array radio frequency chip through the receive chain switch network and the signal coupling network, and the mixing / sampling signal processing circuit receives the signal Signal_Out from the main signal chain of the phased array radio frequency chip through the signal coupling network and the receive chain switch network; When the main signal chain of the phased array radio frequency chip is in a transmit mode, the test signal source generation circuit injects the signal Signal_In into the main signal chain of the phased array radio frequency chip through the transmit chain switch network and the signal coupling network, and the mixing / sampling signal processing circuit receives the signal Signal_Out from the main signal chain of the phased array radio frequency chip through the signal coupling network and the transmit chain switch network. The test signal source generation circuit is composed of a signal source and a frequency multiplier connected in sequence.

2. The on-chip self-test circuit architecture for phased array RF chips of claim 1, wherein: The local oscillator circuit is composed of a phase shifter and a quadrature generation circuit connected in sequence.

3. The on-chip self-test circuit architecture for phased-array RF chips of claim 1, wherein: Based on the chip-on self-test circuit architecture, the following steps are included:

4. An on-chip self-test method for a phased array radio frequency chip, the method comprising: Step 1: injecting a signal Signal_In into a main signal chain of a phased array radio frequency chip; Step 2: obtaining a signal Signal_Out from the main signal chain of the phased array radio frequency chip; Step 3: gain adjusting and quadrature mixing the signal Signal_Out in sequence to obtain a processed signal, wherein the processed signal contains gain information and phase information of the main signal chain of the phased array radio frequency chip; ​ Step 4: gain information and phase information of the main signal chain of the phased array radio frequency chip are acquired from the processed signal, and the gain switching performance, the phase shifter performance, the channel mismatch performance and the absolute gain performance of the main signal chain of the phased array radio frequency chip are tested according to the gain information and the phase information of the main signal chain of the phased array radio frequency chip; The on-chip self-test circuit architecture is the on-chip self-test circuit architecture applied to the phased array radio frequency chip according to any one of claims 1 to 3.

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