Wafer test platform and detection method thereof

Abstract

A wafer test platform and a detection method thereof, the wafer test platform comprising: a bearing disc; a camera mechanism for calibrating the position of the wafer; a chip angle adjustment mechanism for adjusting the horizontal direction angle of the wafer; a chip position adjustment mechanism for adjusting the horizontal position of the wafer; a probe assembly provided with at least two probes; the probe assembly is used for simultaneously detecting a plurality of chips on the wafer, and is used for testing the dark field IV curve of the chip after the plurality of chips on the wafer are powered on; and a fiber test mechanism, a standard light beam emitted by an optical fiber is incident on a chip photosensitive surface to test the light field data of the chip after being powered on. Through the above wafer test platform, a plurality of chips on the wafer can be detected simultaneously, and the problem of low wafer detection efficiency in the prior art is solved.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, specifically to a wafer testing platform and its testing method. Background Technology

[0002] When performing optoelectronic performance testing on chips, it is necessary to perform an IV curve test on each chip on the wafer under power-on conditions in a dark field. After the test is completed, the optical fiber is moved directly above the chip under test, and a standard beam is incident on the photosensitive surface of the chip. The light field data of the chip is then measured by powering on. After the above test is completed, the probe is adjusted to apply power again, thereby testing the dark field and light field data of the next chip under test, and the above process is repeated.

[0003] Because the wafer inspection process requires repeating the above steps multiple times until all individual chips on the wafer have been inspected, the existing wafer testing platforms cannot inspect multiple chips on a wafer simultaneously, resulting in low wafer inspection efficiency. Those skilled in the art urgently need to improve wafer inspection efficiency. Summary of the Invention

[0004] This invention aims to provide a wafer testing platform and its testing method to solve the problem that existing wafer testing equipment cannot simultaneously test multiple chips on a wafer, resulting in low wafer testing efficiency. Therefore, this invention provides a wafer testing platform, comprising:

[0005] A carrier disk is used to hold wafers;

[0006] A camera mechanism for calibrating the position of the wafer, the camera mechanism comprising: a vertical camera positioned toward the wafer;

[0007] The chip angle adjustment mechanism is connected to the carrier disk and drives the carrier disk to rotate in the horizontal direction to adjust the horizontal angle of the wafer.

[0008] The chip position adjustment mechanism is connected to the carrier disk drive and drives the carrier disk to translate horizontally to adjust the horizontal position of the wafer;

[0009] A probe assembly having at least two probes; the probe assembly is used to simultaneously detect multiple chips on the wafer, and to test the dark field IV curve of the multiple chips on the wafer after power-on.

[0010] The fiber optic testing mechanism uses a standard beam of light emitted from an optical fiber to strike the photosensitive surface of the chip, and then applies power to test the chip's optical field data.

[0011] Optionally, the probe assembly includes: a probe holder, and a probe disposed on the probe holder;

[0012] The probe assembly is connected to the probe assembly drive structure via an elastic connector.

[0013] Optionally, the elastic connector is a spring sleeved on the telescopic rod; the two ends of the spring are respectively connected to the probe fixing seat and the probe assembly driving structure.

[0014] Optionally, the probe component driving structure includes:

[0015] The probe holder includes a fixed part and a movable part;

[0016] A movable arm, on which the probe holder is fixedly mounted;

[0017] A first horizontal push rod is disposed on the fixed part and is used to push the moving part to drive the probe fixing seat to move in the first horizontal direction;

[0018] A second horizontal push rod is disposed on the fixed part and is used to push the moving part to drive the probe fixing seat to move in the second horizontal direction;

[0019] The height positioning component includes: a vertical push rod disposed on the fixed part, the vertical push rod pushing the moving part to drive the probe fixing seat to move in the vertical direction;

[0020] The first horizontal push rod, the second horizontal push rod, and the height positioning component are all fixed by limiting pins.

[0021] Optionally, the carrier disk is disposed on the chip stage; the chip position adjustment mechanism includes:

[0022] X-axis drive mechanism, which drives the chip stage to translate in the X-axis direction;

[0023] The Y-axis drive mechanism drives the chip stage to translate in the Y-axis direction.

[0024] A wafer inspection method includes the following steps:

[0025] S1, Wafer Position Detection: Obtain the outline information of the wafer to determine whether the array of chips on the wafer is tilted;

[0026] S2, Wafer Angle Adjustment: Based on the wafer position detection information, the carrier disk is driven to rotate by the chip angle adjustment mechanism to adjust the wafer angle;

[0027] S3, Wafer Offset Detection: Obtain the chip coordinate information on the wafer and compare it with the coordinate information set by the system to determine the horizontal position offset of the wafer;

[0028] S4, Wafer offset adjustment: Based on the wafer position detection information, the wafer position is adjusted by driving the carrier disk to translate through the chip position adjustment mechanism;

[0029] S5, Wafer Inspection: Multiple chips on the wafer are simultaneously inspected using a probe assembly with at least two probes to test the dark field IV curve of the chips; and a standard beam emitted by an optical fiber testing mechanism is incident on the photosensitive surface of the chip, and the chip's light field data is tested by applying power.

[0030] Optionally, step S1 specifically includes the following steps:

[0031] S101, the wafer is moved to the center of the camera's field of view of the image inspection mechanism, and a clear image is obtained through the camera;

[0032] S102, perform image preprocessing, convert the clear image into a grayscale image, and smooth the image using a Gaussian blur algorithm;

[0033] S103, perform Canny operator edge detection on the preprocessed image to determine the contour type, contour center point position, and contour size of each chip on the wafer; the contour size includes: the length and width of the chip's outer contour.

[0034] S104 performs chip tilt detection.

[0035] Optionally, step S104 specifically includes:

[0036] The first chip coordinate (x1, y1) along the wafer length direction and the last chip coordinate (x1, y1) along the wafer length direction are selected. n y n ); Based on the comparison between the coordinates of the two chips and the preset coordinates, it is determined whether the chips are tilted; if the line connecting the coordinates of the two chips on the wafer is parallel to the line connecting the preset coordinates, then the wafer is not tilted, and step S3 is performed; or,

[0037] The first chip coordinate (x1, y1) along the wafer length direction and the last chip coordinate (x1, y1) along the wafer length direction are selected. j y j The coordinates of two chips are compared with preset coordinates to determine if the chips are tilted. If the line connecting the coordinates of the two chips on the wafer is not parallel to the line connecting the preset coordinates, then the array of chips on the wafer is tilted, and the tilt angle of the wafer on the stage is calculated. The tilt angle is called Angle, and the calculation formula is as follows:

[0038]

[0039] Optionally, step S1 may further include: setting step S105 after step S104; if the wafer is not tilted after step S105, proceed to step S3;

[0040] S105, Wafer Angle Verification: Reacquire the outline information of the wafer to determine whether the array chips on the wafer are tilted.

[0041] Optional, wafer angle verification includes:

[0042] The first chip coordinate (x1, y1) along the wafer length direction and the last chip coordinate (x1, y1) along the wafer width direction are selected. j y j ); Based on the comparison between the coordinates of the two chips and the preset coordinates, if the chip coordinates (x1, y1) and the chip coordinates (x... j y j If the line connecting the wafers is parallel to the preset coordinate line, the wafer is not tilted; otherwise, the wafer is tilted, thus determining whether the wafer is tilted.

[0043] If the wafer is not tilted, proceed to step S5;

[0044] If the wafer is tilted, repeat steps S101 to S104.

[0045] The technical solution of this invention has the following advantages:

[0046] 1. The wafer testing platform provided by this invention includes:

[0047] A carrier disk is used to hold wafers;

[0048] A camera mechanism for calibrating the position of the wafer, the camera mechanism comprising: a vertical camera positioned toward the wafer;

[0049] The chip angle adjustment mechanism is connected to the carrier disk and drives the carrier disk to rotate in the horizontal direction to adjust the horizontal angle of the wafer.

[0050] The chip position adjustment mechanism is connected to the carrier disk drive and drives the carrier disk to translate horizontally to adjust the horizontal position of the wafer;

[0051] A probe assembly having at least two probes; the probe assembly is used to simultaneously detect multiple chips on the wafer, and to test the dark field IV curve of the multiple chips on the wafer after power-on.

[0052] The fiber optic testing mechanism uses a standard beam of light emitted from an optical fiber to strike the photosensitive surface of the chip, and then applies power to test the chip's optical field data.

[0053] In this invention, by simultaneously detecting multiple chips on a wafer using multiple probes on a probe assembly, the dark-field IV curve detection efficiency of multiple chips on the wafer can be effectively improved. This, in turn, improves the overall detection efficiency of the wafer testing platform.

[0054] 2. The wafer testing platform provided by the present invention includes a probe assembly comprising: a probe holder and probes disposed on the probe holder; the probe assembly is connected to a probe assembly driving structure via an elastic connector. The elastic connector is a spring sleeved on a telescopic rod; both ends of the spring are respectively connected to the probe holder and the probe assembly driving structure.

[0055] In this invention, the aforementioned elastic connector allows each probe on the probe assembly to have an appropriate amount of elasticity, thereby enabling the probe to make better contact with the chip surface and thus improving detection accuracy.

[0056] 3. The wafer testing platform provided by the present invention, wherein the probe component driving structure includes:

[0057] The probe holder includes a fixed part and a movable part;

[0058] A movable arm, on which the probe holder is fixedly mounted;

[0059] A first horizontal push rod is disposed on the fixed part and is used to push the moving part to drive the probe fixing seat to move in the first horizontal direction;

[0060] A second horizontal push rod is disposed on the fixed part and is used to push the moving part to drive the probe fixing seat to move in the second horizontal direction;

[0061] The height positioning component includes: a vertical push rod disposed on the fixed part, the vertical push rod pushing the moving part to drive the probe fixing seat to move in the vertical direction;

[0062] The first horizontal push rod, the second horizontal push rod, and the height positioning component are all fixed by limiting pins.

[0063] In this invention, a fixed part and a movable part are respectively provided on the probe holder, and the movable arm is driven to move in the horizontal and vertical directions by a first horizontal push rod, a second horizontal push rod, and a height positioning component, respectively, and then the movable position is limited and fixed by a limiting pin. The above structure can simply and reliably change the position of the movable arm.

[0064] 4. The wafer testing platform provided by the present invention includes a carrier disk disposed on a chip stage; the chip position adjustment mechanism includes: an X-axis driving mechanism that drives the chip stage to translate in the X-axis direction; and a Y-axis driving mechanism that drives the chip stage to translate in the Y-axis direction.

[0065] In this invention, the X-axis drive mechanism and the Y-axis drive mechanism described above can drive the chip stage to move in the horizontal direction, thereby adjusting the position of the chip stage.

[0066] 5. The wafer inspection method provided by the present invention includes the following steps:

[0067] S1, Wafer Position Detection: Obtain the outline information of the wafer to determine whether the array of chips on the wafer is tilted;

[0068] S2, Wafer Angle Adjustment: Based on the wafer position detection information, the carrier disk is driven to rotate by the chip angle adjustment mechanism to adjust the wafer angle;

[0069] S3, Wafer Offset Detection: Obtain the chip coordinate information on the wafer and compare it with the coordinate information set by the system to determine the horizontal position offset of the wafer;

[0070] S4, Wafer offset adjustment: Based on the wafer position detection information, the wafer position is adjusted by driving the carrier disk to translate through the chip position adjustment mechanism;

[0071] S5, Wafer Inspection: Multiple chips on the wafer are simultaneously inspected using a probe assembly with at least two probes to test the dark field IV curve of the chips; and a standard beam emitted by an optical fiber testing mechanism is incident on the photosensitive surface of the chip, and the chip's light field data is tested by applying power.

[0072] In existing technologies, chip performance testing requires individual chip identification, severely impacting testing efficiency. To address this issue, this invention first determines chip contour information through wafer position detection, thereby identifying whether the array of chips on the wafer is tilted. If tilted, the wafer angle is adjusted. Subsequently, the offset of the array of chips on the wafer is detected, and the offset is adjusted. This rapid wafer positioning and adjustment method achieves position correction for all chips with only a single rotation and translation operation. After determining the optimal position of the array of chips, the dark-field IV curve and optical field data of the chips are tested using a probe assembly and an optical fiber testing mechanism. The probe assembly with multiple probes effectively improves wafer testing efficiency.

[0073] 6. The wafer inspection method provided by the present invention specifically includes the following steps in step S1:

[0074] S101, the wafer is moved to the center of the camera's field of view of the image inspection mechanism, and a clear image is obtained through the camera;

[0075] S102, perform image preprocessing, convert the clear image into a grayscale image, and smooth the image using a Gaussian blur algorithm;

[0076] S103, perform Canny operator edge detection on the preprocessed image to determine the contour type, contour center point position, and contour size of each chip on the wafer; the contour size includes: the length and width of the chip's outer contour.

[0077] S104 performs chip tilt detection.

[0078] In this invention, the outline type, outline center point position, and outline size of each chip on the wafer can be obtained through the above method. This provides data support for the next step of rotating and translating the positions of the arrayed chips on the wafer.

[0079] 7. The wafer inspection method provided by the present invention specifically includes the following in step S104:

[0080] The first chip coordinate (x1, y1) along the wafer length direction and the last chip coordinate (x1, y1) along the wafer length direction are selected. n y n ); Based on the comparison between the coordinates of the two chips and the preset coordinates, it is determined whether the chips are tilted; if the line connecting the coordinates of the two chips on the wafer is parallel to the line connecting the preset coordinates, then the wafer is not tilted, and step S3 is performed; or,

[0081] The first chip coordinate (x1, y1) along the wafer length direction and the last chip coordinate (x1, y1) along the wafer length direction are selected. j y j The coordinates of two chips are compared with preset coordinates to determine if the chips are tilted. If the line connecting the coordinates of the two chips on the wafer is not parallel to the line connecting the preset coordinates, then the array of chips on the wafer is tilted, and the tilt angle of the wafer on the stage is calculated. The tilt angle is called Angle, and the calculation formula is as follows:

[0082]

[0083] In this invention, the coordinates of the first chip (x1, y1) and the coordinates of the last chip (x1, y1) along the length direction of the array chips on the wafer are selected. n y nThe process involves comparing the measured coordinates of the two chips with the preset standard coordinate values. If the straight line connecting the two measured chips is parallel to the straight line connecting the preset coordinates, then the chips are not tilted; otherwise, the chips are tilted. Furthermore, if chip tilt is detected, the tilt angle of the array chips can be measured based on the aforementioned tilt angle.

[0084] 8. The wafer inspection method provided by the present invention further includes, in step S1: setting step S105 after step S104; if the wafer is not tilted after step S105, proceed to step S3; S105, wafer angle verification: reacquire the outline information of the wafer to determine whether the array chips on the wafer are tilted.

[0085] Wafer angle verification includes: selecting the first chip coordinate (x1, y1) along the wafer length direction and the last chip coordinate (x1, y1) along the wafer width direction. j y j ); Based on the comparison between the coordinates of the two chips and the preset coordinates, if the chip coordinates (x1, y1) and the chip coordinates (x... j y j If the line is parallel to the preset coordinate line, the wafer is not tilted; otherwise, the wafer is tilted, thereby determining whether the wafer is tilted. If the wafer is not tilted, proceed to step S5; if the wafer is tilted, repeat steps S101 to S104.

[0086] In this invention, by selecting the coordinates (x1, y1) of the first chip in the length direction of the array chips on the wafer, and the coordinates (x1, y1) of the last chip in the width direction of the array chips on the wafer... j y j The line connecting the two measured coordinates is compared with the line connecting the preset coordinates along the width of the array chip. If the two lines are parallel, the chip is not tilted; otherwise, the chip is tilted. This method can effectively verify whether the wafer has been rotated into position and whether the chip tilt correction has been completed. Attached Figure Description

[0087] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0088] Figure 1 This is a schematic diagram of the three-dimensional structure of the wafer testing platform provided by the present invention;

[0089] Figure 2 A three-dimensional structural diagram of a probe component driving structure with a probe component provided by the present invention;

[0090] Figure 3 A three-dimensional structural diagram of the optical fiber testing mechanism provided by the present invention;

[0091] Figure 4 A three-dimensional structural diagram of a mounting base with multiple probes provided by the present invention;

[0092] Figure 5 This is a schematic diagram of the connection structure between the probe holder and the elastic connector provided by the present invention;

[0093] Figure 6 This is a schematic diagram of the tilted wafer position provided by the present invention;

[0094] Figure 7 This is a schematic diagram of the wafer inspection method provided by the present invention.

[0095] Explanation of reference numerals in the attached figures:

[0096] 1-Carrier plate; 2-Wafer; 3-Vertical camera; 4-Chip angle adjustment mechanism; 5-Probe assembly; 6-Probe; 7-Fiber optic testing mechanism; 8-Probe holder; 9-Elastic connector; 10-Probe assembly drive structure; 11-Fixing part; 12-Moving part; 13-Moving arm; 14-First horizontal push rod; 15-Second horizontal push rod; 16-Vertical push rod; 17-Limiting pin; 18-Chip stage; 19-X-axis drive mechanism; 20-Y-axis drive mechanism. Detailed Implementation

[0097] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0098] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0099] Example 1

[0100] This describes a wafer testing platform, such as Figure 1 As shown, it includes:

[0101] A carrier disk 1 is used to carry a wafer 2; the carrier disk 1 is disposed on a chip stage 18.

[0102] A camera mechanism for calibrating the position of the wafer 2, the camera mechanism comprising: a vertical camera 3 disposed facing the wafer 2;

[0103] The chip angle adjustment mechanism 4 is connected to the carrier disk 1 and drives the carrier disk 1 to rotate in the horizontal direction to adjust the horizontal angle of the wafer 2.

[0104] The chip position adjustment mechanism is connected to the carrier disk 1 via a transmission, driving the carrier disk 1 to translate horizontally to adjust the horizontal position of the wafer 2; for example... Figure 1 The chip position adjustment mechanism shown includes: an X-axis drive mechanism 19, which drives the chip stage 18 to translate in the X-axis direction; and a Y-axis drive mechanism 20, which drives the chip stage 18 to translate in the Y-axis direction.

[0105] The probe assembly 5 is provided with at least two probes 6; the probe assembly 5 is used to simultaneously detect multiple chips on the wafer 2, and to test the dark field IV curve of the multiple chips on the wafer 2 after power-on. Figure 4 and Figure 5 The probe assembly 5 shown includes a probe holder 8 and a probe 6 disposed on the probe holder 8; the probe assembly 5 is connected to the probe assembly drive structure 10 via an elastic connector 9. The elastic connector 9 is a spring sleeved on a telescopic rod; the two ends of the spring are respectively connected to the probe holder 8 and the probe assembly drive structure 10;

[0106] The probe assembly driving structure 10 is used to drive the probe assembly 5 to the interface with the array of chips on the wafer 2; for example Figure 2 The probe assembly drive structure 10 shown includes: a probe holder, including a fixed part 11 and a moving part 12; a moving arm 13, on which the probe fixing seat 8 is fixedly mounted; a first horizontal push rod 14, mounted on the fixed part 11, for pushing the moving part 12 to drive the probe fixing seat 8 to move in a first horizontal direction; a second horizontal push rod 15, mounted on the fixed part 11, for pushing the moving part 12 to drive the probe fixing seat 8 to move in a second horizontal direction; and a height positioning component, including: a vertical push rod 16 mounted on the fixed part 11, which pushes the moving part 12 to drive the probe fixing seat 8 to move in a vertical direction; the first horizontal push rod 14, the second horizontal push rod 15, and the height positioning component are all limited and fixed by limiting pins 17.

[0107] Fiber optic testing unit 7, such as Figure 3As shown, the fiber optic testing mechanism 7 uses a standard beam emitted from an optical fiber to strike the photosensitive surface of the chip, and then powers on the chip to test its optical field data.

[0108] like Figure 7 The wafer inspection method shown specifically includes the following steps:

[0109] S1, Wafer position detection: Obtain the contour information of wafer 2 to determine whether the array chips on wafer 2 are tilted;

[0110] S2, Wafer Angle Adjustment: Based on the wafer 2 position detection information, the carrier disk 1 is driven to rotate by the chip angle adjustment mechanism 4 to adjust the angle of the wafer 2;

[0111] S3, Wafer offset detection: Obtain the chip coordinate information on the wafer 2 and compare it with the coordinate information set by the system to determine the horizontal position offset of the wafer 2;

[0112] S4, Wafer offset adjustment: Based on the wafer 2 position detection information, the carrier disk 1 is driven to translate through the chip position adjustment mechanism to adjust the position of the wafer 2;

[0113] S5, Wafer Inspection: Multiple chips on the wafer 2 are simultaneously inspected by a probe assembly 5 with at least two probes 6, thereby testing the dark field IV curve of the chip; and a standard beam emitted by an optical fiber testing mechanism 7 is incident on the photosensitive surface of the chip, and the chip's light field data is tested by applying power.

[0114] In this embodiment, step S1 specifically includes the following steps:

[0115] S101, the wafer 2 is moved to the center of the camera's field of view of the image detection mechanism, and a clear image is obtained through the camera;

[0116] S102, perform image preprocessing, convert the clear image into a grayscale image, and smooth the image using a Gaussian blur algorithm;

[0117] S103, perform Canny operator edge detection on the preprocessed image to determine the contour type, contour center point position x, y, and contour size of each chip on the wafer 2; the contour size includes: the length and width of the chip's outer contour.

[0118] S104, performs chip tilt detection;

[0119] S105, Wafer Angle Verification: Reacquire the contour information of wafer 2 to determine whether the array chips on wafer 2 are tilted. If wafer 2 is not tilted after step S105, proceed to step S3.

[0120] In this embodiment, as Figure 6 As shown, step S104 specifically includes:

[0121] The coordinates x1 and y1 of the first chip along the length of wafer 2, and the coordinates x1 and y1 of the last chip along the length of wafer 2 are selected. n y n The coordinates of the two chips are compared with preset coordinates to determine whether the chips are tilted. If the line connecting the coordinates of the two chips on wafer 2 is parallel to the line connecting the preset coordinates, then wafer 2 is not tilted, and step S3 is performed; or,

[0122] The coordinates x1 and y1 of the first chip along the length of wafer 2, and the coordinates x1 and y1 of the last chip along the length of wafer 2 are selected. j y j The coordinates of the two chips are compared with preset coordinates to determine whether the chips are tilted. If the line connecting the coordinates of the two chips on wafer 2 is not parallel to the line connecting the preset coordinates, then the array of chips on wafer 2 is tilted, and the tilt angle of wafer 2 on the stage is calculated. The tilt angle is called Angle, and the calculation formula is as follows:

[0123]

[0124] In this embodiment, as Figure 6 As shown, wafer angle verification includes:

[0125] The coordinates x1 and y1 of the first chip along the length direction of wafer 2, and the coordinates x1 and y1 of the last chip along the width direction of wafer 2 are selected. j y j Based on the comparison between the coordinates of the two chips and the preset coordinates, if the chip coordinates x1, y1 and chip coordinate x... j y j If the connecting line is parallel to the preset coordinate connecting line, then the wafer 2 is not tilted; otherwise, the wafer 2 is tilted, thereby determining whether the wafer 2 is tilted.

[0126] If the wafer 2 is not tilted, proceed to step S5;

[0127] If the wafer 2 is tilted, repeat steps S101 to S104.

[0128] Of course, in this embodiment, the connection method between the probe component 5 and the probe component driving structure 10 is not specifically limited. In other embodiments, the probe component 5 is directly connected to the probe component driving structure 10 without the elastic mechanism.

[0129] Of course, in this embodiment, the connection method between the probe assembly 5 and the probe assembly driving structure 10 is not specifically limited. In other embodiments, a rubber pad for elastically connecting the probe assembly 5 and the probe assembly driving structure 10 may also be provided at the connection position.

[0130] Of course, in this embodiment, there is no specific limitation on whether to set step S105 after step S104. In other embodiments, chip tilt judgment is performed in step S104; if the line connecting the coordinates of the two chips of the wafer 2 is parallel to the line connecting the preset coordinates, then the wafer 2 is not tilted and does not go through the above step S105, and directly proceeds to step S3.

[0131] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A wafer inspection method for a wafer testing platform, the wafer testing platform comprising: A carrier disk (1) is used to carry a wafer (2); A camera mechanism for calibrating the position of the wafer (2), the camera mechanism comprising: a vertical camera (3) disposed toward the wafer (2); The chip angle adjustment mechanism (4) is connected to the carrier disk (1) and drives the carrier disk (1) to rotate in the horizontal direction to adjust the horizontal angle of the wafer (2); The chip position adjustment mechanism is connected to the carrier disk (1) and drives the carrier disk (1) to move horizontally to adjust the horizontal position of the wafer (2); The probe assembly (5) is provided with at least two probes (6); the probe assembly (5) is used to simultaneously detect multiple chips on the wafer (2) and to test the dark field IV curve of the multiple chips on the wafer (2) after power-on. The fiber optic testing mechanism (7) uses a standard beam emitted through an optical fiber to strike the photosensitive surface of the chip and then powers it on to test the chip's optical field data. The wafer inspection method is characterized by comprising the following steps: S1, wafer position detection: obtain the outline information of the wafer (2) to determine whether the array chips on the wafer (2) are tilted; S2, wafer angle adjustment: Based on the wafer (2) position detection information, the carrier disk (1) is driven to rotate by the chip angle adjustment mechanism (4) to adjust the angle of the wafer (2); S3, Wafer offset detection: Obtain the chip coordinate information on the wafer (2), compare it with the coordinate information set by the system, and determine the horizontal position offset of the wafer (2); S4, wafer offset adjustment: Based on the wafer (2) position detection information, the carrier disk (1) is driven to translate by the chip position adjustment mechanism to adjust the position of the wafer (2); S5, Wafer inspection: Multiple chips on the wafer (2) are simultaneously inspected by a probe assembly (5) with at least two probes (6) to test the dark field IV curve of the chip; and a standard beam emitted by an optical fiber testing mechanism (7) is incident on the photosensitive surface of the chip and the chip light field data is tested by powering on. Step S1 specifically includes the following steps: S101, the wafer (2) is moved to the center of the camera field of view of the image detection mechanism, and a clear image is obtained through the camera; S102, perform image preprocessing, convert the clear image into a grayscale image, and smooth the image using a Gaussian blur algorithm; S103, perform Canny operator edge detection on the image after image preprocessing to determine the contour type, contour center point position (x, y), and contour size of each chip on the wafer (2); the contour size includes: the length and width of the chip's outer contour. S104, performs chip tilt detection; Step S104 specifically includes: The first chip coordinate (x1, y1) along the length direction of the wafer (2) and the last chip coordinate (x1, y1) along the length direction of the wafer (2) are selected. n y n ); Based on the comparison between the coordinates of the two chips and the preset coordinates, it is determined whether the chips are tilted; if the line connecting the coordinates of the two chips of the wafer (2) is parallel to the line connecting the preset coordinates, then the wafer (2) is not tilted, and step S3 is performed; or, The first chip coordinate (x1, y1) along the length direction of the wafer (2) and the last chip coordinate (x1, y1) along the length direction of the wafer (2) are selected. j y j The coordinates of the two chips are compared with the preset coordinates to determine whether the chips are tilted. If the line connecting the coordinates of the two chips on the wafer (2) is not parallel to the line connecting the preset coordinates, then the position of the array chips on the wafer (2) is tilted, and the tilt angle of the wafer (2) on the stage is calculated. The tilt angle is called Angle, and the calculation formula is as follows: 。 2. The wafer inspection method according to claim 1, characterized in that, Step S1 also includes: setting step S105 after step S104; if the wafer (2) is not tilted after step S105, proceed to step S3; S105, wafer angle verification: reacquire the contour information of the wafer (2) to determine whether the array chips on the wafer (2) are tilted.

3. The wafer inspection method according to claim 2, characterized in that, Wafer angle verification includes: The first chip coordinate (x1, y1) in the length direction of the wafer (2) and the last chip coordinate (x1, y1) in the width direction of the wafer (2) are selected. j y j ); Based on the comparison between the coordinates of the two chips and the preset coordinates, if the chip coordinates (x1, y1) and the chip coordinates (x... j y j If the line connecting the wafers is parallel to the preset coordinate line, the wafer (2) is not tilted; otherwise, the wafer (2) is tilted. This allows us to determine whether the wafer (2) is tilted. If the wafer (2) is not tilted, proceed to step S5; If the wafer (2) is tilted, repeat steps S101 to S104.

4. The wafer inspection method according to claim 1, characterized in that, The probe assembly (5) includes: a probe holder (8) and a probe (6) disposed on the probe holder (8); The probe assembly (5) is connected to the probe assembly drive structure (10) via an elastic connector (9).

5. The wafer inspection method according to claim 4, characterized in that, The elastic connector (9) is a spring sleeved on the telescopic rod; the two ends of the spring are respectively connected to the probe fixing seat (8) and the probe assembly driving structure (10).

6. The wafer inspection method according to claim 4, characterized in that, The probe assembly driving structure (10) includes: The probe holder includes a fixed part (11) and a movable part (12). The movable arm (13) is fixedly mounted on the probe holder (8); A first horizontal push rod (14) is disposed on the fixed part (11) for pushing the moving part (12) to drive the probe fixing seat (8) to move in the first horizontal direction; A second horizontal push rod (15) is provided on the fixed part (11) for pushing the moving part (12) to drive the probe holder (8) to move in the second horizontal direction; The height positioning component includes: a vertical push rod (16) disposed on the fixed part (11), the vertical push rod (16) pushes the moving part (12) to drive the probe fixing seat (8) to move in the vertical direction; The first horizontal push rod (14), the second horizontal push rod (15), and the height positioning component are respectively fixed by limiting pins (17).

7. The wafer inspection method according to claim 1, characterized in that, The carrier disk (1) is disposed on the chip stage (18); the chip position adjustment mechanism includes: X-axis drive mechanism (19), which drives the chip stage (18) to translate in the X-axis direction; Y-axis drive mechanism (20) drives the chip stage (18) to translate in the Y-axis direction.

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