Method for controlling power-on timing of CPU, control device and electronic equipment

Abstract

Embodiments of the present application provide a CPU power-on timing control method, a control device and electronic equipment, and the method comprises the following steps: in the case that the mainboard CPLD sends a low-level first control signal to the CPU, the baseboard management controller acquires an updated firmware file, writes the updated firmware file into the firmware of the voltage stabilizer to upgrade the firmware of the voltage stabilizer; it is determined whether the updated firmware file is successfully written into the firmware of the voltage stabilizer, in the case of successful writing, a high-level upgrade control signal is sent to the mainboard CPLD, and the high-level upgrade control signal and the high-level second control signal make the mainboard CPLD send a high-level first control signal to the CPU after a delay of a preset time period. Through the present application, the problem that the CPU power-on timing does not meet the condition during the firmware upgrade of the voltage stabilizer is solved, and the CPU power-on timing meets the power-on condition.

Description

Technical Field

[0001] This application relates to the field of server power-on control, and more specifically, to a method, control device, computer-readable storage medium, and electronic device for controlling CPU power-on timing. Background Technology

[0002] In server applications, the voltage regulator controller (VR controller) is used to power the CPU in a server. Voltage regulator vendors typically optimize the firmware (FM) of their controllers and upgrade the firmware files to ensure stable performance. Since servers are generally used in server rooms or data centers, offline firmware flashing is inconvenient; therefore, it is necessary to implement online firmware upgrade functionality. Currently, server BIOS (Basic Input Output System), BMC (Baseboard Management Controller), CPLD (Complex Programmable Logic Device), and VR (Voltage Regulator) generally have online firmware upgrade capabilities. The online firmware upgrade method typically connects the voltage regulator controller to the baseboard management controller via the power management bus (PMBUS), allowing the baseboard management controller to perform online upgrades of the voltage regulator controller through the PMBUS.

[0003] Since the voltage regulator controller supplies power to the CPU, performing an online firmware upgrade while the server is powered on may cause unstable power supply to the CPU, potentially leading to server crashes. To avoid this, the CPU voltage regulator controller firmware should be upgraded online while the server is powered off (S5 state). Currently, Intel CPUs are powered by the main power supply, and the CPU voltage regulator controller only outputs voltage after the server is powered on. Therefore, upgrading the voltage regulator controller firmware in S5 state will not affect the CPU power supply when the server is powered on. However, AMD Genoa platform CPUs require two power supplies, PVDD33_S5 and PVDD18_S5, to control power supply in S5 state. PVDD18_S5 is typically controlled by the voltage regulator controller; therefore, upgrading the firmware file of the PVDD18_S5 voltage regulator controller in S5 state will affect the CPU's power-on timings. To prevent CPU damage due to voltage instability during online firmware upgrades, the output of PVDD18_S5 must be disabled before upgrading the firmware file. After the upgrade, the voltage regulator controller should then turn the PVDD18_S5 output back on. The CPU's power-on sequence in S5 state must meet the following condition: the CPU can only power on after the voltage regulator controller has fully powered on the power supply, followed by a 10ms delay. In other words, the CPU's power-on sequence needs to be updated after any change in the power supply level (from high to low or vice versa). In existing technology, PVDD18_S5 normally powers the CPU in S5 state. However, by disabling the voltage regulator controller's output before firmware upgrades and then powering it on after the upgrade, the CPU's power-on sequence is not updated. The CPU remains powered on throughout this process, failing to meet the aforementioned conditions for the CPU's power-on sequence in S5 state. Therefore, this may cause abnormal CPU operation.

[0004] Therefore, there is an urgent need for a method to solve the problem of CPU timing not meeting power-on conditions caused by voltage level changes during online firmware upgrades of voltage regulators. Summary of the Invention

[0005] This application provides a method, device, computer-readable storage medium, and electronic device for controlling CPU power-on timing, to at least solve the problem in the related art where the CPU power-on timing does not meet the conditions during the firmware upgrade of the voltage regulator controller.

[0006] According to one embodiment of this application, a method for controlling CPU power-on timing is provided, comprising: when a motherboard CPLD sends a low-level first control signal to the CPU, a baseboard management controller obtains an updated firmware file and writes the updated firmware file into the firmware of a voltage regulator to upgrade the firmware of the voltage regulator. The low-level first control signal is issued by the motherboard CPLD upon receiving a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator. The upgrade control signal indicates the upgrade status of the voltage regulator's firmware, and the upgrade status indicates whether the voltage regulator's firmware is being upgraded. The second control signal is used to indicate the power supply status of the CPU corresponding to the power supply control signal of the voltage regulator, and the first control signal represents the power-on timing of the CPU; it is determined whether the updated firmware file has been successfully written into the firmware of the voltage regulator. If the writing is successful, a high-level upgrade control signal is sent to the motherboard CPLD, and the high-level upgrade control signal and the high-level second control signal cause the motherboard CPLD to send a high-level first control signal to the CPU after a preset time delay. The high-level second control signal is a signal sent to the motherboard CPLD by the voltage regulator when it receives the high-level power supply control signal.

[0007] In an exemplary embodiment, when the motherboard CPLD outputs a low-level first control signal, the baseboard management controller acquires the updated firmware file, including: determining whether the system where the CPU is located is in a power-off state; and when the system where the CPU is located is in the power-off state, and the baseboard management controller acquires the updated firmware file when the motherboard CPLD outputs a low-level first control signal.

[0008] In one exemplary embodiment, the low-level second control signal is issued by the voltage regulator controller upon receiving the low-level power supply control signal from the substrate management controller.

[0009] In one exemplary embodiment, determining whether the updated firmware file has been successfully written into the firmware of the voltage regulator includes: verifying the updated firmware file written into the voltage regulator and obtaining a verification completion instruction; if the verification completion instruction indicates that the verification was successful, determining that the updated firmware file was successfully written; if the verification completion instruction indicates that the verification failed, determining that the updated firmware file was not written.

[0010] In one exemplary embodiment, the high-level first control signal is issued by the motherboard CPLD upon receiving the high-level upgrade control signal from the baseboard management controller and the high-level second control signal from the voltage regulator controller.

[0011] In one exemplary embodiment, the method further includes: if writing the updated firmware file fails, writing the updated firmware file to the voltage regulator controller again.

[0012] In one exemplary embodiment, writing the updated firmware file into the firmware of the voltage regulator includes: writing the updated firmware file into the firmware of the voltage regulator via the power management bus.

[0013] According to another embodiment of this application, a method for controlling CPU power-on timing is provided, comprising: upon receiving a low-level upgrade control signal sent by a baseboard management controller and a low-level second control signal sent by a voltage regulator controller, the motherboard CPLD sends a low-level first control signal to the CPU, wherein the upgrade control signal is used to indicate the upgrade status of the firmware of the voltage regulator controller, the upgrade status indicating whether the firmware of the voltage regulator controller is being upgraded, the second control signal being used to indicate the power supply status of the CPU corresponding to the power supply control signal of the voltage regulator controller, and the first control signal indicating the power-on timing of the CPU; receiving a high-level upgrade control signal sent by the baseboard management controller and a high-level second control signal sent by the voltage regulator controller, and after a preset time delay, sending a high-level first control signal to the CPU, wherein the high-level upgrade control signal and the high-level second control signal are triggered by the successful writing of the updated firmware file into the firmware of the voltage regulator controller, the updated firmware file being used to upgrade the firmware of the voltage regulator controller, and the upgrade of the firmware of the voltage regulator controller being triggered by the low-level upgrade control signal.

[0014] In one exemplary embodiment, upon receiving a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator controller, the motherboard CPLD sends a low-level first control signal to the CPU, including: determining whether the system where the CPU resides is in a power-off state; and if the system where the CPU resides is in the power-off state, and the motherboard CPLD receives the low-level upgrade control signal from the baseboard management controller and the low-level second control signal from the voltage regulator controller, sending the low-level first control signal to the CPU.

[0015] In one exemplary embodiment, the low-level second control signal is issued by the voltage regulator controller upon receiving the low-level power supply control signal from the substrate management controller.

[0016] In one exemplary embodiment, the high-level upgrade control signal is issued by the baseboard management controller when the verification completion instruction indicates successful verification, wherein the verification completion instruction is an instruction obtained by the baseboard management controller after verifying the firmware file written to the voltage regulator controller.

[0017] In one exemplary embodiment, the high-level second control signal is issued by the voltage regulator controller upon receiving the high-level power supply control signal from the substrate management controller.

[0018] In one exemplary embodiment, after sending the high-level first control signal to the CPU, the method further includes: controlling the voltage regulator to power on the CPU according to the high-level first control signal.

[0019] In one exemplary embodiment, the upgrade control signal is received from the baseboard management controller via an I2C bus.

[0020] According to another embodiment of this application, a method for controlling CPU power-on timing is provided, comprising: upon receiving a low-level power supply control signal sent by a baseboard management controller, a voltage regulator controller sends a low-level second control signal to a motherboard CPLD; the low-level second control signal and a low-level upgrade control signal cause the motherboard CPLD to send a low-level first control signal to the CPU; wherein the power supply control signal is used to indicate whether the voltage regulator controller supplies power to the CPU, the second control signal is used to indicate the power supply state of the CPU corresponding to the power supply control signal of the voltage regulator controller, the first control signal represents the CPU power-on timing, and the low-level upgrade control signal is sent by the baseboard management controller to the CPU... The CPLD receives signals from the motherboard, including an upgrade control signal indicating the firmware upgrade status of the voltage regulator, which indicates whether the firmware of the voltage regulator is being upgraded; it receives an updated firmware file written by the baseboard management controller, and if the updated firmware file is successfully written to the voltage regulator, it receives a high-level power supply control signal sent by the baseboard management controller and sends a high-level second control signal to the motherboard CPLD, so that the motherboard CPLD, upon receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage regulator, sends a high-level first control signal to the CPU after a preset time delay.

[0021] In one exemplary embodiment, upon receiving a low-level power supply control signal from the baseboard management controller, the voltage regulator controller sends a low-level second control signal to the motherboard CPLD, including: determining whether the system where the CPU is located is in a power-off state; and if the system where the CPU is located is in the power-off state, and the voltage regulator controller receives the low-level power supply control signal from the baseboard management controller, sending the low-level second control signal to the motherboard CPLD.

[0022] In one exemplary embodiment, the low-level first control signal is issued by the motherboard CPLD upon receiving a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator controller.

[0023] In one exemplary embodiment, the high-level upgrade control signal is issued by the baseboard management controller when the verification completion instruction indicates successful verification, wherein the verification completion instruction is an instruction obtained by the baseboard management controller after verifying the firmware file written to the voltage regulator controller.

[0024] In one exemplary embodiment, the high-level first control signal is issued by the motherboard CPLD upon receiving the high-level upgrade control signal from the baseboard management controller and the high-level second control signal from the voltage regulator controller.

[0025] In one exemplary embodiment, the high-level first control signal is used to control the voltage regulator to power on the CPU.

[0026] According to another embodiment of this application, a CPU power-on timing control device is provided, comprising: a writing module, configured to, when a motherboard CPLD sends a low-level first control signal to the CPU, a baseboard management controller obtains an updated firmware file and writes the updated firmware file into the firmware of a voltage regulator controller to upgrade the firmware of the voltage regulator controller, wherein the low-level first control signal is issued by the motherboard CPLD upon receiving a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator controller, the upgrade control signal being used to indicate the upgrade status of the firmware of the voltage regulator controller, the upgrade status indicating whether the firmware of the voltage regulator controller is being upgraded. The second control signal is used to indicate the power supply status of the CPU corresponding to the power supply control signal of the voltage regulator, and the first control signal represents the power-on timing of the CPU; the sending module is used to determine whether the updated firmware file has been successfully written into the firmware of the voltage regulator, and if it has been successfully written, to send a high-level upgrade control signal to the motherboard CPLD, and the high-level upgrade control signal and the high-level second control signal cause the motherboard CPLD to send a high-level first control signal to the CPU after a preset time delay, wherein the high-level second control signal is a signal sent to the motherboard CPLD by the voltage regulator when it receives the high-level power supply control signal.

[0027] According to another embodiment of this application, a CPU power-on timing control device is provided, further comprising: a first transmitting module, configured to send a low-level first control signal to the CPU when the motherboard CPLD receives a low-level upgrade control signal sent by the baseboard management controller and a low-level second control signal sent by the voltage regulator controller, wherein the upgrade control signal is used to indicate the upgrade status of the firmware of the voltage regulator controller, the upgrade status indicating whether the firmware of the voltage regulator controller is being upgraded, the second control signal being used to indicate the power supply status of the CPU corresponding to the power supply control signal of the voltage regulator controller, and the first control signal indicating the power-on timing of the CPU; and a second transmitting module, configured to receive the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage regulator controller, and after a preset time delay, send the high-level first control signal to the CPU, wherein the high-level upgrade control signal and the high-level second control signal are generated and sent when the updated firmware file is successfully written into the firmware of the voltage regulator controller, the updated firmware file is used to upgrade the firmware of the voltage regulator controller, and the upgrade of the firmware of the voltage regulator controller is triggered by the low-level upgrade control signal.

[0028] According to another embodiment of this application, a CPU power-on timing control device is provided, further comprising: a first transmitting module, configured to, upon receiving a low-level power supply control signal from a baseboard management controller, transmit a low-level second control signal to a motherboard CPLD, wherein the low-level second control signal and the low-level upgrade control signal cause the motherboard CPLD to transmit a low-level first control signal to the CPU, wherein the power supply control signal is used to indicate whether the voltage regulator supplies power to the CPU, the second control signal is used to indicate the power supply state of the CPU corresponding to the power supply control signal of the voltage regulator, the first control signal represents the CPU power-on timing, and the low-level upgrade control signal is sent by the baseboard management controller to the CPU. The signal from the motherboard CPLD includes an upgrade control signal used to indicate the firmware upgrade status of the voltage regulator, indicating whether the firmware of the voltage regulator is being upgraded; and a second sending module used to receive the updated firmware file written by the baseboard management controller. If the updated firmware file is successfully written to the voltage regulator, the module receives a high-level power supply control signal sent by the baseboard management controller and sends a high-level second control signal to the motherboard CPLD. This causes the motherboard CPLD, upon receiving both the high-level upgrade control signal from the baseboard management controller and the high-level second control signal from the voltage regulator, to send a high-level first control signal to the CPU after a preset time delay.

[0029] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0030] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0031] According to this application, since the baseboard management controller sends a low-level upgrade control signal to the motherboard CPLD, after receiving the low-level upgrade control signal and the low-level second control signal, the motherboard CPLD sends a low-level first control signal to the CPU to control the CPU to power down. The low-level first control signal is sent to the CPLD by the voltage regulator controller after receiving the low-level power supply control signal sent by the baseboard management controller. Afterwards, the baseboard management controller obtains the updated firmware file and writes the updated firmware file into the firmware of the voltage regulator controller. After successful writing, it sends a high-level upgrade control signal to the motherboard CPLD, so that after receiving the high-level upgrade control signal and the high-level second control signal, the motherboard CPLD sends a high-level first control signal to the CPU to control the CPU to power up. The high-level first control signal is sent to the CPLD by the voltage regulator controller after receiving the high-level power supply control signal sent by the baseboard management controller. Compared to existing technologies where the CPU power-on timing remains high throughout the firmware upgrade process of the voltage regulator and cannot change according to the level of the power supply control signal, this application controls the level change of the first control signal by controlling the level change of the upgrade control signal and the level change of the second control signal. The level change of the second control signal can be controlled by the level change of the power supply control signal. By controlling the level change of the first control signal, the CPU power-on timing is further controlled, so that the CPU power-on timing changes accordingly after the level change of the power supply control signal. Therefore, the condition that the CPU power-on timing only becomes high after the power supply control signal is high (i.e., after all the power supplies for the CPU are powered on) is met can be solved, thus resolving the problem that the CPU power-on timing does not meet the conditions during the firmware upgrade process of the voltage regulator and ensuring that the CPU power-on timing meets the power-on conditions. Attached Figure Description

[0032] Figure 1 This is a hardware structure block diagram of a mobile terminal according to an embodiment of the CPU power-on timing control method of this application.

[0033] Figure 2 This is a flowchart of a prior art method for controlling CPU power-on timing according to an embodiment of this application;

[0034] Figure 3 This is a flowchart of a CPU power-on timing control method according to an embodiment of this application;

[0035] Figure 4 This is a flowchart illustrating a specific CPU power-on timing control method according to an embodiment of this application;

[0036] Figure 5This is a flowchart of another specific CPU power-on timing control method according to an embodiment of this application;

[0037] Figure 6 This is a structural block diagram of a CPU power-on timing control device according to an embodiment of this application.

[0038] The above figures include the following reference numerals:

[0039] 102. Processor; 104. Memory; 106. Transmission device; 108. Input / output device. Detailed Implementation

[0040] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0041] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0042] The methods and embodiments provided in this application can be executed on a mobile terminal, computer terminal, or similar computing device. Taking running on a mobile terminal as an example, Figure 1 This is a hardware structure block diagram of a mobile terminal according to an embodiment of the CPU power-on timing control method of this application. Figure 1 As shown, a mobile terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor (MCU) or a programmable logic device (FPG) for processing second control signals, etc.) and a memory 104 for storing data are also shown. The mobile terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the mobile terminal described above. For example, the mobile terminal may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0043] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the CPU power-on timing control method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a mobile terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0044] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the mobile terminal's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0045] Figure 2 This is a flowchart of a prior art CPU power-on timing control method according to an embodiment of this application, such as... Figure 2As shown, in the prior art, before the VR Controller (voltage regulator) is upgraded online, the server is first shut down and enters the S5 state (shutdown state). The BMC (Baseboard Management Controller) writes to the VR Controller's register via the PMBUS (Power Management Bus) to turn off the output of the S5_VR (Power Supply Control Signal). Then, the BMC burns a new firmware file to the VR Controller via the PMBUS. After the firmware file is successfully written and burned, the BMC writes to the VR Controller's register via the PMBUS to turn on the S5_VR (Power Supply Control Signal) output. The S5_VR (Power Supply Control Signal) then outputs power normally, and the online upgrade of the VR Controller's firmware file is complete. The server then powers on and works normally. Since the CPU requires power from the S5 state, the CPU has power-on timing requirements in the S5 state. For example, the power-on timing requirements for the Genoa platform CPU require that the RSMRST_N (first control signal) signal remain low until all S5_VR (power supply control signals) are powered on, and then be pulled high only after a 10ms delay. Before online upgrades to the existing VR Controller FW (voltage regulator firmware), the server is in S5 state, where the S5_VR (power supply control signal) outputs a high level, allowing normal power supply to the CPU, and the RSMRST_N (first control signal) is also high. During a VR (voltage regulator) firmware upgrade, the S5_VR (power supply control signal) is first powered down. After the upgrade is complete, the PVDD18_S5 is powered on. During this process, the RSMRST_N (first control signal) signal remains high, preventing the S5_VR (power supply control signal) from fully powering on. After a 10ms delay, the RSMRST_N (first control signal) signal is then raised again, meeting the CPU power-on timing requirements. Although existing solutions have been verified in the laboratory that the server can power on and function normally after the VR (voltage regulator) upgrade, the CPU power-on timing does not meet the requirements, posing a risk that the CPU may not function properly. Therefore, this application provides a CPU power-on timing control method, control device, computer-readable storage medium, and electronic device to at least solve the problem of the CPU power-on timing not meeting the requirements during the firmware upgrade of the voltage regulator in related technologies.

[0046] This embodiment provides a method for controlling the power-on timing of the CPU running on the aforementioned mobile terminal. Figure 3This is a flowchart of a CPU power-on timing control method according to an embodiment of this application, as shown below. Figure 3 As shown, the process includes the following steps:

[0047] In step S302, when the motherboard CPLD sends a low-level first control signal to the CPU, the baseboard management controller obtains the updated firmware file and writes the updated firmware file into the firmware of the voltage regulator to upgrade the firmware of the voltage regulator. The low-level first control signal is issued by the motherboard CPLD when it receives a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator. The upgrade control signal is used to indicate the upgrade status of the firmware of the voltage regulator, indicating whether the firmware of the voltage regulator is being upgraded. The second control signal is used to indicate the power supply status of the CPU corresponding to the power supply control signal of the voltage regulator. The first control signal indicates the power-on timing of the CPU.

[0048] Specifically, the CPU in the server is powered by a voltage regulator, and the power-on sequence is controlled by the motherboard's CPLD (Complex Programmable Logic Device). In other words, the motherboard's CPLD controls the changes in high and low voltage levels in the CPU's power-on sequence. When the power-on sequence is high, the voltage regulator can power the CPU; when the power-on sequence is low, the voltage regulator stops powering the CPU. The firmware in the voltage regulator controller usually needs to be upgraded. During the firmware upgrade process, the CPU cannot be powered. Therefore, the firmware upgrade is usually performed when the CPU is in a power-off state, that is, when the server is in a power-off state. After the firmware upgrade of the voltage regulator controller is completed, the CPU needs to be powered on again, that is, to change from a power-off state to a power-on state. The condition for the CPU to be powered on is that all power supplies are powered on. In order to meet the above-mentioned CPU power-on conditions, in step S202, when the motherboard CPLD sends a low-level first control signal to inform the CPU to power off, after the CPU is powered off, the baseboard management controller can obtain the updated firmware file and write the updated firmware file into the voltage regulator controller to complete the firmware upgrade of the voltage regulator controller. The low-level first control signal is issued by the motherboard CPLD when it receives the low-level upgrade control signal sent by the baseboard management controller and the low-level second control signal sent by the voltage regulator controller. The upgrade control signal is low-level, indicating that the updated firmware is about to be written into the firmware of the voltage regulator controller, that is, the firmware of the voltage regulator controller is about to be upgraded.

[0049] Step S304: Determine whether the updated firmware file has been successfully written into the firmware of the voltage regulator. If the writing is successful, send a high-level upgrade control signal to the motherboard CPLD. The high-level upgrade control signal and the high-level second control signal cause the motherboard CPLD to send a high-level first control signal to the CPU after a preset time delay. The high-level second control signal is a signal sent by the voltage regulator to the motherboard CPLD when it receives the high-level power supply control signal.

[0050] Specifically, after the updated firmware file is successfully written to the voltage regulator controller, the baseboard management controller sends a high-level upgrade control signal to the motherboard CPLD, indicating that the firmware upgrade of the voltage regulator controller is complete. Simultaneously, it sends a high-level power supply control signal to the voltage regulator controller, indicating that the voltage regulator controller can supply power to the CPU. The high-level power supply control signal causes the voltage regulator controller to send a high-level second control signal to the motherboard CPLD. Therefore, the high-level upgrade control signal and the high-level second control signal cause the motherboard CPLD to send the aforementioned high-level first control signal to the CPU after a preset time delay. The preset time delay begins when the motherboard CPLD receives both the high-level upgrade control signal and the high-level second control signal. If the high-level upgrade control signal and the high-level second control signal are not received simultaneously by the motherboard CPLD, the preset time delay begins when the last control signal is received. Specifically, this can be set according to the specific application scenario; for example, the preset time delay can be set to 10ms. This application does not impose specific limitations on the value of the aforementioned preset time delay.

[0051] Through the above steps, since the baseboard management controller sends a low-level upgrade control signal to the motherboard CPLD, the motherboard CPLD, after receiving the low-level upgrade control signal and the low-level second control signal, sends a low-level first control signal to the CPU to control the CPU to power down. The low-level first control signal is sent by the voltage regulator controller to the CPLD after receiving the low-level power supply control signal sent by the baseboard management controller. Then, the baseboard management controller obtains the updated firmware file and writes the updated firmware file into the firmware of the voltage regulator controller. After successful writing, it sends a high-level upgrade control signal to the motherboard CPLD, so that the motherboard CPLD, after receiving the high-level upgrade control signal and the high-level second control signal, sends a high-level first control signal to the CPU to control the CPU to power up. The high-level first control signal is sent by the voltage regulator controller to the CPLD after receiving the high-level power supply control signal sent by the baseboard management controller. Compared to existing technologies where the CPU power-on timing remains high throughout the firmware upgrade process of the voltage regulator and cannot change according to the level of the power supply control signal, this application controls the level change of the first control signal by controlling the level change of the upgrade control signal and the level change of the second control signal. The level change of the second control signal can in turn be controlled by the level change of the power supply control signal. By controlling the level change of the first control signal, the CPU power-on timing is further controlled, so that the CPU power-on timing changes accordingly after the level change of the power supply control signal. This satisfies the condition that the CPU power-on timing only becomes high after the power supply control signal is high, i.e., after all the power supplies for the CPU are powered on, in order to control the CPU power-on. This solves the problem that the CPU power-on timing does not meet the conditions during the firmware upgrade process of the voltage regulator, and makes the CPU power-on timing meet the power-on conditions.

[0052] The entity performing the above steps can be a server, but is not limited to this.

[0053] In some embodiments of this application, when the motherboard CPLD outputs a low-level first control signal, the baseboard management controller obtains the updated firmware file, including: determining whether the system containing the CPU is in a power-off state; and if the system containing the CPU is in the power-off state, and the baseboard management controller obtains the updated firmware file when the motherboard CPLD outputs the low-level first control signal. This method ensures that the updated firmware file is only obtained when the CPU is determined to be in a power-off state, thus upgrading the firmware of the voltage regulator controller and preventing situations where the CPU cannot be powered due to firmware upgrades by the voltage regulator controller.

[0054] Specifically, as mentioned in the background section, upgrading the firmware of the voltage regulator controller requires the server to be powered off, i.e., the server's CPU must be powered off. Therefore, before performing the firmware upgrade, it is necessary to first determine whether the CPU is powered off.

[0055] In some embodiments of this application, the low-level second control signal is issued by the voltage regulator controller upon receiving a low-level power supply control signal from the baseboard management controller. This allows the baseboard management controller to instruct the voltage regulator controller to stop supplying power to the CPU by sending a low-level power supply control signal, and the voltage regulator controller to send a low-level second control signal to the motherboard CPLD after stopping power supply to the CPU.

[0056] Specifically, while the baseboard management controller sends a low-level upgrade control signal to the motherboard CPLD to indicate that a firmware upgrade is about to be performed, it also sends a low-level power supply control signal to the voltage regulator controller to inform the voltage regulator controller to stop supplying power to the CPU. This causes the voltage regulator controller to send a low-level second control signal to inform the motherboard CPLD that it has stopped supplying power to the CPU. Therefore, the low-level second control signal is issued by the voltage regulator controller upon receiving the low-level power supply control signal from the baseboard management controller, indicating that the voltage regulator controller has stopped supplying power to the CPU.

[0057] In some embodiments of this application, determining whether the updated firmware file has been successfully written into the firmware of the voltage regulator includes: verifying the updated firmware file written into the voltage regulator and obtaining a verification completion instruction; if the verification completion instruction indicates successful verification, determining that the updated firmware file has been successfully written; if the verification completion instruction indicates failed verification, determining that the updated firmware file has failed to be written. Through this method, the voltage regulator can easily determine whether the firmware upgrade is complete, thereby determining whether to continue with subsequent steps.

[0058] Specifically, after the updated firmware file is written to the firmware of the voltage regulator, the written firmware file is compared with the original updated firmware file. The original updated firmware file is the firmware file before it was written to the firmware of the voltage regulator. If they are the same, the verification is successful to indicate that the firmware writing was successful. If they are different, the verification is failed to indicate that the firmware writing failed.

[0059] In some embodiments of this application, the high-level first control signal is issued by the motherboard CPLD upon receiving a high-level upgrade control signal from the baseboard management controller and a high-level second control signal from the voltage regulator controller. This allows the motherboard CPLD to be notified of a successful firmware upgrade after the voltage regulator controller has been upgraded, via the high-level upgrade control signal and the high-level second control signal, thus enabling the motherboard CPLD to send a high-level first control signal to the CPU to indicate that power-on is possible.

[0060] Specifically, after the firmware upgrade of the voltage regulator is successful, the baseboard management controller sends a high-level upgrade control signal to the motherboard CPLD to indicate that the firmware upgrade is complete. At the same time, it sends a high-level power supply control signal to the voltage regulator, causing the voltage regulator to supply power to the CPU and send a high-level second control signal to the motherboard CPLD to indicate that power can be supplied to the CPU. Therefore, the high-level first control signal is issued by the motherboard CPLD upon receiving the high-level upgrade control signal from the baseboard management controller and the high-level second control signal from the voltage regulator, indicating that the CPU can be powered on.

[0061] In some embodiments of this application, the method further includes: if the updated firmware file fails to be written, rewriting the updated firmware file to the voltage regulator controller. This method, by rewriting the firmware file in the event of a write failure, avoids situations where firmware file writing fails due to accidental factors, ensuring that the updated firmware file can be written to the voltage regulator controller's firmware to upgrade the voltage regulator controller's firmware.

[0062] Specifically, in the event of a write failure, a verification failure command is output. At this point, the updated firmware file needs to be written to the voltage regulator again until the write is successful.

[0063] In some embodiments of this application, writing the updated firmware file into the firmware of the voltage regulator includes: writing the updated firmware file into the firmware of the voltage regulator via a power management bus. This method enables the transfer of the firmware file from the board management controller to the voltage regulator without adding additional transmission equipment.

[0064] Specifically, in the server system, the baseboard management controller and the voltage regulator controller are physically connected through the power management bus, and the firmware files are transferred directly through the power management bus.

[0065] This embodiment provides a method for controlling the power-on timing of the CPU running on the aforementioned mobile terminal, the process including the following steps:

[0066] In step S402, upon receiving a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator controller, the motherboard CPLD sends a low-level first control signal to the CPU. The upgrade control signal is used to indicate the firmware upgrade status of the voltage regulator controller, indicating whether the firmware of the voltage regulator controller is being upgraded. The second control signal is used to indicate the power supply status of the CPU corresponding to the power supply control signal of the voltage regulator controller. The first control signal indicates the power-on timing of the CPU.

[0067] Specifically, the CPU in the server is powered by a voltage regulator, and the power-on sequence is controlled by the motherboard's CPLD (Complex Programmable Logic Device). In other words, the motherboard's CPLD controls the changes in high and low voltage levels in the CPU's power-on sequence. When the power-on sequence is high, the voltage regulator can power the CPU; when the power-on sequence is low, the voltage regulator stops powering the CPU. The firmware in the voltage regulator controller usually needs to be upgraded. During the firmware upgrade process, the CPU cannot be powered. Therefore, the firmware upgrade is usually performed when the CPU is in a power-off state, that is, when the server is in a power-off state. After the firmware upgrade of the voltage regulator controller is completed, the CPU needs to be powered on again, that is, to change from a power-off state to a power-on state. The condition for the CPU to be powered on is that all power supplies have been powered on. In order to meet the above-mentioned CPU power-on conditions, in step S302, the motherboard CPLD sends a low-level first control signal to inform the CPU to power off. The low-level first control signal is issued by the motherboard CPLD after receiving a low-level upgrade control signal sent by the baseboard management controller and a low-level second control signal sent by the voltage regulator controller. The upgrade control signal being low indicates that the updated firmware is about to be written into the firmware of the voltage regulator controller, that is, the firmware of the voltage regulator controller is about to be upgraded.

[0068] Step S404: Receive the high-level upgrade control signal sent by the substrate management controller and the high-level second control signal sent by the voltage regulator controller, and after a preset time delay, send the high-level first control signal to the CPU. The high-level upgrade control signal and the high-level second control signal are generated and sent after the updated firmware file is successfully written into the firmware of the voltage regulator controller. The updated firmware file is used to upgrade the firmware of the voltage regulator controller, and the upgrade of the firmware of the voltage regulator controller is triggered by the low-level upgrade control signal.

[0069] Specifically, the motherboard CPLD sends a high-level first control signal to the CPU after a preset time delay. This high-level first control signal is sent by the motherboard CPLD after receiving a high-level upgrade control signal and a high-level power supply control signal. The high-level power supply control signal causes the voltage regulator controller to send a high-level second control signal to the motherboard CPLD. The preset time period begins when the motherboard CPLD receives the high-level upgrade control signal and the high-level second control signal. If the high-level upgrade control signal and the high-level second control signal are not received simultaneously by the motherboard CPLD, the preset time period begins when the last control signal is received. Specifically, this can be set according to the specific application scenario; for example, the preset time period can be set to 10ms. This application does not impose specific limitations on the value of the preset time period.

[0070] Through the above steps, after receiving the low-level upgrade control signal and the low-level second control signal, the motherboard CPLD sends a low-level first control signal to the CPU to control the CPU to power down. The low-level first control signal is sent to the CPLD by the voltage regulator controller after receiving the low-level power supply control signal sent by the baseboard management controller. Afterwards, after receiving the high-level upgrade control signal and the high-level second control signal, the motherboard CPLD sends a high-level first control signal to the CPU to control the CPU to power up. The high-level first control signal is sent to the CPLD by the voltage regulator controller after receiving the high-level power supply control signal sent by the baseboard management controller. Compared to existing technologies where the CPU power-on timing remains high throughout the firmware upgrade process of the voltage regulator and cannot change according to the level of the power supply control signal, this application controls the level change of the first control signal by controlling the level change of the upgrade control signal and the level change of the second control signal. The level change of the second control signal can in turn be controlled by the level change of the power supply control signal. By controlling the level change of the first control signal, the CPU power-on timing is further controlled, so that the CPU power-on timing changes accordingly after the level change of the power supply control signal. This satisfies the condition that the CPU power-on timing only becomes high after the power supply control signal is high, i.e., after all the power supplies for the CPU are powered on, in order to control the CPU power-on. This solves the problem that the CPU power-on timing does not meet the conditions during the firmware upgrade process of the voltage regulator, and makes the CPU power-on timing meet the power-on conditions.

[0071] The entity performing the above steps can be a server, but is not limited to this.

[0072] In some embodiments of this application, upon receiving a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator controller, the motherboard CPLD sends a low-level first control signal to the CPU. This includes: determining whether the system containing the CPU is in a power-off state; and if the system containing the CPU is in the power-off state, and the motherboard CPLD receives the low-level upgrade control signal from the baseboard management controller and the low-level second control signal from the voltage regulator controller, sending the low-level first control signal to the CPU. This method determines that the CPU is in a power-off state, thus avoiding situations where the CPU cannot be powered due to firmware upgrades by the voltage regulator controller.

[0073] Specifically, as mentioned in the background section, the firmware upgrade of the voltage regulator needs to be performed when the server is powered off, i.e., the server's CPU is powered off. Therefore, before sending the first control signal to indicate that the voltage regulator is about to perform a firmware upgrade, it is necessary to first determine whether the CPU is powered off.

[0074] In some embodiments of this application, the low-level second control signal is issued by the voltage regulator controller upon receiving a low-level power supply control signal from the baseboard management controller. This allows the baseboard management controller to instruct the voltage regulator controller to stop supplying power to the CPU by sending a low-level power supply control signal, and the voltage regulator controller to send a low-level second control signal to the motherboard CPLD after stopping power supply to the CPU.

[0075] Specifically, when the motherboard CPLD receives a low-level upgrade control signal from the baseboard management controller to indicate that a firmware upgrade is about to be performed, it also receives a low-level second control signal from the voltage regulator controller to inform the motherboard CPLD that it has stopped supplying power to the CPU. The low-level second control signal is issued when the baseboard management controller sends a low-level power supply control signal to the voltage regulator controller to inform the voltage regulator controller that it is no longer supplying power to the CPU. Therefore, the low-level second control signal is issued by the voltage regulator controller upon receiving the low-level power supply control signal from the baseboard management controller to indicate that the voltage regulator controller has stopped supplying power to the CPU.

[0076] In some embodiments of this application, the high-level upgrade control signal is issued by the baseboard management controller upon successful verification indicated by a verification completion instruction. This verification completion instruction is obtained by the baseboard management controller after verifying the firmware file written to the voltage regulator. Using this method, the motherboard CPLD can determine that the firmware upgrade of the voltage regulator has been successful based on the high-level upgrade control signal sent by the baseboard management controller.

[0077] Specifically, after receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage regulator controller, the motherboard CPLD sends a high-level first control signal to the CPLD. The high-level upgrade control signal is issued by the baseboard management controller when the verification completion instruction indicates that the verification is successful, that is, the firmware upgrade of the voltage regulator controller is successful.

[0078] In some embodiments of this application, the high-level second control signal is issued by the voltage regulator controller upon receiving the high-level power supply control signal sent by the baseboard management controller. Using this method, the motherboard CPLD can determine that the voltage regulator controller is in a state where it can supply power to the CPU based on the high-level second control signal.

[0079] Specifically, after receiving a high-level upgrade control signal from the baseboard management controller and a high-level second control signal from the voltage regulator controller, the motherboard CPLD sends a high-level first control signal to the CPLD. The high-level second control signal is issued by the voltage regulator controller when it receives a high-level power supply control signal from the baseboard management controller, i.e., when the firmware upgrade of the voltage regulator controller is successful.

[0080] In some embodiments of this application, after sending the high-level first control signal to the CPU, the method further includes controlling the voltage regulator to power on the CPU based on the high-level first control signal. Through this method, the high-level first control signal ensures that the CPU's power-on timing meets the power-on conditions, thus guaranteeing that the CPU powers on when the power-on timing is met and avoiding abnormal CPU operation due to power-on errors.

[0081] Specifically, after the motherboard CPLD sends a low-level first control signal and the firmware upgrade of the voltage regulator is successful, it sends a high-level first control signal. Since the high-level second control signal of the voltage regulator at this time indicates that the voltage regulator can supply power to the CPU, the high-level first control signal is sent to the CPU. The CPU's power-on sequence meets the power-on conditions. Therefore, the voltage regulator is controlled to power on the CPU according to the high-level first control signal.

[0082] In some embodiments of this application, the upgrade control signal sent by the baseboard management controller is received via an I2C bus. This method enables the upgrade control signal to be transmitted from the baseboard management controller to the motherboard CPLD without adding additional transmission equipment.

[0083] Specifically, in a server system, the baseboard management controller and the motherboard CPLD are physically connected via a power management bus, and upgrade control signals are transmitted directly through the power management bus.

[0084] This embodiment provides a method for controlling the power-on timing of the CPU running on the aforementioned mobile terminal, the process including the following steps:

[0085] Step 502: Upon receiving a low-level power supply control signal from the baseboard management controller, the voltage regulator controller sends a low-level second control signal to the motherboard CPLD. The low-level second control signal and the low-level upgrade control signal cause the motherboard CPLD to send a low-level first control signal to the CPU. The power supply control signal indicates whether the voltage regulator controller is supplying power to the CPU, the second control signal indicates the power supply status of the CPU corresponding to the power supply control signal of the voltage regulator controller, the first control signal indicates the power-on sequence of the CPU, and the low-level upgrade control signal is a signal sent from the baseboard management controller to the motherboard CPLD. The upgrade control signal indicates the firmware upgrade status of the voltage regulator controller, and the upgrade status indicates whether the firmware of the voltage regulator controller is being upgraded.

[0086] Specifically, the CPU in the server is powered by a voltage regulator, and the power-on sequence is controlled by the motherboard CPLD (Complex Programmable Logic Device). That is, the CPLD controls the high and low voltage levels in the CPU's power-on sequence. The voltage regulator can only supply power to the CPU when the power-on sequence is high, and stops supplying power when the power-on sequence is low. The firmware in the voltage regulator usually needs to be upgraded. During the firmware upgrade process, power cannot be supplied to the CPU. Therefore, firmware upgrades are typically performed when the CPU is powered off, i.e., when the server is powered off. After the firmware upgrade is complete, the CPU needs to be powered on again, transitioning from a power-off state to a power-on state. The CPU can only be powered on after all power supplies have been powered on. To meet these CPU power-on conditions, in step S402, the voltage regulator sends a low-level second control signal to the CPLD to indicate that the voltage regulator has stopped supplying power to the CPU.

[0087] Step 504: Receive the updated firmware file written by the baseboard management controller. If the updated firmware file is successfully written to the voltage regulator, receive the high-level power supply control signal sent by the baseboard management controller and send the high-level second control signal to the motherboard CPLD. This causes the motherboard CPLD to send the high-level first control signal to the CPU after a preset delay period when it receives the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage regulator.

[0088] Specifically, the voltage regulator receives the updated firmware file sent by the baseboard management controller. If the updated firmware file is successfully written, it receives a high-level power supply control signal from the baseboard management controller to indicate a successful firmware upgrade, supplies power to the CPU, and then sends a high-level second control signal to the motherboard CPLD to indicate power supply to the CPU. After receiving the high-level upgrade control signal and the high-level second control signal, the motherboard CPLD delays for a preset time period before sending a high-level first control signal to the CPU. The preset time period begins when the motherboard CPLD receives both the high-level upgrade control signal and the high-level second control signal. If the high-level upgrade control signal and the high-level second control signal are not received simultaneously by the motherboard CPLD, the preset time period begins when the last control signal is received. This preset time period can be set according to the specific application scenario; for example, it can be set to 10ms. This application does not impose specific limitations on the value of the aforementioned preset time period.

[0089] Through the above steps, after receiving the low-level upgrade control signal and the low-level second control signal, the motherboard CPLD sends a low-level first control signal to the CPU to control the CPU to power down. The low-level first control signal is sent to the CPLD by the voltage regulator controller after receiving the low-level power supply control signal sent by the baseboard management controller. Afterwards, after receiving the high-level upgrade control signal and the high-level second control signal, the motherboard CPLD sends a high-level first control signal to the CPU to control the CPU to power up. The high-level first control signal is sent to the CPLD by the voltage regulator controller after receiving the high-level power supply control signal sent by the baseboard management controller. Compared to existing technologies where the CPU power-on timing remains high throughout the firmware upgrade process of the voltage regulator and cannot change according to the level of the power supply control signal, this application controls the level change of the first control signal by controlling the level change of the upgrade control signal and the level change of the second control signal. The level change of the second control signal can in turn be controlled by the level change of the power supply control signal. By controlling the level change of the first control signal, the CPU power-on timing is further controlled, so that the CPU power-on timing changes accordingly after the level change of the power supply control signal. This satisfies the condition that the CPU power-on timing only becomes high after the power supply control signal is high, i.e., after all the power supplies for the CPU are powered on, in order to control the CPU power-on. This solves the problem that the CPU power-on timing does not meet the conditions during the firmware upgrade process of the voltage regulator, and makes the CPU power-on timing meet the power-on conditions.

[0090] The entity performing the above steps can be a server, but is not limited to this.

[0091] In some embodiments of this application, upon receiving a low-level power supply control signal from the baseboard management controller, the voltage regulator controller sends a low-level second control signal to the motherboard CPLD, including: determining whether the system containing the CPU is in a power-off state; and if the system containing the CPU is in the power-off state, and the voltage regulator controller receives the low-level power supply control signal from the baseboard management controller, sending the low-level second control signal to the motherboard CPLD. This method ensures that the CPU is in a power-off state, thus avoiding situations where the CPU cannot be powered due to firmware upgrades of the voltage regulator controller.

[0092] Specifically, as mentioned in the background section, the firmware upgrade of the voltage regulator needs to be performed when the server is powered off, i.e., the server's CPU is powered off. Therefore, before sending a low-level second control signal to indicate that the voltage regulator is about to be upgraded, it is necessary to first determine whether the CPU is powered off.

[0093] In some embodiments of this application, the low-level first control signal is issued by the motherboard CPLD upon receiving a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator controller. This allows the firmware upgrade indicated by the low-level upgrade control signal and the low-level second control signal to be sent to the motherboard CPLD, causing the motherboard CPLD to send a low-level first control signal to inform the CPU to power down.

[0094] Specifically, the voltage regulator sends a low-level second control signal to the motherboard CPLD to indicate that the voltage regulator stops supplying power to the CPU. At the same time, a low-level upgrade control signal is sent from the baseboard management controller to the motherboard CPLD to indicate that the baseboard management controller is about to upgrade the firmware of the voltage regulator. Therefore, the aforementioned low-level first control signal is issued by the motherboard CPLD upon receiving the low-level upgrade control signal from the baseboard management controller and the aforementioned low-level second control signal from the voltage regulator.

[0095] In some embodiments of this application, the high-level upgrade control signal is issued by the baseboard management controller when a verification completion instruction indicates successful verification. The verification completion instruction is obtained by the baseboard management controller after verifying the firmware file written to the voltage regulator. This method allows the baseboard management controller to send a high-level upgrade control signal to the motherboard CPLD after the firmware upgrade is complete, indicating that the firmware upgrade is finished.

[0096] Specifically, the high-level upgrade control signal is sent by the baseboard management controller after the updated firmware file is written to the voltage regulator and the firmware file is successfully written. Since the baseboard management controller will verify the firmware written to the voltage regulator, it will determine whether the writing is successful by using the verification completion instruction. If the verification completion instruction indicates success, the firmware file is successfully written; if the verification completion instruction indicates failure, the firmware file writing fails.

[0097] In some embodiments of this application, the high-level first control signal is issued by the motherboard CPLD upon receiving a high-level upgrade control signal from the baseboard management controller and a high-level second control signal from the voltage regulator controller. This method allows the motherboard CPLD to be notified of a successful firmware upgrade after the voltage regulator controller has been successfully upgraded via the high-level upgrade control signal and the high-level second control signal, causing the motherboard CPLD to send a high-level first control signal to the CPU to indicate that power-on is possible.

[0098] Specifically, after the firmware upgrade of the voltage regulator is successful, the baseboard management controller sends a high-level upgrade control signal to the motherboard CPLD to indicate that the firmware upgrade is complete. At the same time, it sends a high-level power supply control signal to the voltage regulator, causing the voltage regulator to supply power to the CPU and send a high-level second control signal to the motherboard CPLD to indicate that power can be supplied to the CPU. Therefore, the high-level first control signal is issued by the motherboard CPLD upon receiving the high-level upgrade control signal from the baseboard management controller and the high-level second control signal from the voltage regulator, indicating that the CPU can be powered on.

[0099] In some embodiments of this application, the high-level first control signal is used to control the voltage regulator to power on the CPU. This allows the CPU to power on under the condition that the power-on timing is met.

[0100] Specifically, after the regulator's firmware upgrade is successful, the power supply control signal is at a high level, the first control signal changes from a low level to a high level, and the CPU's power-on sequence meets the power-on conditions. At this time, the regulator controller can be controlled to power on the CPU.

[0101] To enable those skilled in the art to better understand the technical solution of this application, the implementation process of the CPU power-on timing control method of this application will be described in detail below with reference to specific embodiments.

[0102] This embodiment relates to a flowchart of a specific CPU power-on timing control method, as shown in the figure. Figure 4 and Figure 5 As shown, it includes the following steps:

[0103] Step S1: Before the BMC (Baseboard Management Controller) prepares to upgrade the FW (Firmware) file of the VR Controller (Voltage Regulator) online, the server should be powered off and enter the S5 state (power off state).

[0104] Step S2: The BMC (Baseboard Management Controller) writes to the motherboard CPLD register via I2C, setting BMC_VR_UPDATE (upgrade control signal) to 0 (default is 1), informing the motherboard CPLD that the VR_FW (voltage regulator controller firmware) upgrade has begun;

[0105] Step S3: The CPLD outputs BMC_VR_UPDATE (upgrade control signal) = 0 and continuously pulls RSMRST_N (low-level first control signal) low;

[0106] Step S4: The BMC writes to the VR Controller register via PMBUS (Power Management Bus) to turn off the output of S5_VR (Power Supply Control Signal), and the output of S5_VR (Power Supply Control Signal) is turned off (low level);

[0107] Step S5: The BMC flashes the VR FW (updated firmware file of the voltage regulator controller) to the VR Controller via PMBUS (power management bus) and performs verification. If the flashing is successful, proceed to the next step; if the flashing fails, continue to execute step S5.

[0108] Step S6: The BMC writes to the VR Controller (voltage regulator) register via PMBUS (power management bus), turns on the S5_VR (power supply control signal) output and outputs a high level. At the same time, the VR Controller (voltage regulator) output VR_PWRGD (second control signal) changes from a low level to a high level.

[0109] Step S7: The BMC writes to the CPLD register via I2C, setting BMC_VR_UPDATE = 1 (high-level upgrade control signal) to inform the CPLD that the VR_FW (firmware of the voltage regulator controller) upgrade is complete;

[0110] Step S8: The CPLD receives the VR_PWRGD (second control signal) changing from low level to high level, determines that S5_VR (power supply control signal changing from 0 to 1) is supplying power normally, and at the same time, BMC_VR_UPDATE (upgrade control signal) changes from 0 to 1. After a delay of 10ms, it outputs RSMRST_N=1 (high level first control signal);

[0111] Step S9: The online upgrade of the CPU VR Controller's firmware file is complete.

[0112] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / R, second control signal M, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0113] This embodiment also provides a CPU power-on timing control device, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0114] Figure 6 This is a structural block diagram of the CPU power-on timing control device according to an embodiment of this application, as shown below. Figure 6 As shown, the device includes:

[0115] The writing module 22 is used to, when the motherboard CPLD sends a low-level first control signal to the CPU, have the baseboard management controller obtain the updated firmware file and write the updated firmware file into the firmware of the voltage regulator to upgrade the firmware of the voltage regulator. The low-level first control signal is issued by the motherboard CPLD when it receives a low-level upgrade control signal sent by the baseboard management controller and a low-level second control signal sent by the voltage regulator. The upgrade control signal is used to indicate the upgrade status of the firmware of the voltage regulator, indicating whether the firmware of the voltage regulator is being upgraded. The second control signal is used to indicate the power supply status of the CPU corresponding to the power supply control signal of the voltage regulator. The first control signal indicates the power-on timing of the CPU.

[0116] The sending module 24 is used to determine whether the updated firmware file has been successfully written into the firmware of the voltage regulator. If the writing is successful, it sends a high-level upgrade control signal to the motherboard CPLD. The high-level upgrade control signal and the high-level second control signal cause the motherboard CPLD to send a high-level first control signal to the CPU after a preset time delay. The high-level second control signal is a signal sent by the voltage regulator to the motherboard CPLD when it receives the high-level power supply control signal.

[0117] In some embodiments of this application, the writing module includes a determining submodule and a first acquiring submodule. The determining submodule is used to determine whether the system containing the CPU is in a power-off state. The acquiring submodule is used to acquire the updated firmware file when the system containing the CPU is in the power-off state and the baseboard management controller outputs the first control signal with a low level from the motherboard CPLD. This device ensures that the updated firmware file is acquired only when the CPU is determined to be in a power-off state, thus upgrading the firmware of the voltage regulator controller and preventing situations where the CPU cannot be powered due to firmware upgrades by the voltage regulator controller.

[0118] Specifically, as mentioned in the background section, upgrading the firmware of the voltage regulator controller requires the server to be powered off, i.e., the server's CPU must be powered off. Therefore, before performing the firmware upgrade, it is necessary to first determine whether the CPU is powered off.

[0119] In some embodiments of this application, the low-level second control signal is issued by the voltage regulator controller upon receiving a low-level power supply control signal from the baseboard management controller. This allows the baseboard management controller to instruct the voltage regulator controller to stop supplying power to the CPU by sending a low-level power supply control signal, and the voltage regulator controller to send a low-level second control signal to the motherboard CPLD after stopping power supply to the CPU.

[0120] Specifically, while the baseboard management controller sends a low-level upgrade control signal to the motherboard CPLD to indicate that a firmware upgrade is about to be performed, it also sends a low-level power supply control signal to the voltage regulator controller to inform the voltage regulator controller to stop supplying power to the CPU. This causes the voltage regulator controller to send a low-level second control signal to inform the motherboard CPLD that it has stopped supplying power to the CPU. Therefore, the low-level second control signal is issued by the voltage regulator controller upon receiving the low-level power supply control signal from the baseboard management controller, indicating that the voltage regulator controller has stopped supplying power to the CPU.

[0121] In some embodiments of this application, the first sending module includes a second obtaining submodule, a first determining submodule, and a second determining submodule. The first sending submodule is used to verify the updated firmware file written to the voltage regulator and obtain a verification completion instruction. The first determining submodule is used to determine that the updated firmware file was successfully written if the verification completion instruction indicates successful verification. The second determining submodule is used to determine that the updated firmware file was not written if the verification completion instruction indicates failed verification. Through this device, the voltage regulator can conveniently determine whether the firmware upgrade is complete, thereby determining whether to continue with subsequent steps.

[0122] Specifically, after the updated firmware file is written to the firmware of the voltage regulator, the written firmware file is compared with the original updated firmware file. The original updated firmware file is the firmware file before it was written to the firmware of the voltage regulator. If they are the same, the verification is successful to indicate that the firmware writing was successful. If they are different, the verification is failed to indicate that the firmware writing failed.

[0123] In some embodiments of this application, the high-level first control signal is issued by the motherboard CPLD upon receiving a high-level upgrade control signal from the baseboard management controller and a high-level second control signal from the voltage regulator controller. This allows the motherboard CPLD to be notified of a successful firmware upgrade after the voltage regulator controller has been upgraded, via the high-level upgrade control signal and the high-level second control signal, thus enabling the motherboard CPLD to send a high-level first control signal to the CPU to indicate that power-on is possible.

[0124] Specifically, after the firmware upgrade of the voltage regulator is successful, the baseboard management controller sends a high-level upgrade control signal to the motherboard CPLD to indicate that the firmware upgrade is complete. At the same time, it sends a high-level power supply control signal to the voltage regulator, causing the voltage regulator to supply power to the CPU and send a high-level second control signal to the motherboard CPLD to indicate that power can be supplied to the CPU. Therefore, the high-level first control signal is issued by the motherboard CPLD upon receiving the high-level upgrade control signal from the baseboard management controller and the high-level second control signal from the voltage regulator, indicating that the CPU can be powered on.

[0125] In some embodiments of this application, the above-described apparatus further includes a writing submodule, configured to rewrite the updated firmware file to the voltage regulator controller if the writing of the updated firmware file fails. This apparatus, by rewriting the firmware file in the event of a writing failure, avoids situations where the firmware file writing fails due to accidental factors, ensuring that the updated firmware file can be written to the voltage regulator controller's firmware to upgrade the voltage regulator controller's firmware.

[0126] Specifically, in the event of a write failure, a verification failure command is output. At this point, the updated firmware file needs to be written to the voltage regulator again until the write is successful.

[0127] In some embodiments of this application, the writing module includes a writing submodule for writing the updated firmware file to the firmware of the voltage regulator via the power management bus. This device enables the firmware file to be transferred from the baseboard management controller to the voltage regulator without adding additional transmission equipment.

[0128] Specifically, in the server system, the baseboard management controller and the voltage regulator controller are physically connected through the power management bus, and the firmware files are transferred directly through the power management bus.

[0129] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0130] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when it is run.

[0131] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0132] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0133] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0134] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0135] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0136] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for controlling the CPU power-on timing, characterized in that, include: When the motherboard CPLD sends a low-level first control signal to the CPU, the baseboard management controller obtains the updated firmware file and writes the updated firmware file into the firmware of the voltage regulator to upgrade the firmware of the voltage regulator. The low-level first control signal is issued by the motherboard CPLD upon receiving a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator. The upgrade control signal is used to indicate the upgrade status of the firmware of the voltage regulator, indicating whether the firmware of the voltage regulator is being upgraded. The second control signal is used to indicate the power supply status of the CPU corresponding to the power supply control signal of the voltage regulator. The first control signal indicates the power-on timing of the CPU. Determine whether the updated firmware file has been successfully written into the firmware of the voltage regulator controller. If the writing is successful, send a high-level upgrade control signal to the motherboard CPLD. The high-level upgrade control signal and the high-level second control signal cause the motherboard CPLD to send a high-level first control signal to the CPU after a preset time delay. The high-level second control signal is a signal sent by the voltage regulator controller to the motherboard CPLD when it receives the high-level power supply control signal.

2. The control method according to claim 1, characterized in that, When the motherboard CPLD sends a low-level first control signal to the CPU, the baseboard management controller obtains the updated firmware file, including: Determine whether the system containing the CPU is in a powered-off state; When the system containing the CPU is in the power-off state and the baseboard management controller obtains the updated firmware file when the motherboard CPLD outputs a low-level first control signal.

3. The control method according to claim 1, characterized in that, The low-level second control signal is issued by the voltage regulator controller upon receiving the low-level power supply control signal from the substrate management controller.

4. The control method according to claim 1, characterized in that, Determining whether the updated firmware file has been successfully written to the firmware of the voltage regulator includes: The updated firmware file written to the voltage regulator is verified, and a verification completion instruction is obtained; If the verification completion command indicates that the verification was successful, it is determined that the updated firmware file was successfully written. If the verification completion instruction indicates a verification failure, it is determined that the updated firmware file was not written.

5. The control method according to claim 1, characterized in that, The high-level first control signal is issued by the motherboard CPLD when it receives the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage regulator controller.

6. The control method according to claim 1, characterized in that, The method further includes: If the updated firmware file fails to be written, the updated firmware file will be written to the voltage regulator controller again.

7. The control method according to any one of claims 1 to 6, characterized in that, Write the updated firmware file into the firmware of the voltage regulator controller, including: The updated firmware file is written into the firmware of the voltage regulator via the power management bus.

8. A method for controlling the power-on timing of a CPU, characterized in that, include: Upon receiving a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator controller, the motherboard CPLD sends a low-level first control signal to the CPU. The upgrade control signal indicates the firmware upgrade status of the voltage regulator controller, indicating whether the firmware of the voltage regulator controller is being upgraded. The second control signal indicates the power supply status of the CPU corresponding to the power supply control signal of the voltage regulator controller. The first control signal indicates the power-on timing of the CPU. The system receives a high-level upgrade control signal from the baseboard management controller and a high-level second control signal from the voltage regulator controller, and after a preset time delay, sends a high-level first control signal to the CPU. The high-level upgrade control signal and the high-level second control signal are generated and sent when the updated firmware file is successfully written into the firmware of the voltage regulator controller. The updated firmware file is used to upgrade the firmware of the voltage regulator controller, and the upgrade of the firmware of the voltage regulator controller is triggered by the low-level upgrade control signal.

9. The control method according to claim 8, characterized in that, Upon receiving a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator controller, the motherboard CPLD sends a low-level first control signal to the CPU, including: Determine whether the system containing the CPU is in a powered-off state; When the system containing the CPU is in the shutdown state, and the motherboard CPLD receives a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator controller, it sends a low-level first control signal to the CPU.

10. The control method according to claim 8, characterized in that, The low-level second control signal is issued by the voltage regulator controller upon receiving the low-level power supply control signal from the substrate management controller.

11. The control method according to claim 8, characterized in that, The high-level upgrade control signal is issued by the baseboard management controller when the verification completion instruction indicates successful verification. The verification completion instruction is the instruction obtained by the baseboard management controller after verifying the firmware file written to the voltage regulator controller.

12. The control method according to claim 8, characterized in that, The high-level second control signal is issued by the voltage regulator controller upon receiving the high-level power supply control signal from the substrate management controller.

13. The control method according to claim 8, characterized in that, After sending the first high-level control signal to the CPU, the method further includes: The voltage regulator controller powers on the CPU based on the high-level first control signal.

14. The control method according to any one of claims 8 to 13, characterized in that, The upgrade control signal is received from the baseboard management controller via the I2C bus.

15. A method for controlling the power-on timing of a CPU, characterized in that, include: Upon receiving a low-level power supply control signal from the baseboard management controller, the voltage regulator controller sends a low-level second control signal to the motherboard CPLD. The low-level second control signal and the low-level upgrade control signal cause the motherboard CPLD to send a low-level first control signal to the CPU. The power supply control signal indicates whether the voltage regulator controller is supplying power to the CPU, the second control signal indicates the power supply status of the CPU corresponding to the power supply control signal of the voltage regulator controller, the first control signal indicates the power-on timing of the CPU, and the low-level upgrade control signal is a signal sent by the baseboard management controller to the motherboard CPLD. The upgrade control signal indicates the firmware upgrade status of the voltage regulator controller, and the upgrade status indicates whether the firmware of the voltage regulator controller is being upgraded. The system receives the updated firmware file written by the baseboard management controller. If the updated firmware file is successfully written to the voltage regulator controller, the system receives the high-level power supply control signal sent by the baseboard management controller and sends a high-level second control signal to the motherboard CPLD. This causes the motherboard CPLD to send a high-level first control signal to the CPU after a preset time delay, upon receiving the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage regulator controller.

16. The control method according to claim 15, characterized in that, Upon receiving a low-level power supply control signal from the baseboard management controller, the voltage regulator controller sends a low-level second control signal to the motherboard CPLD, including: Determine whether the system containing the CPU is in a powered-off state; When the system containing the CPU is in the shutdown state, and the voltage regulator receives a low-level power supply control signal from the baseboard management controller, it sends a low-level second control signal to the motherboard CPLD.

17. The control method according to claim 15, characterized in that, The low-level first control signal is issued by the motherboard CPLD upon receiving a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator controller.

18. The control method according to claim 15, characterized in that, The high-level upgrade control signal is issued by the baseboard management controller when the verification completion instruction indicates successful verification. The verification completion instruction is the instruction obtained by the baseboard management controller after verifying the firmware file written to the voltage regulator controller.

19. The control method according to claim 15, characterized in that, The high-level first control signal is issued by the motherboard CPLD when it receives the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage regulator controller.

20. The control method according to any one of claims 15 to 19, characterized in that, The high-level first control signal is used to control the voltage regulator to power on the CPU.

21. A control device for CPU power-on timing, characterized in that, include: The writing module is used to, when the motherboard CPLD sends a low-level first control signal to the CPU, have the baseboard management controller obtain an updated firmware file and write the updated firmware file into the firmware of the voltage regulator to upgrade the firmware of the voltage regulator. The low-level first control signal is issued by the motherboard CPLD upon receiving a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator. The upgrade control signal indicates the upgrade status of the voltage regulator's firmware, indicating whether the firmware is being upgraded. The second control signal indicates the power supply status of the CPU corresponding to the power supply control signal of the voltage regulator. The first control signal indicates the power-on timing of the CPU. The sending module is used to determine whether the updated firmware file has been successfully written into the firmware of the voltage regulator controller. If the writing is successful, a high-level upgrade control signal is sent to the motherboard CPLD. The high-level upgrade control signal and the high-level second control signal cause the motherboard CPLD to send a high-level first control signal to the CPU after a preset time delay. The high-level second control signal is a signal sent to the motherboard CPLD by the voltage regulator controller when it receives the high-level power supply control signal.

22. A control device for CPU power-on timing, characterized in that, include: The first transmitting module is configured to, upon receiving a low-level upgrade control signal from the baseboard management controller and a low-level second control signal from the voltage regulator controller, send a low-level first control signal to the CPU via the motherboard CPLD. The upgrade control signal is used to indicate the firmware upgrade status of the voltage regulator controller, indicating whether the firmware of the voltage regulator controller is being upgraded. The second control signal is used to indicate the power supply status of the CPU corresponding to the power supply control signal of the voltage regulator controller. The first control signal indicates the power-on timing of the CPU. The second transmitting module is configured to receive a high-level upgrade control signal sent by the baseboard management controller and a high-level second control signal sent by the voltage regulator controller, and after a preset time delay, send a high-level first control signal to the CPU. The high-level upgrade control signal and the high-level second control signal are generated and sent when the updated firmware file is successfully written into the firmware of the voltage regulator controller. The updated firmware file is used to upgrade the firmware of the voltage regulator controller, and the upgrade of the firmware of the voltage regulator controller is triggered by the low-level upgrade control signal.

23. A control device for CPU power-on timing, characterized in that, include: The first transmitting module is configured to, upon receiving a low-level power supply control signal from the baseboard management controller, send a low-level second control signal to the motherboard CPLD. The low-level second control signal and the low-level upgrade control signal cause the motherboard CPLD to send a low-level first control signal to the CPU. The power supply control signal indicates whether the voltage regulator is supplying power to the CPU, the second control signal indicates the power supply status of the CPU corresponding to the voltage regulator's power supply control signal, the first control signal represents the CPU's power-on timing, and the low-level upgrade control signal is a signal sent from the baseboard management controller to the motherboard CPLD. The upgrade control signal indicates the firmware upgrade status of the voltage regulator, and the upgrade status indicates whether the voltage regulator's firmware is being upgraded. The second transmitting module is used to receive the updated firmware file written by the baseboard management controller. When the updated firmware file is successfully written to the voltage regulator controller, it receives the high-level power supply control signal sent by the baseboard management controller and sends a high-level second control signal to the motherboard CPLD. This causes the motherboard CPLD to send a high-level first control signal to the CPU after a preset time delay when it receives the high-level upgrade control signal sent by the baseboard management controller and the high-level second control signal sent by the voltage regulator controller.

24. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7, or the steps of the method according to any one of claims 8 to 14, or the steps of the method according to any one of claims 15 to 20.

25. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7, or the steps of the method according to any one of claims 8 to 14, or the steps of the method according to any one of claims 15 to 20.

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