Scan driving circuit, display device and driving method thereof

Abstract

The application discloses a scanning driving circuit, a display device and a driving method thereof. The scanning driving circuit comprises a plurality of shift registers arranged in cascade. The shift register comprises a driving control module, a stage transmission output module, a transmission control module and a scanning output module. The driving control module is used for controlling the potential of the first output end and the second output end of the driving control module according to an input signal; the stage transmission output module is used for outputting a stage transmission signal in response to the potential of the first output end and the second output end; the stage transmission signal is used as a next stage input signal; the first connecting end of the transmission control module is connected with the first output end or the second output end, and the second connecting end is connected with the scanning output module; the transmission control module is used for controlling the potential of the second connecting end of the transmission control module according to the stage transmission signal and a frequency division signal, so as to control the frequency of the scanning signal output by the scanning output module. The embodiment of the application can make the display device have the function of partition frequency display.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a scan driving circuit, a display device and a driving method thereof. BACKGROUND

[0002] With the development of display technology, the application scenarios of display devices are more and more, and the display requirements of users for display devices are more and more diversified. Based on the release of folding mobile phones and folding laptops, the application scenarios of display devices are further expanded. For the user's demand for multiple applications to be displayed simultaneously on a terminal product, part of the interface (such as a game interface) in the display screen needs to be displayed at a high frequency to ensure the smoothness of the picture, and part of the interface can meet the display requirement by using low frequency. This part is expected to use low frequency display to reduce product power consumption. However, the scan driving circuit in the prior art cannot meet the user's demand for displaying multiple scenes in one screen of a terminal product, and cannot realize the partition frequency display of the display device. SUMMARY

[0003] The present application provides a scan driving circuit, a display device and a driving method thereof, so as to make the display device have the function of partition frequency display.

[0004] In a first aspect, an embodiment of the present application provides a scan driving circuit, comprising: a plurality of shift registers connected in cascade;

[0005] The shift register comprises:

[0006] A driving control module, the driving control module is configured to control the potential of a first output end and a second output end of the driving control module according to an input signal of the shift register;

[0007] A stage transmission output module connected to the first output end and the second output end respectively, configured to output a stage transmission signal in response to the potential of the first output end and the second output end; the stage transmission signal is used as an input signal of a next stage shift register;

[0008] A transmission control module, a first connection end of the transmission control module is connected to the first output end or the second output end, an input end of the transmission control module is connected to a frequency switching signal, and a control end of the transmission control module is connected to an output end of the stage transmission output module;

[0009] A scan output module connected to a second connection end of the transmission control module, configured to output a scan signal in response to the potential of the second connection end; wherein the transmission control module is configured to control the potential of the second connection end according to the stage transmission signal and the frequency switching signal, so as to control the frequency of the scan signal.

[0010] Optionally, an input end of the transmission control module in each stage of the shift register is connected to the same frequency switching signal.

[0011] The frequency switching signal keeps the potential unchanged in some display frames and changes the potential in some display frames, so that the frequencies of the scanning signals output by at least two shift registers are different, thereby realizing the sub-region frequency division display of the display device.

[0012] Optionally, the transmission control module comprises:

[0013] An output control unit, an input end of the output control unit is connected to the first connection end, and an output end of the output control unit is connected to the second connection end; the output control unit is configured to control the potential of the second connection end according to the potential of the control end of the output control unit;

[0014] An isolation protection unit, a control end of the isolation protection unit is connected to the output end of the stage transmission output module, an input end of the isolation protection unit is connected to the frequency switching signal, and an output end of the isolation protection unit is connected to the control end of the output control unit; the isolation protection unit is configured to cut off the transmission path of the frequency switching signal to the control end of the output control unit in response to the stage transmission signal;

[0015] Preferably, the output control unit comprises a first transistor; a gate of the first transistor is used as the control end of the output control unit, a first pole of the first transistor is used as the input end of the output control unit, and a second pole of the first transistor is used as the output end of the output control unit.

[0016] The isolation protection unit comprises a second transistor; a gate of the second transistor is used as the control end of the isolation protection unit, a first pole of the second transistor is used as the input end of the isolation protection unit, and a second pole of the second transistor is used as the output end of the isolation protection unit.

[0017] Optionally, the shift register further comprises a node potential control module, a control end of the node potential control module is connected to the first output end or connected to the stage transmission signal output by the current stage of the shift register, an input end of the node potential control module is connected to a first potential signal line, and an output end of the node potential control module is connected to the second connection end; the node potential control module is configured to transmit the first potential signal provided by the first potential signal line to the second connection end in response to the potential of the control end of the node potential control module.

[0018] Preferably, the node potential control module comprises a third transistor; a gate of the third transistor is used as a control terminal of the node potential control module; a first pole of the third transistor is used as an input terminal of the node potential control module; and a second pole of the third transistor is used as an output terminal of the node potential control module.

[0019] Optionally, the first connection terminal is connected to the second output terminal; a first control terminal of the scan output module is connected to the first output terminal; a second control terminal of the scan output module is connected to the second connection terminal; and a potential of the second connection terminal is used to control whether the scan output module outputs the on potential of the scan signal.

[0020] Optionally, the scan output module comprises:

[0021] a first output unit, which is electrically connected to the first output terminal, and is used to transmit a second potential signal to an output terminal of the scan output module in response to an on potential of the first output terminal;

[0022] a second output unit, which is electrically connected to the second connection terminal, and is used to transmit a first potential signal to the output terminal of the scan output module in response to an on potential of the second connection terminal;

[0023] Preferably, the first output unit comprises a fourth transistor; a gate of the fourth transistor is connected to the first output terminal; a first pole of the fourth transistor is connected to a second potential signal line; and a second pole of the fourth transistor is connected to the output terminal of the scan output module.

[0024] The second output unit comprises a fifth transistor and a first capacitor; a gate of the fifth transistor is connected to the second connection terminal; a first pole of the fifth transistor is connected to a first potential signal line; a second pole of the fifth transistor is connected to the output terminal of the scan output module; and the first capacitor is connected between the gate and the first pole of the fifth transistor.

[0025] Optionally, the stage transmission output module comprises:

[0026] a third output unit, which is electrically connected to the first output terminal, and is used to transmit a second potential signal to an output terminal of the stage transmission output module in response to an on potential of the first output terminal;

[0027] a fourth output unit, which is electrically connected to the second output terminal, and is used to transmit a first potential signal to the output terminal of the stage transmission output module in response to an on potential of the second output terminal;

[0028] Preferably, the third output unit comprises a sixth transistor; a gate of the sixth transistor is connected to the first output end, a first pole of the sixth transistor is connected to a second potential signal line, and a second pole of the sixth transistor is connected to an output end of the stage transmission output module.

[0029] The fourth output unit comprises a seventh transistor and a second capacitor; a gate of the seventh transistor is connected to the second output end, a first pole of the seventh transistor is connected to a first potential signal line, and a second pole of the seventh transistor is connected to the output end of the stage transmission output module; and the second capacitor is connected between the gate and the first pole of the seventh transistor.

[0030] Optionally, the driving control module comprises:

[0031] an input unit, an output end of the input unit being connected to the first output end, for transmitting the input signal to the first output end in response to a first clock signal;

[0032] a first control unit, for transmitting a second potential signal to an output end of the first control unit in response to the first clock signal;

[0033] a second control unit, connected between the output end of the first control unit and the second output end, for controlling a potential of the second output end according to a second clock signal and the potential of the output end of the first control unit;

[0034] a first node control unit, connected to the first output end and the output end of the first control unit respectively, for controlling the potential of the output end of the first control unit according to the potential of the first output end;

[0035] a second node control unit, connected to the first output end and the output end of the first control unit respectively, for controlling the potential of the first output end according to the potential of the output end of the first control unit;

[0036] a third node control unit, connected to the first output end and the second output end respectively, for controlling the potential of the second output end according to the potential of the first output end;

[0037] Preferably, the driving control module further comprises a protection unit, a first end of the protection unit being connected to the output end of the input unit, a second end of the protection unit being connected to the first output end, and a control end of the protection unit being connected to a second potential signal line.

[0038] The first node control unit is connected to the first end of the protection unit; the second node control unit is connected to the first end or the second end of the protection unit; and the third node control unit is connected to the first end of the protection unit.

[0039] Preferably, the shift register further comprises: a node potential control module; a control end of the node potential control module is connected to the first end of the protection unit or the first output end, or accesses a stage transmission signal output by the current stage shift register; an input end of the node potential control module is connected to a first potential signal line; and an output end of the node potential control module is connected to the second output end.

[0040] In a second aspect, the embodiments of the present application further provide a display device, comprising: a pixel circuit and the scan driving circuit provided by any of the embodiments of the present application.

[0041] In a third aspect, the embodiments of the present application further provide a driving method of a display device, for driving the display device provided by any of the embodiments of the present application, and the driving method comprises:

[0042] The frequency switching signal is controlled to keep the potential unchanged in part of the display frames and to make potential jump in part of the display frames, so that the frequencies of the scan signals output by at least two shift registers are different, to realize the partition frequency display of the display device.

[0043] Optionally, the frequency switching signal makes potential jump after the on potential of the stage transmission signal output by a previous stage shift register and before the on potential of the stage transmission signal output by the current stage shift register, to control the frequency of the current stage scan signal to be different from the frequency of the previous stage scan signal.

[0044] The scan driving circuit provided by the embodiments of the present application comprises a plurality of shift registers arranged in cascade, and each stage shift register comprises a driving control module, a stage transmission output module, a transmission control module and a scan output module. Based on the control of the driving control module on the first output end and the second output end, the stage transmission output module of each stage can realize the step-by-step shift output of the first stage input signal, and provide a basis for freely selecting the output of the scan signal with the same frequency as the first stage input signal or with a frequency lower than the first stage input signal by each stage shift register. Through the cooperation between the stage transmission signals and the frequency switching signal, the on / off of the first connection end and the second connection end of the transmission control module can be adjusted to allow / block the potential of the first output end to be transmitted to the second connection end of the transmission control module, so as to allow / block the on potential of the scan signal output by the scan output module, to realize the control of the working mode of the shift register. Through the control of the potential jump process of the frequency switching signal, the working mode combination of at least two stages of shift registers can be made different, so that the frequencies of the scan signals output by at least two stages of shift registers are different, to realize the partition frequency display of the display device. In summary, compared with the prior art, the embodiments of the present application can make the display device support the partition frequency display function.

[0045] It is to be understood that the details set forth herein do not limit the scope of the embodiments of the application to the specific embodiments described. The foregoing detailed description has been presented for purposes of clarity and description. It is not intended to be exhaustive or to limit the application to the precise form described, and many modifications and variations are possible in light of the above teachings. It is intended that the scope of the application be defined by the claims appended hereto. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0047] Figure 1 is a structural schematic diagram of a scanning driving circuit provided by an embodiment of the present application;

[0048] Figure 2 is a driving timing diagram of a display panel provided by an embodiment of the present application;

[0049] Figure 3 is a driving timing diagram of a display panel provided by an embodiment of the present application;

[0050] Figure 4 is a structural schematic diagram of a shift register provided by an embodiment of the present application;

[0051] Figure 5 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0052] Figure 6 is a driving timing diagram of a shift register in a first working mode provided by an embodiment of the present application;

[0053] Figure 7 is a driving timing diagram of another shift register in a first working mode provided by an embodiment of the present application;

[0054] Figure 8 is a driving timing diagram of a shift register in a second working mode provided by an embodiment of the present application;

[0055] Figure 9 is a driving timing diagram of another shift register in a second working mode provided by an embodiment of the present application;

[0056] Figure 10 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0057] Figure 11 is a structural schematic diagram of another shift register provided by an embodiment of the present application;

[0058] Figure 12 is a driving timing diagram of a shift register in a first working mode according to an embodiment of the present application;

[0059] Figure 13 is a structural diagram of a shift register according to an embodiment of the present application;

[0060] Figure 14 is a structural diagram of a display panel according to an embodiment of the present application;

[0061] Figure 15 is a driving timing diagram of another display panel according to an embodiment of the present application;

[0062] Figure 16 is a driving timing diagram of another display panel according to an embodiment of the present application;

[0063] Figure 17 is a structural diagram of a pixel circuit according to an embodiment of the present application;

[0064] Figure 18 is a driving timing diagram of a pixel circuit according to an embodiment of the present application;

[0065] Figure 19 is a structural diagram of another display panel according to an embodiment of the present application;

[0066] Figure 20 is a driving timing diagram of another display panel according to an embodiment of the present application;

[0067] Figure 21 is a structural diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0068] In order to make the persons skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the persons skilled in the art without creative labor should belong to the protection scope of the present application.

[0069] It should be noted that the terms "first", "second", and the like in the description and claims of the application and the above drawings are used to distinguish between similar objects and not necessarily describe a particular sequential or chronological order. It should be understood that the use of such terms herein is intended to cover the embodiments of the application described herein as appropriate whether or not explicit reference is made to them in other contexts. Furthermore, the terms "comprising", "having", "including", and any variations thereof are intended to cover a non-exclusive inclusion.

[0070] The embodiment of the application provides a scanning driving circuit to enable a display device to support a function of displaying in different frequencies in a screen. Figure 1 is a structural schematic diagram of a scanning driving circuit provided by the embodiment of the application. Referring to Figure 1 The scanning driving circuit comprises a plurality of shift registers 10 which are arranged in cascade, and each shift register 10 can have the same structure. Figure 1 The first two shift registers 10 are exemplarily shown in The shift register 10 can comprise a driving control module 110, a stage transmission output module 120, a transmission control module 130 and a scanning output module 140.

[0071] The driving control module 110 is configured to control the potentials of a first output end N1 and a second output end N2 of the driving control module 110 according to an input signal of the shift register 10. The stage transmission output module 120 is connected to the first output end N1 and the second output end N2 respectively, and is configured to output a stage transmission signal in response to the potentials of the first output end N1 and the second output end N2; the stage transmission signal is used as an input signal of a next shift register 10. The first connection end N3 of the transmission control module 130 is connected to the first output end N1 or the second output end N2 (the second output end N2 is exemplarily shown in Figure 1 The input end of the transmission control module 130 is connected to a frequency switching signal SW, and the control end of the transmission control module 130 is connected to the output end of the stage transmission output module 120; the transmission control module 130 is configured to control the potential of a second connection end N4 of the transmission control module 130 according to the stage transmission signal and the frequency switching signal SW. The scanning output module 140 is connected to the second connection end N4, and is configured to output a scanning signal to an output end of the shift register 10 in response to the potential of the second connection end N4; wherein the transmission control module 130 controls the frequency of the scanning signal by controlling the potential of the second connection end N4.

[0072] The cascade mode of each shift register 10 can be referred to Figure 1 , for example Figure 1As shown, the first stage shift register 101 receives the first stage input signal EIN1, outputs the first stage carry signal Carry1 according to the first stage input signal EIN1, and outputs the first stage scan signal EOUT1 in combination with the clock signal SW. The first stage carry signal Carry1 is transmitted to the second stage shift register 102 as the second stage input signal EIN2. The second stage shift register 102 outputs the second stage carry signal Carry2 (as the third stage input signal EIN3) according to the second stage input signal EIN2, and outputs the second stage scan signal EOUT2 in combination with the clock signal SW, and so on.

[0073] Exemplarily, the carry output module 120 and the scan output module 140 can be output modules with the same structure. The output module can include two control terminals, a turn-on potential input terminal, a turn-off potential input terminal, and an output terminal. The potential of one of the control terminals is used to control whether the turn-off potential input terminal is in communication with the output terminal, and the potential of the other control terminal is used to control whether the turn-on potential input terminal is in communication with the output terminal, so that the output module controls the output signal of the output module to be a turn-on potential or a turn-off potential based on the potentials of the first control terminal and the second control terminal of the output module. It should be noted that the turn-on potential can be understood as a potential for controlling the turn-on of a functional module connected to the output terminal of the output module, and correspondingly, the turn-off potential can be understood as a potential for controlling the turn-off of the functional module connected to the output terminal of the output module. For example, when the functional module includes an N-type transistor, the turn-on potential is a high potential and the turn-off potential is a low potential. The following exemplary description is based on the first control terminal of the output module corresponding to the turn-off potential input terminal and the second control terminal corresponding to the turn-on potential input terminal.

[0074] Then, for the carry output module 120, the two output terminals of the drive control module 110 can be respectively connected to the two control terminals of the carry output module 120, so that the drive control module 110 controls the carry output module 120 to output the carry signal by controlling the potentials of the first output terminal N1 and the second output terminal N2. For example, the first output terminal N1 can be connected to the first control terminal of the carry output module 120, and the second output terminal N2 can be connected to the second control terminal of the carry output module 120. Based on the potential control of the drive control module 110 on the first output terminal N1 and the second output terminal N2, the carry output module 120 can realize the shift output of the turn-on pulse of the input signal. Figure 2 Exemplarily, the output waveform of the 6-stage register 10 is shown in FIG. 6. Referring to FIG. 6, the first stage input signal EIN1 is a pulse signal with a period of 8T, and the clock signal SW is a pulse signal with a period of 4T. The first stage scan signal EOUT1 is a pulse signal with a period of 8T, and the second stage scan signal EOUT2 is a pulse signal with a period of 4T. The third stage scan signal EOUT3 is a pulse signal with a period of 2T, and the fourth stage scan signal EOUT4 is a pulse signal with a period of 1T. The fifth stage scan signal EOUT5 is a pulse signal with a period of 0.5T, and the sixth stage scan signal EOUT6 is a pulse signal with a period of 0.25T. Figure 2It can be seen that the shift register 10 is cascaded through the stage transmission output module 120, and the conduction pulse of the first stage input signal EIN1 can be shifted and output stage by stage, and a high-frequency stage transmission signal sequence with the same frequency as the first stage input signal EIN1 is provided, so that the scanning output module 140 can freely select whether to output the conduction pulse based on the control of the transmission control module 130. The frequency of the first stage input signal EIN1 can be understood as the pulse frequency of the conduction pulse.

[0075] The second connection end N4 of the transmission control module 130 can be connected to the second control end of the scanning output module 140, so that the transmission control module 130 controls whether the scanning output module 140 outputs the conduction potential of the scanning signal by controlling the potential of the second connection end N4. The two output ends of the drive control module 110 can be connected to the first connection end N3 of the transmission control module 130 and the first control end of the scanning output module 140, respectively. For example, the first output end N1 can be connected to the first control end of the scanning output module 140, and the second output end N2 can be connected to the first connection end N3 of the transmission control module 130.

[0076] For any shift register 10, the stage transmission signal and the frequency cutting signal SW control whether the potential of the second output end N2 can be transmitted to the second connection end N4 by controlling the conduction state of the transmission control module 130, and further control whether the scanning output module 140 outputs the conduction potential, so as to control the working mode of the shift register 10.

[0077] Specifically, the transmission control module 130 can control the scanning output module 140 to work in the following two working modes:

[0078] In the first working mode, the transmission control module 130 keeps on during the stage in which the stage transmission output module 120 outputs the conduction potential, and then the potential of the second output end N2 can be transmitted to the second connection end N4, and the conduction potential input end and the output end of the scanning output module 140 can be controlled to be connected, so that the stage scanning signal also has the conduction potential. Therefore, the stage transmission signal and the scanning signal both have the conduction pulse.

[0079] In the second working mode, the transmission control module 130 keeps off during the stage in which the stage transmission output module 120 outputs the conduction potential, so that the potential of the second output end N2 cannot be transmitted to the second connection end N4, and thus the conduction potential input end and the output end of the scanning output module 140 cannot be controlled to be connected, and the stage scanning signal keeps the cut-off potential and cannot jump to the conduction potential. Therefore, only the stage transmission signal has the conduction pulse, and the scanning signal does not have the conduction pulse.

[0080] When the stage shift register 10 is in the first working mode in each display frame, the stage transfer signal outputted by the stage shift register 10 has the same frequency as the scanning signal; when the stage shift register 10 is in the second working mode in at least part of the display frame, the frequency of the scanning signal outputted by the stage shift register 10 is lower than the frequency of the stage transfer signal outputted by the stage shift register 10.

[0081] Exemplarily, each stage scanning signal is transmitted to the functional module related to the data writing process in the pixel circuit of each row through each row scanning line. When a stage shift register 10 is in the first working mode, the pixel circuit of the corresponding row can be controlled to refresh data due to the scanning signal containing the on-pulse, so that the current frame of the pixel circuit of the corresponding row is a refresh frame; when a stage shift register 10 is in the second working mode, the pixel circuit of the corresponding row cannot refresh data due to the scanning signal not containing the on-pulse, so that the current frame of the pixel circuit of the corresponding row is a hold frame. Therefore, the frequency of the scanning signal determines the data refresh frequency of the pixel circuit. Based on this, the frequency of each stage scanning signal can be controlled by controlling the working mode of each stage shift register 10 in each display frame, and the display device can realize display with different frequencies in the column direction by controlling the frequencies of at least two stage scanning signals to be different.

[0082] For example, in the case of a three-part screen in Figure 2 , it is assumed that the display panel is divided into a first display area A1, a second display area A2 and a third display area A3 from top to bottom, and the refresh frequencies of the three display areas are f1, f2 and f1 in turn, for example, f1 > f2. Then, from the first display area A1 to the second display area A2, it is equivalent to realize frequency division display with the display frequency changing from high to low, and from the second display area A2 to the third display area A3, it is equivalent to realize frequency division display with the display frequency changing from low to high. The size of each display area is determined by the number of stage shift registers 10 providing scanning signals with corresponding frequencies. For example, in the case of each display area corresponding to two stage shift registers 10, the frequencies of the scanning signals outputted by the stage shift registers 10 corresponding to the first display area A1 and the third display area A3 are f1, for example, the 1st, 2nd, 5th and 6th stage shift registers 10 are set to work in the first working mode in each display frame. The frequency of the scanning signal outputted by the stage shift register 10 corresponding to the second display area A2 is f2, for example, the 3rd and 4th stage shift registers 10 are set to work in the first working mode in part of the display frame and in the second working mode in part of the display frame.

[0083] In the case of the on-pulse of the stage transfer signal of each stage shift register 10 being overlapped with the on-pulse of the stage transfer signal of the adjacent stage shift register 10, the on-pulse of the stage transfer signal of the stage shift register 10 is overlapped with the off-pulse of the stage transfer signal of the adjacent stage shift register 10, and the off-pulse of the stage transfer signal of the stage shift register 10 is overlapped with the on-pulse of the stage transfer signal of the adjacent stage shift register 10. Figure 2 Exemplarily, the case where the on-pulse of the stage transfer signal of each stage shift register 10 is overlapped with the on-pulse of the stage transfer signal of the adjacent stage shift register 10 is given in Figure 3As shown, the transmission control module 130 in each shift register 10 is controlled by a switch control signal SW' to maintain its on / off state. Each transmission control module 130 responds to the same switch control signal SW' or is turned off. If it is necessary for the shift register 10 at the target position not to output a conduction potential, the corresponding transmission control module 130 needs to be turned off during the period when each shift register 10 at the target position outputs a conduction potential. This causes the conduction pulses of the scanning signals of the preceding or subsequent shift registers 10 at the target position to be cut off prematurely, and the conduction pulses of the subsequent shift registers 10 at the target position to appear later. That is, it shortens the conduction pulse width of the scanning signals of the shift registers at each level that overlap with the conduction pulses of the intermediate transmission signals at the target position, thereby causing data writing to some row pixel circuits to fail normally, affecting the display effect near the display partition position.

[0084] Specifically, such as Figure 3 As shown, if the third-level scan signal EOUT3 and the fourth-level scan signal EOUT4 are required not to output conduction pulses, then each transmission control module 130 needs to be turned off during the period when the third-level transmission signal Carry3 and the fourth-level transmission signal Carry4 output conduction potentials, i.e., during the period between the two dashed lines. This setting will cause the transmission control modules 130 in the first and second-level shift registers 10 to turn off prematurely, failing to stably transmit the potential of the second output terminal N2 to the second connection terminal N4. This will cause the potential of the second connection terminal N4 to change due to leakage and other reasons, resulting in the scan signal potential starting to drop prematurely. It will also cause the transmission control modules 130 in the fifth and sixth-level shift registers 10 to turn on delayedly. Only after the transmission control modules 130 turn on can the potential of the second output terminal N2 be transmitted to the second connection terminal N4, causing the scan signal to change to a conduction potential later than the transmission signal.

[0085] Furthermore, display panels typically contain thousands or more rows of pixel circuits, with each shift register connecting one or more rows of pixel circuits. Therefore, the scan drive circuit requires at least several hundred shift registers 10. Given the limitations of the number of driver chip ports and the area of ​​the non-display area of ​​the display panel, it is impractical to provide a separate switch control signal SW' for each shift register 10.

[0086] In this embodiment of the invention, the conduction state of the transmission control module 130 is jointly controlled by the frequency cutting signal SW and the local cascade signal. During the stage when the local cascade signal outputs the conduction potential, the local transmission control module 130 can be isolated from other transmission control modules 130. This ensures that the potential change of the frequency cutting signal SW during this stage does not affect the on / off state between the first connection terminal N3 and the second connection terminal N4. This allows the scanning output module 140 to output the conduction pulse completely or maintain the cutoff potential during this stage, effectively avoiding the aforementioned problems.

[0087] For example, the intermediate node can be set inside the transmission control module 130. The transmission of the frequency switching signal SW to the intermediate node is controlled by the stage transmission signal, and the on-off state between the first connection end N3 and the second connection end N4 is controlled by the potential of the intermediate node. For example, when the stage transmission signal is in the on potential, the input end of the transmission control module 130 is disconnected from the intermediate node, so that the frequency switching signal SW cannot be transmitted to the intermediate node; when the stage transmission signal is in the off potential, the frequency switching signal SW can be transmitted to the intermediate node. When the intermediate node is in one of the high and low potentials, the first connection end N3 and the second connection end N4 are connected; when the intermediate node is in the other potential, the first connection end N3 and the second connection end N4 are disconnected. Then, during the stage when the stage transmission signal remains in the on potential, the potential change of the frequency switching signal SW in this stage will not be transmitted to the intermediate node because the input end of the transmission control module 130 remains disconnected from the intermediate node. The intermediate node remains in the potential provided by the frequency switching signal SW before the stage transmission signal jumps to the on potential. Therefore, to control the working mode of the current stage shift register 10, the frequency switching signal needs to be changed to the potential required by the intermediate node before the current stage stage transmission signal output is in the on potential. For example, when the intermediate node is in the low potential to control the connection between the first connection end N3 and the second connection end N4, as shown in FIG. 2, in the display frame F2 or F3, the frequency switching signal SW jumps to the high potential before the third stage stage transmission signal Carry3 is in the high potential. The high potential can be transmitted to the intermediate node of the transmission control module 130 (hereinafter referred to as the third stage transmission control module 130) of the third stage shift register. After the third stage stage transmission signal Carry3 is in the high potential, the input end of the third stage transmission control module 130 is disconnected from the intermediate node. The intermediate node remains in the high potential, so that the first connection end N3 and the second connection end N4 in the third stage shift register are disconnected, and the third stage shift register works in the second working mode and does not output the high potential. Correspondingly, the frequency switching signal SW jumps to the low potential before the fifth stage stage transmission signal Carry5 is in the high potential. The low potential can be transmitted to the intermediate node of the fifth stage transmission control module 130. However, because the input end of the third stage transmission control module 130 remains disconnected from the intermediate node under the control of the third stage stage transmission signal Carry3, the low potential will not be transmitted to the intermediate node of the third stage transmission control module 130. After the fifth stage stage transmission signal Carry5 is in the high potential, the input end of the fifth stage transmission control module 130 is disconnected from the intermediate node. The intermediate node remains in the low potential, so that the first connection end N3 and the second connection end N4 in the fifth stage shift register are connected, and the fifth stage shift register works in the first working mode and can output the high potential pulse. Figure 2

[0088] ​In summary, based on the isolation effect of the current stage of the transfer control module 130 on the intermediate node, the working mode switching of each stage of the shift register 10 does not affect the working state of the front and rear stages of the shift register 10, so the input end of the transfer control module 130 in each stage of the shift register 10 can be connected to the same frequency signal SW, to simplify the structure of the scan driving circuit, reduce the output port of the driving chip, and make the scan driving circuit easy to implement and promote. In the entire display process, by controlling the frequency signal SW to remain unchanged in some display frames (for example, display frame F1), and to jump in potential in some display frames (for example, display frames F2 and F3), the display device can realize partitioned frequency display in the column direction. In addition, by adjusting the specific potential jump time of the frequency signal SW, the display partition position of the display device can be flexibly adjusted. For example, for the partition position between the first display area A1 and the second display area A2 in Figure 2 If the rising edge of the frequency signal SW is controlled to occur earlier than the potential jump time in the display frames F2 and F3, Figure 2 the corresponding shift register 10 of the first display area A1 can be reduced, thereby realizing the upward movement of the partition position between the first display area A1 and the second display area A2.

[0089] It should be noted that, Figure 2 The potential jump of the frequency signal SW in each display frame in the above embodiment is only used as an example for illustration, and does not limit the present application. In other embodiments, the frequency signal SW can be set to jump in potential in any required display frame to control the refresh frequency of each display area. The frequency signal SW can be set to jump in potential only once or multiple times in a display frame according to requirements, to control the number of display partitions of the display device. In addition, the time node of the potential jump of the frequency signal SW in different display frames can be different, to realize dynamic adjustment of the display partition position in the display process.

[0090] The scanning driving circuit provided by the embodiment of the present application comprises a plurality of shift registers 10 arranged in cascade, each of the shift registers 10 comprises a driving control module 110, a stage transmission output module 120, a transmission control module 130 and a scanning output module 140. Based on the control of the driving control module 110 on the first output end N1 and the second output end N2, the stage transmission output module 120 can realize the step-by-step shift output of the first-stage input signal EIN1, and provide the stage transmission signal with the same frequency as the first-stage input signal EIN1, thereby providing the basis for freely selecting the output of the scanning signal with the same frequency as the first-stage input signal EIN1 or the frequency lower than the first-stage input signal EIN1 by each shift register 10. By the cooperation between the stage transmission signal and the frequency switching signal SW, the conduction / disconnection between the first connection end N3 and the second connection end N4 of the transmission control module 130 can be adjusted to allow / block the potential of the first output end N1 to be transmitted to the second connection end N4 of the transmission control module 130, thereby allowing / blocking the conduction potential of the scanning output module 140 to output the scanning signal, and realizing the control of the working mode of the shift register 10. By controlling the potential jump process of the frequency switching signal SW, the working mode combination mode of at least two shift registers 10 can be different, so that the frequencies of the scanning signals output by the at least two shift registers 10 are different, thereby realizing the partition frequency display of the display device. In summary, compared with the prior art, the embodiment of the present application can make the display device support the partition frequency display function.

[0091] Firstly, the structure of the shift register 10 will be exemplarily described, and then the specific driving process of driving the display device to realize the partition multi-frequency display based on the scanning driving circuit will be exemplarily described.

[0092] Figure 4 is a structural schematic diagram of a shift register provided by the embodiment of the present application. Referring to Figure 4 In an embodiment, optionally, the driving control module 110 controls the potentials of the first output end N1 and the second output end N2 in response to the first clock signal ECK1, the second clock signal ECK2, the input signal EIN, the first potential signal VGH and the second potential signal VGL. The stage transmission output module 120 outputs the first potential signal VGH or the second potential signal VGL as the stage transmission signal Carry according to the potentials of the first output end N1 and the second output end N2. The transmission control module 130 is used for controlling whether the potential of the second output end N2 is transmitted to the second connection end N4 according to the frequency switching signal SW and the stage transmission signal Carry. The scanning output module 140 is used for outputting the first potential signal VGH or the second potential signal VGL as the scanning signal EOUT to the pixel circuit in response to the potentials of the first output end N1 and the second connection end N4.

[0093] Exemplarily, the first potential signal VGH and the second potential signal VGL can be direct current voltage signals with different potential levels, for example, the first potential signal VGH is a high potential, and the second potential signal VGL is a low potential. The first clock signal ECK1 and the second clock signal ECK2 are clock signals with high and low potential levels alternately changing.

[0094] With reference to Figure 4 On the basis of the above embodiments, optionally, the transmission control module 130 comprises an isolation protection unit 132 and an output control unit 131, which respectively control the on-off of the signal transmission path from the input end of the transmission control module 130 to the intermediate node N5 and the signal transmission path from the first connection end N3 to the second connection end N4. The input end of the output control unit 131 is connected to the first connection end N3, and the output end of the output control unit 131 is connected to the second connection end N4; the output control unit 131 is used to control the potential of the second connection end N4 according to the potential of the control end (i.e. the intermediate node N5). The control end of the isolation protection unit 132 is connected to the output end of the stage transmission output module 120 and accesses the stage transmission signal Carry; the input end of the isolation protection unit 132 accesses the frequency switching signal SW, and the output end of the isolation protection unit 132 is connected to the intermediate node N5. The isolation protection unit 132 is used to cut off the transmission path of the frequency switching signal SW to the intermediate node N5 in response to the stage transmission signal Carry. Exemplarily, when the stage transmission signal Carry is at a high potential, the isolation protection unit 132 can be controlled to be turned off to cut off the transmission path of the frequency switching signal SW to the intermediate node N5.

[0095] Specifically, as Figure 5 shown, the output control unit 131 can comprise a first transistor M1; the gate of the first transistor M1 serves as the control end of the output control unit 131, the first pole of the first transistor M1 serves as the input end of the output control unit 131, and the second pole of the first transistor M1 serves as the output end of the output control unit 131. The isolation protection unit 132 can comprise a second transistor M2; the gate of the second transistor M2 serves as the control end of the isolation protection unit 132, the first pole of the second transistor M2 serves as the input end of the isolation protection unit 132, and the second pole of the second transistor M2 serves as the output end of the isolation protection unit 132. In this embodiment, the isolation protection unit 132 and the output control unit 131 are both composed of one transistor, so that the transmission control module 130 is simple in structure and easy to implement.

[0096] With reference to Figure 5In one embodiment, the driving control module 110 comprises an input unit 111, a first control unit 112, a second control unit 113, a first node control unit 114, a second node control unit 115 and a third node control unit 116. The output of the input unit 111 is connected to the first output N1, and is configured to transmit the input signal EIN to the first output N1 in response to the first clock signal ECK1. The first control unit 112 is configured to transmit the second potential signal VGL to the output of the first control unit 112 in response to the first clock signal ECK1. The second control unit 113 is connected between the output of the first control unit 112 and the second output N2 of the driving control module 110, and is configured to control the potential of the second output N2 according to the second clock signal ECK2 and the potential of the output of the first control unit 112. The first node control unit 114 is connected to the first output N1 and the output of the first control unit 112 respectively, and is configured to control the potential of the output of the first control unit 112 according to the potential of the first output N1. The second node control unit 115 is connected to the first output N1 and the output of the first control unit 112 respectively, and is configured to control the potential of the first output N1 according to the potential of the output of the first control unit 112. The third node control unit 116 is connected to the first output N1 and the second output N2 respectively, and is configured to control the potential of the second output N2 according to the potential of the first output N1.

[0097] Exemplarily, the input unit 111 comprises a transistor M11, the gate of the transistor M11 is connected to the first clock signal ECK1, the first electrode is connected to the input signal EIN, and the second electrode is electrically connected to the first output terminal N1. The first control unit 112 comprises a transistor M12, the gate of the transistor M12 is connected to the first clock signal ECK1, the first electrode is connected to the second potential signal VGL, and the second electrode is the output terminal of the first control unit 112. The second control unit 113 comprises a transistor M17, a transistor M18 and a capacitor C3, the gate of the transistor M17 is connected to the output terminal of the first control unit 112, the first electrode of the transistor M17 and the gate of the transistor M18 are both connected to the second clock signal ECK2, the second electrode of the transistor M17 is connected to the first electrode of the transistor M18, the second electrode of the transistor M18 is connected to the second output terminal N2, and the capacitor C3 is connected between the gate and the second electrode of the transistor M17. The first node control unit 114 comprises a transistor M13, the gate of the transistor M13 is connected to the first output terminal N1, the first electrode is connected to the first clock signal ECK1, and the second electrode is connected to the output terminal of the first control unit 112. The second node control unit 115 comprises a transistor M14 and a transistor M15, the transistor M14 and the transistor M15 are connected in series between the first output terminal N1 and the first potential signal line (for transmitting the first potential signal), the gate of the transistor M14 is connected to the output terminal of the first control unit 112, and the gate of the transistor M15 is connected to the second clock signal ECK2. The third node control unit 116 comprises a transistor M19, the gate of the transistor M19 is connected to the first output terminal N1, the first electrode is connected to the first potential signal, and the second electrode is connected to the second output terminal N2.

[0098] Continuing to refer to Figure 4 In an embodiment, optionally, the scan output module 140 comprises a first output unit 141 and a second output unit 142, which respectively control the on state between the on potential input terminal and the output terminal of the scan output module 140 and the off state between the off potential input terminal and the output terminal. The control terminal of the first output unit 141 is the first control terminal of the scan output module 140, which is electrically connected to the first output terminal N1, and is used to transmit the second potential signal VGL to the output terminal of the scan output module 140 in response to the on potential of the first output terminal N1. The control terminal of the second output unit 142 is the second control terminal of the scan output module 140, which is electrically connected to the second connection terminal N4, and is used to transmit the first potential signal VGH to the output terminal of the scan output module 140 in response to the on potential of the second connection terminal N4.

[0099] Specifically, referring to Figure 5The first output unit 141 can include a fourth transistor M4, a gate of the fourth transistor M4 being connected to the first output end N1, a first pole of the fourth transistor M4 being connected to the second potential signal line and being connected to the second potential signal VGL, and a second pole of the fourth transistor M4 being connected to the output end of the scan output module 140. The second output unit 142 includes a fifth transistor M5 and a first capacitor C1, a gate of the fifth transistor M5 being connected to the second connection end N4, a first pole of the fifth transistor M5 being connected to the first potential signal line, a second pole of the fifth transistor M5 being connected to the output end of the scan output module 140, and the first capacitor C1 being connected between the gate and the first pole of the fifth transistor M5. The first capacitor C1 is used to maintain the gate potential of the fifth transistor M5.

[0100] Continuing to refer to Figure 4 In an embodiment, the stage transmission output module 120 can include a third output unit 121 and a fourth output unit 122, respectively controlling the on state between the on potential input end and the off potential input end of the stage transmission output module 120 and the output end. The third output unit 121 is electrically connected to the first output end N1, and is used to transmit the second potential signal VGL to the output end of the stage transmission output module 120 in response to the on potential of the first output end N1. The fourth output unit 122 is electrically connected to the second output end N2, and is used to transmit the first potential signal VGH to the output end of the stage transmission output module 120 in response to the on potential of the second output end N2.

[0101] Specifically, the third output unit 121 includes a sixth transistor M6, a gate of the sixth transistor M6 being connected to the first output end N1, a first pole of the sixth transistor M6 being connected to the second potential signal line, and a second pole of the sixth transistor M6 being connected to the output end of the stage transmission output module 120. The fourth output unit 122 includes a seventh transistor M7 and a second capacitor C2, a gate of the seventh transistor M7 being connected to the second output end N2, a first pole of the seventh transistor M7 being connected to the first potential signal line, a second pole of the seventh transistor M7 being connected to the output end of the stage transmission output module 120, and the second capacitor C2 being connected between the gate and the first pole of the seventh transistor M7. The second capacitor C2 is used to maintain the gate potential of the seventh transistor M7.

[0102] Further, the third output unit 121 can further include a capacitor C4, one end of the capacitor C4 is connected to the second clock signal ECK2, and the other end is connected to the gate of the sixth transistor M6. Based on the coupling effect of the capacitor C4, the potential jump can be coupled to the gate of the sixth transistor M6 at the falling edge of the second clock signal ECK2, so as to reduce the gate potential of the sixth transistor M6, so as to ensure that the sixth transistor M6 is fully turned on. Since the gate of the fourth transistor M4 and the gate of the sixth transistor M6 are directly connected to the first output end N1, the capacitor C4 can simultaneously control the gate potential of the fourth transistor M4, so that the capacitor does not need to be additionally arranged at the gate of the fourth transistor M4.

[0103] The following is based on Figure 5 the structure of the shift register 10, taking the shift register 10 in which all the transistors are P-type transistors as an example, and combining Figures 5-9 the driving process of the shift register 10 is described. In order to clearly describe the working process of the circuit, the potential VN5 of the intermediate node N5 and the potential VN4 of the second connection end N4 are represented by dashed lines when there is no signal source and the potentials are maintained.

[0104] Figure 6 is a driving timing diagram of a shift register provided by an embodiment of the present application in a first working mode. In combination with Figure 5 and Figure 6 , the driving process of the shift register 10 in the first working mode includes:

[0105] In the first stage T11, the first clock signal ECK1 and the frequency cutting signal SW are low potentials, and the second clock signal ECK2 and the input signal EIN are high potentials. The transistor M11 and the transistor M12 are turned on, and the transistor M15 and the transistor M18 are turned off. The high potential of the input signal EIN is transmitted to the first output end N1 through the transistor M11, so that the potential VN1 of the first output end N1 is a high potential, and the transistors M13, M19, M6 and M4 are controlled to be turned off. The low potential of the second potential signal VGL is transmitted to the output end of the first control unit 112 through the transistor M12, so that the transistors M14 and M17 are turned on. Due to the storage effect of the second capacitor C2, the potential VN2 of the second output end N2 remains the high potential of the previous stage, so that the transistor M7 is turned off. Therefore, the stage transfer signal Carry remains the low potential of the previous stage. The stage transfer signal Carry controls the second transistor M2 to be turned on, the low potential of the frequency cutting signal SW is transmitted to the intermediate node N5, so that the potential VN5 of the intermediate node N5 is a low potential, and the transistor M1 is controlled to be turned on. The high potential of the second output end N2 is transmitted to the second connection end N4 through the first transistor M1, so that the potential VN4 of the second connection end N4 is a high potential, and the fifth transistor M5 is controlled to be turned off, and therefore the scan signal EOUT also remains the low potential of the previous stage.

[0106] In the second stage T12, the second clock signal ECK2 and the chopping signal SW are at low level, and the first clock signal ECK1 and the input signal EIN are at high level. The transistor M15 and the transistor M18 are turned on, and the transistor M11 and the transistor M12 are turned off. Due to the storage effect of the capacitor C3, the output end of the first control unit 112 keeps the low level of the last stage, so that the transistor M14 and the transistor M17 are turned on. The high level of the first potential signal VGH is transmitted to the first output end N1 through the transistor M14 and the transistor M15, so that the transistor M13, the transistor M19, the sixth transistor M6 and the fourth transistor M4 are kept in the off state. The low level of the second clock signal ECK2 is transmitted to the second output end N2 through the transistor M17 and the transistor M18, so that the potential VN2 of the second output end N2 changes to low level, the seventh transistor M7 is turned on, the first potential signal VGH is output through the seventh transistor M7, and the stage transmission signal Carry changes to high level. The stage transmission signal Carry controls the second transistor M2 to be turned off, the low level of the chopping signal SW cannot be transmitted to the intermediate node N5, the intermediate node N5 keeps the low level of the last stage, and the transistor M1 is turned on. The low level of the second output end N2 is transmitted to the second connection end N4 through the first transistor M1, so that the potential VN4 of the second connection end N4 is at low level, the fifth transistor M5 is turned on, the first potential signal VGH is output through the fifth transistor M5, and the scanning signal EOUT also changes to high level.

[0107] In the third stage T13, the first clock signal ECK1 and the frequency cutting signal SW are at low level, and the second clock signal ECK2 and the input signal EIN are at high level. The transistor M11 and the transistor M12 are turned on, and the transistor M15 and the transistor M18 are turned off. The high level of the input signal EIN is transmitted to the first output end N1 through the transistor M11, so that the transistor M13, the transistor M19, the sixth transistor M6 and the fourth transistor M4 are turned off. The low level of the second potential signal VGL is transmitted to the output end of the first control unit 112 through the transistor M12, so that the transistor M14 and the transistor M17 are turned on. The high level of the second clock signal ECK2 is outputted through the transistor M17, but cannot be transmitted to the second output end N2 due to the turning off of the transistor M18. The second output end N2 keeps the low level of the previous stage due to the storage effect of the capacitor C2, so that the transistor M7 keeps being turned on and the carry signal keeps being at high level. The carry signal controls the second transistor M2 to be turned off, so that the low level of the frequency cutting signal SW cannot be transmitted to the intermediate node N5, and the intermediate node N5 keeps the low level to control the transistor M1 to be turned on. The low level of the second output end N2 is transmitted to the second connection end N4 through the first transistor M1, so that the fifth transistor M5 is turned on, the first potential signal VGH is outputted through the fifth transistor M5, and the scanning signal EOUT keeps being at high level.

[0108] In the fourth stage T14, the first clock signal ECK1 is at high level, and the second clock signal ECK2, the frequency cutting signal SW and the input signal EIN are at low level. The transistor M11 and the transistor M12 are turned off, and the transistor M15 and the transistor M18 are turned on. The output end of the first control unit 112 keeps the low level of the previous stage due to the storage effect of the capacitor C3, so that the transistor M14 and the transistor M17 are turned on. The high level of the first potential signal VGH is transmitted to the first output end N1 through the transistor M14 and the transistor M15, so that the transistor M13, the transistor M19, the sixth transistor M6 and the fourth transistor M4 keep being turned off. The low level of the second clock signal ECK2 is transmitted to the second output end N2 through the transistor M17 and the transistor M18, so that the transistor M7 is turned on, the high level of the first potential signal VGH is transmitted through the transistor M7, and the carry signal keeps being at high level. The carry signal controls the second transistor M2 to be turned off, so that the low level of the frequency cutting signal SW cannot be transmitted to the intermediate node N5, and the intermediate node N5 keeps the low level to control the transistor M1 to be turned on. The low level of the second output end N2 is transmitted to the second connection end N4 through the first transistor M1, so that the fifth transistor M5 is turned on, the first potential signal VGH is outputted through the fifth transistor M5, and the scanning signal EOUT keeps being at high level.

[0109] In the fifth stage T15, the second clock signal ECK2 is at high level, the first clock signal ECK1, the frequency cutting signal SW and the input signal EIN are at low level. The transistor M11 and the transistor M12 are turned on, the transistor M15 and the transistor M18 are turned off. The low level of the input signal EIN is transmitted to the first output end N1 through the transistor M11, so that the potential VN1 of the first output end N1 changes to low level, and the transistor M13, the transistor M19, the sixth transistor M6 and the fourth transistor M4 are all turned on. The low level of the first clock signal ECK1 is transmitted to the output end of the first control unit 112 through the transistor M13, so that the transistor M14 and the transistor M17 are turned on, and the high level of the second clock signal ECK2 is outputted through the transistor M17, but the high level cannot be transmitted to the second output end N2 because the transistor M18 is turned off. The high level of the first potential signal VGH is transmitted to the second output end N2 through the transistor M19, so that the potential VN2 of the second output end N2 changes to high level, and the seventh transistor M7 is turned off. The low level of the second potential signal VGL is outputted through the sixth transistor M6, and the stage transmission signal Carry changes to low level. The second transistor M2 is turned on under the control of the stage transmission signal Carry, and the low level of the frequency cutting signal SW is transmitted to the intermediate node N5, so that the potential VN5 of the intermediate node N5 is at low level, and the transistor M1 is turned on. The high level of the second output end N2 is transmitted to the second connection end N4 through the first transistor M1, so that the potential VN4 of the second connection end N4 changes to high level, the fifth transistor M5 is turned off, and the low level of the second potential signal VGL is transmitted through the fourth transistor M4, so the scanning signal EOUT also changes to low level.

[0110] In the sixth stage T16, the first clock signal ECK1 is at high level, the second clock signal ECK2, the frequency cutting signal SW and the input signal EIN are at low level. The transistor M15 and the transistor M18 are turned on. Due to the coupling effect of the capacitor C4, when the second clock signal ECK2 becomes low level, the potential of the first output end N1 becomes a lower low level than that in the fifth stage T25, so that the sixth transistor M6 and the fourth transistor M4 are turned on more fully; the high level of the first clock signal ECK1 is transmitted to the output end of the first control unit 112 through the transistor M13, so that the transistor M17 and the transistor M14 are turned off. The high level of the first potential signal VGH is transmitted to the second output end N2 through the transistor M19, so that the transistor M7 is kept turned off. Compared with the previous stage, although the transistor M18 is turned on in this stage, the low level of the second clock signal ECK2 cannot be transmitted through the transistor M17 which is turned off, so the potential of the second output end N2 cannot be pulled down, and thus the second output end N2 can keep high level. The low level of the second potential signal VGL is outputted through the sixth transistor M6, and the stage transmission signal Carry keeps low level; at the same time, the low level of the second potential signal VGL is outputted through the fourth transistor M4, and the scanning signal EOUT also keeps low level.

[0111] The fifth stage T15 and the sixth stage T16 are repeated subsequently, and the stage transmission signal Carry and the scanning signal EOUT both keep low level until the input signal EIN becomes high level again.

[0112] It should be noted that the stage transmission signal Carry actually has a potential drop in the fifth stage T15, but the stage transmission signal Carry can change to the required low level only after further potential drop in the sixth stage T16. In this embodiment, the process of potential change of the related nodes of the transmission control module 130 is mainly described, and thus the stage-wise drop of the potential VN1 of the first output end N1 and the stage-wise drop of the potential of the stage transmission signal Carry are not embodied. Similarly, the stage-wise drop of the scanning signal EOUT in the fifth stage T15 and the sixth stage T16 is not embodied.

[0113] The above embodiment exemplarily shows that the frequency cutting signal SW keeps low level VL in the whole display frame when the shift register 10 works in the first working mode, but this is not a limitation of the present application. In other embodiments, as shown in FIG. 6, the frequency cutting signal SW can also have potential jump when the shift register 10 works in the first working mode, and can include at least one high level keeping stage, as long as the potential VN5 of the intermediate node N5 can keep low level before and after each potential jump of the second output end N2, so that the second connection end VN4 can change following the potential VN2 of the second output end N2, and thus the driving process in the first working mode can be realized. Figure 7 ​

[0114] Exemplarily, in the time period when the carry signal Carry keeps high potential (i.e. the time period when the potential VN2 of the second output terminal N2 keeps low potential, including the second stage T12 to the fourth stage T14), the frequency switching signal SW can perform potential jump; in this time period, the frequency switching signal SW can include one high potential keeping stage as shown, or can include multiple high potential keeping stages, as long as the first rising edge of the frequency switching signal SW in the stage is located after the rising edge of the carry signal Carry, and the last falling edge of the frequency switching signal SW is located before the falling edge of the carry signal Carry. And in the time period when the carry signal Carry keeps low potential (i.e. the time period when the potential VN2 of the second output terminal N2 keeps high potential, including the fifth stage T15 until the end of the display frame), the frequency switching signal SW can also perform potential jump; in this time period, the frequency switching signal SW can include one high potential keeping stage as shown, or can include multiple high potential keeping stages, in the high potential keeping stage of the frequency switching signal SW, since the carry signal Carry is low potential, the second transistor M2 can be controlled to be turned on, the high potential of the frequency switching signal is transmitted to the intermediate node N5, the first transistor M1 is controlled to be turned off, thus the signal transmission path of the second output terminal N2 to the second connection terminal N4 is cut off, and the second connection terminal N4 keeps high potential based on the storage effect of the first capacitor C1. Figure 7 Figure 7

[0115] Figure 8 is a driving timing diagram of a shift register in the second working mode provided by an embodiment of the present application. In combination with Figure 5 and Figure 8 , when the shift register 10 works in the second working mode, the working states of the driving control module 110 and the carry output module 120, and the potential changes of the first output terminal N1, the second output terminal N2 and the carry signal Carry are all the same as in Figure 6 and Figure 7 . The difference lies in the potential jump of the frequency switching signal SW, which is different from that in Figure 6 and Figure 7 , so that the potential changes of the intermediate node N5 and the second connection terminal N4 are different from those in Figure 6 and Figure 7 , thus the waveform of the scan signal EOUT output by the scan output module 140 is different from that in Figure 6 and Figure 7 . The difference between the driving processes in the second working mode and the first working mode will be mainly described below, and the same parts will not be described again.

[0116] ​​Specifically, in the second operating mode, the rising edge of the frequency switching signal SW is set before the rising edge of the stage transmission signal Carry (i.e., before the falling edge of the potential VN2 of the second output terminal N2, for example, set at any position in the first stage T11), and the high potential holding phase of the frequency switching signal SW covers the falling edge of the potential VN2 of the second output terminal N2. In this way, the high potential of the frequency switching signal SW can be transmitted to the intermediate node N5 in advance, before the rising edge of the stage transmission signal Carry, while the second transistor M2 is still conducting. This signal transmission process continues until the rising edge of the stage transmission signal Carry arrives (e.g., before the rising edge of the stage transmission signal Carry). Figure 8 During the high-potential phase of the intermediate node potential VN5 (solid line stage); during the high-potential holding phase of the stage transmission signal Carry, the second transistor M2 is turned off, and the intermediate node potential VN5 is maintained at a high potential (e.g., solid line stage of the high-potential phase of the intermediate node potential VN5); during the high-potential holding phase of the stage transmission signal Carry, the second transistor M2 is turned off, and the intermediate node potential VN5 is maintained at a high potential (e. Figure 8 The high-potential phase of intermediate node N5 (dashed line). Therefore, the high-potential holding phase of intermediate node N5 begins before the rising edge of the transmission signal Carry and ends when the falling edge of the transmission signal Carry arrives. Before the high-potential holding phase of intermediate node N5, the potential VN2 of the second output terminal N2 remains high. Therefore, until the high-potential holding phase of intermediate node N5 begins, the second connection terminal N4 maintains the same high potential as the second output terminal N2. During the high-potential holding phase of intermediate node N5, since the first transistor M1 is turned off, the potential jump and low potential of the second output terminal N2 cannot be transmitted to the second connection terminal N4. Therefore, the second connection terminal N4 maintains a high potential in this display frame, controlling the fifth transistor M5 to remain off, and cannot output the high potential of the first potential signal VGH. Therefore, in this display frame, the scan signal EOUT remains low.

[0117] The above embodiments exemplify that in the second operating mode, the falling edge of the frequency cutter signal SW occurs before the falling edge of the stage transfer signal Carry, but this is not intended to limit the invention. In other embodiments, exemplarily, such as... Figure 9 As shown, the falling edge of the frequency-cutting signal SW can occur after the falling edge of the stage transmission signal Carry. Therefore, after the falling edge of the stage transmission signal Carry, the second transistor M2 turns on again, transmitting the frequency-cutting signal SW to the intermediate node N5. Thus, the intermediate node N5 continues to maintain a high potential (e.g., ...). Figure 9 The second solid line segment of the high potential VN5 at the intermediate node (in the middle node N5) indicates that the first transistor M1 remains off, and the second connection terminal N4 continues to maintain a high potential. It can be seen that the dashed line segment of the potential VN4 at the second connection terminal N4 extends as the high potential holding stage of the intermediate node N5 extends, still enabling the control process in the second operating mode. Furthermore, the high potential holding stage of the intermediate node N5 can even extend until the end of the current display frame, ensuring that the frequency switching signal SW does not include a falling edge in this display frame.

[0118] Figure 10 is another structure diagram of a shift register provided by an embodiment of the present application. Referring to Figure 10 On the basis of the above embodiments, the drive control module 110 can optionally further include a protection unit 117 to improve the output stability of the shift register 10. The first end N11 of the protection unit 117 is connected to the output end of the input unit 111, the second end N12 of the protection unit 117 is connected to the first output end N1, and the control end of the protection unit 117 is connected to the second potential signal line and accesses the second potential signal VGL. Specifically, the protection unit 117 can be configured to include a transistor M21, the gate of the transistor M21 accesses the second potential signal VGL, the first pole serves as the first end N11 of the protection unit 117, and the second pole serves as the second end N12 of the protection unit 117.

[0119] For example, the first node control unit 114 and the second node control unit 115 can both be connected to the first end N11 of the protection unit 117, and the third node control unit 116 can be connected to the second end N12 of the protection unit 117.

[0120] From the above analysis, it can be known that in the sixth stage T16, due to the coupling effect of the capacitor C4, the gate potential of the sixth transistor M6 is coupled to an extremely low potential lower than the second potential signal VGL. By setting the protection unit 117, the extremely low potential can be prevented from being transmitted to the first end N11 of the protection unit 117, and the transistors connected to the first end N11 of the protection unit 117 can be prevented from being damaged due to excessive voltage stress. Specifically, the conduction condition of the transistor M21 is that the gate-source voltage difference is less than the threshold voltage. When the gate of the sixth transistor M6 is coupled to the extremely low potential, if the extremely low potential is transmitted to the first end N11 of the protection unit 117 through the transistor M21, the gate-source voltage difference of the transistor M21 will be greater than the threshold voltage, which does not meet the conduction condition of the transistor M21, so that the transistor M21 is turned off, and thus the transmission of the extremely low potential to the first end N11 of the protection unit 117 is blocked.

[0121] For example, as shown in Figure 10 the second control unit 113 can further be configured to include a transistor M16 connected between the output end of the first control unit 112 and the gate of the transistor M17, and the gate of the transistor M16 accesses the second potential signal VGL. Similar to the principle of the transistor M21, the transistor M16 can also prevent the extremely low potential generated due to the coupling effect of the capacitor C3 from being transmitted forward, so as to protect the transistors connected to the output end of the first control unit 112 from being damaged.

[0122] Figure 11 is another structure diagram of a shift register provided by an embodiment of the present application. Referring toFigure 11 Based on the above embodiments, optionally, the shift register 10 further includes: a node potential control module 150, the control terminal of which is connected to the first output terminal N1; the input terminal of which is connected to the first potential signal line and receives the first potential signal VGH; and the output terminal of which is connected to the second connection terminal N4. The node potential control module 150 in this embodiment can function similarly to the third node control unit 116. Specifically, the node potential control module 150 is turned on when the fourth transistor M4 outputs (i.e., when the first output terminal N1 is at a low potential), stably transmitting the high potential of the first potential signal VGH to the second connection terminal N4, keeping the fifth transistor M5 off, and ensuring the accuracy of the scan signal EOUT potential.

[0123] Specifically, the node potential control module 150 may include: a third transistor M3; the gate of the third transistor M3 serves as the control terminal of the node potential control module 150, the first terminal of the third transistor M3 serves as the input terminal of the node potential control module 150, and the second terminal of the third transistor M3 serves as the output terminal of the node potential control module 150.

[0124] After setting the node potential control module 150, the shift register 10 can still be used. Figures 6-9 The difference in the driving process shown is that, due to the presence of the node potential control module 150, the second connection terminal N2 can stably receive the high potential of the first potential signal VGH during the period when the potential VN1 of the first output terminal N1 is low. Therefore, from the fifth stage T15 until the end of the display frame, the second connection terminal N4 has a stable source of high potential, making... Figure 7 and Figure 9 In the middle, from the fifth stage T15 onwards, the potential VN4 of the second connection terminal N4 is all solid lines, excluding the dashed line stage.

[0125] Based on this, when shift register 10 needs to operate in the first working mode, it can also use, for example... Figure 12 The driving timing shown is as follows: Figure 12 and Figure 7 The difference is that the high-potential holding phase of the frequency switching signal SW can cover the falling edge of the transmission signal Carry (i.e., the rising edge of the potential VN2 of the second output terminal N2). Since the potential VN2 of the second output terminal N2 is no longer the only potential source of the second connection terminal N4, when the first transistor M1 remains off at the rising edge of the potential VN2 of the second output terminal N2 and cannot transmit the potential transition to the second connection terminal N4, the first potential signal VGH can be transmitted to the second connection terminal N4 by the third transistor M3. Therefore, the high-potential holding phase of the frequency switching signal SW can be extended to after the fifth stage T15, or even until the end of the display frame.

[0126] The above embodiment exemplarily shows that the control end of the node potential control module 150 is connected to the first output end N1 (i.e., the second end N12 of the protection unit 117), but does not limit the present application. In other embodiments, the control end of the node potential control module 150 can also be connected to the first end N11 of the protection unit 117, in which case the conduction period of the node potential control module 150 is consistent with the case where the control end of the node potential control module 150 is connected to the second end N12 of the protection unit 117. Alternatively, the control end of the node potential control module 150 can also be connected to the carry signal Carry of the current stage, which is also at a low potential in the first stage T11 compared with the first output end N1, so as to control the node potential control module 150 to conduct and make the second connection end N4 at a high potential, as shown in FIG. 6. Figures 6-9 Figure 12 It can be seen that the second connection end N4 needs to be kept at a high potential in the first stage T11, and thus it is beneficial for the node potential control module 150 to conduct in this stage to keep the second connection end N4 at a high potential and to stabilize the output of the shift register 10 in various working modes.

[0127] The above embodiments exemplarily show a specific structure of the shift register 10, but do not limit the present application. In other embodiments, as shown in FIG. 7, the second potential control unit 115 can also be of other structures, which can also control the potential change of the first output end N1. Figure 13

[0128] Specifically, as shown in FIG. 8, the second potential control unit 115 can include transistors M31 to M35 and a capacitor C31. The gate of the transistor M31 is connected to the output end of the first control unit 112, the first electrode is connected to the first potential signal VGH, and the second electrode is connected to the second electrode of the transistor M32 and the first end of the capacitor C31. The first electrode of the transistor M32 is connected to the second clock signal ECK2. The second end (i.e., node N31) of the capacitor C31 is connected to the gate of the transistor M32, the gate of the transistor M33 and the second electrode of the transistor M34. The first electrode of the transistor M35 is connected to the input signal EIN, the second electrode is connected to the first electrode of the transistor M34, the gate of the transistor M34 is connected to the second potential signal VGL, and the gate of the transistor M35 is connected to the first clock signal ECK1. Figure 13

[0129] Among them, the potential of the node N31 is controlled by the transistors M31 and M32, the potential of the node N32 is controlled by the transistors M34 and M35 and the coupling effect of the capacitor C31, and the transistor M33 is connected in a diode form and conducts when the node N32 is at a low potential.

[0130] ​​​Figure 13 The other functional units in the driving control module 110 have the same structure as Figure 11 The analysis of the above embodiments shows that the output terminal of the first control unit 112 keeps low potential in the first stage T11 to the fifth stage T15, and changes to high potential in the sixth stage T16. Therefore, in the first stage T11 to the fifth stage T15, the transistor M31 is turned on, keeping the node N31 at high potential, and in the sixth stage T16, the transistor M31 is turned off, not affecting the potential of the node N31. The connection mode of the transistor M35 and the transistor M34 is the same as that of the transistor M11 and the transistor M21, so the potential change of the node N32 is similar to that of the first output terminal N1 in Figure 6 In the first stage T11 to the fourth stage T14, the node N32 keeps high potential, turning off the transistors M32 and M33. In the fifth stage T15, the node N32 changes to low potential, turning on the transistors M32 and M33, the transistor M32 transmits the high potential of the second clock signal ECK2 to the node N31, not affecting the keeping of the high potential of the node N31; the low potential of the input signal EIN is transmitted to the first output terminal N1 through the transistors M35, M34 and M33. At the beginning of the sixth stage T16, the node N32 keeps low potential, turning on the transistors M32 and M33, the transistor M32 transmits the low potential of the second clock signal ECK2 to the node N31, making the node N31 jump to low potential, the capacitor C31 couples the potential jump to the node N32, making the potential of the node N32 change to an extremely low potential lower than the second potential signal, making the transistor M33 more fully turned on, transmitting the extremely low potential to the first output terminal N1, thereby controlling the more fully turned on of the sixth transistor M6. Therefore, the capacitor C4 in the third output unit 121 can be no longer needed.

[0131] As shown in Figure 13 Further, the driving control module 110 can further include a transistor M36 to provide a source of high potential for the first output terminal N1, specifically for transmitting the first potential signal VGH to the first terminal N11 of the protection unit 117 when the reset control signal RST is at low potential, thereby controlling the sixth transistor M6 and the fourth transistor M4 to be turned off. In actual application, the potential of the reset control signal RST can be set according to the requirement.

[0132] The above embodiments exemplarily describe the specific structure of the shift register 10. The specific connection relationship between the scanning driving circuit and the pixel circuit in the display panel, and the driving process of the display panel are described below.

[0133] Figure 14is a structural schematic diagram of a display panel provided by an embodiment of the present application. Referring to Figure 14 Exemplarily, the display panel comprises a display area AA and a non-display area NAA, the display area AA is provided with pixel circuits 20 arranged in an array, the scan driving circuit 100 is arranged in the non-display area NAA, and each stage of shift register 10 is connected to a clock signal SW. In order to provide various signals required by the scan driving circuit 100, the non-display area NAA can further be provided with a first potential signal line for providing a first potential signal VGH, a second potential signal line for providing a second potential signal VGL, a first clock signal line for providing a first initial clock signal CLK1, a second clock signal line for providing a second initial clock signal CLK2, a clock control signal line for providing a clock signal SW, and an input signal line for providing a first stage input signal EIN1. Wherein, two clock terminals of each stage of shift register 10 are alternately connected to the first clock signal line and the second clock signal line, that is, the first initial clock signal CLK1 can be used as the first clock signal ECK1 of the odd stage shift register and the second clock signal ECK2 of the even stage shift register; correspondingly, the second initial clock signal CLK2 can be used as the second clock signal ECK2 of the odd stage shift register and the first clock signal ECK1 of the even stage shift register. The pixel circuit 20 can have the structure of any existing pixel circuit. Exemplarily, the output end of the scan output module of each stage of shift register 10 is connected to a row of pixel circuits 20 through a scan line LS, for example, connected to a functional module in the pixel circuit 20 for controlling the data writing process.

[0134] Still taking the display device comprising three display areas as an example, the driving process as shown in Figure 2 is taken as an example for description. In the display frame F1, the clock signal SW can be controlled to maintain a low potential, so that each stage of shift register 10 performs the driving process as shown in Figure 6 , the scan signal EOUT of each stage is consistent with the corresponding stage of carry signal, and the scan driving circuit 100 can realize the step-by-step transmission of the on-potential of the scan signal, so that all the pixel circuits of the display areas are refreshed. Such a display frame can be called a full refresh frame.

[0135] Figure 15 is another driving timing diagram of a display panel provided by an embodiment of the present application, Figure 15 exemplarily gives a specific implementation mode of the driving process in the display frame F2 (or F3). In combination with Figure 14 and Figure 15 , in the display frame F2 (or F3), part of the row of pixel circuits are refreshed, and such a display frame can be called a partial refresh frame.

[0136] Specifically, in the display frame F2 (or F3): the rising edge of the frequency switching signal SW is set before the rising edge of the third stage carry signal Carry3, and the falling edge of the frequency switching signal SW is set before the rising edge of the fifth stage carry signal Carry5, so that the first two stages and the last two stages of the shift register 10 work in the first working mode, and the middle two stages of the shift register 10 work in the second working mode. In this way, the second stage shift register 10 and the third stage shift register 10 correspond to the two rows of pixel circuits 20 between the low-frequency display partition position of the display panel, and the fourth stage shift register 10 and the fifth stage shift register 10 correspond to the two rows of pixel circuits 20 between the high-frequency display partition position of the display panel.

[0137] It should be noted that if the target position of the low-frequency display partition corresponds to between the second stage shift register 10 and the third stage shift register 10, the rising edge of the frequency switching signal SW also needs to be controlled to be after the rising edge of the second stage carry signal Carry2, that is, the rising edge jump time t01 is set within the time period of the first shaded area in Figure 15 , so that each stage of the shift register 10 before the third stage shift register 10 can normally output the on-potential pulse of the scan signal EOUT.

[0138] Specifically, since the high-potential maintaining stage of the frequency switching signal SW covers the falling edge of the potential VN21 of the second output end in the first stage shift register 10, the driving process of the first stage shift register 10 is consistent with that in Figure 12 ; since the high-potential maintaining stage of the frequency switching signal SW does not cover the falling edge of the potential VN22 of the second output end in the second stage shift register 10, the driving process of the second stage shift register 10 is basically consistent with that in Figure 7 , except that it does not include the second high-potential maintaining stage of the frequency switching signal SW in Figure 7 . Since the rising edge of the frequency switching signal SW is set before the rising edge of the third stage carry signal Carry3, the driving process of the third stage shift register 10 is consistent with that in Figure 8 . When the frequency switching signal SW controls more stages of the shift register 10 to work in the second working mode, and the high-potential maintaining stage of the frequency switching signal SW covers the on-pulse of the third stage carry signal Carry3, the driving process of the third stage shift register 10 can be Figure 9 consistent with that in . If the rising edge of the frequency switching signal SW is advanced to before the rising edge of the second stage carry signal Carry2, the second stage shift register 10 will work in the second working mode, thereby moving the low-frequency display partition position of the display panel upward. Therefore, by controlling the rising edge of the frequency switching signal SW between the rising edges of the carry signals Carry output by the two stages of the shift register 10, the low-frequency display partition position of the display panel corresponds to the two rows of pixel circuits connected by the two stages of the shift register 10.

[0139] It should also be noted that if the target position of the up-scaling display partition corresponds to the fourth stage shift register 10 and the fifth stage shift register 10, the falling edge of the frequency switching signal SW should be controlled to be after the rising edge of the fourth stage carry signal Carry4, i.e. the falling edge jump time t02 is set within the time period of the second shaded area in FIG. 6, so that the third stage and the fourth stage shift register 10 can maintain the off potential of the output scan signal EOUT. Figure 15

[0140] Specifically, since the rising edge of the frequency switching signal SW is set before the rising edge of the third stage carry signal Carry3, and also before the rising edge of the fourth stage carry signal Carry3, and the falling edge of the frequency switching signal SW is after the rising edge of the fourth stage carry signal Carry4, the driving process of the fourth stage shift register 10 is consistent with that in FIG. 5. Since the falling edge of the frequency switching signal SW is before the rising edge of the fifth stage carry signal Carry5, the high potential maintaining stage of the frequency switching signal SW is completely before the rising edge of the fifth stage carry signal Carry5, and before that the potential VN55 of the intermediate node N5 of the fifth stage shift register 10 is transformed to high potential without affecting the high potential maintaining of the second connection N4 in the stage, after the falling edge jump time t02, the driving process of the fifth stage shift register 10 is consistent with that in FIG. 6. Figure 8 Figure 6 Figure 6 Similarly, after the falling edge jump time t02, the driving process of the sixth stage shift register 10 is consistent with that in FIG. 7. If the rising edge of the frequency switching signal SW is ahead of the rising edge of the fourth stage carry signal Carry4, the fourth stage shift register 10 will work in the first working mode, so as to move the up-scaling display partition position of the display panel upward. Therefore, by controlling the falling edge of the frequency switching signal SW to be between the rising edges of the carry signals Carry outputted by two stage shift registers 10, the up-scaling display partition position of the display panel corresponds to the two rows of pixel circuits connected by the two stage shift registers 10.

[0141] ​​​For example, the timing and number of potential transitions in the frequency switching signal SW can differ in different partial refresh frames. In this embodiment, whether the scan signal EOUT of each stage shift register 10 outputs a conduction potential is controlled by the transmission control module 130 of that stage and is independent of the output state of the scan signals EOUT of other stages. Therefore, the refresh frequency corresponding to each display area is only related to the output state of the shift register 10 corresponding to that display area and has no correlation with the refresh frequency of other display areas. Thus, this embodiment of the invention easily enables arbitrary switching of refresh frequencies for different display areas. In practical applications, by adjusting the order and number of full refresh frames and various partial refresh frames, combinations of various display frequencies for various partitions can be achieved.

[0142] For example, when the first display area A1 displays at a refresh rate f, the second display area A2 displays at a refresh rate f / 4, and the third display area A3 displays at a refresh rate f / 2, the combination of various display frames is as follows: Figure 16 As shown. See also Figure 16 For example, the first display area A1 corresponds to the shift registers from level 1 to level k-1, the second display area A2 corresponds to the shift registers from level k to level m-1, and the third display area A3 corresponds to the shift registers from level m to level n. i, k, m, and n are all positive integers and increase sequentially. Figure 16 The diagram illustrates the waveforms of the scan signals output by the first-stage shift registers for each display area. For each row of sub-pixels in the first display area A1, data refresh can be performed in each display frame. For each row of sub-pixels in the second display area A2, a three-hold frame interval can be set between two adjacent refresh frames. The scan signals for each stage of this display area can contain conduction pulses only in the 4i-3rd display frames, maintaining a cutoff potential in other display frames. For each row of sub-pixels in the third display area A3, odd-numbered frames can be set as refresh frames and even-numbered frames as hold frames. The scan signals for each stage of this display area can contain conduction pulses only in odd-numbered frames.

[0143] Then, the display frame F1 is a full refresh frame, and the frequency switching signal SW keeps low potential in the display frame F1. The display frames F2-F4 are partial refresh frames. In the display frame F2 (or F4), the shift registers corresponding to the first display area A1 work in the first working mode, and the other shift registers work in the second working mode, that is, the frequency reduction display sub-area position between the first display area A1 and the second display area A2 is included, so the frequency switching signal has a rising edge between the rising edges of the (k-1)th and kth stage transfer signals, and only one potential jump is performed in the display frame. In the display frame F3, the shift registers corresponding to the first display area A1 and the third display area A3 work in the first working mode, and the other shift registers work in the second working mode, that is, the frequency reduction display sub-area position between the first display area A1 and the second display area A2, and the frequency increase display sub-area position between the second display area A2 and the third display area A2 are included; so the frequency switching signal has a rising edge between the rising edges of the (k-1)th and kth stage transfer signals, and a falling edge between the rising edges of the (m-1)th and mth stage transfer signals, and two potential jumps are performed in the display frame.

[0144] The four display frames F1-F4 are taken as one cycle (CYCLE1), and the driving process in the cycle is repeated, so that stable sub-area multi-frequency display can be realized, in which the refresh frequency of the first display area A1 is f, the refresh frequency of the second display area A2 is f / 4, and the refresh frequency of the third display area A3 is f / 2. If it is necessary to adjust the sub-area positions between the display areas, the potential jump time of the frequency switching signal SW in each type of display frame can be adjusted. If it is necessary to adjust the refresh frequencies of the display areas, the sequence and number of each type of display frame in different cycles can be controlled. In addition, different cycles can be used for display in different time periods of the display process, so that a display scheme with dynamic refresh frequency adjustment can be realized.

[0145] The structure of the pixel circuit 20 using the above-mentioned scanning signal and the connection mode of the pixel circuit 20 and the scanning driving circuit 100 will be described below.

[0146] Figure 17 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application. Referring to Figure 17 In an embodiment, optionally, the pixel circuit 20 includes a driving transistor DTFT, a data writing transistor M24, a threshold compensation transistor M25, a gate initialization transistor M22, an anode initialization transistor M23, a first light-emitting control transistor M26, a second light-emitting control transistor M27, and a storage capacitor Cst, and constitutes a 7T1C architecture pixel circuit.

[0147] The first light-emitting control transistor M26, the driving transistor DTFT, the second light-emitting control transistor M27 and the light-emitting device OLED are connected in series; the data writing transistor M24 is connected to the data voltage Vdata and is electrically connected to the first electrode of the driving transistor DTFT; the threshold compensation transistor M25 is connected between the gate and the second electrode of the driving transistor DTFT; the gate initialization transistor M22 is connected to the first initialization signal Vref1 and is electrically connected to the gate of the driving transistor DTFT; the anode initialization transistor M23 is connected to the second initialization signal Vref2 and is electrically connected to the anode of the light-emitting device OLED; the cathode of the light-emitting device OLED is connected to the second power supply signal VSS; one end of the storage capacitor Cst is connected to the gate of the driving transistor DTFT, and the other end is connected to the first power supply signal VDD. The gate of the gate initialization transistor M22 is connected to the first control signal S1, the gates of the data writing transistor M24 and the anode initialization transistor M23 are connected to the second control signal S2, the gate of the threshold compensation transistor M25 is connected to the third control signal S3, and the gates of the first light-emitting control transistor M26 and the second light-emitting control transistor M27 are connected to the light-emitting control signal EM.

[0148] Exemplarily, the threshold compensation transistor M25 and the gate initialization transistor M22 can be N-type transistors, and the other transistors can be P-type transistors, to form the LTPO pixel circuit.

[0149] Figure 18 is a driving timing diagram of a pixel circuit provided by an embodiment of the present application. In combination with Figure 17 and Figure 18 Exemplarily, in the low-frequency display, the pixel circuit 20 can include one refresh frame FA and at least one holding frame FI in one display period. In the high-frequency display, the pixel circuit 20 can only include the refresh frame FA in one display period. The refresh frame FA includes an initialization stage T21, a data writing stage T22 and a first light-emitting stage T23. The holding frame FI includes a black insertion stage T24 and a second light-emitting stage T25, and the data writing is not performed in the black insertion stage T24.

[0150] Specifically, taking the low-frequency refresh scenario as an example, the driving process of the pixel circuit includes:

[0151] In the initialization stage T21, the first control signal S1, the second control signal S2 and the light-emitting control signal EM are all high potentials. The transistor M22 is turned on, and the first initialization signal Vref1 is initialized to the gate of the driving transistor DTFT through the transistor M22.

[0152] In the data writing stage T22, the first control signal S1 and the second control signal S2 are both at low potential, and the third control signal S3 and the light emitting control signal EM are both at high potential. The transistor M22 is turned off, and the transistors M23, M24 and M25 are all turned on. The data signal Vdata is transmitted to the gate of the driving transistor DTFT through the transistor M24, the first electrode and the second electrode of the driving transistor DTFT, and the transistor M25, so as to complete data writing. Meanwhile, the second initialization signal Vref2 is transmitted to the anode of the light emitting device OLED through the transistor M23, so as to realize initialization of the anode of the light emitting device OLED.

[0153] In the first light emitting stage T23, the first control signal S1, the third control signal S3 and the light emitting control signal EM are all at low potential, and the second control signal S2 is at high potential. The transistor M25 is turned off, and the transistors M26 and M27 are both turned on, so as to transmit the driving current generated by the driving transistor DTFT to the light emitting device OLED, and drive the light emitting device OLED to emit light.

[0154] In the black frame insertion stage T24, the first control signal S1 and the third control signal S3 remain at low potential, the second control signal S2 remains at high potential, and the light emitting control signal EM becomes high potential. The transistors M26 and M27 are both turned off, and the light emitting device OLED stops emitting light.

[0155] In the second light emitting stage T25, the first control signal S1 and the third control signal S3 remain at low potential, the second control signal S2 remains at high potential, and the light emitting control signal EM again becomes low potential. The transistors M26 and M27 are again turned on, so as to drive the light emitting device OLED to emit light by the driving current generated by the driving transistor DTFT.

[0156] The driving process of the frame FI is repeated until the next refresh frame FA arrives.

[0157] In the scanning driving circuit 100 provided by the embodiment of the present application, the scanning signal EOUT output by each stage of the shift register 10 can be used as the first control signal S1 and / or the third control signal S3 required in the pixel circuit 20.

[0158] In an embodiment, two groups of scanning driving circuits 100 can be arranged in the display panel, and are respectively used to provide the first control signal S1 and the third control signal S3 required by each row of pixel circuits 20. Both groups of scanning driving circuits 100 can adopt the driving process as shown in Figure 15 and Figure 16 .

[0159] In another embodiment, the scanning driving circuit 100 can be arranged in the display panel as shown in Figure 19As shown, a group of scan driving circuits 100 can be arranged in the display panel to provide the first control signal S1 and the third control signal S3 for each row of pixel circuits 20. The connection relationship between the scan driving circuit 100 and the pixel circuit 20 will be described below in combination with Figure 19 In this case, the connection relationship between the scan driving circuit 100 and the pixel circuit 20 will be described. Referring to Figure 19 For example, the scan signal output by the jth-stage shift register 10 can be used as the third control signal required by the j-1th-row pixel circuit 20 and as the first control signal required by the jth-row pixel circuit 20, so as to provide the first control signal S1 and the third control signal S3 with overlapping conduction pulses as shown in Figure 19 For example, the second-stage scan signal EOUT2 can be used as the third control signal S3 required by the first-row pixel circuit 20 and as the first control signal S1 required by the second-row pixel circuit 20; the third-stage scan signal EOUT3 can be used as the third control signal S3 required by the second-row pixel circuit 20 and as the first control signal S1 required by the third-row pixel circuit 20, and so on. Figure 18 In this case, the data writing stage T22 of each row of pixel circuits 20 can be arranged to avoid the overlapping period of the conduction pulses of the first control signal S1 and the third control signal S3, and the data writing stage T22 can be arranged between the falling edge of the first control signal S1 and the falling edge of the third control signal S3 to which the pixel circuit 20 is connected.

[0160] For example, the data writing stage T22 of the current row of pixel circuits 20 can be arranged between the falling edge of the previous-stage shift signal and the falling edge of the current-stage shift signal, so as to realize the row-by-row scanning of the pixel circuits 20. For example, the driving process shown in

[0161] Figure 2 For example, the driving process shown in Figure 20 . Figure 20 In the display frame F2, the data refresh is not performed for the middle two rows of pixel circuits, and the signal transition edge of the slice frequency signal SW is filled with sparse dotted shading, and the data refresh is represented by dense dotted shading, and no data refresh is represented by blank filling. It can be seen that the display frame F1 is a full refresh frame, and the data refresh is performed for each row of pixel circuits; the display frame F2 is a partial refresh frame, and the data refresh is not performed for the middle two rows of pixel circuits.

[0162] ​In addition, other drive circuits can also be included in the display panel, such as a second control signal S2 required for providing a gate of a data writing transistor M24 in the pixel circuit 20, and an emission control signal EM required for providing a gate of two emission control transistors; and both types of drive circuits can always maintain high-frequency output.

[0163] It should be noted that the above embodiments show the case where the conduction pulses between adjacent two-stage stage transmission signals overlap, but this is not a limitation of the present application. In other embodiments, the structure of the transmission control module 110 in the shift register 10 and / or the waveform of the first-stage input signal EIN1 can be adjusted so that the conduction pulses between adjacent two-stage stage transmission signals do not overlap.

[0164] It should also be noted that the structure of the shift register 10 in the above embodiments is not a limitation of the present application, and in other embodiments, the shift register 10 can be improved based on any existing structure of a shift register circuit. For any type of shift register circuit, the original output module is used as a stage transmission output module 120 only for cascading, and a set of scan output modules 140 are added, and a transmission control module 130 and its related structures are added between the control end for controlling the communication state between the conduction potential input end and the output end and one of the output ends of the drive control module 110, so as to realize the function of the shift register 10 in the embodiments of the present application.

[0165] It should also be noted that the scan driving circuit 100 provided in the above embodiments can be applied to an LTPO pixel circuit, but this is not a limitation of the present application. In other embodiments, each shift register 10 is replaced with a long high-potential output structure to output a low-potential conduction potential pulse, such as a modification on the basis of an 8T2C architecture, so that the scan driving circuit 100 can be applied to an LTPS pixel circuit.

[0166] It should also be noted that each transistor involved in the above embodiments can have a first electrode referred to as a source or a drain, and a second electrode referred to as a drain or a source. Since the structure of the transistor in the display panel is symmetrical, the source and the drain of each transistor are not distinguished.

[0167] The embodiments of the present application also provide a display device including the scan driving circuit provided by any of the embodiments of the present application, which has the corresponding beneficial effects. Figure 21 is a structural schematic diagram of a display device provided by an embodiment of the present application. Referring to Figure 21The display device may, for example, include a display panel and a driving chip 50. The scan driving circuit 100 and the pixel circuit 20 are arranged in the display panel, and the scan driving circuit 100 provides a scan signal to each row of pixel circuits 20 through each row of scan lines LS. The driving chip 50 may, through an input signal line, provide a first-stage input signal EIN1 to the first-stage shift register 10 in the scan driving circuit 100, and through each data line LD, provide a data voltage to each column of pixel circuits 20.

[0168] The display device driving method may, for example, include the following steps.

[0169] The cut frequency signal is controlled to remain unchanged in some display frames and to jump in potential in some display frames, so that the frequencies of the scan signals output by at least two shift registers are different, to realize the partitioned frequency display of the display device.

[0170] The display device driving method provided by the embodiment of the present application. The stage transmission output module can realize the stage-by-stage shift output of the first-stage input signal, and provide a stage transmission signal with the same frequency as the first-stage input signal, to provide a basis for the free selection of the scan signal with the same frequency as the first-stage input signal or the scan signal with a frequency lower than the first-stage input signal by each stage shift register. Through the cooperation between the stage transmission signals and the cut frequency signal, the on / off between the first connection end and the second connection end of the transmission control module can be adjusted to allow / block the transmission of the potential of the first output end to the second connection end of the transmission control module, to allow / block the on potential of the scan output module to output the scan signal, to realize the control of the working mode of the shift register. Through the control of the potential jump process of the cut frequency signal, the working mode combination of at least two shift registers can be different, so that the frequencies of the scan signals output by at least two shift registers are different, to realize the partitioned frequency display of the display device.

[0171] Specifically, in each display frame, the cut frequency signal may, after the on potential of the stage transmission signal output by the previous stage shift register, jump in potential before the on potential of the stage transmission signal output by the current stage shift register, to control the frequency of the current stage scan signal to be different from the frequency of the previous stage scan signal.

[0172] Exemplarily, the potential jump of the frequency switching signal can be controlled to occur in any required display frame, so as to control the refresh frequency of each display area. The potential jump of the frequency switching signal can be set to occur only once or multiple times in a display frame according to requirements, so as to control the number of display partitions of the display device. In addition, the time node of the potential jump of the frequency switching signal in different display frames can be different, so as to realize dynamic adjustment of the display partition position in the display process. Accordingly, the multi-partition and multi-frequency display of the display device can be realized, and the display partition position and the display frequency of each area are dynamically adjustable.

[0173] It should be noted that in the above embodiments of the scan driving circuit, the driving methods are specifically described for different scan driving circuits and display panels constituted by the scan driving circuits. These driving methods can be considered as the driving method of the display device provided by the embodiments of the present application, and the repeated contents will not be described herein.

[0174] It should be understood that the steps shown above can be reordered, added, or deleted using various forms of flow. For example, each step described in the present application can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, and the present application is not limited herein.

[0175] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A scanning drive circuit, characterized in that, include: Multiple shift registers configured in a cascaded manner; The shift register includes: A drive control module, wherein the drive control module is used to control the potential of the first output terminal and the second output terminal of the drive control module according to the input signal of the shift register; A stage transmission output module is connected to the first output terminal and the second output terminal respectively, and is used to output a stage transmission signal in response to the potential of the first output terminal and the second output terminal; the stage transmission signal serves as the input signal for the next stage shift register. A transmission control module, wherein the first connection terminal of the transmission control module is connected to the second output terminal, the input terminal of the transmission control module is connected to a frequency cutting signal, and the control terminal of the transmission control module is connected to the output terminal of the stage transmission output module; A scanning output module is provided, wherein a first control terminal of the scanning output module is connected to a first output terminal, and a second control terminal of the scanning output module is connected to a second connection terminal of the transmission control module. The scanning output module is used to output a scanning signal in response to the potential of the second connection terminal. The transmission control module is used to control whether the potential of the second output terminal is transmitted to the second connection terminal according to the transmission signal and the frequency cutting signal, so as to control the frequency of the scanning signal.

2. The scanning drive circuit according to claim 1, characterized in that, The input terminals of the transmission control modules in each of the shift registers are connected to the same frequency switching signal; The frequency switching signal maintains a constant potential in some display frames and undergoes a potential jump in other display frames, so that the scanning signals output by at least two shift registers have different frequencies, thereby realizing the segmented frequency display of the display device.

3. The scanning drive circuit according to claim 1 or 2, characterized in that, The transmission control module includes: An output control unit, wherein the input terminal of the output control unit is connected to the first connection terminal, and the output terminal of the output control unit is connected to the second connection terminal; the output control unit is used to control the potential of the second connection terminal according to the potential of its control terminal; An isolation protection unit is provided, wherein the control terminal of the isolation protection unit is connected to the output terminal of the stage transmission module, the input terminal of the isolation protection unit is connected to the frequency cutting signal, and the output terminal of the isolation protection unit is connected to the control terminal of the output control unit; the isolation protection unit is used to respond to the stage transmission signal and cut off the transmission path of the frequency cutting signal to the control terminal of the output control unit.

4. The scanning drive circuit according to claim 3, characterized in that, The output control unit includes a first transistor; the gate of the first transistor serves as the control terminal of the output control unit, the first electrode of the first transistor serves as the input terminal of the output control unit, and the second electrode of the first transistor serves as the output terminal of the output control unit. The isolation protection unit includes a second transistor; the gate of the second transistor serves as the control terminal of the isolation protection unit, the first terminal of the second transistor serves as the input terminal of the isolation protection unit, and the second terminal of the second transistor serves as the output terminal of the isolation protection unit.

5. The scanning drive circuit according to claim 1, characterized in that, The shift register further includes a node potential control module, wherein the control terminal of the node potential control module is connected to the first output terminal or to the stage transmission signal output by the shift register of this stage, the input terminal of the node potential control module is connected to the first potential signal line, and the output terminal of the node potential control module is connected to the second connection terminal; the node potential control module is used to respond to the potential of its control terminal and transmit the first potential signal provided by the first potential signal line to the second connection terminal.

6. The scanning drive circuit according to claim 5, characterized in that, The node potential control module includes: a third transistor; the gate of the third transistor serves as the control terminal of the node potential control module, the first terminal of the third transistor serves as the input terminal of the node potential control module, and the second terminal of the third transistor serves as the output terminal of the node potential control module.

7. The scanning drive circuit according to claim 1, characterized in that, The potential of the second connection terminal is used to control whether the scan output module outputs the on potential of the scan signal.

8. The scanning drive circuit according to claim 1, characterized in that, The scan output module includes: The first output unit is electrically connected to the first output terminal and is used to transmit the second potential signal to the output terminal of the scanning output module in response to the potential conduction of the first output terminal. The second output unit is electrically connected to the second connection terminal and is used to transmit the first potential signal to the output terminal of the scanning output module in response to the potential conduction of the second connection terminal.

9. The scanning drive circuit according to claim 8, characterized in that, The first output unit includes a fourth transistor, the gate of which is connected to the first output terminal, the first terminal of which is connected to a second potential signal line, and the second terminal of which is connected to the output terminal of the scan output module. The second output unit includes a fifth transistor and a first capacitor; the gate of the fifth transistor is connected to the second connection terminal, the first electrode of the fifth transistor is connected to the first potential signal line, and the second electrode of the fifth transistor is connected to the output terminal of the scan output module; the first capacitor is connected between the gate and the first electrode of the fifth transistor.

10. The scanning drive circuit according to claim 1, characterized in that, The level transmission output module includes: The third output unit is electrically connected to the first output terminal and is used to transmit the second potential signal to the output terminal of the stage transmission module in response to the potential conduction of the first output terminal. The fourth output unit is electrically connected to the second output terminal and is used to transmit the first potential signal to the output terminal of the stage transmission module in response to the potential conduction of the second output terminal.

11. The scanning drive circuit according to claim 10, characterized in that, The third output unit includes a sixth transistor; the gate of the sixth transistor is connected to the first output terminal, the first terminal of the sixth transistor is connected to the second potential signal line, and the second terminal of the sixth transistor is connected to the output terminal of the stage transmission module. The fourth output unit includes a seventh transistor and a second capacitor; the gate of the seventh transistor is connected to the second output terminal, the first terminal of the seventh transistor is connected to the first potential signal line, and the second terminal of the seventh transistor is connected to the output terminal of the stage transmission module. The second capacitor is connected between the gate and the first electrode of the seventh transistor.

12. The scanning drive circuit according to claim 1, characterized in that, The drive control module includes: An input unit, the output terminal of which is connected to the first output terminal, is used to transmit the input signal to the first output terminal in response to a first clock signal; The first control unit is used to respond to the first clock signal and transmit the second potential signal to the output terminal of the first control unit; The second control unit is connected between the output terminal of the first control unit and the second output terminal, and is used to control the potential of the second output terminal according to the second clock signal and the potential of the output terminal of the first control unit; The first node control unit is connected to the first output terminal and the output terminal of the first control unit respectively, and is used to control the potential of the output terminal of the first control unit according to the potential of the first output terminal; The second node control unit is connected to the first output terminal and the output terminal of the first control unit respectively, and is used to control the potential of the first output terminal according to the potential of the output terminal of the first control unit; The third node control unit is connected to the first output terminal and the second output terminal respectively, and is used to control the potential of the second output terminal according to the potential of the first output terminal.

13. The scanning drive circuit according to claim 12, characterized in that, The drive control module further includes: a protection unit, the first end of which is connected to the output end of the input unit, the second end of which is connected to the first output end, and the control end of which is connected to the second potential signal line; The first node control unit is connected to the first end of the protection unit; the second node control unit is connected to either the first or second end of the protection unit; and the third node control unit is connected to the first end of the protection unit.

14. The scanning drive circuit according to claim 13, characterized in that, The shift register further includes: a node potential control module; the control terminal of the node potential control module is connected to the first terminal or the first output terminal of the protection unit, or connected to the stage transmission signal output by the shift register of this stage; the input terminal of the node potential control module is connected to the first potential signal line, and the output terminal of the node potential control module is connected to the second connection terminal.

15. A display device, characterized in that, include: The pixel circuit and the scanning drive circuit according to any one of claims 1-14.

16. A driving method for a display device, characterized in that, The driving method for driving the display device of claim 15 includes: The frequency switching signal is controlled to maintain a constant potential in some display frames and to perform potential jumps in some display frames, so that the frequencies of the scanning signals output by at least two shift registers are different, so as to realize the segmented frequency display of the display device.

17. The driving method for a display device according to claim 16, characterized in that, The frequency switching signal undergoes a potential jump after the on-potential of the output signal of the previous stage shift register and before the on-potential of the output signal of the current stage shift register, so as to control the frequency of the current stage scanning signal to be different from the frequency of the previous stage scanning signal.

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