Display device

Abstract

A display device is disclosed, comprising: a display panel, on which one or more sub-pixels, including light-emitting devices and driving transistors for driving the light-emitting devices, are disposed in the display area, and the shape of the display panel changes during a transition period; a timing controller for receiving image data and a command signal defining the transition period, and converting the image data to output converted image data; and a data driving circuit for receiving the converted image data and outputting a data voltage, wherein, during the transition period, at least one sub-pixel emits light based on the image data input to the timing controller, and emits light having a brightness lower than the brightness corresponding to a gray level of the image data. Therefore, a display device capable of changing shape during an image display period can be provided.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display device. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images in various forms is constantly increasing, and in recent years, various display devices such as liquid crystal displays and organic light-emitting diode displays have been used.

[0003] Recently, display devices with various shape factors have been used to provide users with a highly immersive image viewing environment.

[0004] As an example of various shape factors, a flexible display device has been proposed. Flexible display devices can be implemented in a variety of designs and offer advantages in portability and durability. Flexible display devices can be implemented as various types of display devices, such as bendable display devices, foldable display devices, and rollable display devices.

[0005] At the same time, in order to provide users with a more diverse image viewing experience, there is a need for a display device that can change the shape of the display panel while the user is viewing the image. Summary of the Invention

[0006] Embodiments of this disclosure may provide a display device in which the shape of the display panel can be changed during an image display period.

[0007] Embodiments of this disclosure may provide a display device comprising: a display panel, wherein one or more sub-pixels, including light-emitting devices and driving transistors configured to drive the light-emitting devices, are disposed in the display area, and the shape of the display panel changes during a transition period; a timing controller configured to receive image data and a command signal defining the transition period, and to convert the image data to output converted image data; and a data driving circuit configured to receive the converted image data and output a data voltage, wherein, during the transition period, at least one sub-pixel emits light based on the image data input to the timing controller, and emits light having a brightness lower than the brightness corresponding to a gray level of the image data.

[0008] According to embodiments of the present disclosure, a display device may be provided in which the shape of the display panel can be changed during an image display period. Attached Figure Description

[0009] Figure 1 A display device according to an embodiment of the present disclosure is shown schematically.

[0010] Figure 2 This is a perspective view of a flexible display device including a display element according to an embodiment of the present disclosure.

[0011] Figure 3 The subpixel structure and configuration for compensating the characteristic values ​​of subpixels of a display device according to embodiments of the present disclosure are schematically illustrated.

[0012] Figure 4 The present disclosure illustrates configurations for supplying various voltages to a display panel in a display device, according to embodiments thereof.

[0013] Figures 5 to 7 This is a diagram used to explain the configuration of a timing controller that controls the power management circuitry and / or data drive circuitry during changing time periods based on command signals.

[0014] Figure 8 This illustrates the reduction in brightness across the entire display area during the transition period of the display panel.

[0015] Figure 9 This illustrates a reduction in brightness in at least a portion of the display area during a transition period of the display panel.

[0016] Figure 10 The circuit film on which the active driver integrated circuit is mounted is shown. Detailed Implementation

[0017] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and wherein the same reference numerals and symbols may be used to denote the same or similar parts even when shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and components incorporated herein will be omitted where it is determined that such description may make the subject matter of some embodiments of the invention considerably unclear. Terms used herein, such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from,” are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” When used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0018] In this document, terms such as "first," "second," "A," "B," "(A)," or "(B)" may be used to describe elements of the invention. Each of these terms is not used to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0019] When referring to the first element and the second element as "connected or joined," "in contact or overlapping," etc., it should be understood that not only can the first element be "directly connected or joined" or "directly in contact or overlapping" with the second element, but a third element can also be "inserted" between the first element and the second element, or the first element and the second element can be "connected or joined," "in contact or overlapping," etc., with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or joined," "in contact or overlapping," etc., with each other.

[0020] When time-related terms (such as “after,” “after,” “next,” “before,” etc.) are used to describe a process or operation of an element or configuration, or a flow or step in an operation, processing, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless the terms “direct” or “immediate” are used simultaneously.

[0021] Furthermore, when referring to any size, relative size, etc., even if no specific description is specified, the numerical or corresponding information of the component or feature (e.g., level, range, etc.) should be considered to include the range of tolerances or errors that can be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0022] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 This is a schematic diagram illustrating a display device 100 according to an embodiment of the present disclosure.

[0024] Reference Figure 1 The display device 100 according to the embodiments of the present disclosure may include a display panel 110, a data driving circuit 120 and a gating driving circuit 130 for driving the display panel 110, and a timing controller 140 configured to control the data driving circuit 120 and the gating driving circuit 130.

[0025] Signal lines such as multiple data lines DL and multiple gating lines GL can be provided on the display panel 110 on the substrate. Multiple sub-pixels SP electrically connected to the multiple data lines DL and multiple gating lines GL can be provided on the display panel 110.

[0026] The display panel 110 may include a display area AA for displaying images and a non-display area NA for not displaying images. Multiple sub-pixels SP for displaying images are disposed in the display area AA. The data driving circuit 120 and the gating driving circuit 130 may be installed in the non-display area NA, or may be disposed on pad portions connected to the data driving circuit 120 or the gating driving circuit 130.

[0027] Data drive circuit 120 is configured to drive multiple data lines DL and can provide data voltages to the multiple data lines DL. Gating drive circuit 130 is configured to drive multiple gating lines GL and can provide gating signals (also called gating voltages or scan signals) to the multiple gating lines GL. Timing controller 140 can provide a data drive timing control signal DCS to data drive circuit 120 to control the operation of data drive circuit 120. Timing controller 140 can provide a gating drive timing control signal GCS to gating drive circuit 130 to control the timing of the operation of gating drive circuit 130.

[0028] The timing controller 140 can start scanning according to the timing implemented in each frame, convert the input image data from the external input to match the data signal format used by the data drive circuit 120, provide the converted image data DATA to the data drive circuit 120, and control the data drive at the appropriate time according to the scanning.

[0029] The timing controller 140 can receive various timing signals from the host system 150 along with the input image data, including the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the input image data enable signal DE, and the clock signal CLK.

[0030] In order to control the data drive circuit 120 and the gating drive circuit 130, the timing controller 140 can receive vertical synchronization signal Vsync, horizontal synchronization signal Hsync, input data enable signal DE and clock signal CLK, etc., and can generate various control signals (e.g., DCS, GCS, etc.) to output to the data drive circuit 120 and the gating drive circuit 130.

[0031] The timing controller 140 can output various data drive timing control signals DCS, including the source start pulse SSP and the source sampling clock SSC, in order to control the data drive circuit 120.

[0032] The timing controller 140 can output various gating drive timing control signals GCS, including gating start pulse GSP, gating shift clock GSC, gating output enable signal GOE, etc., in order to control the gating drive circuit 130.

[0033] The data drive circuit 120 receives the converted image data DATA from the timing controller 140 and drives multiple data lines DL.

[0034] The data drive circuit 120 may include one or more source driver integrated circuits (SDICs).

[0035] Each source driver integrated circuit (SDIC) can be connected to the display panel 110 via a tape auto-bonding (TAB) method, or to a bonding pad of the display panel 110 via a chip-on-glass (COG) method, or electrically connected to the display panel 110 via a chip-on-film (COF) method.

[0036] The gating drive circuit 130 can output a gating signal with an on-level voltage or a gating signal with an off-level voltage under the control of the timing controller 140. The gating drive circuit 130 can drive multiple gating lines GL by providing gating signals with on-level voltages to multiple gating lines GL.

[0037] The gate drive circuit 130 can be connected to the display panel 110 via the tape automatic bonding (TAB) method, or via the chip on glass (COG) method or the chip on panel (COP) method, or can be electrically connected to the display panel 110 via the chip on film (COF) method.

[0038] The gate driving circuit 130 can be formed in the non-display area NA of the display panel 110 in the form of a gate in-panel (GIP) type. The gate driving circuit 130 can be disposed on the substrate of the display panel 110 or connected to the substrate of the display panel 110. In the case of the gate in-panel (GIP) type, the gate driving circuit 130 can be disposed in the non-display area NA of the substrate. In the case of the chip-on-glass (COG) method or the chip-on-film (COF) method, the gate driving circuit 130 can be connected to the substrate of the display panel 110.

[0039] If a specific gating line GL is turned on by the gating drive circuit 130, the data drive circuit 120 can convert the image data DATA received from the timing controller 140 into an analog data voltage to provide to multiple data lines DL.

[0040] The data driving circuit 120 can be connected to or disposed on one side of the display panel 110 (e.g., the top or bottom side). Depending on the driving method, panel design method, etc., the data driving circuit 120 can be connected to or disposed on both sides of the display panel 110 (e.g., the top and bottom sides), or it can be connected to two or more of the four sides of the display panel 110.

[0041] The gating drive circuit 130 can be connected to one side of the display panel 110 (e.g., the left or right side). Depending on the driving method, panel design method, etc., the gating drive circuit 130 can be connected to both sides of the display panel 110 (e.g., the left and right sides), or it can be connected to two or more of the four sides of the display panel 110.

[0042] The timing controller 140 may be a timing controller used in conventional display technology, or it may be a control device capable of further performing other control functions including the timing controller, or it may be circuitry within a control device. The timing controller 140 may be implemented using various circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0043] The timing controller 140 can be mounted on a printed circuit board (PCB), flexible printed circuit board (FPCB), etc., and can be electrically connected to the data drive circuit 120 and the gating drive circuit 130 via the PCB, FPCB, etc.

[0044] The timing controller 140 can send signals to / receive signals from the data drive circuit 120 according to one or more predetermined interfaces. Here, for example, the interface may include a low-voltage differential signaling (LVDS) interface, an EPI interface, and a serial peripheral interface (SPI).

[0045] The timing controller 140 may include a storage medium, such as one or more registers.

[0046] The display device 100 according to the embodiments of this disclosure may be a display device including a liquid crystal display (LCD) device with a backlight unit, or it may be a self-emissive display device such as an organic light-emitting diode (OLED) display, a quantum dot display, and a micro LED display.

[0047] When the display device 100 according to an embodiment of the present disclosure is an OLED display, each sub-pixel SP may include an organic light-emitting diode (OLED) as a light-emitting device. If the display device 100 according to an embodiment of the present disclosure is a quantum dot display, each sub-pixel SP may include a light-emitting device made of quantum dots, where quantum dots are self-emissive semiconductor crystals. In the case of a micro-LED display according to an embodiment of the present disclosure, each sub-pixel SP may include a micro-LED as a light-emitting device, which is self-emissive and made of inorganic materials. Hereinafter, for ease of description, an OLED display will be used as an example to describe the display device 100 according to an embodiment of the present disclosure, but the present disclosure is not limited thereto.

[0048] Meanwhile, if the display device 100 according to the embodiments of the present disclosure is a self-emissive display device, the display panel 110 according to the embodiments of the present disclosure may be a flexible display panel.

[0049] Figure 2This is a perspective view of a flexible display device 200 including a display device 100 according to an embodiment of the present disclosure.

[0050] Reference Figure 2 The flexible display device 200 according to embodiments of the present disclosure may include a display device 100 and a rear cover 210 disposed on the rear side of the display device 100. Additionally, the flexible display device 200 according to embodiments of the present disclosure may also include a cover member 220 disposed on the rear side of the rear cover 210.

[0051] The flexible display device 200 according to embodiments of the present disclosure may have a shape that can be changed into a flat shape or a curved shape. Specifically, in the flexible display device 200 according to embodiments of the present disclosure, the shape can be changed from a flat shape to a curved shape, or the shape can be changed from a curved shape to a flat shape. Therefore, the flexible display device 200 according to embodiments of the present disclosure can be implemented in various forms, such as a bendable display device, a foldable display device, or a rollable display device.

[0052] Reference Figure 2 The flexible display device 200 according to embodiments of the present disclosure may have one or more bending axes. For example, in the flexible display device 200, the shape of the flexible display device 200 may be changed such that the left and right sides of the display device 100 face forward relative to the bending axes.

[0053] The flexible display device 200 can be folded based on one or more bending axes.

[0054] One or more bending axes may be located at the center of the flexible display device 200, or near the edge away from the center. However, embodiments of this disclosure are not limited thereto. One or more bending axes may be located at any position on the flexible display device 200.

[0055] Reference Figure 2 The bending axis can extend from the upper side to the lower side of the flexible display device 200. Alternatively, the bending axis can extend from the left side to the right side of the flexible display device, or alternatively, from one side to the other.

[0056] Meanwhile, when the shape of the flexible display device 200 changes from a flat shape to a curved shape or from a curved shape to a flat shape, stress can be applied to the components disposed in the display device 100 and the back cover 210 due to the change in shape.

[0057] For example, the shape of the flexible display device 200 can change from a normal flat shape in the normal phase or normal state during the transition period. When the transition period ends, the flexible display device 200 can have a normal curved shape in the normal phase or normal state.

[0058] Alternatively, the shape of the flexible display device 200 can change from a normal curved shape during the transition period. When the transition period ends, the shape of the flexible display device can be a normal flat shape.

[0059] Compared to the normal state, more stress may be applied to the display device 100 during the transformation period when shape changes occur. Therefore, during the transformation period, the bonding condition between each component of the display device 100 may deteriorate, and a solution to this problem is required.

[0060] Figure 3 This is a diagram that briefly illustrates the structure of the sub-pixel SP of a display device according to an embodiment of the present disclosure and the configuration for compensating the characteristic values ​​of the sub-pixel SP.

[0061] Reference Figure 3 Each of the multiple sub-pixels SP may include a light-emitting device ED, a driving transistor DRT, a scanning transistor SCT, and a storage capacitor Cst.

[0062] A light-emitting device (ED) may include a first electrode, a second electrode, and a light-emitting layer (EL) located between the first electrode and the second electrode.

[0063] The first electrode of the light-emitting device (ED) is the pixel electrode (PE), and the second electrode of the ED is the common electrode (CE).

[0064] The pixel electrode PE of the light-emitting device ED can be an electrode disposed in each sub-pixel SP, and the common electrode CE can be an electrode commonly disposed in all sub-pixels SP. Here, the pixel electrode PE can be an anode electrode, and the common electrode CE can be a cathode electrode. Alternatively, the pixel electrode PE can be a cathode electrode, and the common electrode CE can be an anode electrode.

[0065] For example, the light-emitting device (ED) can be an organic light-emitting diode (OLED), a light-emitting diode (LED), or a quantum dot light-emitting device.

[0066] A driving transistor (DRT) is a transistor used to drive a light-emitting device (ED), and may include a first node N1, a second node N2, a third node N3, etc.

[0067] The first node N1 of the driving transistor DRT can be the gate node of the driving transistor DRT and can be electrically connected to the source or drain node of the scanning transistor SCT. The second node N2 of the driving transistor DRT can be the source or drain node of the driving transistor DRT and can be electrically connected to the source or drain node of the sensing transistor SENT, and can also be electrically connected to the pixel electrode PE of the light-emitting device ED. The third node N3 of the driving transistor DRT can be electrically connected to the driving voltage line DVL that provides the high-potential driving voltage EVDD.

[0068] The scanning transistor SCT can be controlled by the scanning pulse SCAN, which is a gating signal. The scanning transistor SCT can switch the electrical connection between the first node N1 of the driving transistor DRT and the data line DL. That is, the scanning transistor SCT can be turned on or off according to the scanning pulse SCAN provided from the scanning line SCL, which acts as a gating line GL, and can control the electrical connection between the data line DL and the first node N1 of the driving transistor DRT.

[0069] The scanning transistor SCT can be turned on by the scanning pulse SCAN with a turn-on voltage, and the data voltage Vdata supplied from the data line DL can be transmitted to the first node N1 of the driving transistor DRT.

[0070] Here, when the scanning transistor SCT is an n-type transistor, the on-state voltage of the scanning pulse SCAN can be a high-level voltage. If the scanning transistor SCT is a p-type transistor, the on-state voltage of the scanning pulse SCAN can be a low-level voltage.

[0071] The storage capacitor Cst can be electrically connected to the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst is charged with an amount of charge corresponding to the voltage difference between its two ends, and is used to maintain the voltage difference between its two ends for a predetermined frame time. Therefore, the corresponding sub-pixel SP can emit light during the predetermined frame time.

[0072] Reference Figure 3 Each of the plurality of sub-pixels SP disposed on the display panel 110 of the display device 100 according to embodiments of the present disclosure may further include a sensing transistor SENT.

[0073] The sensing transistor SENT can be controlled by a sensing pulse SENSE, which is a gating signal. The sensing transistor SENT can be electrically connected to the second node N2 of the driving transistor DRT and the reference voltage line RVL. That is, the sensing transistor SENT is turned on or off according to the sensing pulse SENSE provided from the sensing line SENL (which is another gating line GL), and the sensing transistor SENT can switch the electrical connection between the reference voltage line RVL and the second node N2 of the driving transistor DRT.

[0074] The second node N2 of the driving transistor DRT is also called the sensing node.

[0075] The sensing transistor SENT can be turned on by a sensing pulse SENSE with a conduction level voltage, and the initialization voltages VpreR, VpreS, etc., provided from the reference voltage line RVL can be transmitted to the second node N2 of the driving transistor DRT. The reference voltage line RVL is also called the sensing line.

[0076] The first initialization switch RPRE can switch the electrical connection between the reference voltage line RVL and the initialization voltage supply node NpreR. The first initialization switch RPRE includes a first terminal electrically connected to the reference voltage line RVL and a second terminal electrically connected to the first initialization voltage supply node NpreR.

[0077] The first initialization voltage VpreR is applied to the first initialization voltage supply node NpreR.

[0078] The second initialization switch SPRE can switch the electrical connection between the reference voltage line RVL and the second initialization voltage supply node NpreS. The second initialization switch SPRE includes a first terminal electrically connected to the reference voltage line RVL and a second terminal electrically connected to the second initialization voltage supply node NpreS.

[0079] A second initialization voltage VpreS is applied to the second initialization voltage supply node NpreS. The voltage level of the second initialization voltage VpreS may be different from the voltage level of the first initialization voltage VpreR.

[0080] The first initialization voltage VpreR can be a voltage input used to initialize the voltage of the second node N2 of the driving transistor DRT when the data voltage Vdata for image display is input to the data line DL. For example, the data voltage Vdata for image display is provided to the first node N1 of the driving transistor DRT, and the first initialization voltage VpreR is provided to the second node N2 of the driving transistor DRT, so that a potential difference can be generated across the storage capacitor Cst.

[0081] The second initialization voltage VpreS can be a voltage input that initializes the voltage at the second node N2 of the driving transistor DRT when the voltage used to sense the characteristic value of the sub-pixel SP is input to the data line DL. For example, the voltage Vdata used to sense the characteristic value of the sub-pixel SP is provided to the first node N1 of the driving transistor DRT, and the second initialization voltage VpreS can be provided to the second node N2 of the driving transistor DRT, so that a potential difference can be generated between the two ends of the storage capacitor Cst.

[0082] The power management circuit can generate a first initialization voltage VpreR and / or a second initialization voltage VpreS, and output the generated voltages to each node.

[0083] The sensing transistor SENT can be turned on by a sensing pulse SENSE with a turn-on level voltage, and transmits the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL.

[0084] Here, if the sensing transistor SENT is an n-type transistor, the on-state voltage of the sensing pulse SENSE can be a high-level voltage. If the sensing transistor SENT is a p-type transistor, the on-state voltage of the sensing pulse SENSE can be a low-level voltage.

[0085] When driving to sense the characteristic value of sub-pixel SP, the function of sensing transistor SENT, which transmits the voltage of the second node N2 of driving transistor DRT to reference voltage line RVL, can be used. In this case, the voltage transmitted to reference voltage line RVL can be a voltage used to calculate the characteristic value of sub-pixel SP or a voltage reflecting the characteristic value of sub-pixel SP.

[0086] Each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT can be an n-type transistor or a p-type transistor. In embodiments of this disclosure, for ease of description, each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT is n-type as an example.

[0087] The storage capacitor Cst may not be a parasitic capacitor (e.g., Cgs, Cgd) that serves as an internal capacitor between the gate node and source node (or drain node) of the driving transistor DRT, but may be an external capacitor intentionally designed outside the driving transistor DRT.

[0088] The scan line SCL and the sensing line SENL can be different gating lines GL. In this case, the scan pulse SCAN and the sensing pulse SENSE can be separate gating signals, and the on-off timing of the scan transistor SCT and the sensing transistor SENT in a sub-pixel SP can be independent. That is, the on-off timing of the scan transistor SCT and the sensing transistor SENT in a sub-pixel SP can be the same or different.

[0089] Alternatively, the scan line SCL and the sensing line SENL can be the same gating line GL. That is, the gate node of the scan transistor SCT and the gate node of the sensing transistor SENT in a sub-pixel SP can be connected to a single gating line GL. In this case, the scan pulse SCAN and the sensing pulse SENSE can be the same gating signal, and the turn-on / off timing of the scan transistor SCT and the turn-on / off timing of the sensing transistor SENT in a sub-pixel SP can be the same.

[0090] Figure 3 The structure of the sub-pixel SP shown is merely an example and can be modified in various ways by further including one or more transistors or one or more capacitors, or by omitting one or more transistors or capacitors.

[0091] In addition, Figure 3 In this description, the sub-pixel SP structure is assumed to be a self-emissive display device. However, in the case where the display device 100 is a liquid crystal display device, each sub-pixel SP may include a transistor and a pixel electrode.

[0092] Reference Figure 3 The display device 100 according to this disclosure may include a line capacitor Crvl. The line capacitor Crvl may be a capacitor element with its first terminal electrically connected to a reference voltage line RVL and its second terminal electrically connected to ground GND, or a parasitic capacitor formed on the reference voltage line RVL.

[0093] Meanwhile, the aforementioned data driving circuit may include one or more source driver integrated circuits (SDICs).

[0094] Reference Figure 3 The source driver integrated circuit (SDIC) may include a digital-to-analog converter (DAC). The timing controller 140 can convert the input image data according to a preset interface and output the converted image data to the DAC.

[0095] In some cases, the source driver integrated circuit (SDIC) may also include an analog-to-digital converter (ADC). The ADC can sense the voltage value of the reference voltage line RVL. The voltage sensed by the ADC can be a voltage reflecting the characteristic value of the sub-pixel SP.

[0096] The sampling switch (SAM) can be configured to switch the electrical connection between the analog-to-digital converter (ADC) and the reference voltage line (RVL). The sampling switch (SAM) can be integrated into the source driver integrated circuit (SDIC).

[0097] Meanwhile, the characteristic values ​​of the sub-pixel SP can be the characteristic values ​​of the driving transistor DRT or the light-emitting device ED. The characteristic values ​​of the driving transistor DRT can include the threshold voltage and mobility of the driving transistor DRT. The characteristic values ​​of the light-emitting device ED can include the threshold voltage of the light-emitting device ED.

[0098] The analog-to-digital converter (ADC) can receive analog voltages, convert them into digital values, and output the digital values ​​to the timing controller 140.

[0099] The timing controller 140 may include a memory 310 for storing characteristic value information of sub-pixels SP, and a compensation circuit 320 for performing calculations to compensate for changes in the characteristic values ​​of sub-pixels SP based on the information stored in the memory 310.

[0100] Information used to compensate for the characteristic values ​​of sub-pixels SP can be stored in memory 310. For example, information about the threshold voltage and mobility of the driving transistor DRT for each of the plurality of sub-pixels SP can be stored in memory 310, or information about the threshold voltage of the light-emitting device ED included in the sub-pixel SP can be stored in memory 310.

[0101] Information about the threshold voltage of the light-emitting device (ED) can be stored in a lookup table (LUT) in memory 310.

[0102] The compensation circuit 320 can calculate the degree of change in the characteristic value of the sub-pixel SP based on the digital value input from the analog-to-digital converter (ADC) and the characteristic value information of the sub-pixel SP stored in the memory 310. The characteristic value of the sub-pixel SP stored in the memory 310 can be updated based on the calculated information.

[0103] The timing controller 140 can convert image data by reflecting changes in the characteristic values ​​of sub-pixels SP calculated by the compensation circuit 320, and output the converted image data to the digital-to-analog converter DAC.

[0104] The digital-to-analog converter (DAC) can output the data voltage Vdata, which reflects the change in the characteristic value of the sub-pixel SP, to the data line DL.

[0105] The process of sensing and compensating for changes in the characteristic values ​​of sub-pixels SP is also known as the "sub-pixel characteristic value compensation process".

[0106] Figure 4 The present disclosure schematically illustrates components configured to supply various voltages to a display panel 110 in a display device according to an embodiment of the present disclosure.

[0107] Reference Figure 4 The display device according to embodiments of the present disclosure may include one or more circuit films CF connected to the display panel 110 and a source driver integrated circuit SDIC mounted on the circuit films CF.

[0108] Reference Figure 4 One end of the circuit film CF can be connected to the display panel 110. One end of the circuit film CF can be bonded to a pad portion (not shown) of the display panel 110. The circuit film CF can be bonded to a pad portion located on the front surface of the display panel 110 and is bent in the rearward direction of the display panel 110.

[0109] The other end of the circuit film CF can be connected to the source printed circuit board SPCB.

[0110] The source printed circuit board (SPCB) can be connected to the other end of one or more circuit films (CF). For example, refer to... Figure 4 A source printed circuit board (SPCB) can be connected to the first circuit film CF1 through the eighth circuit film CF8.

[0111] The source printed circuit board (SPCB) can be electrically connected to the control printed circuit board (CPCB) via connecting components.

[0112] The connecting component can be implemented as a flexible flat cable (FFC). The flexible flat cable (FFC) can be connected to the connector CNT disposed on the source printed circuit board (SPCB) and the control printed circuit board (CPCB), respectively, and can be electrically connected between the source printed circuit board (SPCB) and the control printed circuit board (CPCB).

[0113] The timing controller 140 can be mounted on the control printed circuit board (CPCB). The power management circuit 410 can be further mounted on the control printed circuit board (CPCB). One control printed circuit board (CPCB) can be connected to two or more source printed circuit boards (SPCBs).

[0114] At the same time, refer to Figure 4 When the display panel 110 is a flexible display panel, the shape of the display panel 110 can be changed.

[0115] For example, such as Figure 2As shown, the display device 100 can be bent during the transition period based on a bending axis extending in the vertical direction. Therefore, the shape of the display panel 110 can also be bent based on the bending axis.

[0116] If the display panel 110 is bent, stress may be applied to the circuit film CF, which is configured to electrically connect the display panel 110 and the source printed circuit board SPCB.

[0117] In particular, the stress may be stronger in the direction of the two ends of the source printed circuit board (SPCB), and a stronger force may be applied to the circuit films (e.g., CF1 to CF8) connected at the two ends of the source printed circuit board (SPCB).

[0118] When the shape of the display panel 110 is changed while displaying an image, the bonding between the display panel 110 and the circuit film CF may be further weakened due to the heat generated in the display panel 110.

[0119] The power of the display panel 110 can be calculated using Equation 1 below.

[0120] [Equation 1]

[0121] P = I 2 R

[0122] In Equation 1, P is the power, I is the current flowing through the display panel 110, and R is the resistance of the display panel 110. The current flowing through the display panel 110 can be through the drive voltage line DVL (see...). Figure 3 The current flowing through the light-emitting device (ED).

[0123] Since power P can be converted into heat, the amount of heat generated in the display panel 110 can increase proportionally to the square of the current (I^2) when the value of the current I flowing in the drive voltage line DVL of the display panel 110 increases.

[0124] Therefore, the bonding between the display panel 110 and the circuit film CF may be weakened. In particular, the bonding with the circuit film CF at the two ends of the source printed circuit board SPCB that are subjected to the maximum stress may be weakened.

[0125] Therefore, there is a need for a display device that provides a good connection between the display panel 110 and the circuit film CF even when the shape of the display panel 110 is changed while displaying an image.

[0126] Figures 5 to 7 This is a diagram used to explain the configuration of a timing controller that controls the power management circuitry and / or data drive circuitry during changing time periods based on command signals.

[0127] Reference Figure 5 The host system 150 can output a command signal CMD to the timing controller 140, which defines the changing time period of the display device. The command signal CMD can define a normal state or a normal phase.

[0128] For example, the transition period and normal state can be defined according to the logic level of the command signal CMD.

[0129] For example, during a transition period, the display panel can be bent to a preset angle.

[0130] The timing controller 140 can control the power management circuit 410 and / or the data drive circuit 120 to reduce or decrease the brightness of the display device during the transition period based on the input command signal CMD.

[0131] The timing controller 140 can output a first control signal CS1 to the power management circuit 410 during the transition period. The power management circuit 410 can receive the first control signal CS1 and can output a voltage with a different voltage level than the voltage output in the normal state during the transition period.

[0132] For example, compared to the normal state, the power management circuit 410 can output a low-potential drive voltage EVSS (refer to) with a higher (e.g., larger) voltage level during the transition period. Figure 3 Therefore, the voltage difference between the voltages applied to the two ends of the light-emitting device ED can be reduced, thereby reducing the brightness or luminance of at least one sub-pixel.

[0133] In another example, the power management circuit 410 can output a first initialization voltage VpreR with a higher voltage level during the switching period than in the normal state (refer to...). Figure 3 Therefore, the voltage difference between the source and drain nodes of the driving transistor DRT can be reduced, and the voltage value of the current flowing through the light-emitting device ED can also be reduced. Thus, the brightness of at least one sub-pixel can be reduced.

[0134] The timing controller 140 can output the converted image data DATA to the data drive circuit 120 during the conversion period. The timing controller 140 can be based on the data stored in the aforementioned memory 310 (see reference 120). Figure 3 The different characteristic values ​​of the sub-pixels in the image are output as the converted image data DATA.

[0135] For example, the timing controller 140 can control the data drive circuit 120 to output a lower voltage level (or a higher voltage level) data voltage to the data line so that at least one sub-pixel emits light with lower brightness.

[0136] The timing controller 140 can control the power management circuit 410 and / or the data drive circuit 120 during the transition period to cause at least one sub-pixel to emit light with reduced brightness, thereby allowing for a lower current flow through the display panel 110 during the transition period. Therefore, the heat generated in the display panel 110 during the transition period can be significantly reduced.

[0137] Reference Figure 6 and Figure 7 According to one embodiment, when the command signal CMD is at the first logic level LL1, the display device is in a normal phase or normal state, and if the command signal CMD is at the second logic level LL2, the display device can be in a transition period.

[0138] The first logic level LL1 can be low or high, and the second logic level LL2 can be high or low. For ease of description, it is assumed hereafter that the first logic level LL1 is low and the second logic level LL2 is high, but this is not a limitation.

[0139] Reference Figure 6 When the command signal CMD is at a low level, the first initialization voltage VpreR can be a first voltage level V1. When the command signal CMD is at a high level, the first initialization voltage VpreR can be a second voltage level V2. In this case, the second voltage level V2 can be a voltage increased by a preset voltage ΔV from the first voltage level V1.

[0140] That is, refer to Figure 5 and Figure 6 The timing controller 140 can receive the command signal CMD and output the first control signal CS1 to the power management circuit 410 during the transition period. The power management circuit 410 can receive the first control signal CS1 and increase the voltage level of the first initialization voltage VpreR from the first voltage level V1 by a preset voltage ΔV, so as to output the first initialization voltage VpreR of the second voltage level V2 during the transition period.

[0141] Therefore, in the driving transistor of at least one sub-pixel, the voltage difference between the source and drain nodes can be reduced, thereby reducing the current flowing through the driving transistor. This, in turn, reduces the current flowing through the light-emitting device.

[0142] Reference Figure 7When the command signal CMD is at a low level, the low-level drive voltage EVSS can be a first voltage level V1. When the command signal CMD is at a high level, the low-level drive voltage EVSS can be a second voltage level V2. In this case, the second voltage level V2 can be a voltage that is increased by a preset voltage ΔV from the first voltage level V1.

[0143] That is, refer to Figure 5 and Figure 7 The timing controller 140 can receive the command signal CMD and output the first control signal CS1 to the power management circuit 410 during the transition period. The power management circuit 410 can receive the first control signal CS1 and increase the voltage level of the low-level drive voltage EVSS from the first voltage level V1 by a preset voltage ΔV to output the low-level drive voltage EVSS of the second voltage level V2 during the transition period.

[0144] Therefore, the difference between the voltage applied to the first electrode of the light-emitting device and the voltage applied to the second electrode of the light-emitting device can be reduced. Therefore, the magnitude of the current flowing through the light-emitting device can also be reduced.

[0145] Even by slightly reducing the current flowing through the drive voltage lines of the display panel, the heat generated in the display panel can be reduced proportionally to the square of the current (I^2). Therefore, the likelihood of the aforementioned bonding defects occurring can be greatly reduced.

[0146] Therefore, the timing controller can control the power management circuit 410 and / or the data drive circuit 120 to reduce the brightness of the sub-pixels during the transition period and reduce the heat generated from the display panel during the transition period.

[0147] Figure 8 This illustrates the reduction (decrease) in brightness across the entire display area during the transition period of the display panel 110.

[0148] Reference Figure 8 Even if the same image data is input to the timing controller during normal phases and transition periods, differences in the brightness of the image displayed in the display area AA may occur.

[0149] The brightness of the image displayed in the display area AA during the transition period may be lower than the brightness during the normal phase or normal state.

[0150] For example, if the voltage level of the low potential common voltage EVSS, which is the common voltage applied to all sub-pixels, increases during the transition period, the brightness of the sub-pixels in the entire display area AA may decrease.

[0151] Additionally, if the first initialization voltage VpreR is a voltage commonly applied to all sub-pixels, and the voltage level of the first initialization voltage VpreR increases during the transition period, the brightness of the sub-pixels in the entire display area AA may decrease.

[0152] In addition, when the timing controller converts the image data, causing the brightness of all sub-pixels to decrease and outputs the converted image data to the data drive circuit, the brightness of the sub-pixels may decrease in the entire display area AA.

[0153] Figure 9 This illustrates a reduction in brightness in at least a portion of the display area during a transition period of the display panel.

[0154] Reference Figure 9 The brightness of a subpixel can be reduced in at least a portion of the display area AA during the transition period.

[0155] For example, a timing controller can control a data drive circuit so that subpixels located in at least a portion of the display area AA emit light with lower brightness.

[0156] Alternatively, the timing controller can control the power management circuitry to cause subpixels located in at least a portion of the display area AA to emit light with lower brightness.

[0157] Meanwhile, when the brightness of at least one sub-pixel is reduced, the area where the at least one sub-pixel is located can overlap with the curved area in the display panel.

[0158] Reference Figure 9 When the display panel is curved in the central area, the curved area of ​​the display panel and the area where sub-pixels emit light with lower brightness can overlap each other.

[0159] Reference Figure 8 and Figure 9 The display device according to embodiments of the present disclosure may also output a message (not shown) in the display area to notify the user that the shape of the display device is changing during a transformation period in which the shape of the display device changes.

[0160] For example, a message indicating that the shape of the display device is changing can be a text message or an image message displayed together with images of other content in the display area (e.g., movies, games, broadcasts, etc.).

[0161] For example, in a display device according to an embodiment of the present disclosure, the brightness of a subpixel may be reduced in a portion of an area where an image displaying other content is shown, and a message indicating that the shape of the display device is changing may be output in the area where the brightness is reduced.

[0162] Meanwhile, during the transition period, the display device according to the embodiments of the present disclosure can display an image by reducing the brightness of the image data input to the timing controller in at least a portion of the display area.

[0163] Therefore, if preset first image data is input to the timing controller during the transition period, the brightness of the image displayed in at least a portion of the display area can be reduced.

[0164] For example, in a display device according to an embodiment of the present disclosure, even if the same voltage level is applied during a transition period and a normal state period to display a first image in any one of the sub-pixels, the sub-pixels may emit light with different brightness.

[0165] For example, if the preset first image data is image data of a monochrome pattern, the brightness of the monochrome pattern can be reduced and displayed in at least some areas of the display area. Therefore, a brightness difference may occur between areas where the brightness is reduced and not displayed and areas where the brightness is reduced and displayed.

[0166] Meanwhile, in the display device according to the embodiments of the present disclosure, the degree of brightness reduction of the sub-pixels may be different for each region in the display area AA.

[0167] For example, in a display device according to an embodiment of the present disclosure, the degree of brightness reduction of a subpixel may be greatest near the center of the display area AA, and may gradually decrease towards the edge of the display area AA. Therefore, the boundary between the area displaying an image with reduced brightness and the area displaying an image with unreduced brightness in the display area AA may be blurred. Thus, the brightness reduction can be visually perceived by the user of the display device with relatively little. However, embodiments of the present disclosure are not limited to this. For example, the degree of brightness reduction of a subpixel may be greatest at one or more locations in the display area AA, and may be smaller in the remaining areas.

[0168] In addition, by reducing the brightness in the central area of ​​the display area AA, which frequently displays relatively high grayscale images, the effect of reducing the current flowing through the display panel can be significantly increased even if the overall brightness of the display area AA is not reduced.

[0169] Figure 10 The circuit film CF on which the active driver integrated circuit SDIC is mounted is shown.

[0170] Reference Figure 10The circuit film CF may include one or more first pins 1010a and one or more second pins 1010b connected to the display panel, and one or more third pins 1020a and one or more fourth pins 1020b connected to the source printed circuit board SPCB.

[0171] One or more first pins 1010a can be configured to output data voltages transmitted from the source driver integrated circuit SDIC to the display panel.

[0172] One or more second pins 1010b may be electrically connected to a fourth pin 1020b. The circuit film CF may also include a line 1030 for electrically connecting the second pins 1010b and the fourth pin 1020b. The circuit film CF may also include a line 1030 for electrically connecting the source driver integrated circuit SDIC and the first pin 1010a. The circuit film CF may also include a line 1030 for electrically connecting the third pin 1020a and the source driver integrated circuit SDIC.

[0173] DC voltages (such as EVSS, VpreR, etc.) transmitted from the source printed circuit board can be input to one or more fourth pins 1020b. The voltage input to the fourth pin 1020b can be transmitted to the second pin 1010b via line 1030. One or more second pins 1010b can transmit the DC voltage transmitted via line 1030 to the display panel.

[0174] Image data DATA input from the timing controller can be input to one or more third pins 1020a. Image data DATA can be image data converted according to a preset interface (e.g., LVDS interface, etc.). Data-driven control signals input from the timing controller can be input to one or more third pins 1020a.

[0175] Image data DATA input to one or more third pins 1020a can be transmitted to the source driver integrated circuit SDIC via line 1030.

[0176] The source driver integrated circuit SDIC can output data voltage to one or more first pins 1010a based on the input image data DATA.

[0177] One or more first pins 1010a and one or more second pins 1010b may be connected to pad portions provided on the display panel. One or more third pins 1020a and one or more fourth pins 1020b may be electrically connected to pad portions of the source printed circuit board.

[0178] The circuit film CF can be bent at the bend line, so that at least a portion of the circuit film CF can be disposed on the rear side of the display panel.

[0179] At the same time, as mentioned above, the voltage levels of the voltage output from the power management circuit to the display panel can be different during the transition periods when the display device is in normal operation and when the shape of the display device changes.

[0180] Therefore, during the transition period, the voltage level input to the fourth pin 1020b of the circuit membrane CF can be different from the voltage level when the display device is in normal operation.

[0181] For example, in the fourth pin 1020b of the circuit film CF, which is input with a low-potential drive voltage EVSS or a first initialization voltage VpreR, different voltage levels can be applied when the display device is in normal operation and during transition periods when the shape of the display device changes.

[0182] Therefore, embodiments of this disclosure can provide a display device in which the shape of the display device can be changed during an image display period.

[0183] Therefore, embodiments of this disclosure can provide a display device that can greatly reduce the possibility of image quality defects even if the shape of the display device changes during the image display period.

[0184] The above-described embodiments of this disclosure can be briefly summarized as follows.

[0185] Embodiments of this disclosure may provide a display device 100, comprising: a display panel 110, on which one or more sub-pixels SP, including a light-emitting device ED and a driving transistor DRT for driving the light-emitting device ED, are disposed in a display area, and the shape of the display panel 110 changes during a transition period; a timing controller 140 configured to receive image data and a command signal CMD defining the transition period, and to convert the image data to output converted image data DATA; and a data driving circuit 120 configured to receive the converted image data and output a data voltage Vdata, wherein, during the transition period, at least one sub-pixel SP emits light based on the image data input to the timing controller 140, and emits light having a brightness lower than the brightness corresponding to the gray level of the image data.

[0186] In the display device according to the embodiments of the present disclosure, the command signal CMD can define a transition period and a normal state or normal phase, in which the shape of the display panel 110 is fixed.

[0187] In a display device according to an embodiment of the present disclosure, the light-emitting device may include a first electrode PE electrically connected to a driving transistor DRT, a second electrode CE configured to apply a low-potential driving voltage EVSS, and a light-emitting layer EL disposed between the first electrode PE and the second electrode CE.

[0188] The display device according to an embodiment of the present disclosure may further include a power management circuit 410 configured to output a first initialization voltage VpreR and a low-potential drive voltage EVSS applied to a first initialization voltage supply node NpreR to a display panel 110, wherein the first initialization voltage supply node NpreR may be located on the display panel 110 and may be electrically connected to the first electrode PE of the light-emitting device ED via a reference voltage line RVL.

[0189] In the display device according to an embodiment of the present disclosure, the voltage level of the first initialization voltage VpreR output by the power management circuit 410 during the switching period can be higher than the voltage level of the first initialization voltage VpreR output by the power management circuit 410 under normal conditions.

[0190] In the display device according to an embodiment of the present disclosure, the voltage level of the low-potential drive voltage EVSS output by the power management circuit 410 during the switching period can be higher than the voltage level of the low-potential drive voltage EVSS output by the power management circuit 410 under normal conditions.

[0191] In a display device according to an embodiment of the present disclosure, the timing controller 140 may further include a memory 310 storing values ​​for compensating for changes in characteristic values ​​of one or more sub-pixels SP, wherein, during a transition period, the timing controller 140 may compensate at least one sub-pixel with a value different from the value stored in the memory 310.

[0192] In the display device according to an embodiment of the present disclosure, the timing controller 140 can convert image data with a value different from the value stored in the memory 310 according to a preset interface, and output the converted image data to the data driving circuit 120.

[0193] In a display device according to an embodiment of the present disclosure, the data driving circuit 120 may include at least one source driver integrated circuit SDIC, and the source driver integrated circuit SDIC may be mounted on the circuit film CF in a chip-on-film (COF) manner.

[0194] In a display device according to an embodiment of the present disclosure, the circuit film CF may include one or more first pins 1010a configured to output a data voltage Vdata to a display panel 110, one or more second pins 1010b configured to output a DC voltage (e.g., EVSS, VpreR, etc.) to the display panel 110, one or more third pins 1020a electrically connected to a data driving circuit 120 and inputting image data DATA converted according to a preset interface, and one or more fourth pins 1020b configured to receive the DC voltage and transmit the DC voltage to one or more second pins 1010b.

[0195] In the display device according to the embodiments of the present disclosure, the voltage levels of the DC voltage input to one or more fourth pins 1020b during the switching period and in the normal state can be different from each other.

[0196] In a display device according to an embodiment of the present disclosure, at least one sub-pixel SP may be located in a curved area of ​​the curved display panel 110.

[0197] In a display device according to an embodiment of the present disclosure, the display panel 110 can be bent to a preset angle during a transition period.

[0198] According to embodiments of this disclosure, the display device may further include a host system 150 configured to output image data and command signals CMD.

[0199] The above description is presented to enable those skilled in the art to implement and use the technical concepts of the invention, and is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The above description and drawings provide examples of the technical concepts of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention. Therefore, the scope of the invention is not limited to the embodiments shown, but is consistent with the widest scope consistent with the claims. The scope of protection of the invention should be interpreted based on the appended claims, and all technical concepts within their equivalents should be interpreted as being included within the scope of the invention.

[0200] Cross-reference to related applications

[0201] This application claims priority to Korean Patent Application No. 10-2021-0191004, filed on December 29, 2021, which is incorporated herein by reference for all purposes as fully set forth herein.

Claims

1. A display device, the display device comprising: The display panel includes one or more sub-pixels in a display area, the one or more sub-pixels having light-emitting devices and driving transistors configured to drive the light-emitting devices, and the display panel having a shape that changes during a transition period; A timing controller configured to receive image data and a command signal defining the transformation period, and configured to transform the image data to output transformed image data; A data driving circuit, configured to receive the converted image data and output a data voltage; as well as A power management circuit, configured to output a first initialization voltage and a low-level drive voltage applied to a first initialization voltage supply node to the display panel. During the transition period, at least one sub-pixel emits light based on the image data input to the timing controller, and emits light with a brightness lower than the brightness corresponding to the gray level of the image data. The command signal defines the transition period and the normal state in which the shape of the display panel is fixed. The light-emitting device includes a first electrode, which is electrically connected to the driving transistor and configured to be applied with the first initialization voltage. During the transition period, the voltage level of the first initialization voltage output by the power management circuit is greater than the voltage level of the first initialization voltage output by the power management circuit in the normal state.

2. The display device according to claim 1, wherein In the normal state, the display panel has a flat shape or a curved shape.

3. The display device of claim 2, wherein, During the transition period, the shape of the display device changes from the flat shape to the curved shape, or from the curved shape to the flat shape.

4. The display device of claim 1, wherein, The light-emitting device further includes: A second electrode, the second electrode being configured to be applied with the low-potential driving voltage; and A light-emitting layer is located between the first electrode and the second electrode.

5. The display device according to claim 1, wherein The first initialization voltage supply node is electrically connected to the first electrode of the light-emitting device via a reference voltage line.

6. The display device according to claim 1, wherein The first initialization voltage is configured to initialize the voltage of the first electrode of the light-emitting device when the data voltage is input to the gate node of the driving transistor.

7. The display device according to claim 1, wherein The timing controller also includes: A memory configured to store values ​​for compensating for changes in the characteristic values ​​of the one or more sub-pixels. During the transformation period, the timing controller compensates for at least one sub-pixel using a value that is different from the value stored in the memory.

8. The display device of claim 7, wherein, The timing controller is configured to convert the image data compensated for by values ​​different from those stored in the memory according to a preset interface, and output the converted image data to the data driving circuit.

9. The display device according to claim 1, wherein The data driving circuit includes at least one source driver integrated circuit, and the at least one source driver integrated circuit is mounted on the circuit film in a chip-on-film manner.

10. The display device of claim 9, wherein, The circuit film includes: One or more first pins, said one or more first pins being configured to output the data voltage to the display panel; One or more second pins, said one or more second pins being configured to output a DC voltage to the display panel; One or more third pins, electrically connected to the data driving circuit, and image data converted according to a preset interface format is input to the one or more third pins; and One or more fourth pins, the one or more fourth pins being configured to receive the DC voltage and transmit the DC voltage to the one or more second pins.

11. The display device according to claim 1, wherein The at least one sub-pixel is located in the curved region of the curved display panel.

12. The display device according to claim 1, wherein During the transition period, the display panel is bent to a preset angle.

13. The display device according to claim 1, further comprising a host system configured to output the image data and the command signal.

14. The display device of claim 1, wherein, During the transformation period, the at least one sub-pixel emits light with a brightness lower than that corresponding to the gray level of the transformed image data.

15. The display device of claim 1, wherein, When the same image data is input to the timing controller during the normal state and the transition period, the at least one sub-pixel emits light with a lower brightness during the transition period than it does in the normal state.

16. The display device of claim 1, wherein, In the at least one sub-pixel, the degree of brightness reduction of the at least one sub-pixel is different from that of the other sub-pixel.

17. A display device, the display device comprising: The display panel includes one or more sub-pixels in a display area, the one or more sub-pixels having light-emitting devices and driving transistors configured to drive the light-emitting devices, and the display panel having a shape that changes during a transition period; A timing controller configured to receive image data and a command signal defining the transformation period, and configured to transform the image data to output transformed image data; A data driving circuit, configured to receive the converted image data and output a data voltage; as well as A power management circuit, configured to output a first initialization voltage and a low-level drive voltage applied to a first initialization voltage supply node to the display panel. During the transition period, at least one sub-pixel emits light based on the image data input to the timing controller, and emits light with a brightness lower than the brightness corresponding to the gray level of the image data. The command signal defines the transition period and the normal state in which the shape of the display panel is fixed. The light-emitting device includes a first electrode and a second electrode. The first electrode is electrically connected to the driving transistor, and the second electrode is configured to be applied with the low-potential driving voltage. During the transition period, the voltage level of the low-potential drive voltage output by the power management circuit is greater than the voltage level of the low-potential drive voltage output by the power management circuit in the normal state.

18. A display device, the display device comprising: The display panel includes one or more sub-pixels in a display area, the one or more sub-pixels having light-emitting devices and driving transistors configured to drive the light-emitting devices, and the display panel having a shape that changes during a transition period; A timing controller configured to receive image data and a command signal defining the transformation period, and configured to transform the image data to output transformed image data; as well as A data driving circuit, configured to receive the converted image data and output a data voltage, The command signal defines the transition period and the normal state in which the shape of the display panel is fixed. During the transition period, at least one sub-pixel emits light based on the image data input to the timing controller, and emits light with a brightness lower than the brightness corresponding to the gray level of the image data. The data driving circuit includes at least one source driver integrated circuit, and the at least one source driver integrated circuit is mounted on the circuit film in a chip-on-film manner. The circuit film includes: One or more first pins, said one or more first pins being configured to output the data voltage to the display panel; One or more second pins, said one or more second pins being configured to output a DC voltage to the display panel; One or more third pins, electrically connected to the data driving circuit, and image data converted according to a preset interface format is input to the one or more third pins; and One or more fourth pins, said one or more fourth pins being configured to receive the DC voltage and transmit the DC voltage to said one or more second pins, and The voltage levels of the DC voltage input to one or more fourth pins are different from each other during the transition period and the normal state.

Images