Image sensor element and image sensor

Abstract

An image sensor element and an image sensor are provided. The image sensor element includes a transfer transistor TX, a lateral overflow integrated capacitor selection transistor LF, a photodiode PD, and a first overflow path OFP. The transfer transistor TX outputs a readout signal from a first terminal. The lateral overflow integrated capacitor selection transistor LF includes a first terminal connected to a second terminal of the transfer transistor TX, and a second terminal connected to a capacitor. The photodiode PD is commonly connected to a third terminal of the transfer transistor and a third terminal of the lateral overflow integrated capacitor selection transistor LF. The first overflow path OFP is formed between the photodiode PD and the second terminal of the lateral overflow integrated capacitor selection transistor LF. Each of the transfer transistor TX and the lateral overflow integrated capacitor selection transistor LF is configured as a vertical gate transistor.

Description

Technical Field

[0001] The present disclosure relates to an image sensor element using a CMOS pixel including a LOFIC and an image sensor. Background Art

[0002] CMOS image sensors (CIS) have been widely used as imaging elements and a wide variety of CISs having various functions are available.

[0003] Because CIS typically cannot store a large amount of signal charge in the photodiode, the dynamic range is insufficient, which can easily cause image saturation and flicker in LEDs. Therefore, multiple exposures are often performed to obtain high dynamic range (HDR) images. However, multiple exposures can cause a time lag between images obtained at different exposures.

[0004] Several methods have been proposed to increase the amount of signal charge in CIS. For example, Patent Document 1 (US2008 / 0237446A1) uses lateral overflow integration capacitor (LOFIC) pixels. Because LOFIC pixels can handle large amounts of signal charge, they are resistant to charge saturation under high illumination conditions. However, since LOFIC pixels cannot share components between pixels, miniaturization of each LOFIC pixel is difficult.

[0005] Non-patent document 1 (Sakai et al., "ITE Technical Report," Vol. 34, No. 16, pp. 59-62) proposes a source follower shared pixel as an improved version of the LOFIC pixel. This proposal makes it possible to miniaturize the pixel because components such as source follower transistors and capacitors can be shared between two pixels.

[0006] However, in addition to the components of a conventional pixel, a source-follower shared LOFIC pixel requires a LOFIC overflow transistor and a LOFIC select transistor. In other words, while some components can be shared, additional components are required. Therefore, the desired pixel miniaturization cannot be achieved through this improvement alone. Summary of the Invention

[0007] An image sensor element according to aspects of the present disclosure includes a transfer transistor, a LOFIC selection transistor, a photodiode, and a first overflow path. The transfer transistor outputs a readout signal from a first end. The LOFIC selection transistor includes a first end connected to the second end of the transfer transistor, and a second end connected to a capacitor. The photodiode is commonly connected to the third end of the transfer transistor and the third end of the LOFIC selection transistor. The first overflow path is formed between the photodiode and the second end of the LOFIC selection transistor. Each of the transfer transistor and the LOFIC selection transistor is configured with a vertical gate transistor. Each vertical gate transistor includes a gate and a first end to a third end. The gate extends vertically. The first end and the second end are arranged around the gate along a horizontal periphery. The third end is arranged below the gate. The connection between the first end, the second end, and the third end is connected and disconnected by controlling the voltage supplied to the gate.

[0008] The transfer transistor and the LOFIC select transistor may be disposed in close proximity to each other in a well, and the photodiode may be disposed below the well.

[0009] The first terminal of the transfer transistor may be connected to a floating diffusion that is electrically floating, and the floating diffusion may be connected to the gate of the output transistor.

[0010] The second overflow path may be disposed between the second terminal of the LOFIC select transistor and the first terminal of the transfer transistor.

[0011] An image sensor may include a plurality of image sensor elements described above.

[0012] Utilizing the present disclosure, LOFIC pixels can be miniaturized. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Embodiments of the present disclosure will be described based on the following drawings, in which:

[0014] Figure 1A is a cross-sectional view showing the structure of a vertical gate (VG) transistor.

[0015] Figure 1B A circuit diagram of a vertical gate (VG) transistor.

[0016] Figure 1C is a diagram showing symbols for a vertical gate (VG) transistor.

[0017] Figure 2 is a circuit diagram of an image sensor element according to an embodiment of the present disclosure.

[0018] Figure 3A FIG. 1 is a plan view showing a schematic configuration of an image sensor element according to an embodiment of the present disclosure.

[0019] Figure 3B To follow Figure 3A A cross section taken along line AA′ in FIG. 1 shows a schematic structure of an image sensor element according to an embodiment of the present disclosure.

[0020] Figure 4 is a timing diagram illustrating the behavior of an image sensor element according to an embodiment of the present disclosure.

[0021] Figure 5A : is a diagram showing a charge accumulation state (potential) at the BB' cross section of a pixel.

[0022] Figure 5B Graph showing the charge accumulation state (potential) at the B'-B" cross section of a pixel.

[0023] Figure 6A To show that Figure 5A and Figure 5B Graph of the potential at the cross section shown in (potential graph with no signal during the exposure period).

[0024] Figure 6B To show that Figure 5A and Figure 5B Graph of the potential at the cross section shown in (potential graph during PD readout).

[0025] Figure 6C To show that Figure 5A and Figure 5B Graph of the potential at the cross section shown in (potential graph during LOFIC readout).

[0026] Figure 7 is a diagram of an example of a configuration having a transfer transistor TX and a LOFIC selection transistor LF, each of which includes a plurality of VG transistors (two in the example).

[0027] Figure 8 is a diagram of an example having a plurality of VG transistors, each of which has an elliptical cross-section.

[0028] Figure 9 A circuit diagram of an example of a configuration including a conversion efficiency switching mechanism.

[0029] Figure 10 is a block diagram illustrating a structure of an image sensor according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] The following describes embodiments of the present disclosure with reference to the accompanying drawings, but the present disclosure is not limited to these embodiments.

[0031] vertical gate transistor

[0032] The image sensor element according to the embodiment of the present disclosure uses the following Figures 1A to 1C A vertical gate (VG) transistor is described.

[0033] Figure 1A 1 is a cross-sectional view showing an example of the structure of each VG transistor. A p-well 12 doped with p-type impurities is disposed on the front side of the semiconductor substrate 10, and an n-well 14 doped with n-type impurities is disposed on the bottom side.

[0034] A trench 16, which is a hole extending from the front side toward the bottom side, is formed in the semiconductor substrate 10. The trench 16 extends through the p-well 12, and the bottom end of the trench 16 reaches the upper portion of the n-well 14. A gate insulating film 18 covers the inner circumferential surface of the trench 16. A gate 20 made of a conductive material is disposed inside the trench 16. Two conductive regions 22 and 24 doped with n-type impurities are disposed in the p-well 12 around the trench 16. The conductive region 22 is a first terminal P1 (drain); the conductive region 24 is a second terminal P2 (drain); the n-well 14 is a third terminal P3 (source); and one end of the gate 20 is externally connected as a terminal G.

[0035] The semiconductor substrate 10 may be a silicon (Si) substrate, and the gate insulating film 18 may be made of silicon oxide. The gate 20 may be made of a well-known material such as polysilicon. The impurity may also be a well-known material.

[0036] In such a VG transistor, when a positive voltage is applied to the gate 20 , a channel is formed in the p-well around the gate 20 in vertical and horizontal directions, thereby generating a conductive path between the first terminal, the second terminal, and the third terminal.

[0037] Figure 1B To correspond to Figure 1A Circuit diagram. Figure 1B As shown in FIG, the gates of the three transistors Q1 to Q3 are connected to the terminal G. The terminals (sources or drains) of the transistors Q1 to Q3 are connected in sequence so that the connections between Q1 and Q3, Q3 and Q2, and Q2 and Q1 become the first terminal P1 to the third terminal P3, respectively.

[0038] Therefore, the three transistors Q1 to Q3 are simultaneously turned on or off according to the input voltage to the gate G. Therefore, the connections between the first terminal P1 and the second terminal P2, between the second terminal P2 and the third terminal P3, and between the third terminal P3 and the first terminal P1 are simultaneously turned on and off.

[0039] Figure 1C The symbols of the VG transistors used in the above configuration according to the present embodiment are shown. The symbols will be mentioned below when describing the circuits.

[0040] Pixel Configuration Overview

[0041] <Circuit Configuration>

[0042] Figure 2 2 is a circuit diagram of an image sensor element according to this embodiment, showing circuits for two pixels PX0 and PX1.

[0043] Although the configuration of pixel PX0 is described below, pixel PX1 has the same configuration. Note that the suffix "0" indicates a component in pixel PX0, while the suffix "1" indicates a component in pixel PX1. No suffix indicates a common component for both pixels.

[0044] The first terminal of transfer transistor TX0 is connected to an electrically isolated floating diffusion FD. The second terminal of transfer transistor TX0 is connected to the first terminal of LOFIC select transistor LF0. The second terminal of LOFIC select transistor LF0 is connected to one of the two terminals of capacitor Cs0. This terminal serves as the LOFIC node. The other terminal of capacitor Cs0 is connected to a power supply.

[0045] The third terminals of the LOFIC selection transistor LF0 and the transfer transistor TX0 are commonly connected to the cathode of the photodiode PD0. The anode of the photodiode PD0 is connected to GND or a pixel reference power supply equivalent to the GND of the pixel.

[0046] Figure 2 The first overflow path OFPO shown in dotted line form in FIG. 5 is provided between the photodiode PD0 and the second end of the LOFIC selection transistor LF0 .

[0047] The floating diffusion FD connected to the first terminal of the transfer transistor TX0 is connected to the gate of the source follower transistor SF (output transistor) for signal readout and amplification. The source of the source follower transistor SF is connected to a rated current source (not shown) via the select transistor SEL. The source of the source follower transistor SF serves as a signal output terminal. Therefore, a source voltage that depends on the gate input voltage of the source follower transistor SF (the floating diffusion FD voltage) is output as a readout signal.

[0048] The floating diffusion FD is connected to a reset power supply via a reset transistor RST. When the reset transistor RST is turned on, the floating diffusion FD is reset to a reset voltage.

[0049] <Component Structure>

[0050] Figure 3A and Figure 3B A schematic structure of an image sensor element according to an embodiment of the present disclosure is shown. Figure 3A is a plan view, and Figure 3B To follow Figure 3AA vertical cross section taken along line AA' in FIG.

[0051] like Figure 3B As shown in FIG1 , the VG transistor described above is used for the transfer transistor TX and the LOFIC select transistor LF. The third terminals of the transfer transistor TX and the LOFIC select transistor LF are not disposed in the n-well 14 as in FIG1 , but are disposed in the n-region of the photodiode PD so that the third terminals are connected to the cathode of the photodiode PD. Therefore, the third terminals (sources) of the transfer transistor TX and the LOFIC select transistor LF are commonly connected to the cathode of the photodiode PD.

[0052] A first overflow path OFPO connecting the n-region of the photodiode PD and the capacitor Cs (connecting the LOFIC node of the LOFIC select transistor LF and the capacitor Cs) is vertically formed in the p-well 12. In other words, the first overflow path OFPO extends vertically along the gate of the LOFIC select transistor LF. The first overflow path OFPO contains a sufficient concentration of impurities, and overflowing signal charge passes through this path after being saturated with the signal charge generated by the photodiode PD. The signal charge from the first overflow path OFPO is stored in the capacitor Cs.

[0053] The capacitor connected to the LOFIC node can be of any type, such as metal-insulator-metal (MIM) or metal-oxide-silicon (MOS) type.

[0054] N-type impurities are doped into the Si surface channel between the LOFIC select transistor LF0 and the transfer transistor TX0, connecting the LOFIC node and the floating diffusion FD. The section between the first terminal P1 of the LOFIC select transistor LF0 and the second terminal P2 of the transfer transistor TX0 acts as a so-called deep depletion transistor. This n-type channel between P1 and P2 is not fully closed even when the LOFIC select transistor LF0 and the transfer transistor TX0 are disconnected, and serves as a second overflow path. When the signal charge stored in capacitor Cs exceeds a certain level and overflows from the LOFIC node, the overflowed signal charge is discharged to the floating diffusion FD via the second overflow path (n-type channel) and cleared by the floating diffusion FD set to a reset voltage.

[0055] like Figure 3A and Figure 3B As shown in FIG, the transfer transistor TX and the LOFIC selection transistor LF are arranged adjacent to each other in the horizontal direction in the pixel PX0 and the pixel PX1. Figure 1AIn the pixel structure according to this embodiment, an N+ diffusion layer is positioned at the first and second terminals of the VG transistor. Because the distance between the transfer transistor TX and the LOFIC select transistor LF is sufficiently short, an n-type diffusion layer is still necessary in this region, but it does not need to be of high concentration. By placing the two VG transistors adjacent to each other in the p-well, a conductive path spanning these two VG transistors is eliminated. When the transfer transistor TX and the LOFIC select transistor LF are turned on, a channel is created across the two transistors, establishing a conductive path between the LOFIC node and the floating diffusion FD.

[0056] like Figure 3A As shown in , the reset transistor RST is arranged between the pixel PX0 and the pixel PX1 and is commonly used by these pixels. The first ends of the transfer transistor TX0 and the transfer transistor TX1 are connected to the reset transistor RST via the floating diffusion FD. The floating diffusion FD is connected to the gate of the source follower transistor SF.

[0057] <Behavior>

[0058] References below Figure 4 The timing diagrams shown in describe the behavior of circuit components.

[0059] Figure 4 The timing diagram in FIG starts with the exposure process.

[0060] -exposure

[0061] During the exposure process, select transistor SEL is turned off, reset transistor RST is turned on, and transfer transistor TX and LOFIC select transistor LF are turned off. In this state, photodiode PD stores charge corresponding to the received light. When charge overflows from photodiode PD, it is stored in capacitor Cs via a first overflow path OFP.

[0062] -PD readout

[0063] The selection transistor SEL is turned on and the reset transistor RST is turned off in preparation for readout. In other words, by turning on the reset transistor RST (FD reset), the floating diffusion FD is set to the reset voltage (voltage at the reset power supply).

[0064] Turning on the transfer transistor TX allows charge from the photodiode PD to flow to the floating diffusion FD, which is then set to a voltage corresponding to the charge stored in the photodiode PD. Under these conditions, the transfer transistor TX is turned off. Because the select transistor SEL is turned on, the voltage output based on the current of the source follower transistor SF is a voltage (readout signal) corresponding to the amount of light received by the photodiode PD (PD readout).

[0065] It should be noted that by turning on the reset transistor RST (FD reset) before turning on the transfer transistor TX, the floating diffusion FD is set at the reset voltage (the voltage at the reset power supply). When the transfer transistor is subsequently turned on to allow the introduction of charge from the photodiode PD, the floating diffusion FD is set at a differential voltage from the reset voltage at the FD reset. Regarding PD readout, this can be achieved by using Figure 4 The signals at the PD readout and FD reset in the timing diagram of FIG. 1 are subjected to so-called “correlated double sampling (CDS)”.

[0066] -LOFIC readout

[0067] Next, both the transfer transistor TX and the LOFIC select transistor LF are turned on. Since this connects the floating diffusion FD and the LOFIC node, the charge stored in the capacitor Cs is added to the charge of the floating diffusion FD set at the PD readout.

[0068] At this time, the gate of the source follower transistor SF is set to the voltage of the floating diffusion FD, and this voltage is read out (LOFIC readout).

[0069] -LOFIC reset

[0070] After LOFIC readout, with the transfer transistor TX and the LOFIC select transistor LF turned on, the reset transistor RST is turned on, resetting the floating diffusion FD, the photodiode PD, and the LOFIC node (capacitor Cs).

[0071] After this reset, the LOFIC select transistor LF, the transfer transistor TX, and the reset transistor RST are turned off in this order (from the transistor farthest from the source follower transistor SF).

[0072] In this state, the transistor settings are the same as those at the start of the readout sequence described above (at FD reset). When the transfer transistor TX and the LOFIC select transistor LF are subsequently turned on, the transistors are in the same state as those at the LOFIC readout without inputting the charge signal from the photodiode PD. The signal in the reset state can be read out by turning on the source follower transistor SF in this state and reading out the signal at this time (reset state readout).

[0073] The amount of signal generated by the photoelectric conversion can be measured by calculating the difference between the readout signal in the reset state and the readout signal described above (LOFIC readout).

[0074] By turning on the reset transistor RST again after reading out the signal in the above-described manner, resetting the floating diffusion FD and the LOFIC node again, and turning off the transfer transistor TX and the LOFIC selection transistor LF, it becomes possible to start exposure.

[0075] <Overflow Path>

[0076] Figure 5A : is a cross-sectional view showing the charge storage state (potential) at a cross section taken along the dotted line BB' in the left figure in the right figure. Figure 5A As shown, the photodiode PD stores charge in a space enclosed by the transfer transistor TX and the walls of the first overflow path OFP. When the charge exceeds a certain amount, the charge flows into the LOFIC node via the first overflow path OFP and is stored in the capacitor Cs.

[0077] Figure 5B The charge storage state (potential) in the LOFIC node at the cross section taken along line B'-B" in the left figure is shown in the right figure. As described above, an n-type channel region is formed in the Si surface of the transfer transistor TX and the LOFIC selection transistor LF, resulting in a so-called deep depletion transistor. Even when the transfer transistor TX and the LOFIC selection transistor LF are disconnected, the channel is not completely closed but acts as an overflow path. The impurity concentration is adjusted so that the potential at each transistor becomes as shown in the cross-sectional potential diagram. When the potential for the transfer transistor TX and the LOFIC selection transistor LF is inclined from the LOFIC node toward the floating diffusion FD, when the LOFIC node is saturated, the charge is discharged to the floating diffusion FD. This prevents blurring, in which charge overflows into the adjacent pixel above the p-well even when the photodiode PD and the LOFIC node are saturated.

[0078] One of the issues addressed by the pixel structure of the present disclosure is the generation of a dark signal between the transfer transistor TX and the LOFIC select transistor LF. Because the potential dip in the channel discharges this generated dark signal to the floating diffusion FD, this dark signal is prevented from causing problems when reading out signals from the photodiode PD and the LOFIC signal. It should be noted that the distance between the transfer transistor TX and the LOFIC select transistor LF can be shortened to prevent a potential dip that would otherwise occur.

[0079] Figures 6A to 6C Show Figure 5A and Figure 5B Potential diagram at the cross section shown in . Figure 6A The potential diagram shows no signal during the exposure period. Figures 5A to 5BAs previously mentioned, when the photodiode PD is saturated, the signal charge overflows through the overflow path OFP into the LOFIC node. Furthermore, even when the LOFIC node is saturated and the signal charge overflows, the overflowing signal charge is discharged into the reset power supply via the n-type channel region (second overflow path), thereby preventing the overflowing signal charge from flowing into adjacent pixels and causing blurring. Figure 6B The potential diagram during PD readout is shown. The transfer transistor TX is turned on, so the signal charge in the photodiode PD is transferred to the FD. At this time, the LOFIC selection transistor LF is turned on, so the LOFIC signal charge is held in the LOFIC node. Figure 6C The potential diagram during LOFIC readout is shown. The transfer transistor TX and the LOFIC select transistor LF are turned on, so the FD and LOFIC nodes are connected to each other through those transistors.

[0080] <Characteristics of this embodiment>

[0081] As described above, in this embodiment, the transfer transistor TX and the LOFIC select transistor LF are VG transistors positioned adjacent to each other. When both the transfer transistor TX and the LOFIC select transistor LF are turned on, the floating diffusion FD is connected to the LOFIC node of the LOFIC select transistor, to which the capacitor Cs is already connected. This eliminates the need for a transistor that would otherwise be required to control the connection between the LOFIC node and the floating diffusion FD. This eliminates the need for one transistor from the circuit of non-patent document 1 (Sakai et al., "ITE Technical Report," Vol. 34, No. 16, pp. 59-62). As the number of transistors connected to the floating diffusion FD decreases, the conversion gain can be increased. By placing the VG transistors adjacent to each other, a highly efficient arrangement can be achieved, thereby reducing the size of the pixel while maintaining the LOFIC architecture.

[0082] Other embodiments

[0083] Although each of the transfer transistor TX and the LOFIC selection transistor LF includes a single VG transistor in the above embodiment, each of the transfer transistor TX and the LOFIC selection transistor LF may include a plurality of VG transistors.

[0084] Figure 7 FIG. 1 is a plan view of a configuration in which each of the transfer transistor TX and the LOFIC selection transistor LF includes two VG transistors. Figure 8 As shown in , the VG transistor may have a cross-section with vertical and horizontal axes of different lengths, such as an elliptical shape.

[0085] The advantage of providing multiple VG transistors is that the potential modulation between the VG transistors can be increased. Figure 8The VG transistor shown has an oval cross section comparable to that having Figure 7 While the circular cross-section VG transistor shown in FIG has a larger surface area facing the opposing VG transistor, the potential modulation degree of the elliptical VG transistor is likely to be higher. A higher potential modulation degree means higher on / off performance of the transistor, thereby achieving the advantage of easier signal readout (PD signal) from the photodiode PD.

[0086] Figure 9 A configuration of switchable signal charge conversion efficiency is shown. The gain control switching transistor CG is disposed between the reset transistor RST and the floating diffusion FD (the gate of the source follower transistor SF). One end of the capacitor Cc is connected between the gain control switching transistor CG and the reset transistor RST, and the other end of the capacitor Cc is connected to the power supply. The capacity of the floating diffusion FD can be switched by turning the gain control switching transistor CG on and off. When the gain control switching transistor CG is turned off, a higher conversion efficiency with a lower capacity can be obtained, and when it is turned on, a higher capacity with a lower conversion efficiency can be obtained. In general, it is well known that although LOFIC is suitable for obtaining high-brightness signals, LOFIC causes greater noise for low-brightness signals. When the output range of the PD signal from the photodiode PD is too narrow, the signal-to-noise ratio in the area where the known PD signal is converted into the LOFIC signal is reduced. Switching of the conversion efficiency of the known PD signal is advantageous in ensuring a sufficient PD output range while reducing low-brightness noise, and in combination with LOFIC effectively maintains image quality within the signal conversion range.

[0087] This conversion efficiency switching configuration is applicable to the pixel configuration of the present disclosure.The present application implements ultra-compact pixels according to the configuration of the present disclosure to obtain wide dynamic range images while maintaining image quality.

[0088] [Image sensor]

[0089] Figure 10 FIG1 is a block diagram illustrating the structure of an image sensor according to an embodiment of the present disclosure. The image sensor 100 of this example configuration includes a pixel array 110 , a readout circuit 114 , and function logic 116 .

[0090] The pixel array 110 is a two-dimensional array in which pixels P are arranged in rows and columns. Each pixel P may have a color filter on the light incident side, and light of a specific color having passed through the color filter is incident on the pixel P.

[0091] The control circuit 112 controls the operation of the pixel array 110. For example, the control circuit 112 controls an exposure period of each pixel P, an output of an image signal of each pixel P, or the like.

[0092] The readout circuit 114 individually reads out the image signal of each pixel P, an analog-to-digital converter (ADC) converts the read signal to obtain digital data, and supplies the digital data to the function logic 116 .

[0093] Function logic 116 applies a process to the data from each pixel P to obtain image data and outputs the data. The image data is supplied to an electronic device, such as a display, a storage device, or something else. Function logic 116 may be partially located outside the sensor chip, for example, where the function logic includes processing using an application processing unit (APU).

[0094] Application Examples

[0095] The image sensor element according to embodiments of the present disclosure can be applied to various types of image sensors, specifically, not only single-exposure HDR systems, but also multiple-exposure systems including multiple pixels with different exposure times. The image sensor element can also be used not only in single-size pixel HDR sensors, but also in multi-size pixel sensors in which pixels of different sizes are combined to achieve a higher dynamic range. The image sensor element can further be used in combination with voltage-domain global shutter sensors, including chip-stacked sensors.

[0096] In this specification, it is assumed that the signal charge is electrons. However, the signal charge may be holes. Even in this case, the above description can still be applied by exchanging semiconductor type N and semiconductor type P and the source and drain.

Claims

1. An image sensor element, comprising: a transfer transistor, outputting a readout signal from a first terminal; a LOFIC select transistor including a first terminal connected to the second terminal of the transfer transistor and a second terminal connected to a capacitor; a photodiode commonly connected to the third terminal of the transfer transistor and the third terminal of the LOFIC select transistor; as well as a first overflow path formed between the photodiode and the capacitor, wherein each of the transfer transistor and the LOFIC select transistor is configured with a vertical gate transistor, the vertical gate transistor comprising: a grid, extending vertically; a first end and a second end disposed along a horizontal perimeter around the gate; and The third terminal is placed below the gate. The connection between the first end, the second end, and the third end is connected and disconnected by controlling the voltage supplied to the gate. When a positive voltage is applied to the gate, a channel is formed around the gate in the vertical and horizontal directions between the first end, the second end, and the third end, thereby generating a conductive path between the first end, the second end, and the third end.

2. The image sensor element according to claim 1, wherein The transfer transistor and the LOFIC select transistor are disposed in close proximity to each other in a well, and The photodiode is disposed below the well.

3. The image sensor element according to claim 2, wherein The first terminal of the transfer transistor is connected to an electrically floating floating diffusion, and the floating diffusion is connected to a gate of an output transistor.

4. The image sensor element according to claim 3, wherein During an exposure period in which the photodiode generates charge due to exposure, potential gradients exist in the channel regions of the LOFIC selection transistor and the transfer transistor to transfer charge from the second end of the LOFIC selection transistor toward the first end of the transfer transistor.

5. The image sensor element according to claim 4, wherein A path disposed between the second end of the LOFIC select transistor and the first end of the transfer transistor serves as a second overflow path.

6. An image sensor comprising a plurality of image sensor elements arranged in a row direction and a column direction, Each of the image sensor elements comprises: a transfer transistor, outputting a readout signal from a first terminal; a LOFIC select transistor including a first terminal connected to the second terminal of the transfer transistor and a second terminal connected to a capacitor; a photodiode commonly connected to the third terminal of the transfer transistor and the third terminal of the LOFIC select transistor; as well as a first overflow path formed between the photodiode and the capacitor, wherein each of the transfer transistor and the LOFIC select transistor is configured with a vertical gate transistor, the vertical gate transistor comprising: a grid, extending vertically; a first end and a second end disposed along a horizontal perimeter around the gate; and The third terminal is placed below the gate. The connection between the first end, the second end, and the third end is connected and disconnected by controlling the voltage supplied to the gate. When a positive voltage is applied to the gate, a channel is formed around the gate in the vertical and horizontal directions between the first end, the second end, and the third end, thereby generating a conductive path between the first end, the second end, and the third end.

7. The image sensor according to claim 6, wherein The transfer transistor and the LOFIC select transistor are disposed in close proximity to each other in a well, and The photodiode is disposed below the well.

8. The image sensor according to claim 7, wherein The first terminal of the transfer transistor is connected to an electrically floating floating diffusion, and the floating diffusion is connected to a gate of an output transistor.

9. The image sensor according to claim 8, wherein During an exposure period in which the photodiode generates charge due to exposure, potential gradients exist in the channel regions of the LOFIC selection transistor and the transfer transistor to transfer charge from the second end of the LOFIC selection transistor toward the first end of the transfer transistor.

10. The image sensor according to claim 9, wherein A path disposed between the second end of the LOFIC select transistor and the first end of the transfer transistor serves as a second overflow path.

Images