Solar cell, photovoltaic module, and method for manufacturing solar cell

Abstract

This application relates to the photovoltaic field, providing a solar cell, a photovoltaic module, and a method for fabricating a solar cell. The solar cell includes: a substrate having a front side and a back side, the back side including a textured region and a flat region adjacent to the textured region, the textured region having a doped surface field, and the doped surface field containing a doped element, which is N-type or P-type; a tunneling dielectric layer located on the flat region of the back side of the substrate; a doped conductive layer located on the surface of the tunneling dielectric layer away from the back side of the substrate, the doped conductive layer containing a doped element, the type of which is the same as the type of which is doped in the doped surface field; and a back electrode, a portion of the bottom surface of the back electrode located within the doped conductive layer and in contact with the doped surface field, which can at least reduce the contact resistance of the solar cell.

Description

Technical Field

[0001] This application relates to the photovoltaic field, and in particular to a solar cell, a photovoltaic module, and a method for preparing a solar cell. Background Technology

[0002] Factors affecting the performance of solar cells (such as photoelectric conversion efficiency) include optical losses and electrical losses. Optical losses include reflection losses from the front surface of the cell, shading losses from the contact grid lines, and non-absorption losses in the long wavelength range. Electrical losses include photogenerated carrier recombination on the semiconductor surface and within the cell, contact resistance between the semiconductor and metal grid lines, and contact resistance between the metal and semiconductor.

[0003] To reduce electrical and optical losses in solar cells, a polishing process is generally required on the back side of the cell. Back-side polishing primarily utilizes wet chemical methods to polish the boron-doped pyramidal textured surface structure on the back side, increasing internal light reflection, reducing the carrier surface recombination rate, and improving the cell's photoelectric conversion efficiency. In the back-side polishing process, the morphology of the polished back surface of crystalline silicon cells is beneficial for back reflection of long-wavelength light and the uniformity of subsequent film formation on the back side, playing a crucial role in improving solar cell efficiency. While back-side polishing can optimize solar cell performance, many factors still influence the performance of this type of solar cell, making the development of high-efficiency passivated contact solar cells of significant importance. Summary of the Invention

[0004] This application provides a solar cell that at least helps to reduce the contact resistance of the solar cell.

[0005] According to some embodiments of this application, one aspect of this application provides a solar cell, comprising: a substrate having a front side and a back side, the back side including a textured region and a flat region adjacent to the textured region, the textured region having a doped surface field, and the doped surface field having a doped element, the doped element being N-type or P-type; a tunneling dielectric layer located in the flat region on the back side of the substrate; a doped conductive layer located on the surface of the tunneling dielectric layer away from the back side of the substrate, the doped conductive layer having a doped element, the type of the doped element in the doped conductive layer being the same as the type of the doped element in the doped surface field; and a back electrode, a portion of the bottom surface of the back electrode being located within the doped conductive layer and the portion of the bottom surface of the back electrode being in contact with the doped surface field.

[0006] In addition, for the same back electrode, the ratio of the contact area between the doped surface field and the back electrode to the contact area between the doped conductive layer and the back electrode ranges from 1:2 to 2:1.

[0007] In addition, along the back electrode arrangement direction, the ratio of the cross-sectional width of the doped surface field and the back electrode contact surface to the width of the back electrode ranges from 1:4 to 1:2.

[0008] In addition, the cross-sectional width of the contact surface between the doped surface field and the back electrode ranges from 5 μm to 20 μm.

[0009] In addition, along the back electrode arrangement direction, the ratio of the base width of the textured area to the base width of the flat area ranges from 1:3 to 1:1.

[0010] In addition, the width of the substrate in the velvety area is 10μm to 30μm.

[0011] In addition, along the direction of the back electrode arrangement, the base width of the textured area is smaller than the width of the back electrode.

[0012] In addition, the back side includes multiple textured areas arranged along the extension direction of the back electrode; the spacing between adjacent textured areas ranges from 10mm to 20mm.

[0013] In addition, on the same back electrode, the back side includes multiple textured areas arranged along the back electrode arrangement direction; the spacing between adjacent textured areas ranges from 5μm to 20μm.

[0014] In addition, along the direction from the back to the front, the doped surface field includes a first doped region and a second doped region, with the doping concentration of the first doped region being greater than that of the second doped region; the back electrode is in surface contact with the first doped region.

[0015] In addition, the doping concentration of the first doped region includes 2E20cm. -3 ~2E21 cm -3 .

[0016] In addition, the depth of the first doped region is 1.5% to 4% of the height of the conductive textured structure.

[0017] In addition, the doped surface field includes at least one protrusion structure; the height difference between the top of the protrusion structure and the back surface of the substrate is 2 μm to 10 μm.

[0018] In addition, there are two protrusions; the spacing between adjacent protrusions ranges from 2μm to 4μm.

[0019] In addition, the raised structures include pyramid-shaped structures.

[0020] According to some embodiments of this application, another aspect of this application provides a photovoltaic module, including: at least one battery string, the battery string being formed by connecting a plurality of solar cells according to any one of the above; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film facing away from the battery string.

[0021] According to some embodiments of this application, another aspect of this application provides a method for fabricating a solar cell, comprising: providing a substrate having a front side and a back side, the back side including a textured region and a flat region adjacent to the textured region; forming a doped surface field located on the substrate in the textured region, the doped surface field containing doped elements, the doped elements being N-type or P-type; forming a tunneling dielectric layer located in the flat region on the back side of the substrate; forming a doped conductive layer located on the surface of the tunneling dielectric layer away from the back side of the substrate, the doped conductive layer containing doped elements, the type of doped elements in the doped conductive layer being the same as the type of doped elements in the doped surface field; and forming a back electrode, a portion of the bottom surface of the back electrode being located within the doped conductive layer and the portion of the bottom surface of the back electrode being in contact with the doped surface field.

[0022] In addition, the process steps for forming a doped surface field include: providing an initial substrate having a front side and a back side, the back side including a textured region and a flat region adjacent to the textured region; texturing the back side of the initial substrate to form an initial textured structure; forming a tunneling dielectric film and a conductive film on the flat region on the back side of the initial substrate and on the surface of the initial textured structure; removing the tunneling dielectric film and the conductive film located on the surface of the initial textured structure; doping the initial textured structure and the conductive film to form a doped surface field, with the remaining tunneling dielectric film serving as a tunneling dielectric layer and the remaining conductive film serving as a doped conductive layer.

[0023] In addition, the texturing process is a laser process; the parameters of the laser process include: laser wavelength of 355nm to 460nm, laser pulse width of 20ps to 80ps, and laser power of 30W to 100W.

[0024] The technical solution provided in this application has at least the following advantages:

[0025] The back side of the substrate includes a textured region and a flat region adjacent to the textured region. The substrate surface of the textured region has a doped surface field containing doped elements. Part of the bottom surface of the back electrode is in contact with the doped surface field, meaning the back electrode is in direct contact with the doped surface field. The doped conductive layer forms a good ohmic contact with the back electrode, which helps reduce the contact resistivity of the back side of the solar cell and improves the overall cell efficiency. The doped elements in the doped surface field can act as charge carriers, increasing the carrier mobility and further reducing the contact resistivity of the back side of the solar cell. The substrate in the flat region has a non-textured structure. A conventional tunneling dielectric layer and a doped conductive layer are formed in the flat region of the substrate. The back electrode is in direct contact with the doped conductive layer, resulting in good passivation. This also reduces the carrier recombination rate on the back side and improves light utilization, thereby enhancing the photoelectric conversion efficiency of the solar cell. Attached Figure Description

[0026] One or more embodiments are illustrated by way of example with corresponding figures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the accompanying drawings are not tolerable. To more clearly illustrate the technical solutions in the embodiments of this application or in conventional technology, the figures used in the embodiments will be briefly described below. Obviously, the figures described below are only some embodiments of this application. For those skilled in the art, other figures can be obtained based on these figures without creative effort.

[0027] Figure 1 This is a schematic diagram of a solar cell structure provided in an embodiment of this application;

[0028] Figure 2 This is a schematic diagram of a photovoltaic module provided in one embodiment of this application;

[0029] Figure 3 This is a schematic diagram of a substrate provided in a method for fabricating a solar cell according to an embodiment of this application;

[0030] Figure 4 This is a schematic diagram of a structure for forming an emitter in a solar cell fabrication method provided in an embodiment of this application;

[0031] Figure 5 This is a schematic diagram of the back side of a solar cell substrate provided in an embodiment of this application;

[0032] Figure 6 A schematic diagram of another structure on the back side of a solar cell substrate provided in an embodiment of this application;

[0033] Figure 7 This is a schematic diagram of another structure on the back side of a solar cell substrate provided in an embodiment of this application;

[0034] Figure 8 This is a schematic diagram of another structure on the back side of a solar cell substrate provided in an embodiment of this application;

[0035] Figure 9 This is a schematic diagram of a structure for forming an initial textured surface structure in a solar cell fabrication method provided in an embodiment of this application;

[0036] Figure 10 This is a schematic diagram of a structure for forming a conductive film in a solar cell fabrication method provided in an embodiment of this application;

[0037] Figure 11 This is a schematic diagram of a structure for etching a conductive film in a solar cell fabrication method provided in an embodiment of this application.

[0038] Figure 12 This is a schematic diagram of a structure for forming a doped surface field in a solar cell fabrication method provided in an embodiment of this application;

[0039] Figure 13 This is a schematic diagram of a structure for forming a passivation layer in a solar cell fabrication method provided in an embodiment of this application;

[0040] Figure 14 This is a schematic diagram of a structure for forming a back electrode in a solar cell fabrication method provided in an embodiment of this application. Detailed Implementation

[0041] As can be seen from the background technology, existing technologies suffer from the problem of high contact resistance in solar cells.

[0042] Analysis revealed that one reason for the high contact resistance of solar cells is that current processes typically polish the textured surface of the back side of the solar cell after texturing. This improves the back reflection of long-wavelength light and the uniformity of the subsequent backsheet, which helps reduce carrier recombination on the back side and improve light utilization. However, after backside polishing, the subsequently formed doped conductive layer is difficult to match with the back metal electrode, failing to form a good ohmic contact. This results in a high contact resistivity of the doped conductive layer and a high contact resistance between the back electrode and the doped conductive layer, thus affecting the efficiency of the solar cell.

[0043] This application provides a solar cell. The back surface of the solar cell substrate includes a textured region and a flat region adjacent to the textured region. The substrate surface of the textured region has a doped surface field containing doped elements. Part of the bottom surface of the back electrode is in contact with the doped surface field, i.e., the back electrode is in direct contact with the doped surface field. The doped surface field and the back electrode form a good ohmic contact, which helps to reduce the contact resistivity of the back surface of the solar cell and improve the overall cell efficiency. The doped surface field contains doped elements, which can act as charge carriers, increasing the carrier mobility and further reducing the contact resistivity of the back surface of the solar cell. The substrate of the flat region is a non-textured structure. A conventional tunneling dielectric layer and a doped conductive layer are formed in the flat region of the substrate. The back electrode is in direct contact with the doped conductive layer, resulting in good passivation effect. At the same time, it reduces the carrier recombination rate on the back surface and improves the light utilization rate, thereby improving the photoelectric conversion efficiency of the solar cell.

[0044] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0045] Figure 1 This is a schematic diagram of a solar cell provided in an embodiment of this application.

[0046] refer to Figure 1 This application provides a solar cell comprising: a substrate 100 having a front side 101 and a back side 102, the back side 102 including a textured region A and a flat region B (or approximately flat region) adjacent to the textured region A; a doped surface field 120 within the textured region A of the substrate 100, the doped surface field 120 containing a doped element, the doped element being N-type or P-type; a tunneling dielectric layer 131 located in the flat region B of the back side 102 of the substrate 100; a doped conductive layer 132 located on the surface of the tunneling dielectric layer 131 away from the back side 102 of the substrate 100, the doped conductive layer 132 containing a doped element, the type of the doped element in the doped conductive layer 132 being the same as the type of the doped element in the doped surface field 120; and a back electrode 141, a portion of the bottom surface of the back electrode 141 located within the doped conductive layer 132 and a portion of the bottom surface of the back electrode 141 in contact with the doped surface field 120.

[0047] In some embodiments, the solar cell is a tunnel oxide passivated contact (TOPCon) cell, which may include a double-sided tunnel oxide passivated contact cell or a single-sided tunnel oxide passivated contact cell. For example, the solar cell is a single-sided tunnel oxide passivated contact cell, and the back side of the solar cell has a tunnel oxide passivation layer.

[0048] The substrate 100 is a region that absorbs incident photons to generate photogenerated carriers. In some embodiments, the substrate 100 is a silicon substrate 100, which may include one or more of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In other embodiments, the material of the substrate 100 may also be silicon carbide, organic materials, or multi-component compounds. Multi-component compounds may include, but are not limited to, materials such as perovskite, gallium arsenide, cadmium telluride, and copper indium selenide. Exemplarily, in this application, the substrate 100 is a monocrystalline silicon substrate.

[0049] In some embodiments, the front surface 101 of the substrate 100 is a light-receiving surface that absorbs incident light, and the back surface 102 of the substrate 100 is a backlight surface. The substrate 100 contains doped elements, which are either N-type or P-type. N-type elements can be group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), while P-type elements can be group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In). For example, when the substrate 100 is a P-type substrate, its internal doped element type is P-type. Similarly, when the substrate 100 is an N-type substrate, its internal doped element type is N-type.

[0050] In some embodiments, the type of dopant element in the doped surface field 120 is the same as the type of dopant element in the substrate 100. For example, when the substrate 100 is a P-type substrate, the type of dopant element in the doped surface field 120 is P-type. As another example, when the substrate 100 is an N-type substrate, the type of dopant element in the doped surface field 120 is N-type.

[0051] The textured region A can be a region on the back surface 102 of the substrate 100 that has a textured structure, and the flat region B is a region on the back surface 102 of the substrate 100 after a back-side polishing process. In some embodiments, along the arrangement direction X of the back electrode 141, the ratio of the width of the substrate 100 in the textured region A to the width of the substrate 100 in the flat region B ranges from 1:3 to 1:1. Specifically, it can be 1:2.8, 1:2.3, 1:1.9, 1:1.3, or 1:1. Preferably, the ratio of the width of the substrate 100 in the textured region A to the width of the substrate 100 in the flat region B ranges from 1:2. This ensures that the flat region B is relatively large, and the integrity of the tunneling dielectric layer 131 and the doped conductive layer 132 film on the substrate of the flat region B is good, resulting in good passivation and anti-PDI effects of the solar cell, while reducing the carrier recombination rate on the back surface and improving light utilization, thereby enhancing the photoelectric conversion efficiency of the solar cell. Furthermore, the width of the substrate 100 in the velvety region A is 10μm to 30μm. Specifically, it can be 10.3μm, 13μm, 15μm, 23μm, or 29μm.

[0052] In some embodiments, along the direction from the back side 102 to the front side 101, the textured area A and the partially flat area B are opposite to the back electrode 141.

[0053] In some embodiments, along the arrangement direction X of the back electrode 141, the width of the substrate 100 of the textured region A is smaller than the width of the back electrode 141. An excessively large width of the substrate 100 in the textured region A may affect the integrity and uniformity of the film in the flat region B, reducing internal light reflection and thus hindering the improvement of carrier surface recombination rate and the photoelectric conversion efficiency of the solar cell. Simultaneously, it affects the interface passivation effect of the passivation contact structure constructed by the tunneling dielectric layer 131 and the doped conductive layer 132, resulting in a higher Jo load current and a lower carrier surface recombination rate.

[0054] In some embodiments, the extension direction of the textured region A is the same as the extension direction of the back electrode, and the extension length of the textured region A corresponds to the extension length of the back electrode 141. Thus, the doped surface field 120 located in the textured region A can increase the lateral transport of the cell, reduce the lateral transport loss, and improve the photoelectric conversion efficiency of the solar cell. In other embodiments, the back surface 102 includes multiple textured regions A arranged along the extension direction of the back electrode 141; the spacing between adjacent textured regions A ranges from 10 mm to 20 mm, reducing the carrier recombination rate, increasing the area for collecting carriers, and resulting in a better passivation effect of the formed passivated contact structure, which is beneficial for improving the open-circuit voltage Voc and the fill factor FF. The spacing between adjacent textured regions A can specifically be 10.3 mm, 13 mm, 15.1 mm, 17 mm, or 19 mm. On the same back electrode 141, the back surface 102 includes multiple textured regions A arranged along the X-direction of the back electrode 141; the spacing between adjacent textured regions A ranges from 5 μm to 20 μm. The spacing between adjacent velvet areas A can be 5.3μm, 7μm, 13μm, 15μm or 18.3μm.

[0055] In some embodiments, the ratio of the contact area between the doped surface field 120 and the back electrode 141 to the contact area between the doped conductive layer 132 and the back electrode 141 on the same back electrode 141 ranges from 1:2 to 2:1, specifically 1.3:2, 1.6:2, 1:1.2, 2:1.8, or 2:1.3. Preferably, the ratio of the contact area between the doped surface field 120 and the back electrode 141 to the contact area between the doped conductive layer 132 and the back electrode 141 ranges from 1:1.2 to 1.2:1, specifically 1:1.15, 1:1.1, 1:1, or 1.13:1. This ratio range ensures that the back electrode 141 is in contact with the doped surface field 120, or can be considered as the back electrode 141 being in direct contact with the substrate 100, forming a good ohmic contact and reducing the contact resistance of the back electrode 141. Meanwhile, the integrity of the tunneling dielectric layer 131 and the doped conductive layer 132 on the substrate located in the flat region B is good. The back electrode 141 is in direct contact with the doped conductive layer 132, resulting in good passivation effect. This also reduces the carrier recombination rate on the back side and improves the light utilization rate, thereby enhancing the photoelectric conversion efficiency of the solar cell.

[0056] In some embodiments, along the X-direction of the back electrode 141, the ratio of the cross-sectional width of the contact surface between the doped surface field 120 and the back electrode 141 to the width of the back electrode 141 is in the range of 1:4 to 1:2. Specifically, it can be 1:3.8, 1:3.3, 1:2.9, 1:2.3, or 1:2. Preferably, the ratio of the cross-sectional width of the contact surface between the doped surface field 120 and the back electrode 141 to the width of the back electrode 141 is in the range of 1:2.5 to 1:3.2, specifically 1:2.6, 1:2.9, 1:3, or 1:3.2. Based on a back electrode 141 width of 40 μm, the cross-sectional width of the contact surface between the doped surface field 120 and the back electrode 141 can range from 5 μm to 20 μm. Specifically, it can be 6 μm, 8 μm, 12 μm, 15 μm, or 19 μm.

[0057] In some embodiments, along the direction from the back surface 102 to the front surface 101, the doped surface field 120 includes a first doped region 121 and a second doped region 122, wherein the doping concentration of the first doped region 121 is greater than the doping concentration of the second doped region 122; the back electrode 141 is in surface contact with the first doped region 121. The higher doping concentration of the first doped region 121 is beneficial for improving carrier transport efficiency, open-circuit voltage and current transmission efficiency, thereby improving the photoelectric conversion efficiency of the solar cell. The doping concentration of the first doped region 121 includes 2E20 cm⁻¹. -3 ~2E21 cm -3 .

[0058] In some embodiments, the doping concentration of the first doped region 121 is greater than or equal to the doping concentration of the doped conductive layer 132. This reduces recombination losses between the tunneling dielectric layer 131 and the doped surface field 120, and between the doped surface field 120 and the doped conductive layer 132, which improves carrier transport efficiency, open-circuit voltage, and current transmission efficiency, thereby enhancing the photoelectric conversion efficiency of the solar cell. Furthermore, since the doping concentration of the doped surface field 120 is greater than that of the doped conductive layer 132, the contact resistance of the back electrode 141 can be further reduced, thereby improving the photoelectric conversion efficiency.

[0059] In some embodiments, the depth of the first doped region 121 is 1.5% to 4% of the height of the doped surface field 120. Preferably, the depth of the first doped region 121 is 90 nm to 200 nm, specifically 90 nm, 130 nm, 160 nm, 178 nm, or 193 nm. The doping depth of the first doped region 121 can avoid the tunneling effect caused by high doping in the first doped region 121, that is, the dopant element in the first doped region 121 will not diffuse to the surface of the substrate 100 in contact with the emitter 110 or into the emitter 110, thereby improving the open-circuit voltage of the solar cell and improving the photoelectric conversion efficiency of the solar cell.

[0060] In some embodiments, the doped surface field 120 includes at least one protruding structure; the height difference between the top of the protruding structure and the back surface 102 of the substrate 100 is 2 μm to 10 μm. Utilizing the light-trapping effect of the protruding structure and the height difference between the top of the protruding structure and the back surface 102 of the substrate 100, light rays are incident on the inclined surface of the protruding structure and then reflected to the inclined surface of another protruding structure, thus forming multiple absorptions. After multiple reflections, the incident light changes its direction of travel in the solar cell, which both extends the optical path and increases the absorption of long-wavelength photons.

[0061] In other embodiments, the number of protrusions is at least two; the spacing between adjacent protrusions ranges from 2μm to 4μm. The spacing between adjacent protrusions can ensure that the incident light is reflected multiple times between adjacent protrusions, thereby extending the optical path of the incident light and thus facilitating the absorption of long-wavelength photons.

[0062] In some embodiments, the raised structure includes a pyramidal structure. The textured surface formed by the pyramidal structure has a better anti-reflective effect, that is, it reduces light reflectivity and increases the short-circuit current Isc, thereby improving the photoelectric conversion efficiency of the battery. In other embodiments, the raised structure includes a pyramidal structure or other cone-shaped structures with sloping surfaces.

[0063] In some embodiments, the material of the tunneling dielectric layer 131 may include, but is not limited to, dielectric materials with tunneling properties such as alumina, silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, and intrinsic polycrystalline silicon. The thickness of the tunneling dielectric layer 131 may be 0.5 nm to 2.5 nm, optionally 0.5 nm to 2 nm, and further 0.5 nm to 1.2 nm. The material of the doped conductive layer 132 may be at least one of polycrystalline semiconductor, amorphous semiconductor, or microcrystalline semiconductor. Preferably, the material of the doped conductive layer 132 includes at least one of polycrystalline silicon, amorphous silicon, or microcrystalline silicon. The thickness of the doped conductive layer 132 ranges from 40 nm to 150 nm, optionally 60 nm to 90 nm. This thickness range ensures low optical loss in the doped conductive layer 132 and good interface passivation of the tunneling dielectric layer 131, thereby improving battery efficiency. For example, the material of the doped conductive layer 132 in this application is polycrystalline silicon, and the thickness of the doped conductive layer 132 is 80 nm.

[0064] In some embodiments, the passivation layer 133 is located on the surface of the doped conductive layer 132, and the passivation layer 133 can be regarded as a post-passivation layer. The passivation layer 133 can be a single-layer structure or a stacked structure, and the material of the passivation layer 133 can be one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0065] The back electrode 141 is the grid line of the solar cell, used to collect and summarize the current of the solar cell. The back electrode 141 can be sintered from a burn-through paste. The material of the back electrode 141 can be one or more of aluminum, silver, gold, nickel, molybdenum, or copper. In some cases, the back electrode 141 refers to fine grid lines or finger grid lines to distinguish it from the main grid lines or busbars.

[0066] In some embodiments, the solar cell further includes: a first passivation layer 113 located on the surface of the emitter 110 away from the substrate 100, the first passivation layer 113 being regarded as a front passivation layer; and a plurality of spaced electrodes 142, the electrodes 142 penetrating the first passivation layer 113 and in contact with the emitter 110.

[0067] In some embodiments, the first passivation layer 113 may be a single-layer structure or a stacked structure, and the material of the first passivation layer 113 may be one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0068] Electrode 142 may be sintered from a burn-through slurry. The contact between electrode 142 and emitter 110 may be localized or complete. The material of electrode 142 may be one or more of aluminum, silver, nickel, gold, molybdenum, or copper. In some embodiments, electrode 142 is an upper electrode or a front electrode. In some cases, electrode 142 refers to fine grid lines or finger grid lines to distinguish it from main grid lines or busbars.

[0069] The solar cell provided in this application embodiment has a textured region on the back side of the substrate and a flat region adjacent to the textured region. The substrate surface of the textured region has a doped surface field containing doped elements. Part of the bottom surface of the back electrode is in contact with the doped surface field, meaning the back electrode is in direct contact with the doped surface field. The doped conductive layer forms a good ohmic contact with the back electrode, which helps to reduce the contact resistivity of the back side of the solar cell and improve the overall cell efficiency. The doped surface field contains doped elements, which can act as charge carriers, increasing the carrier mobility and further reducing the contact resistivity of the back side of the solar cell. The substrate in the flat region is a non-textured structure. A conventional tunneling dielectric layer and a doped conductive layer are formed in the flat region of the substrate. The back electrode is in direct contact with the doped conductive layer, resulting in good passivation. This also reduces the carrier recombination rate on the back side and improves light utilization, thereby enhancing the photoelectric conversion efficiency of the solar cell.

[0070] Figure 2 This is a schematic diagram of a photovoltaic module provided in an embodiment of this application.

[0071] Accordingly, refer to Figure 2 In another aspect, this application also provides a photovoltaic module for converting received light energy into electrical energy and transmitting it to an external load. The photovoltaic module includes: at least one battery string, the battery string consisting of multiple of the above-mentioned (e.g., Figure 1 The solar cells 10 are connected together; an encapsulating film 21 is used to cover the surface of the battery string; and a cover plate 22 is used to cover the surface of the encapsulating film 21 facing away from the battery string.

[0072] The encapsulating film 21 can be an organic encapsulating film such as EVA or POE, and it covers the surface of the battery string to seal and protect it. In some embodiments, the encapsulating film 21 includes an upper encapsulating film and a lower encapsulating film respectively covering both sides of the surface of the battery string. The cover plate 22 can be a glass cover plate or a plastic cover plate, etc., used to protect the battery string, and it covers the surface of the encapsulating film 21 facing away from the battery string. In some embodiments, the cover plate 22 is provided with a light-trapping structure to increase the utilization rate of incident light. Photovoltaic modules have high current collection capacity and low carrier recombination rate, which can achieve high photoelectric conversion efficiency. In some embodiments, the cover plate 22 includes an upper cover plate and a lower cover plate located on both sides of the battery string.

[0073] Accordingly, another aspect of this application provides a method for preparing a solar cell, used to prepare the above-described embodiments ( Figure 1 The solar cell provided. Details of contents or elements that are the same as or similar to those described in the above embodiments will not be repeated; only descriptions that differ from the above descriptions will be described in detail. Figure 3 This is a schematic diagram of a substrate provided in a method for fabricating a solar cell according to an embodiment of this application; Figure 4 This is a schematic diagram of a structure for forming an emitter in a solar cell fabrication method provided in an embodiment of this application; Figure 5 This is a schematic diagram of the back side of a solar cell substrate provided in an embodiment of this application; Figure 6 A schematic diagram of another structure on the back side of a solar cell substrate provided in an embodiment of this application; Figure 7 This is a schematic diagram of another structure on the back side of a solar cell substrate provided in an embodiment of this application; Figure 8 This is a schematic diagram of another structure on the back side of a solar cell substrate provided in an embodiment of this application; Figure 9 This is a schematic diagram of a structure for forming an initial textured surface structure in a solar cell fabrication method provided in an embodiment of this application; Figure 10 This is a schematic diagram of a structure for forming a conductive film in a solar cell fabrication method provided in an embodiment of this application; Figure 11 This is a schematic diagram of a structure for etching a conductive film in a solar cell fabrication method provided in an embodiment of this application. Figure 12 This is a schematic diagram of a structure for forming a doped surface field in a solar cell fabrication method provided in an embodiment of this application; Figure 13 This is a schematic diagram of a structure for forming a passivation layer in a solar cell fabrication method provided in an embodiment of this application; Figure 14 This is a schematic diagram of a structure for forming a back electrode in a solar cell fabrication method provided in an embodiment of this application.

[0074] refer to Figure 3 A substrate 100 is provided, having a front side 101 and a back side 102, both having a textured surface. In some embodiments, the textured surface can be prepared using a solution texturing method. This textured surface increases the number of refractions of light on the surface of the solar cell, facilitating light absorption and maximizing the utilization of solar energy. Specifically, if the substrate 100 is monocrystalline silicon, a mixed solution of alkaline and alcoholic solutions can be used to texturize its surface; if the substrate 100 is polycrystalline silicon, an acidic solution can be used. It is understood that the initial substrate can be considered as substrate 100, having a front side and a back side.

[0075] In some embodiments, the substrate 100 has doped elements, and the doped element type is N-type or P-type.

[0076] refer to Figure 4 An emitter 110 is formed on the front side 101 of the substrate 100, while the back side of the substrate 100 is polished to form a textured region A and a flat region B adjacent to the textured region A. In some embodiments, an alkaline solution or an acidic solution can be used for polishing, and the back side 102 of the substrate 100 is a polished surface, which can increase internal light reflection, reduce the surface recombination rate of charge carriers, and improve the photoelectric conversion efficiency of the battery. The back side of the initial substrate includes a textured region and a flat region adjacent to the textured region.

[0077] In some embodiments, along the back electrode arrangement direction X, the ratio of the width of the substrate 100 of the textured region A to the width of the substrate 100 of the flat region B ranges from 1:3 to 1:1. Specifically, it can be 1:2.8, 1:2.3, 1:19, 1:1.3, or 1:1. Preferably, the ratio of the width of the substrate 100 of the textured region A to the width of the substrate 100 of the flat region B ranges from 1:2. Further, the width of the substrate 100 of the textured region A is 10 μm to 30 μm.

[0078] refer to Figure 5 The extension direction of the textured region A is the same as the extension direction Y of the subsequently formed back electrode, and the extension length of the textured region A corresponds to the extension length of the back electrode. Thus, the doped surface field subsequently formed in the textured region A can increase the lateral transport of the cell, reduce the lateral transport loss, and improve the photoelectric conversion efficiency of the solar cell. In other embodiments, refer to... Figure 6 The back surface 102 includes multiple textured regions A arranged along the extension direction of the back electrode 141; the spacing between adjacent textured regions A ranges from 10 mm to 20 mm, reducing the carrier recombination rate, increasing the area for collecting carriers, and improving the passivation effect of the formed passivated contact structure, which is beneficial for improving the open-circuit voltage Voc and the fill factor FF. In some embodiments, in the same region where the back electrode is subsequently formed, the back surface 102 includes multiple textured regions A arranged along the back electrode arrangement direction X; the spacing between adjacent textured regions A ranges from 5 μm to 20 μm. In still other embodiments, in the same region where the back electrode is subsequently formed, the back surface 102 includes multiple textured regions A arranged along the back electrode arrangement direction X, and multiple textured regions A arranged along the extension direction Y of the back electrode.

[0079] refer to Figures 9 to 12A doped surface field 120 is formed, located on the substrate 100 in the textured region A. The doped surface field 120 contains doped elements, which are N-type or P-type. A tunneling dielectric layer 131 is formed, located in the flat region B of the back surface 102 of the substrate 100. A doped conductive layer 132 is formed, located on the surface of the tunneling dielectric layer 131 away from the back surface 102 of the substrate. The doped conductive layer 132 contains doped elements, and the type of doped elements in the doped conductive layer 132 is the same as the type of doped elements in the doped surface field 130.

[0080] In some embodiments, along the direction from the back surface 102 to the front surface 101, the doped surface field 120 includes a first doped region 121 and a second doped region 122, wherein the doping concentration of the first doped region 121 is greater than the doping concentration of the second doped region 122. The doping concentration of the first doped region 121 is greater than or equal to the doping concentration of the doped conductive layer 132. Specifically, the doping concentration of the first doped region 121 includes 2E20 cm⁻¹. -3 ~2E21 cm -3 .

[0081] In some embodiments, the depth of the first doped region 121 is 1.5% to 4% of the height of the doped surface field 120. Preferably, the depth of the first doped region 121 is 90 nm to 200 nm, specifically 90 nm, 130 nm, 160 nm, 178 nm or 193 nm.

[0082] Specifically, refer to Figure 9 The initial substrate back surface of the textured area A is textured to form an initial textured structure 103. In some embodiments, the textured process is a laser process; the parameters of the laser process include: laser wavelength of 355nm to 460nm, laser pulse width of 20ps to 80ps, laser power of 30W to 100W, laser spot size of 15μm to 50μm, laser frequency of 200kHz to 2MHz, and laser linear velocity of 20m / s to 40m / s. Preferably, the parameters of the laser process include: laser wavelength of 355nm to 400nm, laser pulse width of 20ps to 50ps, laser power of 50W to 80W, laser spot size which can be set according to 10% to 30% of the size of the desired laser area, laser frequency of 300kHz to 800kHz, and laser linear velocity of 20m / s to 30m / s.

[0083] In some embodiments, the initial velvet structure 103 includes at least one raised structure; the height difference between the top of the raised structure and the back surface 102 of the substrate 100 is 2 μm to 10 μm; the raised structure includes a pyramidal structure. In other embodiments, the number of raised structures is at least two; the spacing between adjacent raised structures ranges from 2 μm to 4 μm; the raised structure includes a pyramidal structure or other raised structures with slopes.

[0084] refer to Figure 10 A tunneling dielectric film 104 and a conductive film 105 are formed on the flat region B on the back side of the initial substrate and on the surface of the initial textured structure 103.

[0085] refer to Figure 11 The tunneling dielectric film 104 and the conductive film 105 located on the surface of the initial textured structure 130 are removed so that the top surface of the conductive film 105 away from the substrate 100 is slightly lower than the highest end of the initial textured structure 103. Preferably, the height difference between the top surface of the conductive film 105 away from the substrate 100 and the highest end of the initial textured structure 130 can be 1nm to 4nm, thereby exposing the top of the initial textured structure 103 and avoiding a small area of ​​the first doped region formed after subsequent doping treatment.

[0086] refer to Figure 12 For the initial velvet structure 103 (reference) Figure 11 ) and conductive film 105 (reference) Figure 11 The surface field 120 is formed by doping, and the remaining tunneling dielectric film 104 (reference) is then processed. Figure 11 As the tunneling dielectric layer 131, the remaining conductive film 105 (reference) Figure 11 ) as a doped conductive layer 132. In some embodiments, firstly on the initial textured structure 103 (reference) Figure 11 ) and conductive film 105 (reference) Figure 11 A borosilicate glass (BSG) layer is formed, followed by laser doping, and finally the remaining BSG layer is removed. In other embodiments, ion implantation is used for doping.

[0087] refer to Figure 13 A passivation layer 133 and a first passivation layer 113 are formed on the surface of the doped conductive layer 132. The passivation layer 133 can be regarded as a post-passivation layer. The first passivation layer 113 is located on the surface of the emitter 110 away from the substrate 100. The first passivation layer 113 can be regarded as a pre-passivation layer.

[0088] refer to Figure 14A back electrode 141 is formed, with a portion of the bottom surface of the back electrode 141 located within the doped conductive layer 131, and a portion of the bottom surface of the back electrode 142 contacting the doped surface field 120. The back electrode is in contact with the surface of the first doped region 121 of the doped surface field 120. In some embodiments, along the arrangement direction X of the back electrode 141, the width of the substrate 100 of the textured region A is smaller than the width of the back electrode 141.

[0089] In some embodiments, on the same back electrode 141, the ratio of the contact area between the doped surface field 120 and the back electrode 141 to the contact area between the doped conductive layer 132 and the back electrode 141 ranges from 1:2 to 2:1, specifically 1.3:2, 1.6:2, 1:1.2, 2:1.8, or 2:1.3. Preferably, the ratio of the contact area between the doped surface field 120 and the back electrode 141 to the contact area between the doped conductive layer 132 and the back electrode 141 ranges from 1:1.2 to 1.2:1, specifically 1:1.15, 1:1.1, 1:1, or 1.13:1. On the same back electrode 141, along the X-direction of the back electrode 141 arrangement, the ratio of the cross-sectional width of the contact surface between the doped surface field 120 and the back electrode 141 to the width of the back electrode 141 ranges from 1:4 to 1:2. Specifically, the ratio can be 1:3.8, 1:3.3, 1:2.9, 1:2.3, or 1:2. Preferably, the ratio of the cross-sectional width of the contact surface between the doped surface field 120 and the back electrode 141 to the width of the back electrode 141 is in the range of 1:2.5 to 1:3.2, specifically 1:2.6, 1:2.9, 1:3, or 1:3.2.

[0090] Continue to refer to Figure 14 An electrode 142 is formed, which penetrates the first passivation layer 113 and is in contact with the emitter 110.

[0091] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A solar cell, characterized in that, include: A substrate having opposing front and back sides, the back side including a velvety area and a flat area adjacent to the velvety area; The textured region on the back side has a doped surface field; the type of doped element in the doped surface field is the same as the type of doped element in the substrate; A tunneling medium layer located in a flat region on the back side of the substrate; A doped conductive layer is located on the surface of the tunneling dielectric layer away from the back side of the substrate. The doped conductive layer has doped elements, and the type of doped elements in the doped conductive layer is the same as the type of doped elements in the doped surface field. The doping concentration of the doped surface field is greater than the doping concentration of the doped conductive layer. A back electrode, wherein a portion of the bottom surface of the back electrode is located within the doped conductive layer and the portion of the bottom surface of the back electrode is in direct contact with the doped surface field, and the width of the textured region on the back side is smaller than the width of the back electrode along the direction in which the back electrode is arranged; wherein, along the direction from the back side to the front side, the textured region and a portion of the flat region are opposite to the back electrode.

2. The solar cell according to claim 1, characterized in that, In the same back electrode, the ratio of the area of ​​the doped surface field and the contact surface of the back electrode to the area of ​​the doped conductive layer and the contact surface of the back electrode ranges from 1:2 to 2:

1.

3. The solar cell according to claim 1, characterized in that, In the same back electrode, along the back electrode arrangement direction, the ratio of the cross-sectional width of the doped surface field and the contact surface of the back electrode to the width of the back electrode ranges from 1:4 to 1:

2.

4. The solar cell according to claim 3, characterized in that, The cross-sectional width of the contact surface between the doped surface field and the back electrode ranges from 5 μm to 20 μm.

5. The solar cell according to claim 1, characterized in that, The doped surface field includes at least one protrusion structure; the height difference between the top of the protrusion structure and the back surface of the substrate is 2 μm to 10 μm.

6. The solar cell according to claim 5, characterized in that, The number of protrusions is at least two, and the spacing between adjacent protrusions ranges from 2μm to 4μm.

7. The solar cell according to claim 5, characterized in that, The protruding structure includes a pyramid-shaped structure.

8. The solar cell according to claim 1, characterized in that, Along the direction from the back side to the front side, the doped surface field includes a first doped region and a second doped region, wherein the doping concentration of the first doped region is greater than the doping concentration of the second doped region; the back electrode is in contact with the surface of the first doped region.

9. The solar cell according to claim 8, characterized in that, The doping concentration of the first doped region is greater than or equal to the doping concentration of the doped conductive layer.

10. The solar cell according to claim 8, characterized in that, The doping concentration of the first doped region includes 2E20cm. -3 ~2E21cm -3 .

11. The solar cell according to claim 8, characterized in that, The depth of the first doped region is 1.5% to 4% of the height of the doped surface field.

12. The solar cell according to claim 1, characterized in that, Along the direction of the back electrode arrangement, the ratio of the width of the textured area to the width of the flat area ranges from 1:3 to 1:

1.

13. The solar cell according to claim 12, characterized in that, Along the direction of the back electrode arrangement, the ratio of the width of the textured area to the width of the flat area ranges from 1:2.3 to 1:1.

3.

14. The solar cell according to claim 12, characterized in that, The width of the velvet area is 10μm~30μm.

15. The solar cell according to claim 1, characterized in that, The back surface includes multiple textured areas arranged along the extension direction of the back electrode; the spacing between adjacent textured areas ranges from 10mm to 20mm.

16. The solar cell according to claim 1 or 15, characterized in that, On the same back electrode, the back surface includes multiple textured areas arranged along the arrangement direction of the back electrode; the spacing between adjacent textured areas ranges from 5μm to 20μm.

17. A photovoltaic module, characterized in that, include: At least one battery string, said battery string being formed by connecting a plurality of solar cells according to any one of claims 1 to 16; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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