A method, device and system for fast clock locking of master-slave clock switching

Abstract

The present invention relates to a method, device, and system for fast clock locking during master-slave clock switching. The method comprises: splitting a master clock signal and a backup clock signal into two, performing phase detection processing on one of the master clock signal and the backup clock signal to obtain a feedback signal; and applying the feedback signal to the master clock signal or the backup clock signal via a phase-locked loop (PLL) to align the phases of the master clock signal and the backup clock signal. This method can reduce the time interval for clock locking during clock switching, facilitating a smooth transition between master and backup clock switching.

Description

Technical Field

[0001] The present invention relates to the technical field of optical transmission network clock synchronization, and in particular to a method, device and system for fast clock locking for switching between a master and a standby clock. Background Art

[0002] In the current optical transmission network, clock synchronization is crucial for data transmission. Therefore, a primary and backup clock unit is often used for protection. The service disk selects the system clock based on the primary and backup status of the clock unit. When the primary clock fails or a primary-backup switchover occurs, the previous primary clock switches to the backup clock and the previous backup clock switches to the primary clock, completing a primary-backup switchover.

[0003] When the primary clock fails or a primary-backup switchover occurs, phase jumps in the primary and backup clocks can impact service disks, leading to service outages, service interruptions, and bit errors, severely impacting service stability. Related technologies use high-frequency clocks to sample and phase-shift the primary and backup clocks, and use frequency multiplication to phase-align the primary and backup clocks to reduce bit errors and LOF alarms generated during the switchover process. However, shifting the backup clock to the same phase as the frequency multiplier clock will result in a phase error of 1-2 frequency multiplier clocks. Other technologies use analog phase detectors, DDSs, DAs, and other analog devices to achieve a smooth transition. Currently, the accuracy achieved using FPGAs is approximately 10-200ps, which does not meet customer needs. Therefore, reducing the time interval between clock switching and clock lock to ensure a smooth transition between primary and backup clocks has become a key technology that needs to be addressed. Summary of the Invention

[0004] The embodiment of the present invention provides a method, device and system for fast clock locking during master / slave clock switching, which can reduce the time interval of clock locking during clock switching and facilitate smooth transition of master / slave clock switching.

[0005] In a first aspect, an embodiment of the present invention provides a method for fast clock locking during master / slave clock switching, characterized in that it includes:

[0006] After the main clock signal and the backup clock signal are respectively divided into two, one of the main clock signal and the backup clock signal are subjected to phase detection processing to obtain a feedback signal;

[0007] The feedback signal is applied to the main clock signal or the backup clock signal through a phase-locked loop to make the main clock signal and the backup clock signal consistent in phase.

[0008] In some embodiments, the step of dividing the primary clock signal and the backup clock signal into two comprises the following steps:

[0009] The main clock signal is passed through the main phase-locked loop to obtain two main clock sub-signals with the same frequency and phase;

[0010] After the standby clock signal passes through a standby phase-locked loop, two standby clock sub-signals with the same frequency and phase are obtained.

[0011] In some embodiments, performing phase detection processing on one of the main clock signals and one of the backup clock signals to obtain a feedback signal includes the steps of:

[0012] A main clock signal and a backup clock signal are processed by the main TDC for phase detection to output the main clock feedback signal.

[0013] The other main clock sub-signal and the other standby clock sub-signal are subjected to phase detection processing by a standby TDC to output a standby clock feedback signal.

[0014] In some embodiments, the phase detection process includes the steps of:

[0015] The master TDC outputs a master clock feedback signal capable of reducing the phase difference between the one master clock sub-signal and the one backup clock sub-signal according to the phase difference between the two signals;

[0016] The backup TDC outputs a backup clock feedback signal capable of reducing the phase difference between the other main clock sub-signal and the other backup clock sub-signal according to the phase difference between the other main clock sub-signal and the other backup clock sub-signal.

[0017] In some embodiments, applying the feedback signal to the primary clock signal or the backup clock signal through a phase-locked loop to make the primary clock signal and the backup clock signal consistent in phase comprises the following steps:

[0018] Inputting the master clock feedback signal into the master phase-locked loop, the master phase-locked loop being configured to adjust the phase of the master clock sub-signal to be consistent with the master clock feedback signal;

[0019] The backup clock feedback signal is input into the backup phase-locked loop, and the backup phase-locked loop is used to adjust the phase of the backup clock sub-signal to be consistent with the backup clock feedback signal.

[0020] Some embodiments further include the steps of:

[0021] Using the signal output by the master TDC as the final output signal of the master clock signal;

[0022] The signal output by the backup TDC is used as the final output signal of the backup clock signal.

[0023] Some embodiments further include the step of performing frequency division processing on the final output signal.

[0024] In a second aspect, an embodiment of the present invention further provides a fast clock locking device for switching between a master and a slave clock, characterized in that it includes:

[0025] A master-slave phase adjustment module is used to split the master clock signal and the backup clock signal into two, and then perform phase detection processing on one of the master clock signal and the backup clock signal to obtain a feedback signal;

[0026] The phase feedback processing module is used to apply the feedback signal to the main clock signal or the backup clock signal through a phase-locked loop to make the main clock signal and the backup clock signal consistent in phase.

[0027] In a third aspect, an embodiment of the present invention further provides a system for fast clock locking during master / slave clock switching, characterized in that it includes:

[0028] A master phase-locked loop (PLL) is used to split the master clock signal into two to obtain two master clock sub-signals with the same frequency and phase;

[0029] A standby phase-locked loop, which is used to split the standby clock signal into two to obtain two standby clock sub-signals with the same frequency and phase;

[0030] A main phase adjustment module is used to perform phase detection processing on a main clock signal and a backup clock signal through a main TDC to output a main clock feedback signal;

[0031] A standby phase adjustment module is used to perform phase detection processing on another main clock signal and another standby clock signal through a standby TDC to output a standby clock feedback signal;

[0032] The master phase-locked loop is further configured to adjust the phase of the master clock sub-signal to be consistent with the master clock feedback signal according to the master clock feedback signal;

[0033] The standby phase-locked loop is further configured to adjust the phase of the standby clock component signal to be consistent with the standby clock feedback signal according to the standby clock feedback signal.

[0034] In some embodiments, the master phase adjustment module is further configured to output a master clock feedback signal capable of reducing the phase difference between the one master clock sub-signal and the one backup clock sub-signal according to the phase difference between the two signals;

[0035] The backup phase adjustment module is further configured to output a backup clock feedback signal capable of reducing the phase difference between the other main clock sub-signal and the other backup clock sub-signal according to the phase difference between the other main clock sub-signal and the other backup clock sub-signal.

[0036] The embodiment of the present invention provides a method and device for fast clock locking in master-slave clock switching. By implementing a digital phase-locked loop through a clock network offset correction model and a TDC time-to-digital converter, the phase detection function can be realized, and at the same time, the TDC also greatly improves the precision control of the phase difference, thereby solving the problem of long-term loss of lock during master-slave switching. Implementing it through the TDC time-to-digital converter is equivalent to inserting a small counting module into the existing clock cycle of the FPGA, so as to achieve a redivision of one cycle of the existing clock, making it more accurate, and thus the phase difference between the two master-slave clocks after adjustment is smaller. The accuracy of the FPGA implementation in the related art is approximately 10-200ps. Under the same conditions, the solution provided by the embodiment of the present invention has an approximate error of 0-103ns (evaluated with a 19.44M clock), which effectively improves the accuracy of delay measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A flowchart of a method for fast clock locking during master / slave clock switching provided by an embodiment of the present invention;

[0039] Figure 2 A schematic diagram of the structure of a fast clock locking system for switching between master and backup clocks provided by an embodiment of the present invention;

[0040] Figure 3 A phase-locked loop calibration flow chart provided in an embodiment of the present invention;

[0041] Figure 4 A phase-locked loop correction timing diagram provided by an embodiment of the present invention;

[0042] Figure 5 A schematic diagram of a TDC phase detection circuit according to an embodiment of the present invention;

[0043] Figure 6 A schematic structural diagram of a fast clock locking device for switching between master and standby clocks provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0045] like Figure 1 As shown, an embodiment of the present invention provides a method for fast clock locking during master / slave clock switching, which includes:

[0046] S100: After splitting the main clock signal and the backup clock signal into two, one of the main clock signal and the backup clock signal are subjected to phase detection processing to obtain a feedback signal;

[0047] S200: Applying the feedback signal to the main clock signal or the backup clock signal through a phase-locked loop to make the main clock signal and the backup clock signal consistent in phase.

[0048] It's understandable that the phase-locked loop (PLL) performs frequency detection, ensuring the frequency accuracy of the signal after it's divided, avoiding issues with the FPGA's own distribution. The goal of phase detection is to generate a processed clock with a phase close to that of the other direction. This is then fed back into the PLL for feedback adjustment, ensuring that the primary and backup phases are ultimately aligned.

[0049] In this embodiment of the present invention, a phase-locked loop (PLL) is combined with phase-detection processing to form a digital PLL. After multiple feedback signal adjustments, the phases of the master and slave clock signals are ultimately aligned, effectively achieving interlocking between the master and slave clocks. This effectively improves the smoothness and stability of clock switching, thereby resolving the issue of prolonged loss of lock during master-slave switching. This provides better service for latency-sensitive customers and possesses significant practical value. Furthermore, this embodiment provides a purely digital circuit FPGA implementation. Compared to related art approaches based on oversampling phase detection or phase-locked loops constructed using digital circuits and digital chips, this approach is independent of chip accuracy, simplifies circuit board space usage, and reduces hardware costs, while also ensuring calibration accuracy.

[0050] In some embodiments, the primary clock signal and the backup clock signal are each divided into two in S100, including the steps of:

[0051] S110: Passing the main clock signal through a main phase-locked loop to obtain two main clock sub-signals with the same frequency and phase;

[0052] S120: Passing the standby clock signal through a standby phase-locked loop to obtain two standby clock sub-signals with the same frequency and phase.

[0053] In some embodiments, performing phase detection on one of the main clock signals and one of the backup clock signals to obtain a feedback signal in S100 includes the following steps:

[0054] S130: A main clock signal and a backup clock signal are subjected to phase detection by a main TDC to output a main clock feedback signal.

[0055] S140: The other main clock signal and the other backup clock signal are subjected to phase detection processing by the backup TDC to output a backup clock feedback signal.

[0056] It is understood that the use of a TDC in this embodiment improves the precision of phase difference control. This can be achieved through a TDC time-to-digital converter (TDC). This is equivalent to inserting a small counting module within the existing FPGA clock cycle, redividing the existing clock cycle for higher precision. This adjustment results in a smaller phase difference between the two primary and backup clocks. Related technologies using FPGAs achieve an accuracy of approximately 10-200ps. Under the same conditions, the solution provided in this embodiment achieves an approximate error of 0-103ns (evaluated using a 19.44M clock), effectively improving delay measurement accuracy.

[0057] In some embodiments, during the phase detection processing in S130 and S140, the main TDC outputs a main clock feedback signal capable of reducing the phase difference between the one main clock sub-signal and the one backup clock sub-signal according to the phase difference between them; the backup TDC outputs a backup clock feedback signal capable of reducing the phase difference between the other main clock sub-signal and the other backup clock sub-signal according to the phase difference between them.

[0058] like Figure 5 As shown in the figure, T0 is the measured interval time, that is, the phase difference between the master and slave clock signals, T1 is the measured start time, and T2 is the measured end time. Theoretically, T0 = T2 - T1, but in practice, since FPGA sampling is done on the rising edge of the clock, t0 is 1 sampling clock, so the calculated phase difference is T0 = n*t0 ( Figure 5 (where n = 20), the calculated error is t1 + t2. Based on the calculated clock phase difference, a clock with any phase at time T1-T2 can be constructed.

[0059] Preferably, when the main TDC performs phase detection processing, it outputs a main clock feedback signal with a phase difference reduced by half, and when the backup TDC performs phase detection processing, it outputs a backup clock feedback signal with a phase difference reduced by half. For example, if the phase of the main clock signal is 7.8 and the phase of the backup clock signal is 7.2, the main TDC outputs a main clock feedback signal with an average phase (i.e., (7.8+7.2) / 2=7.5), and the backup TDC outputs a backup clock feedback signal with an average phase (i.e., (7.2+7.8) / 2=7.5). After each feedback, the phase difference can be reduced by half, thereby ultimately ensuring that the output phases of the main and backup clocks are consistent.

[0060] In some embodiments, S200 includes:

[0061] S210: Inputting the master clock feedback signal into the master phase-locked loop, wherein the master phase-locked loop is configured to adjust the phase of the master clock component signal to be consistent with the master clock feedback signal according to the master clock feedback signal;

[0062] S220: Input the backup clock feedback signal into the backup phase-locked loop, and the backup phase-locked loop is used to adjust the phase of the backup clock component signal to be consistent with the backup clock feedback signal according to the backup clock feedback signal.

[0063] In some embodiments, the signal output by the main TDC may be used as the final output signal of the main clock signal; and the signal output by the backup TDC may be used as the final output signal of the backup clock signal.

[0064] It is understandable that if Figure 3 As shown by signals 2 and 3 in Figure 1, the final phase-locked loop adjustment results in the master and backup input clocks being completely aligned, thus achieving interlocking between the master and backup clocks. Furthermore, maintaining the feedback mechanism improves stability and prevents unexpected situations from causing the phase-locked loop to lose lock.

[0065] In some embodiments, the final output signal is further subjected to frequency division processing. It should be noted that the communication system requires an 8K clock, but the main and backup input clocks are 19.44M, and the clock signal required by the system can be obtained through frequency division processing.

[0066] like Figure 6 As shown, an embodiment of the present invention further provides a fast clock locking device for switching between a master and a slave clock, comprising:

[0067] A master-slave phase adjustment module is used to split the master clock signal and the backup clock signal into two, and then perform phase detection processing on one of the master clock signal and the backup clock signal to obtain a feedback signal;

[0068] The phase feedback processing module is used to apply the feedback signal to the main clock signal or the backup clock signal through a phase-locked loop to make the main clock signal and the backup clock signal consistent in phase.

[0069] In some embodiments, the active / standby phase adjustment module is further configured to:

[0070] The main clock signal is passed through the main phase-locked loop to obtain two main clock sub-signals with the same frequency and phase;

[0071] After the standby clock signal passes through a standby phase-locked loop, two standby clock sub-signals with the same frequency and phase are obtained.

[0072] In some embodiments, the active / standby phase adjustment module is further configured to:

[0073] A main clock signal and a backup clock signal are processed by the main TDC for phase detection to output the main clock feedback signal.

[0074] The other main clock sub-signal and the other standby clock sub-signal are subjected to phase detection processing by a standby TDC to output a standby clock feedback signal.

[0075] In some embodiments, when the master-slave phase adjustment module performs phase detection processing, the master TDC outputs a master clock feedback signal that can reduce the phase difference between the one master clock sub-signal and the one backup clock sub-signal; and the backup TDC outputs a backup clock feedback signal that can reduce the phase difference between the other master clock sub-signal and the other backup clock sub-signal.

[0076] In some embodiments, the phase feedback processing module is further configured to:

[0077] Inputting the master clock feedback signal into the master phase-locked loop, the master phase-locked loop being configured to adjust the phase of the master clock sub-signal to be consistent with the master clock feedback signal;

[0078] The backup clock feedback signal is input into the backup phase-locked loop, and the backup phase-locked loop is used to adjust the phase of the backup clock sub-signal to be consistent with the backup clock feedback signal.

[0079] In some embodiments, the signal output by the main TDC may be used as the final output signal of the main clock signal; and the signal output by the backup TDC may be used as the final output signal of the backup clock signal.

[0080] In some embodiments, a frequency divider is further included, which is used to perform frequency division processing on the final output signal.

[0081] like Figure 2As shown, a master-slave clock switching fast clock locking system includes:

[0082] A master phase-locked loop (PLL) is used to split the master clock signal into two to obtain two master clock sub-signals with the same frequency and phase;

[0083] A standby phase-locked loop, which is used to split the standby clock signal into two to obtain two standby clock sub-signals with the same frequency and phase;

[0084] A main phase adjustment module is used to perform phase detection processing on a main clock signal and a backup clock signal through a main TDC to output a main clock feedback signal;

[0085] A standby phase adjustment module is used to perform phase detection processing on another main clock signal and another standby clock signal through a standby TDC to output a standby clock feedback signal;

[0086] The master phase-locked loop is further configured to adjust the phase of the master clock sub-signal to be consistent with the master clock feedback signal according to the master clock feedback signal;

[0087] The standby phase-locked loop is further configured to adjust the phase of the standby clock component signal to be consistent with the standby clock feedback signal according to the standby clock feedback signal.

[0088] In some embodiments, the master phase adjustment module is further configured to output a master clock feedback signal capable of reducing the phase difference between the one master clock sub-signal and the one backup clock sub-signal according to the phase difference between the one master clock sub-signal and the one backup clock sub-signal;

[0089] The standby phase adjustment module is further configured to output a standby clock feedback signal capable of reducing the phase difference between the other main clock sub-signal and the other standby clock sub-signal according to the phase difference between the other main clock sub-signal and the other standby clock sub-signal.

[0090] like Figure 2As shown, in a specific embodiment, Clk1ai is the primary source clock sent from the active CCU, and Clk1bi is the backup source clock sent from the standby CCU. Specifically, after entering the phase-locked loop (PLL), the primary clock Clk1ai is split into two (Clk1ao and Clk1ao_fbout). Clk1ao is sent to the active TDC for phase processing, while Clk1ao_fbout is sent to the standby TDC for phase processing. The clock signal Clk1ao_fbout sent to the standby TDC undergoes phase detection with the standby clock Clk1bo at the standby end. The phase-adjusted clock feedback signal Clk1bo_fbin is output and fed back to the standby PLL for clock offset correction. Similarly, of the two split backup clock signals (Clk1bo and Clk1bo_fbout) output from the backup phase-locked loop, one backup clock signal Clk1bo_fbout is sent to the master TDC and phase-detected with the master clock Clk1ao at the master end. The phase-adjusted clock feedback signal Clk1ao_fbin is output and fed back to the master phase-locked loop for clock offset correction. After multiple clock input cycles, the master end outputs a clock with the same phase as the backup clock, which is then divided and output. The backup end also outputs a clock with the same phase as the master clock, which is divided and output. The same applies to the backup direction.

[0091] like Figure 3 In the phase-locked loop (PLL) offset correction process for the clock network shown, signal 1 is the master / backup clock, and signal 6 is the backup / master output clock. The master / backup clock signal 1 is sent to the input global buffer bufg (indicated by the small triangle between 1 and 2) and generates signal 2, which is then sent to the PLL as the input clock. After being divided into two by the PLL, signals 4 and 6 with the same frequency and phase are obtained. From the characteristics of the PLL, it can be seen that the phase of the PLL input signal 2 is consistent with that of signal 3, and the phase of the PLL output signal 4 is consistent with that of signal 5. Among them, 4 is the master / backup clock PLL output clock, and 5 is the master / backup clock PLL feedback output clock. The function of the phase adjustment module is to adjust the backup / master output clock signal 6, and send it and the master / backup feedback output clock signal 5 to the phase adjustment module (TDC) to adjust its phase to be consistent with the phase of the signal 5 output, and output the master / backup feedback input clock signal 3 after the phase adjustment. Since the clock phases of signals 4 and 5 are consistent, the clock phases of signals 3 and 4 are also consistent. Therefore, as Figure 4 As shown in the timing diagram, after repeated positive feedback adjustments, the clock phases of signals 2, 3, 4, 5, and 6 are aligned. Ultimately, the master and slave clocks are fully interlocked in the two feedback loops, achieving a smooth transition during master-slave switching.

[0092] It will be understood by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer-readable storage medium (or a non-transitory medium) and a communication medium (or a temporary medium).

[0093] It should be noted that, in the present invention, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0094] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is intended to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for fast clock locking during master / slave clock switching, characterized in that: It includes: After the main clock signal and the backup clock signal are respectively divided into two, one of the main clock signal and the backup clock signal are subjected to phase detection processing to obtain a feedback signal; Applying the feedback signal to the main clock signal or the backup clock signal through a phase-locked loop to make the main clock signal and the backup clock signal consistent in phase; The method of performing phase detection processing on one of the main clock signals and one of the backup clock signals to obtain a feedback signal comprises the following steps: A main clock signal and a backup clock signal are processed by the main TDC for phase detection to output the main clock feedback signal. The other main clock signal and the other backup clock signal are subjected to phase detection processing by the backup TDC to output the backup clock feedback signal; The phase discrimination process comprises the steps of: The master TDC outputs a master clock feedback signal capable of reducing the phase difference between the one master clock sub-signal and the one backup clock sub-signal according to the phase difference between the two signals; The backup TDC outputs a backup clock feedback signal capable of reducing the phase difference between the other main clock sub-signal and the other backup clock sub-signal according to the phase difference between the other main clock sub-signal and the other backup clock sub-signal.

2. The method for fast clock locking during master / slave clock switching according to claim 1, wherein: The method of dividing the main clock signal and the backup clock signal into two respectively comprises the steps of: The main clock signal is passed through the main phase-locked loop to obtain two main clock sub-signals with the same frequency and phase; After the standby clock signal passes through a standby phase-locked loop, two standby clock sub-signals with the same frequency and phase are obtained.

3. The method for fast clock locking during master / slave clock switching according to claim 2, wherein: The step of applying the feedback signal to the main clock signal or the backup clock signal through a phase-locked loop so that the main clock signal and the backup clock signal are in phase with each other comprises the following steps: Inputting the master clock feedback signal into the master phase-locked loop, the master phase-locked loop being configured to adjust the phase of the master clock sub-signal to be consistent with the master clock feedback signal; The backup clock feedback signal is input into the backup phase-locked loop, and the backup phase-locked loop is used to adjust the phase of the backup clock sub-signal to be consistent with the backup clock feedback signal.

4. The method for fast clock locking during master / slave clock switching according to claim 2, wherein: Also includes the steps: Using the signal output by the master TDC as the final output signal of the master clock signal; The signal output by the backup TDC is used as the final output signal of the backup clock signal.

5. The method for fast clock locking during master / slave clock switching according to claim 4, wherein: The method further comprises the step of performing frequency division processing on the final output signal.

6. A fast clock locking device for switching between master and standby clocks, characterized in that: It includes: A master-slave phase adjustment module is used to split the master clock signal and the backup clock signal into two, and then perform phase detection processing on one of the master clock signal and the backup clock signal to obtain a feedback signal; a phase feedback processing module, configured to apply the feedback signal to the primary clock signal or the backup clock signal through a phase-locked loop so that the primary clock signal and the backup clock signal are in phase with each other; The active / standby phase adjustment module is also used to: A main clock signal and a backup clock signal are processed by the main TDC for phase detection to output the main clock feedback signal. The other main clock signal and the other backup clock signal are subjected to phase detection processing by the backup TDC to output the backup clock feedback signal; When the master-slave phase adjustment module performs phase detection processing, the master TDC outputs a master clock feedback signal that can reduce the phase difference between the one master clock sub-signal and the one backup clock sub-signal based on the phase difference between them; the backup TDC outputs a backup clock feedback signal that can reduce the phase difference between the other master clock sub-signal and the other backup clock sub-signal based on the phase difference between them.

7. A fast clock locking system for master / slave clock switching, characterized in that: It includes: A master phase-locked loop (PLL) is used to split the master clock signal into two to obtain two master clock sub-signals with the same frequency and phase; A standby phase-locked loop, which is used to split the standby clock signal into two to obtain two standby clock sub-signals with the same frequency and phase; A main phase adjustment module is used to perform phase detection processing on a main clock signal and a backup clock signal through a main TDC to output a main clock feedback signal; A standby phase adjustment module is used to perform phase detection processing on another main clock signal and another standby clock signal through a standby TDC to output a standby clock feedback signal; The master phase-locked loop is further configured to adjust the phase of the master clock sub-signal to be consistent with the master clock feedback signal according to the master clock feedback signal; The standby phase-locked loop is further configured to adjust the phase of the standby clock sub-signal to be consistent with the standby clock feedback signal according to the standby clock feedback signal; The main phase adjustment module is further configured to output a main clock feedback signal capable of reducing the phase difference between the main clock sub-signal and the backup clock sub-signal according to the phase difference between the main clock sub-signal and the backup clock sub-signal; The backup phase adjustment module is further configured to output a backup clock feedback signal capable of reducing the phase difference between the other main clock sub-signal and the other backup clock sub-signal according to the phase difference between the other main clock sub-signal and the other backup clock sub-signal.

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