Error detection, prediction, and handling techniques for in-system package storage architecture

Abstract

System-in-a-package including a logic die and one or more memory dies can include a reliability availability serviceability (RAS) memory management unit (MMU) for memory error detection, memory error prediction, and memory error handling. The RAS MMU can receive memory health state information, on-die memory error information, system error information, and read address information for the one or more memory dies. The RAS MMU can manage individual memory blocks of the one or more memory dies based on the memory health state information, on-die memory error type, system error type, and read address. The RAS MMU can further manage the individual memory blocks based on received on-die memory temperature information and / or system temperature information.

Description

Technical Field

[0001] This disclosure relates to the field of processor technology, and more particularly to an error detection, prediction and processing technology for in-system packaged storage architecture. Background Technology

[0002] To further alter the scale of integrated circuits (ICs), various techniques have emerged to reduce memory accesses and / or increase processing speed, as well as to combine memory and logic circuits in two-dimensional or three-dimensional architectures. References will now be made to... Figure 1A-1E The illustrations depict some exemplary two-dimensional and three-dimensional architectures. Figure 1A A two-dimensional (2D) proximity processing PNM IC package is shown. The 2D PNM 105 may include a memory die 110 and a logic die 115 coupled together in a single package. Figure 1B The 2D In-Memory Processing (PIM) package is shown. The 2D PIM 120 can include both arithmetic logic and memory on the same die 125. Figure 1C A 2.5D PNM package is shown. The 2.5D PNM 130 includes a memory die 135 and a logic die 140 coupled together via an interposer layer 145. Figure 1D A 3D hybrid PNM package 150 is shown. The 3D hybrid PNM 150 may include a memory die 155 coupled to a logic die 160. Figure 1E A 3D Through Silicon Via (TSV) PNM package is shown. The 3D TSV PNM 165 may include multiple memory dies 170-180 coupled to a logic die 185 through multiple through silicon vias 190.

[0003] The reliability of 2D and 3D memory architectures is affected by various factors, including but not limited to operating temperature within the package, bonding between logic dies and one or more memory dies, and variations in the size of one or more memory dies. Therefore, techniques for error detection, error prediction, and / or error handling are needed in 2D PNM, 3D PNM, PIM, and other architectures. Summary of the Invention

[0004] This disclosure is best understood by referring to the following description and accompanying drawings, which illustrate various embodiments of this disclosure for a near-memory processing (PNM) architecture with memory error detection, error prediction, and error handling mechanisms.

[0005] In one embodiment, the system-in-package (SiP) may include one or more memory dies and logic dies. The one or more memory dies may include a corresponding memory array arranged in multiple memory blocks, an eFuse module, and a D flag register. The eFuse may be configured to store memory health status information for one or more memory dies. The D flag register may be configured to store on-chip memory error information for one or more memory dies. The logic die may include arithmetic logic, a memory controller, and a Reliability, Availability and Maintainability (RAS) Memory Management Unit (MMU). The memory controller may include an S flag register configured to store system memory error information and a read address buffer configured to store memory read addresses. The RAS MMU may be configured to manage memory error detection, memory error prediction, and memory error handling based on the eFuse module, the Memory Error Correction Code (ECC) flag register, the System Error Correction Code (ECC) flag register, and the read address buffer.

[0006] In another embodiment, the management method for memory error detection, memory error prediction, and memory error handling may include receiving health status information, on-chip memory error information, system error information, and read address information of one or more memory dies in the system-in-package (SIP) via a memory management unit (MMU) of the logic die. The method may further include managing individual memory blocks of one or more memory dies based on the memory health status information, on-chip memory error type, system error type, and read address via the MMU.

[0007] The summary is provided to introduce selected concepts in a simplified form, which will be further described in the detailed description below. The summary is not intended to define key or essential features of the subject matter in the claims, nor is it intended to limit the scope of the claimed subject matter. Attached Figure Description

[0008] Embodiments of this disclosure are shown in the accompanying drawings by way of example rather than by way of limitation, and wherein similar reference numerals refer to similar elements, and wherein:

[0009] Figures 1A-1E Exemplary two-dimensional and three-dimensional PMN and PIM architectures are shown.

[0010] Figure 2 System-in-Package (SiP) solutions according to various schemes of this disclosure are shown.

[0011] Figure 3 The Reliability, Availability, and Maintainability (RAS) Memory Management Unit (MMU) of various schemes according to this disclosure is shown.

[0012] Figure 4Methods for error detection, prediction, and handling according to various schemes of this disclosure are shown.

[0013] Figure 5 Methods for managing individual memory blocks of one or more memory dies in a SiP according to various schemes of this disclosure are shown.

[0014] Figure 6 Methods for handling blacklisted memory blocks according to various schemes of this disclosure are shown. Detailed Implementation

[0015] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While the present disclosure will be described in conjunction with these embodiments, it should be understood that they are not intended to limit the technology to these embodiments. Rather, the invention is intended to cover alternatives, modifications, and equivalents that may be included within the scope of the invention as defined by the appended claims. Furthermore, numerous specific details are set forth in the following detailed description of the present disclosure to provide a thorough understanding of the disclosure. However, it should be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure.

[0016] The following embodiments of this disclosure are presented according to routines, modules, logic blocks, and other symbolic representations of operations on data within one or more electronic devices. Description and representation are means used by those skilled in the art to most effectively convey the essence of their work to others skilled in the art. Routines, modules, logic blocks, and / or the like are, herein and generally, considered as self-consistent sequences of processes or instructions that lead to desired results. These processes include physical operations on physical quantities. Typically, but not necessarily, these physical operations take the form of electrical or magnetic signals capable of being stored, transmitted, compared, and otherwise operated in an electronic device. For convenience and with reference to common usage, and with reference to embodiments of this disclosure, these signals are referred to as data, bits, values, elements, symbols, characters, terms, numbers, strings, etc.

[0017] However, it should be remembered that these terms are to be interpreted as references to physical operations and quantities and are merely convenient labels and will be further interpreted according to terms commonly used in the art. Unless otherwise clearly stated from the following discussion, it should be understood that, through the discussion of this disclosure, the use of terms such as “receive” and / or similar terms refers to the actions and processes of electronic devices, such as an electronic computing device that processes and converts data. Data is represented as physical (e.g., electronic) quantities within the logic circuits, registers, memory, etc., of electronic devices and is converted into other data similarly represented as physical quantities within electronic devices.

[0018] In this disclosure, the use of extractive terms is intended to include conjunctions. The use of definite or indefinite articles is not intended to indicate cardinality. In particular, references to “the” object or “an” object are also intended to indicate one of a possible plurality of such objects. The use of terms such as “comprising,” “including,” “including,” “comprise,” etc., specifies the presence of the element, but does not preclude the presence or addition of one or more other elements and / or groups thereof. It should also be understood that although the terms first, second, etc., may be used herein to describe various elements, such elements should not be limited by these terms. These terms are used herein to distinguish one element from another. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. It should also be understood that when an element is referred to as “coupled” to another element, it may be directly or indirectly connected to the other element, or there may be intermediate elements. Conversely, when an element is referred to as “directly connected” to another element, there are no intermediate elements. It should also be understood that the term “and or” includes any and all combinations of one or more associated elements. It should also be understood that the wording and terminology used herein are for descriptive purposes and should not be considered limiting.

[0019] refer to Figure 2 The diagram illustrates system-in-package (SiP) solutions according to various embodiments of the present disclosure. The PNM SiP 200 may include one or more memory dies 202 coupled to a logic die 204 via one or more interfaces. The one or more memory dies 202 and logic die 204 may be arranged in architectures such as Near-Memory Processing (PNM), 2D PNM, 2.5D PNM, In-Memory Processing (PIM), 2DPIM, 3D Hybrid (HB) PNM, and 3D Through-Silicon Via (TSV) PNM. In one embodiment, the one or more memory dies 202 may be volatile memory (VM) memory, which is exemplary, but not limited to, dynamic random access memory (DRAM). In one embodiment, the logic die may include, but is not limited to, one or more processors, one or more controllers, one or more combinational logic circuits, one or more programmable gate arrays, one or more engines, and any combination thereof.

[0020] One or more memory dies 202 may include, but are not limited to, a VM cell array 206, an input / output (I / O) gate controller 208, a VM write controller 210, a VM read controller 212, a memory array temperature sensor 214, and an eFuse 216. The VM cell array 206 may include multiple VM cells coupled in columns and rows via word lines and bit lines for storing data in the VM cells. The VM cells of array 206 may be arranged in multiple memory blocks. The I / O gate controller 208 may be configured to drive word lines and bit lines and sense current or voltage on them to read data from or write data to VM cells in selected memory blocks of the memory cell array 206. The VM write controller 210 may be configured to control the I / O gate controller 208 to write data to VM cells in selected memory blocks of the memory cell array 206. Similarly, the VM read controller 212 may be configured to control the I / O gate controller 208 to read data from VM cells in selected memory blocks of the memory cell array 206.

[0021] VM write controller 210 may include an on-chip memory error correction code (OD-ECC) encoder 218, which is configured to generate error detection and correction codes for data written to VM cells having selected memory blocks. The error detection and correction codes may be used to detect errors occurring during data writing due to one or more faulty VM cells, and / or during data reading, and to correct at least some of the detected errors. VM read controller 212 may include an OD-ECC decoder 220 and a data flag (D flag) register 222. OD-ECC decoder 220 may be configured to detect errors and correct at least some of the detected errors using the ECC codes generated by OD-ECC encoder 218. In one implementation, OD-ECC decoder 218 may detect both correctable and uncorrectable bit errors on the memory die and may correct correctable bit errors on the memory die. For example, a given ECC code may be configured to detect up to two bit errors in a word and correct a single bit error in the word. The OD-ECC decoder 234 can be configured to set the D flag register 222 to indicate whether a read operation for a given read address resulted in the detection of a correctable or uncorrectable bit error on the memory die. For example, a first state of the D flag register can indicate a correctable error, and a second state can indicate an uncorrectable error.

[0022] A memory array temperature sensor 214 can be disposed in the memory cell array 206 and configured to sense the operating temperature of the memory cell array 206. Generally, as the operating temperature of the memory cell array 206 increases, the data error rate in the memory cell array 206 also increases. A fuse 216 can be configured to store health status information for one or more memory dies 202.

[0023] Logic die 204 may include arithmetic logic 224, a memory controller 226, a Reliability, Availability and Serviceability (RAS) Memory Management Unit (MMU) 228, and a Non-Volatile Memory (NVM) interface 230. Arithmetic logic 224 may include, but is not limited to, a processor controller, combinational logic circuits, a programmable gate array, an engine, etc. Memory controller 226 may include a system ECC encoder 232, a system ECC decoder 234, a buffer 236 as a read address buffer, a system flag (S flag) register 238, and a temperature register 240. System ECC encoder 232 may be configured to generate error detection and correction codes for data to be sent to one or more memory dies 202. System ECC decoder 234 may be configured to detect errors and correct at least some detected errors using ECC codes generated by OD-ECC encoder 218. In one embodiment, system ECC decoder 234 may detect correctable and uncorrectable system bit errors and may correct correctable system bit errors. For example, a given ECC code may be configured to detect up to two bit errors in a word and correct a single bit error in the word. The system ECC decoder 234 can be configured to set the S-flag register 238 to indicate whether a read operation for a given read address results in the detection of a correctable or uncorrectable system bit error. For example, a first state of the S-flag register can indicate a correctable error, and a second state can indicate an uncorrectable error.

[0024] Buffer 236 can be configured to store the read address of a read command sent to one or more memory dies 202. Temperature register 240 can be located in the memory controller 226 of logic die 204 and configured to store the operating temperature sensed by temperature sensor 214 of memory cell array 206. RAS MMU 228 can be configured to communicatively couple the memory controller to host 242. RAS MMU 228 can be configured to manage memory error detection, memory error prediction, and / or memory error handling based on fuse 216, D flag, S flag, buffer 236, and the temperature sensed by memory array temperature sensor 214 and stored in temperature register 240, or optionally directly from memory array temperature sensor 214. NVM interface can be configured to communicatively couple RAS MMU 228 to Reliability Availability Serviceable (RAS) Nonvolatile Memory (NVM) 244. RAS NVM 244 can be configured to store memory management information received from RAS MMU 228. In one implementation, the RAS NVM 244 may be a flash memory. The RAS NVM 244 may also be communicatively coupled to the host 242. Memory management information stored in the RAS NVM 244 may also be read by the host 242.

[0025] In one implementation, the RAS MMU 228 can be coupled to the fuse 216 of a corresponding memory die in one or more memory dies via a corresponding interface. The RAS MMU 228 can be configured to read the health status information of the corresponding memory die from the corresponding fuse 216. In one implementation, the RAS MMU 228 can also be coupled to the D flag register 222 via a corresponding interface. The RAS MMU 228 can be configured to read on-chip ECC information from the D flag register 222 of the VM control logic 212. In one implementation, the RAS MMU 228 can also be coupled to the S flag register 238 via a corresponding interface. The RAS MMU 228 can be configured to read system ECC information from the S flag register 238. In one implementation, the RAS MMU 228 can also be coupled to a buffer 236 via a corresponding interface. The RAS MMU 228 can be configured to read the address of a pending read operation from the buffer 236. The RAS MMU 228 can also be coupled to the temperature register 240 or optionally to the memory array temperature sensor 214 via a corresponding interface. The RAS MMU 228 can be configured to read temperature information from the temperature register 240 or optionally directly from the memory array temperature sensor 214. In one implementation, the RAS MMU 228 can detect and manage memory errors based on information detected from the fuse register 216, the D flag register 222, the S flag register 238, and the buffer 236. The RAS MMU 228 can also predict memory errors based on temperature information from the temperature register 240 or optionally directly from the memory array temperature sensor 214.

[0026] RAS MMU 228 can report uncorrectable system memory errors to host 242. In one implementation, if the host application associated with the read request that caused the uncorrectable system memory error is fault-tolerant, host 242 can be configured to acknowledge the uncorrectable system memory error and continue execution of the host application without any further action. If the host application is not fault-tolerant, the host application can receive an uncorrectable system memory error event notification from host 242 so that the host application can gracefully exit. Host 242 can also be configured to send back an acknowledgment of the uncorrectable system memory error report to RAS MMU 228. If RAS MMU 228 does not receive an acknowledgment response from host 242 for the uncorrectable system error, MMU 228 can be configured to blacklist the associated memory block during runtime operation. If an acknowledgment is received from host 242 for the uncorrectable system memory error report, RAS MMU 228 can blacklist the associated memory block at the next reset or power cycle event. If the blacklist of associated memory blocks is not caused by an uncorrectable system memory error, the RAS MMU 228 can blacklist the associated memory blocks on the next reset or power cycle event.

[0027] Now for reference Figure 3 The diagram illustrates a Reliability, Availability, and Maintainability (RAS) MMU 228 according to various embodiments of the present disclosure. The RAS MMU 228 may include a Reliability, Availability, and Maintainability (RAS) module 305, a capacity register 310, an optional block size register 315, an effective block mapping module 320, and a page table 325. The RAS module 305 may include an error handling module 330 and an error prediction module 335. The error handling module 330 may be configured to detect and manage memory errors based on information from a fuse register 216, a D flag register 222, an S flag register 238, and a buffer 236. The error prediction module 335 may be configured to predict memory errors based on temperature information from a temperature register 240 or optionally from a memory array temperature sensor 214.

[0028] In one implementation, the capacity register 310 can be configured to store the total number of available memory blocks of one or more memory dies 202 (i.e., Value). capacity_reg The total number of available memory blocks of one or more memory dies 202 can be read from the RAS NVM 244. If the value in the fuse register 216 is in a given state indicating a failure of the entire VM block, the capacity register can be set to a zero value (0). In one implementation, the block size register 315 can be configured to store the smallest error handling granularity of the VM (i.e., Value). block_sizeFor example, block size register 315 can indicate that a hard error in a 64-bit memory access may prevent access to an entire kilobyte (KB) of DRAM. The smallest processing granularity of the VM can be read from the RASNVM244. The total available VM capacity of the memory die (Capacity) Total (Can be based on Capacity) Total =Value capacity_reg *Value block_size To calculate.

[0029] In one implementation, the valid block mapping module 320 can be configured to store a mapping of currently available VM block addresses. In a first example, the valid block mapping module 320 can store a bitmap of all VM blocks of the memory die 202. In a second example, the valid mapping module 320 can store a list of faulty block addresses. Valid block mapping information can be read from the RAS NVM 244. In one implementation, the individual values ​​of the capacity register and the valid block mapping information can be changed during operation and should be written back to the RAS NVM 244 before power-down or periodically during operation. The block size register is read-only and does not change during operation.

[0030] References will be included in the text. Figure 2 Further explanation of SiP 200 operation, Figure 4 Methods for error detection, prediction, and handling according to various schemes of this disclosure are illustrated. The method may include: in step 410, receiving memory health status information, on-chip memory error information, system error information, and read address information. The memory health status information, on-chip memory error information, system error information, and read address information of one or more logic dies 204 for the SiP may be received by the RAS MMU 228 of the logic die 204. In one embodiment, the RAS MMU 228 may read the health status information of the corresponding memory die from the corresponding fuse 216. The RAS MMU 228 may also read on-chip ECC information from the D flag register 222 of the VM read control logic 212. The RAS MMU 228 may also read system ECC information from the S flag register 238. The RAS MMU 228 may also read the address of a pending read operation from the buffer 236.

[0031] In step 420, individual memory blocks of one or more memory dies can be managed based on memory health status information, on-chip memory error information, system error information, and read address information. In one embodiment, the RAS MMU 228 can manage individual memory blocks using the received memory health status information, on-chip memory error information, system error information, and read address information.

[0032] At step 430, on-chip memory temperature information may optionally be received. In one embodiment, the RAS MMU 228 may optionally receive on-chip memory temperature information of one or more memory dies. At step 440, individual memory blocks of one or more memory dies may be further managed based on the on-chip memory temperature information. In one embodiment, the RAS MMU 228 may manage memory blocks based on error prediction using the on-chip memory temperature information of one or more memory dies. At step 450, memory management information may optionally be stored for later use while managing individual memory blocks of one or more memory dies. In one embodiment, the RAS MMU 228 may store memory management information, including but not limited to: memory health status information of one or more memory dies and / or logic dies, memory error information on the memory dies, system error information and read address information, and on-chip memory temperature information. In one embodiment, the RAS MMU 228 may store the memory management information externally or internally to the SiP in optional RAS non-volatile memory. Furthermore, the RAS MMU 228 may provide memory management information to the host 442. Furthermore, the processing of steps 410-450 can be performed iteratively for multiple memory accesses.

[0033] Now for reference Figure 5 This document illustrates methods for managing individual memory blocks of one or more memory dies in a SiP according to various schemes of this disclosure. The method may include: in step 510, initializing a risk indicator for a corresponding memory block of the one or more memory dies. In one embodiment, the RAS MMU 228 may initialize the risk indicator value mapped to the corresponding memory block label in the RAS table by setting the risk indicator to zero.

[0034] In step 520, on-chip memory error information and system error information can be read. Additionally, the on-chip memory temperature can be read. In one embodiment, the RAS MMU 228 can read OD-ECC information from the D flag register 222, system ECC information from the S flag register 238, and optionally read the temperature register 240 or the memory array temperature sensor 214. In step 530, a given risk indicator can be determined based on the error type and error location indicated by the on-chip memory error information and system error information. The given risk indicator can also be further determined based on the optional memory array temperature. In one embodiment, the risk indicator value can be associated with each detected memory error for a given location and a given error type. For example, a first error value 'a' may be associated with a correctable error type detected on the memory die as indicated by D flag register 222, a second error value 'b' may be associated with an uncorrectable error type detected on the memory die as indicated by D flag register 222, a third error value 'c' may be associated with a correctable error type detected on the system as indicated by S flag register 238, and a fourth error value 'd' may be associated with a correctable error type detected on the system as indicated by S flag register 238. In one implementation, the fourth error value 'd' may be set to be greater than or equal to a predetermined threshold. In one example, the first error value 'a' may be less than the second error value 'b', the second error value 'b' may be less than the third error value 'c', and the third error value 'c' may be less than the fourth error value 'd'. Optionally, each error value may be multiplied by a temperature compensation scalar (T) based on optional memory temperature and / or system temperature to decouple temperature-induced memory errors. Table 1 illustrates exemplary error locations, error types, and risk indicators.

[0035] Flags Error Location Error Type RiskIndicator D mark - CE Memory Die Correctable RI=+a·T D mark - CE Memory Die Uncorrectable RI = + b·T S mark - CE system Correctable RI = +c·T S mark - CE system Uncorrectable RI > threshold

[0036] In step 540, the accumulated risk indicators can be mapped to corresponding memory blocks. In one implementation, RASMMU 228 can map the accumulated risk indicator values ​​to corresponding virtual memory block labels in the RAS table. In step 550, the processing of steps 520-540 can be performed iteratively for multiple memory accesses.

[0037] In step 560, individual memory blocks with risk indicators greater than or equal to a threshold can be identified and marked as inaccessible. In one implementation, the RAS MMU 228 can identify memory blocks with a set (1) most significant bit (MSB) in the RAS table and can set a blacklist indicator for a given memory block in the RAS table. The processing of step 560 can be performed iteratively for each of the multiple memory accesses, and in step 570, repeated at specified time intervals, etc.

[0038] refer to Figure 6 This document illustrates methods for handling blacklisted memory blocks according to various schemes of this disclosure. Method 600 may include receiving an indication of a blacklisted memory block in step 610. In one embodiment, RAS MMU 228 may determine the blacklisted memory block from a RAS table that maps risk indicator values ​​to corresponding virtual memory block labels. In step 620, when a given memory block is blacklisted due to an uncorrectable system error, the uncorrectable system error may be optionally reported to the host device. In one embodiment, RAS MMU 228 may report the uncorrectable system error to host 442. In step 630, the capacity register may be updated based on the blacklisted memory block. In one embodiment, RAS MMU 228 may update the capacity register 310 in response to receiving an indication of a given blacklisted memory block. In step 640, the mapping of valid blocks may be updated based on the blacklisted memory block. In one implementation, the valid block mapping module 320 of the RAS MMU 228 can update the mapping of valid memory blocks in response to receiving an indication of a given blacklisted memory block. In step 650, the page table can be updated based on the blacklisted memory block. In one implementation, the RAS MMU 228 can update the page table 325 in response to receiving an indication of a given blacklisted memory block and setting a valid page table entry for the corresponding memory block.

[0039] According to the various schemes of this disclosure, memory error detection, error prediction, and error handling mechanisms can be advantageously used in in-memory processing (PIM), near-memory processing (PNM), and other similar architectures. Memory error detection, prediction, and handling mechanisms are advantageously suited for fault-tolerant applications. Bit error rate in volatile memory can be a significant issue in various die bonding technologies for system-in-package (SiP), and the various schemes of the error detection, error prediction, and error handling mechanisms of this disclosure can advantageously provide cost and / or yield improvements (VM) for volatile memory in PIM, PNM, or similar SiP architectures.

[0040] The foregoing description of specific embodiments of this disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed, and many modifications and variations will be apparent from the foregoing teachings. The embodiments were chosen and described in order to best explain the principles of this disclosure and its practical application, thereby enabling others skilled in the art to best utilize this disclosure and various embodiments with various modifications suited to the intended particular use. The scope of the invention is intended to be defined by the appended claims and their equivalents.

Claims

1. A system-in-package (SiP), comprising: One or more memory dies, including; The memory array is arranged into multiple memory blocks; An electric fuse (eFuse) module is configured to store storage health status information of the one or more memory dies; and The Memory Error Correction Code (ECC) flag register is configured to store on-chip memory error information for the one or more memory dies; as well as Logic chips, including; Operational logic; A memory controller is configured to communicatively couple the arithmetic logic to one or more memory dies, wherein the memory controller includes a system error correction code (ECC) flag register configured to store system memory error information, and a read address buffer configured to store memory read addresses; and A Reliability, Availability and Serviceability (RAS) Memory Management Unit (MMU) is configured to communicatively couple the memory controller to a host, wherein the RAS MMU is configured to manage memory error detection, memory error prediction and memory error handling based on an electric fuse module, the memory error correction code (ECC) flag register, the system error correction code (ECC) flag register and a read address buffer.

2. The system-level packaging according to claim 1, wherein, The logic chip also includes: A non-volatile memory interface is configured to communicatively couple a RAS non-volatile memory to the RAS MMU, the RAS non-volatile memory being configured to store memory management information.

3. The system-level encapsulation according to claim 1, wherein: The one or more memory dies include a temperature sensor; The memory controller also includes a temperature register; and The RAS MMU is also configured to manage memory error detection, memory error prediction, and memory error handling based on temperature information from temperature sensors or temperature registers of the memory controller or one or more memory dies.

4. The system-level packaging according to claim 1, wherein, The first state of the memory error correction code (ECC) flag register indicates that the error can be corrected, and the second state indicates that the error cannot be corrected.

5. The system-level packaging according to claim 1, wherein, The first state of the system error correction code (ECC) flag register indicates that the error can be corrected, and the second state indicates that the error cannot be corrected.

6. The system-level encapsulation of claim 1, wherein the RAS MMU is configured to manage memory error detection, memory error prediction, and memory error handling, including: When the corresponding risk indicator reaches a predetermined level, the memory blocks in one or more memory dies are blacklisted.

7. The system-in-package according to claim 1, wherein the RAS MMU comprises: The error handling module is configured to detect and manage memory errors based on information from the electric fuse module, the memory error correction code (ECC) flag register, the system error correction code (ECC) flag register, and the read address buffer; The error prediction module is configured to predict memory errors based on temperature information from a temperature register of the memory controller or a temperature sensor of one or more memory dies. A capacity register is configured to store the total number of available memory blocks of the one or more memory dies; The block size register is configured to store the smallest possible error handling granularity; as well as The valid block mapping module is configured to store the mapping of risk indicators to corresponding memory blocks in a plurality of memory blocks of the memory array.

8. The system-level packaging according to claim 1, wherein, The logic die and the one or more memory dies are arranged in near-memory processing (PNM), two-dimensional (2D) PNM, 2.5D PNM, in-memory processing (PIM), 2DPIM, three-dimensional (3D) hybrid (HB) PNM, and 3D through-silicon via (TSV) PNM architectures.

9. A method for managing memory error detection, memory error prediction, and memory error handling, comprising: The system-in-package (SIP) receives memory health status information, on-chip memory error information, system error information, and read address information from one or more memory dies in the SIP via the memory management unit (MMU) of the logic die, wherein the system-in-package is a system-in-package according to any one of claims 1-8; as well as The MMU manages the individual memory blocks of one or more memory dies based on the memory health status information, the on-chip memory error type, the system error type, and the read address.

10. The method of claim 9, further comprising: The MMU receives temperature information for one or more on-chip memory modules. as well as The MMU manages the individual memory blocks of the one or more memory dies based on the on-chip memory temperature information.

11. The method of claim 9, further comprising: The MMU stores memory management information.

12. The method of claim 9, further comprising: The MMU is used to read on-chip memory error information, system error information, and memory temperature for a given memory block access. The risk indicator is determined by the MMU based on the on-chip memory error information, system error information, error type and error location indicated by memory temperature for the access of the given memory block; as well as The MMU maps accumulated risk indicators to corresponding memory blocks.

13. The method of claim 12, further comprising: The MMU identifies individual memory blocks whose risk indicators are higher than a predetermined value and sets their blacklist indicators to a given state.

14. The method of claim 13, further comprising: The MMU receives an indication of a blacklisted memory block. The capacity register is updated based on the blacklisted memory blocks via the MMU; The effective block mapping is updated based on the blacklisted memory blocks through the MMU; as well as The page table is updated based on the blacklisted memory blocks via the MMU.

15. The method of claim 14, further comprising: When a memory block is blacklisted due to an uncorrectable system memory error, the MMU reports the uncorrectable system memory error to the host.

16. A system comprising: Host; Reliability, Availability, Serviceability (RAS), Non-volatile Memory (NVM); as well as System-in-Package (SIP), including; One or more memory dies, including; The memory array is arranged into multiple memory blocks; An electric fuse module is configured to store memory health status information of the one or more memory dies; and The D flag register is configured to store on-chip memory error information for the one or more memory dies; and Logic chips include; Operational logic; A memory controller is configured to communicatively couple the arithmetic logic to the one or more memory dies, wherein the memory controller includes an S-flag register configured to store system memory error information and a read address buffer configured to store memory read addresses; The RAS Memory Management Unit (MMU) is configured to communicatively couple the memory controller to a host, wherein the RAS MMU is configured to manage memory error detection, memory error prediction, and memory error handling based on the memory health status information, the on-chip memory error information, the system memory error information, and the memory read address; and A non-volatile memory interface is provided to communicatively couple the RAS MMU to the RAS non-volatile memory.

17. The system according to claim 16, wherein, The RAS NVM is configured to store memory management information.

18. The system according to claim 16, wherein: The one or more memory dies include a temperature sensor; The memory controller also includes a temperature register; and The RAS MMU is also configured to manage memory error detection, memory error prediction, and memory error handling based on temperature information from a temperature register of the memory controller or a temperature sensor of one or more memory dies.

19. The system according to claim 16, wherein, The RAS MMU is configured to manage memory error detection, memory error prediction, and memory error handling, including: When the corresponding risk indicator reaches a predetermined level, the memory blocks in one or more memory dies are blacklisted.

20. The system of claim 16, wherein the RAS MMU comprises: The error handling module is configured to detect and manage memory errors based on information from memory health status information, on-chip memory error information, system memory error information, and memory read addresses. The error prediction module is configured to predict memory errors based on temperature information from a temperature register of the memory controller or a temperature sensor of one or more memory dies. A capacity register is configured to store the total number of available memory blocks of the one or more memory dies; The block size register is configured to store the smallest possible error handling granularity; as well as The valid block mapping module is configured to store risk indicators as mappings to corresponding memory blocks in multiple memory blocks of the memory array.

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