White light interference 3D sensor system control circuit

Abstract

This invention discloses a control circuit for a white light interferometric 3D sensor system, relating to the field of 3D sensor technology. It includes a power module, an ARM main control module, an input / output module, a network module, a camera trigger module, a stepper motor drive module, a laser LD drive module, and a grating ruler encoder receiving module. This invention employs an Arm + 50nm grating ruler decoding + 2µm stepper motor control + laser LD drive + high-speed trigger camera control system. This circuit eliminates the need for a professional motion control card, ultra-high precision, high-cost motion platform, servo / linear motors, etc. Through a self-implemented motion control algorithm within the ARM processor, it only requires a conventional stepper motor and high-precision grating ruler feedback to achieve the requirement of rapid nanometer-level position triggering for image acquisition. This also achieves miniaturization, low cost, and high precision in circuit board installation, reducing the requirements for process assembly.

Description

Technical Field

[0001] This invention relates to the field of 3D sensor technology, specifically to a white light interferometry 3D sensor system control circuit. Background Technology

[0002] A white-light interferometer is an ultra-precise surface profile measurement instrument developed using the principle of optical interference. The illumination beam is split into two beams by a semi-reflective beam splitter, which are projected onto the sample surface and the reference mirror surface, respectively. The two beams reflected from the two surfaces are then combined into a single beam after passing through the beam splitter again, and the imaging system forms two superimposed images on the photosensitive surface of the CCD camera. Due to the interference of the two beams, alternating bright and dark interference fringes are observed on the photosensitive surface of the CCD camera. The brightness of the interference fringes depends on the optical path difference between the two beams. The relative height of the sample under test can be determined from the brightness and position of the white-light interference fringes. Because it uses the principle of white-light interference, it is unaffected by material / color or blind spots, achieving nanometer-level high-precision measurement.

[0003] Because white light interferometric 3D sensors need to achieve nanometer-level measurement accuracy (the product's defined accuracy is 0.1µm), the electronic control system has very high requirements. It needs to control the position accuracy of the motor movement at a speed of 0.1mm / s, trigger the camera to acquire signals at a frequency of less than 1ms, acquire high-resolution (50nm) grating ruler signals, control the constant current of the LED light source, and so on. At the same time, due to the requirements for product weight and size, there are also very high requirements for the miniaturization of the PCB circuit. Summary of the Invention

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a white light interferometry 3D sensor system control circuit, including a power supply module, an ARM main control module, an input / output module, a network module, a camera trigger module, a stepper motor drive module, a laser LD drive module, and a grating ruler encoder receiving module. The output terminals of the power supply module and the grating ruler encoder receiving module are respectively connected to the input terminal of the ARM main control module; the output terminal of the ARM main control module is respectively connected to the input terminals of the input / output module, the network module, the camera trigger module, the stepper motor drive module, and the laser LD drive module; the power supply module is externally connected to a power adapter; the input / output module is externally connected to an external signal receiver; the network module is externally connected to a computer; the camera trigger module is externally connected to a high-speed CMOS camera; the stepper motor drive module is externally connected to a motor driver and a motor; and the grating ruler encoder receiving module is externally connected to a grating ruler.

[0005] Preferably, the power module includes chip U1 (LDO power step-down chip), chip U2 (DC-DC power step-down chip), chip U3 (DC-DC power step-down chip), laser diodes LD1, LD2, LD3, LD4, and LD5, and button KEY1; one end of laser diode LD1 is connected to VCC5V via resistor R8, and the other end of laser diode LD1 is grounded; the 2-pin interface of chip U2 is connected in series with the 24V_IN terminal via Zener diode D1; the 1-pin interface of chip U2, capacitor C1, inductor L1, capacitor C11, bidirectional Zener diode D3, and the 2-pin interface of chip U2 are connected in series in sequence; the connection between capacitor C11 and bidirectional Zener diode D3 is grounded; an electrolytic capacitor C15 is connected in parallel outside capacitor C11, one end of electrolytic capacitor C15 is electrically connected between inductor L1 and capacitor C11, and one end of electrolytic capacitor C15 is externally connected to VCC5. At the CC5V terminal, the other end of the electrolytic capacitor C15 is electrically connected between capacitor C11 and the bidirectional Zener diode D3; the 7th interface of chip U2 is connected between inductor L1 and electrolytic capacitor C15 through resistor R1, and the 7th interface of chip U2 is electrically connected between electrolytic capacitor C15 and bidirectional Zener diode D3 through resistors R6 and R5; resistors R6 and R5 are connected in series; the 8th interface of chip U2 is electrically connected between resistor R5 and bidirectional Zener diode D3 through capacitor C12. A capacitor C8 and a resistor R4 are connected in parallel outside the capacitor C12; the capacitor C8 and the resistor R4 are connected in series; the capacitor C8 is electrically connected between the chip U2 and the capacitor C12; the resistor R4 is electrically connected between the capacitor C12 and the bidirectional Zener diode D3; a Zener diode D2 is electrically connected between the resistor R5 and the capacitor C12; the Zener diode D2 is electrically connected between the capacitor C1 and the inductor L1; the I / O interface of the chip U2 is electrically connected between the capacitor C1 and the Zener diode D2.

[0006] The 9th interface of chip U2 is electrically connected between resistor R4 and bidirectional Zener diode D3; the 11th interface of chip U2 is electrically connected between the 9th interface of chip U2 and bidirectional Zener diode D3; the 5th interface of chip U2 is electrically connected between the 11th interface of chip U2 and bidirectional Zener diode D3 through resistor R3; the 4th interface of chip U2 is electrically connected between resistor R3 and bidirectional Zener diode D3 through capacitor C14.

[0007] The 3rd interface of chip U2 is electrically connected between capacitor C14 and bidirectional Zener diode D3 through resistor R7. The 2nd interface of chip U2 is electrically connected between resistor R2 and resistor R7. The 2nd interface of chip U2 is electrically connected between resistor R7 and bidirectional Zener diode D3 through capacitor C13. The 2nd interface of chip U2 is electrically connected between capacitor C13 and bidirectional Zener diode D3 through electrolytic capacitor C10. The connection point of electrolytic capacitor C10 and chip U2 is externally connected to a 24V-1 terminal.

[0008] One end of the laser diode LD2 is connected to an external 12V terminal via resistor R16, and the other end of the laser diode LD2 is grounded; the 2nd interface of the chip U3 is connected in series with the 24V_IN terminal via Zener diode D4; the 1st interface of the chip U3, capacitor C16, inductor L2, capacitor C19, bidirectional Zener diode D6, and the 2nd interface of the chip U3 are connected in series in sequence; the connection between capacitor C19 and bidirectional Zener diode D6 is grounded; an electrolytic capacitor C21 is connected in parallel outside capacitor C19, one end of electrolytic capacitor C21 is electrically connected between inductor L2 and capacitor C19, and one end of electrolytic capacitor C21 is connected to an external 12V terminal, and the other end of electrolytic capacitor C21 is electrically connected between capacitor C19 and bidirectional Zener diode D6;

[0009] The 7th interface of chip U3 is connected between inductor L2 and electrolytic capacitor C21 via resistor R9. The 7th interface of chip U3 is also electrically connected between electrolytic capacitor C21 and bidirectional Zener diode D6 via resistors R12 and R14; resistors R12 and R14 are connected in series. The 8th interface of chip U3 is connected between resistor R14 and bidirectional Zener diode D6 via capacitor C20. A capacitor C17 and resistor R13 are connected in parallel outside capacitor C20; capacitor C17 and resistor R13 are connected in series. Capacitor C17 is electrically connected between chip U3 and capacitor C20, and resistor R13 is electrically connected to capacitor C21. Between 0 and bidirectional Zener diode D6; Zener diode D5 is electrically connected between resistor R14 and capacitor C20, Zener diode D5 is electrically connected between capacitor C16 and inductor L2, and the 10 interface of chip U3 is electrically connected between capacitor C16 and Zener diode D5; the 9 interface of chip U3 is electrically connected between resistor R13 and bidirectional Zener diode D6, and the 11 interface of chip U3 is electrically connected between the 9 interface of chip U3 and bidirectional Zener diode D6; the 5 interface of chip U3 is electrically connected between the 11 interface of chip U3 and bidirectional Zener diode D6 through resistor R11; the chip U... Interface 4 of chip U1 is electrically connected between resistor R11 and bidirectional Zener diode D6 via capacitor C22; Interface 3 of chip U3 is electrically connected between capacitor C22 and bidirectional Zener diode D6 via resistor R15; Interface 2 of chip U3 is electrically connected between resistor R10 and resistor R15; Interface 2 of chip U3 is electrically connected between resistor R15 and bidirectional Zener diode D6 via capacitor C23; Interface 2 of chip U3 is electrically connected between capacitor C23 and bidirectional Zener diode D6 via electrolytic capacitor C18; the connection point of electrolytic capacitor C18 with chip U3 is externally connected to a 24V-2 terminal; Interface 3 of chip U1... The interface is externally connected to the VCC 5V terminal; the five components of chip U1—interface 2, ferrite bead FB1, capacitor C3, capacitor C2, and interface 3—are connected in series in sequence; the connection lines of capacitors C3 and C2 are grounded; the connection line of ferrite bead FB1 and capacitor C3 is externally connected to the AVDD 33 terminal; a capacitor C7 is connected in parallel outside capacitor C3; one end of capacitor C7 is electrically connected between ferrite bead FB1 and the AVDD 33 terminal; the other end of capacitor C7 is electrically connected between capacitor C3 and capacitor C2; a capacitor C9 is connected in parallel outside capacitor C2; interface 1 of chip U1 is electrically connected between capacitor C7 and capacitor C9.

[0010] The connection line between capacitors C3 and C2 is grounded. Capacitors C5, C6, and electrolytic capacitor C4 are connected in parallel between capacitors C9 and C7. One end of capacitor C5 is electrically connected between one end of electrolytic capacitor C4 and one end of capacitor C6. One end of capacitor C5 is externally connected to the VDD33 terminal. The other end of capacitor C5 is electrically connected between the other end of electrolytic capacitor C4 and the other end of capacitor C6. One end of electrolytic capacitor C4 is electrically connected between interface 2 of chip U1 and capacitor C5. The other end of electrolytic capacitor C4 is electrically connected between interface 1 of chip U1 and capacitor C5. One end of capacitor C6 is electrically connected between capacitor C5 and ferrite bead FB1. The other end of capacitor C6 is electrically connected between capacitor C7 and capacitor C5.

[0011] One end of the button KEY1 is connected to the VDD33 terminal through resistor R17, and the other end of the button KEY1 is grounded. The laser diode LD3 is connected to the VDD33 terminal through resistor R18; the laser diode LD4 is connected to the VDD33 terminal through resistor R19; and the laser diode LD5 is connected to the VDD33 terminal through resistor R21.

[0012] Preferably, the ARM main control module includes chip U13 (main control chip ARM), chip U12 (reset IC chip), crystal oscillator Y2, chip U14 (surface-mount TVS diode), chip U19 (memory chip SDRAM), and chip U20 (flash chip); the 31 interface of chip U13 is connected to the 2 interface of chip U12, the 1 interface of chip U12 is grounded, the 3 interface of chip U12 is electrically connected to capacitor C40, one end of capacitor C40 is grounded, and the connection between capacitor C40 and the 3 interface of chip U12 is grounded; the 29 interface of chip U13, the 3 interface of crystal oscillator Y2, the 1 interface of crystal oscillator Y2, and the 30 interface of chip U13 are connected in series; the 4 interface of crystal oscillator Y2 is electrically connected to the 1 interface of crystal oscillator Y2 through capacitor C50, and the connection between the 4 interface of crystal oscillator Y2 and capacitor C50 is grounded; the 21 interface of crystal oscillator Y2 is connected to the 11 interface of crystal oscillator Y2. The port is electrically connected to the 3rd interface of crystal oscillator Y2 via capacitor C51. The connection between the 2nd interface of crystal oscillator Y2 and capacitor C51 is grounded. Chip U14 has an external USB interface. Chip U13 includes an FMC bus, and chip U13 is interconnected with chip U19 via the FMC bus. The 4th interface of chip U20 is grounded. The 8th interface of chip U20 is externally connected to VDD33, and there is an electrical connection between the 8th interface of chip U20 and VDD33. Capacitor C74, one end of which is grounded; interface 1 of chip U20 is connected to interface 164 of chip U13, interface 2 of chip U20 is connected to interface 27 of chip U13, interface 3 of chip U20 is connected to interface 25 of chip U13, interface 5 of chip U20 is connected to interface 26 of chip U13, interface 6 of chip U20 is connected to interface 58 of chip U13, and interface 7 of chip U20 is connected to interface 24 of chip U13.

[0013] The 166 interface of the chip U13, resistors R62, R63, R64, and the 48 interface of the chip U13 are connected in series. The connection between resistors R63 and R64 is grounded. The connection between resistors R62 and R63 is connected to interface 2 of socket P6 via BOOT. Interface 1 of socket P6 is externally connected to VDD33.

[0014] The 6-pin connector of chip U13 is externally connected to the VDD33 terminal. A capacitor C41 is externally connected to the connection between the 6-pin connector of chip U13 and the VDD33 terminal, and capacitor C41 is grounded. The 38-pin connector of chip U13 is externally connected to the VDDA terminal through resistor R65. Capacitors C43 and C44 are externally connected to the connection between the 38-pin connector of chip U13 and resistor R65. One end of each of capacitors C43 and C44 is grounded. The 81-pin connector of chip U13, capacitors C42 and C45, and the 125-pin connector of chip U13 are connected in series. The C45 connection is grounded; the 39 interface of the chip U13 is externally connected to the VDD33 terminal through resistor R66; the connection between the 39 interface of the chip U13 and resistor R66 is externally connected to capacitors C46 and C47; one end of each of capacitors C46 and C47 is grounded; the 37 interface of the chip U13, resistor R67, and the 171 interface of the chip U13 are connected in series; the connection between the 37 interface of the chip U13 and resistor R67 is grounded; the connection between resistor R67 and the 171 interface of the chip U13 is externally connected to the VDD33 terminal through resistor R68.

[0015] Preferably, the camera trigger module includes a socket P1, with its interfaces 1 and 3 grounded; the socket P1 includes six components connected in series: interface 2, resistor R35, interface 3 of transistor Q4, interface 1 of transistor Q4, resistor R37, and CAM_Trigger terminal; the CAM_Trigger terminal is connected to interface 101 of chip U13; interface 4 of socket P1 is electrically connected between resistor R35 and interface 3 of transistor Q4; interface 2 of transistor Q4 is grounded; and resistor R38 is electrically connected between interface 1 and interface 2 of transistor Q4.

[0016] The socket P1 has five terminals connected in series: terminal 5, resistor R34, terminals 1 and 3 of transistor Q3, and the CAM_Feedback terminal. The CAM_Feedback terminal is connected to the 100 terminal of chip U13. An external resistor R31 is connected to the connection line between terminals 3 of transistor Q3 and the CAM_Feedback terminal. One end of resistor R31 is connected to the VDD33 terminal. Terminal 2 of transistor Q3 is grounded. A resistor R38 is electrically connected between terminals 1 and 2 of transistor Q3. An external resistor R32 is connected to the connection line between terminals 5 of socket P1 and resistor R34. One end of resistor R32 is connected to the 12V terminal. Terminal 6 of socket P1 is connected to the CAM_IO terminal via resistor R33. The CAM_IO terminal is connected to the 99 terminal of chip U13. Preferably, the stepper motor drive module includes chip U15 (optical isolation chip), chip U16 (optical isolation chip), chip U17 (single-ended to differential signal chip), and chip U23 (optical isolation chip).

[0017] Interface 1 of chip U15 is connected in series with VDD33 via resistor R73, and interface 3 of chip U15 is connected in series with VDD33 via resistor R72. Interface 2 of chip U15 is connected to MCU_AWO_O, MCU_AWO_O is connected to interface 134 of chip U13, interface 4 of U15 is connected to MCU_CS_O, and MCU_CS_O is connected to interface 132 of chip U13. Interfaces 5 and 7 of chip U15 are grounded. Interface 6 of chip U15 is connected to MOTOR_CS- via fuse F6, and MOTOR_CS- is connected to interface 8 of socket P8. Interface 8 of chip U15 is connected to MOTOR_AWO- via fuse F5, and MOTOR_AWO- is connected to interface 6 of socket P8.

[0018] Both interfaces 5 and 7 of chip U16 are grounded. The following four components of chip U16 are connected in series: interface 6, MCU_ALM_I terminal, resistor R74, and VDD33 terminal. Similarly, the following four components of chip U16 are connected in series: interface 8, MCU_TIM_I terminal, resistor R75, and VDD33 terminal. The MCU_ALM_I terminal is connected to interface 128 of chip U13, and the MCU_TIM_I terminal is connected to interface 129 of chip U13. Interface 1 of chip U16 is connected to the VCC5V terminal via resistor R76, and interface 3 of chip U16 is connected to the VCC5V terminal via resistor R77. Interface 2 of chip U16 is externally connected to the MOTOR_TIM+ terminal, which is connected to interface 11 of socket P8. Interface 4 of chip U16 is externally connected to the MOTOR_ALM+ terminal, which is connected to interface 9 of socket P8.

[0019] The 8th interface of chip U17 is grounded; the 4th interface of chip U17 is connected to the VCC 5V terminal; the 16th interface of chip U17 is also connected to the VCC 5V terminal; the 1st interface of U17 is connected to the MCU_Dir_O terminal, which is connected to the 131st interface of chip U13; the 1st interface of U17 is also connected to the MCU_Pulse_O terminal, which is connected to the 133rd interface of chip U13; the 2nd interface of chip U17 is connected to the MOTOR_Dir+ terminal. The MOTOR_Dir+ terminal is connected to interface 3 of socket P8; interface 3 of chip U17 is externally connected to the MOTOR_Dir- terminal, which is connected to interface 4 of socket P8; interface 14 of U17 is externally connected to the MOTOR_Pulse+ terminal, which is connected to interface 1 of socket P8; interface 13 of U17 is externally connected to the MOTOR_Pulse- terminal, which is connected to interface 2 of socket P8.

[0020] Both interfaces 5 and 7 of chip U23 are grounded; the 6th interface, MCU_END_I terminal, resistor R20, and VDD33 terminal of chip U23 are connected in series; the 8th interface, MCU_ZERO_I terminal, resistor R105, and VDD33 terminal of chip U23 are also connected in series; the MCU_END_I terminal is connected to interface 118 of chip U13; the MCU_ZERO_I terminal is connected to interface 117 of chip U13; interface 2 of chip U23 is connected to interface 3 of socket P11 through the MOTOR_ZERO terminal; interface 4 of chip U23 is connected to interface 4 of socket P11 through the MOTOR_END terminal; the MOTOR_ZERO terminal is connected to the interface of chip U13; the MOTOR... The _END terminal is connected to the interface of chip U13; the 1st interface of chip U23, resistor R106, and the 2nd interface of socket P11 are connected in series. Resistors R108 and R109 are externally connected to the connection between resistor R106 and the 2nd interface of socket P11. Resistor R108 is externally connected to the VCC 5V terminal, and resistor R109 is externally connected to the 24V _IN terminal. The 3rd interface of chip U23 is electrically connected between resistors R106 and R108 through resistor R107. The 1st interface of socket P11 is grounded, and the 1st interface of socket P11 is electrically connected between resistor R109 and the 2nd interface of socket P11 through capacitor C92. The 5th and 7th interfaces of socket P8 are externally connected to the VCC 5V terminal. The 10th and 12th interfaces of socket P8 are grounded.

[0021] Preferably, the grating ruler encoder receiving module includes a chip U18 (differential to single-ended chip), with interface 8 of the chip U18 grounded, interface 4 of the chip U18 externally connected to a VCC 5V terminal, interface 12 of the chip U18 grounded, interface 16 of the chip U18 externally connected to a VCC 5V terminal, and a capacitor C94 directly connected to both interface 16 and the VCC 5V terminal of the chip U18, with one end of the capacitor C94 grounded.

[0022] The following four components of chip U18 are connected in series: interface 3, MCU_EA terminal, resistor R80, and VDD33 terminal; interface 5, MCU_EB terminal, resistor R79, and VDD33 terminal; interface 11, MCU_EZ terminal, resistor R79, and VDD33 terminal; the MCU_EA terminal is connected to interface 87 of chip U13; the MCU_EB terminal is connected to interface 88 of chip U13; the MCU_EZ terminal is connected to interface 89 of chip U13; interface 1 of chip U18 is externally connected to the Extern_EAz- terminal; interface 2 of chip U18 is externally connected to the Extern_EAz+ terminal; interface 6 of chip U18 is externally connected to the Extern_EBz+ terminal; interface 7 of chip U18 is externally connected to the Extern_EBz- terminal; interface 10 of chip U18 is externally connected to the Extern_EZz+ terminal; the following four components of chip U18 are connected in series: interface 3, MCU_EB terminal, resistor R79, and VDD33 terminal; the following four components of chip U18 are connected in series: interface 3, MCU_EB terminal, resistor R79, and VDD33 terminal; the MCU_EA terminal is connected to interface 87 of chip U13; the MCU_EB terminal is connected to interface 88 of chip U13; the MCU_EZ terminal is externally connected to interface 89 of chip U13; the MCU_EA terminal is externally connected to interface 2 of chip U18; the MCU_EB terminal is externally connected to interface 6 of chip U18; the MCU_EB_EZ terminal is externally connected to interface 7 of chip U18; the MCU_EB_EZ terminal is externally connected to interface 89 of chip U18; the MCU_EB_EZ terminal is externally connected to interface 89 of chip U18; the MCU_EB_EZ terminal is externally connected to interface 9. The external Extern_EZz- terminal is connected to the interface; the Extern_EAz+, Extern_EAz-, Extern_EBz+, Extern_EBz-, Extern_EZz+, and Extern_EZz- terminals are all connected to socket P10; the 8th terminal of socket P10 is grounded; the 7th terminal of socket P10 is connected to VCC5V; the 1st terminal, Extern_EAz+ terminal, resistor R81, Extern_EAz- terminal, and the 2nd terminal of socket P10 are connected in series; the 3rd terminal, Extern_EBz+ terminal, resistor R110, Extern_EBz- terminal, and the 4th terminal of socket P10 are connected in series; the 5th terminal, Extern_EZz+ terminal, resistor R111, Extern_EZz- terminal, and the 6th terminal of socket P10 are connected in series.

[0023] Preferably, the laser LD driving module includes chip U6 (LDO power step-down chip), chip U7 (constant current drive chip), chip U8 (LDO power step-down chip), and socket P2; the 1st interface, LD_SCL terminal, and 9th interface of the socket P2 are connected in series; the 2nd interface, LD_SDA terminal, and 8th interface of the chip U7 are connected in series; the 5th interface of the socket P2, capacitor C28, chip, and 5th interface of U7 are connected in series; the 4th interface of the chip U7 is electrically connected between the 5th interface of the socket P2 and capacitor C28; an external resistor R49 is connected between the LD_SDA terminal and the 8th interface of the chip U7; an external resistor R50 is connected between the LD_SDA terminal and the 8th interface of the chip U7; and resistors R49, R50, and the 1st interface of the chip U7 are all connected to the VDD33_LDREF terminal.

[0024] The socket P2's 4th interface, LD_EN terminal, and chip U6's 1st interface are connected in series. The socket P2's 6th interface is connected to chip U6's 2nd interface, and the connection wire between the socket P2's 6th interface and chip U6's 2nd interface is externally connected to VCC2_5V. The chip U6's 3rd interface is electrically connected between the socket P2's 5th interface and capacitor C28, and the chip U6's 3rd interface is grounded. The chip U6's 4th interface, laser diode LD6's 1st interface, laser diode LD6's 3rd interface, resistor RS1, resistor RS2, and socket P2's 5th interface are connected in series. The laser diode LD... A resistor R48 is connected in parallel between interface 1 of chip U6 and interface 2 of laser diode LD6. The connection between resistor RS2 and interface 5 of socket P2 is grounded. Interface 5 of chip U6, resistor R51, and interface 3 of chip U7 are connected in series. The connection between interface 5 of chip U6 and resistor R51 is externally connected to resistors R52 and R53. One end of resistor R52 is electrically connected between interface 3 of laser diode LD6 and resistor RS1. Resistor R53 is externally connected to the VDD33_LDREF terminal. A resistor R54 is connected in parallel to the outside of resistor R53. The connection between resistors R51 and R52 is externally connected to capacitor C. 30. One end of capacitor C30 is electrically connected between resistor RS2 and socket P2's 5th interface; the connection between resistor R51 and chip U7's 3rd interface is externally connected to capacitor C29; one end of capacitor C29 is electrically connected between capacitor C30 and socket P2's 5th interface; the 2nd interface of chip U7 is electrically connected between capacitor C29 and socket P2's 5th interface; the 10th interface of chip U7 is electrically connected between chip U7's 2nd interface and socket P2's 5th interface; the 6th interface of chip U7 is electrically connected between chip U7's 10th interface and socket P2's 5th interface; the 3rd interface of chip U8, capacitor C33, capacitor C31, and chip... For interface 2 of chip U8, the aforementioned four items are connected in series. The connection between interface 3 of chip U8 and capacitor C33 is externally connected to the VCC2_5V terminal. The connection between capacitor C31 and interface 2 of chip U8 is externally connected to the VDD33_LDREF terminal. The connection between capacitor C33 and capacitor C31 is grounded. Interface 1 of chip U8 is electrically connected between capacitor C33 and capacitor C31. A capacitor C32 is connected in parallel outside capacitor C31. The LD_SDA terminal is connected to interface 46 of chip U13. The LD_SCL terminal is connected to interface 45 of chip U13. The LD_EN terminal is connected to interface 44 of chip U13.

[0025] Preferably, the input / output module includes an input signal circuit, an output signal circuit, and a connector CN1.

[0026] Preferably, the input signal circuit includes chip U4 (optical isolation chip); interfaces 5 and 7 of chip U4 are grounded, and interfaces 2 and 4 of chip U4 are grounded; interface 6 of chip U4 is connected to the TGR-DSI1 terminal, and interface 8 of chip U4 is connected to the TGR-DSI2 terminal; an external resistor R26 is connected between interface 6 of U4 and the TGR-DSI1 terminal; an external resistor R25 is connected between interface 8 of chip U4 and the TGR-DSI2 terminal; Resistors R26 and R25 are both connected to the VDD33 terminal; the four terminals of chip U4 (interface 1), transistor Q1 (interface 3), transistor Q1 (interface 2), and DSI2 are connected in series. A resistor R27 is connected in parallel between the terminals of transistor Q1 and Q1 (interface 3). A capacitor C24 is connected between the terminals of chip U4 (interface 1) and chip U4 (interface 2). One end of capacitor C24 is electrically connected between the terminals of chip U4 (interface 1) and transistor Q1 (interface 3), and a resistor R27 is connected in parallel to the outside of capacitor C24. There is a resistor R28 and a diode D7, and the resistor R28 and the diode D7 are connected in parallel; the 3-pin terminal of the chip U4, the 3-pin terminal of the transistor Q2, the 2-pin terminal of the transistor Q2, and the DSI1 terminal are connected in series. A resistor R29 is connected in parallel between the 1-pin terminal and the 3-pin terminal of the transistor Q2. A capacitor C25 is connected between the 3-pin terminal and the 4-pin terminal of the chip U4. One end of the capacitor C25 is electrically connected between the 3-pin terminal of the chip U4 and the 3-pin terminal of the transistor Q2. A resistor R30 and a diode D8 are connected in parallel on the outside of C25; the TGR-DSI1 terminal is connected to the 167 interface of chip U13, and the TGR-DSI2 terminal is connected to the 168 interface of chip U13; the DSI1 terminal is connected to the 7 interface of connector CN1, and the DSI2 terminal is connected to the 6 interface of connector CN1; the 1 and 8 interfaces of connector CN1 are grounded respectively, and the 2 interface of connector CN1 is connected to the 24V_IN terminal.

[0027] Preferably, the output signal circuit includes chip U5 (optical isolation chip). Interfaces 2, 4, and 6 of chip U5 are all grounded. Interface 1 of chip U5 is connected to the TGR-DSO1 terminal via resistor R42. Interface 3 of chip U5 is connected to the TGR-DSO2 terminal via resistor R43. Interface 5 of chip U5 is connected to the TGR-DSO3 terminal via resistor R44. The connection between interface 1 of chip U5 and resistor R42 is externally connected to resistor R47. The connection between interface 3 of chip U5 and resistor R43 is externally connected to resistor R46. The connection between interface 5 of chip U5 and resistor R44 is externally connected to resistor R45. Resistors R45, R46, and R47 are all grounded.

[0028] The following five components are connected in series: chip U5 (interface 16), transistor Q5 (interface 1), transistor Q5 (interface 2), fuse F2, and DSO1; chip U5 (interface 15) is connected to transistor Q5 (interface 3); chip U5 (interface 14), transistor Q6 (interface 1), transistor Q6 (interface 2), fuse F3, and DSO2; chip U5 (interface 13) is connected to transistor Q6 (interface 3); chip U5 (interface 12), transistor Q7 (interface 1), transistor Q7 (interface 2), fuse F4, and DSO3; chip U5 (interface 11) is connected to transistor Q7 (interface 3); and the three terminals of transistors Q5, Q6, and Q7 are all grounded.

[0029] The connection between transistor Q7's pin 2 and fuse F4 is externally connected to resistor R41. Resistor R41 is connected to VCC 5V via diode D9. The connection between transistor Q6's pin 2 and fuse F3 is externally connected to resistor R40. Resistor R40 is electrically connected between resistor R41 and diode D9. The connection between transistor Q5's pin 2 and fuse F2 is externally connected to resistor R39. Resistor R39 is electrically connected between resistor R40 and diode D9. The connection between resistor R39 and diode D9 is externally connected to capacitor C27, which is grounded. The connection between diode D9 and VCC 5V is externally connected to capacitor C26, which is grounded. Fuse F1 is connected between capacitor C26 and capacitor C27. The connection between resistor R39 and diode D9 is externally connected to VCC_PULL.

[0030] The TGR-DSO1 terminal is connected to interface 174 of chip U13, the TGR-DSO2 terminal is connected to interface 175 of chip U13, the TGR-DSO3 terminal is connected to interface 176 of chip U13, the DSO1 terminal is connected to interface 3 of connector CN1, the DSO2 terminal is connected to interface 4 of connector CN1, and the DSO3 terminal is connected to interface 5 of connector CN1.

[0031] Compared with the prior art, the beneficial effects achieved by this invention are as follows: This invention, by setting up a power supply module, an ARM main control module, an input / output module, a network module, a camera trigger module, a stepper motor drive module, a laser LD drive module, and a grating ruler encoder receiving module, adopts an Arm STM32F767 + 50nm grating ruler decoding + 2µm stepper motor control + laser LD drive + high-speed trigger camera control system. This circuit does not require a professional motion control card, ultra-high precision, high-cost motion platform, servo / linear motors, etc. Through the motion control algorithm implemented in the ARM, only conventional stepper motors and high-precision grating ruler feedback are needed to achieve the requirement of rapid triggering and image acquisition at the nanometer level (100nm). It also takes into account the miniaturization, low cost, and high precision of the circuit board installation, and reduces the requirements for process assembly. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the overall circuit of the present invention. Figure 2 This is a circuit connection diagram of a part of the ARM main control module of the present invention; Figure 3 This is a circuit connection diagram of another part of the ARM main control module of the present invention; Figure 4 This is a circuit connection diagram of the power module of the present invention; Figure 5 This is a circuit connection diagram of the stepper motor drive module of the present invention; Figure 6 This is a circuit connection diagram of the receiving module of the grating ruler encoder of the present invention; Figure 7 This is a circuit connection diagram of the camera trigger module of the present invention; Figure 8 This is a circuit connection diagram of the laser LD driving module of the present invention; Figure 9 This is a schematic diagram of the circuit connection of the input signal circuit of the present invention; Figure 10 This is a circuit connection diagram of the output signal circuit of the present invention; Figure 11 This is a circuit connection diagram of the connector CN1 of the present invention; Figure 12 This is a circuit connection diagram of the network module of the present invention; Figure 13 This is a schematic diagram of the power supply connection of each module of the present invention; Figure 14 This is a schematic diagram showing the connections of various devices in the ARM main control module of this invention; Figure 15 This is a schematic diagram of the communication timing between the ARM and SDRAM of this invention; Figure 16 This is a schematic diagram of the communication timing between the ARM and Flash memory in this invention; Figure 17 This is a schematic diagram showing the working relationship between the stepper motor control module and the grating ruler encoder receiving module of the present invention; Figure 18 This is a schematic diagram of the pulse and motor rotation of the present invention; Figure 19 This is a schematic diagram showing the connection between the network module of this invention and the ARM and external components. Detailed Implementation

[0033] Please see Figures 1-19 This invention provides a technical solution: a white light interferometry 3D sensor system control circuit, including a power supply module, an ARM main control module, an input / output module, a network module, a camera trigger module, a stepper motor drive module, a laser LD drive module, and a grating ruler encoder receiving module. The output terminals of the power supply module and the grating ruler encoder receiving module are respectively connected to the input terminal of the ARM main control module; the output terminal of the ARM main control module is respectively connected to the input terminals of the input / output module, the network module, the camera trigger module, the stepper motor drive module, and the laser LD drive module; the power supply module is externally connected to a power adapter; the input / output module is externally connected to an external signal receiver; the network module is externally connected to a computer; the camera trigger module is externally connected to a high-speed CMOS camera; the stepper motor drive module is externally connected to a motor driver and a motor; and the grating ruler encoder is externally connected to a laser LD drive module. The encoder receiving module is connected to an external grating ruler. This control circuit is a white light interferometric 3D sensor main control board, which mainly completes the collection of external signals / communication data, controls the motor movement according to instructions, receives the counting information input by the external encoder grating ruler, and triggers the CMOS camera to acquire images at equal intervals. After the circuit starts working, the PC is configured with working parameters via the network: trigger mode, LED brightness, camera exposure, motor movement parameters, etc. The network module monitors the network trigger signals sent by the PC, and the input / output module monitors the hardware trigger signals sent by external PLCs, etc. As long as one is active, the ARM controls the motor to move, and at the same time drives the grating ruler read head to move. Based on the count feedback from the grating ruler, the CMOS camera is triggered at equal intervals to acquire 2D images with interference fringes and send them to the PC, where the 3D image is reconstructed.

[0034] like Figure 4 As shown, the power module includes chip U1 (LDO power step-down chip), chip U2 (DC-DC power step-down chip), chip U3 (DC-DC power step-down chip), laser diodes LD1, LD2, LD3, LD4, and LD5, and button KEY1; one end of laser diode LD1 is connected to the VCC 5V terminal via resistor R8, and the other end of laser diode LD1 is grounded; the 2 interface of chip U2 is connected to the 24V_IN terminal via Zener diode D1. The following six components are connected in series: interface 1 of chip U2, capacitor C1, inductor L1, capacitor C11, bidirectional Zener diode D3, and interface 2 of chip U2. The connection between capacitor C11 and bidirectional Zener diode D3 is grounded. An electrolytic capacitor C15 is connected in parallel to capacitor C11. One end of electrolytic capacitor C15 is electrically connected between inductor L1 and capacitor C11, and one end of electrolytic capacitor C15 is externally connected to VCC 5V. The other end of electrolytic capacitor C15 is electrically connected between capacitor C11 and bidirectional Zener diode D3.

[0035] The 7th interface of chip U2 is connected between inductor L1 and electrolytic capacitor C15 through resistor R1. The 7th interface of chip U2 is electrically connected between electrolytic capacitor C15 and bidirectional Zener diode D3 through resistors R6 and R5; resistors R6 and R5 are connected in series. The 8th interface of chip U2 is electrically connected between resistor R5 and bidirectional Zener diode D3 through capacitor C12. A capacitor C8 and resistor R4 are connected in parallel outside capacitor C12; capacitor C8 and resistor R4 are connected in series. Capacitor C8 is electrically connected between chip U2 and capacitor C12. Resistor R4 is electrically connected between capacitor C12 and bidirectional Zener diode D3. Zener diode D2 is electrically connected between resistor R5 and capacitor C12. Zener diode D2 is electrically connected between capacitor C1 and inductor L1. The 10th interface of chip U2 is electrically connected between capacitor C1 and Zener diode D2.

[0036] The 9th interface of chip U2 is electrically connected between resistor R4 and bidirectional Zener diode D3; the 11th interface of chip U2 is electrically connected between the 9th interface of chip U2 and bidirectional Zener diode D3; the 5th interface of chip U2 is electrically connected between the 11th interface of chip U2 and bidirectional Zener diode D3 through resistor R3; the 4th interface of chip U2 is electrically connected between resistor R3 and bidirectional Zener diode D3 through capacitor C14.

[0037] The 3rd interface of chip U2 is electrically connected between capacitor C14 and bidirectional Zener diode D3 through resistor R7. The 2nd interface of chip U2 is electrically connected between resistor R2 and resistor R7. The 2nd interface of chip U2 is electrically connected between resistor R7 and bidirectional Zener diode D3 through capacitor C13. The 2nd interface of chip U2 is electrically connected between capacitor C13 and bidirectional Zener diode D3 through electrolytic capacitor C10. The connection point of electrolytic capacitor C10 and chip U2 is externally connected to a 24V-1 terminal.

[0038] One end of the laser diode LD2 is connected to an external 12V terminal via resistor R16, and the other end of the laser diode LD2 is grounded; the 2nd interface of the chip U3 is connected in series with the 24V_IN terminal via Zener diode D4; the 1st interface of the chip U3, capacitor C16, inductor L2, capacitor C19, bidirectional Zener diode D6, and the 2nd interface of the chip U3 are connected in series in sequence; the connection between capacitor C19 and bidirectional Zener diode D6 is grounded; an electrolytic capacitor C21 is connected in parallel outside capacitor C19, one end of electrolytic capacitor C21 is electrically connected between inductor L2 and capacitor C19, and one end of electrolytic capacitor C21 is connected to an external 12V terminal, and the other end of electrolytic capacitor C21 is electrically connected between capacitor C19 and bidirectional Zener diode D6;

[0039] The 7th interface of chip U3 is connected between inductor L2 and electrolytic capacitor C21 via resistor R9. The 7th interface of chip U3 is also electrically connected between electrolytic capacitor C21 and bidirectional Zener diode D6 via resistors R12 and R14; resistors R12 and R14 are connected in series. The 8th interface of chip U3 is connected between resistor R14 and bidirectional Zener diode D6 via capacitor C20. A capacitor C17 and resistor R13 are connected in parallel outside capacitor C20; capacitor C17 and resistor R13 are connected in series. Capacitor C17 is electrically connected between chip U3 and capacitor C20, and resistor R13 is electrically connected to capacitor C21. Between 0 and bidirectional Zener diode D6; Zener diode D5 is electrically connected between resistor R14 and capacitor C20, Zener diode D5 is electrically connected between capacitor C16 and inductor L2, and the 10 interface of chip U3 is electrically connected between capacitor C16 and Zener diode D5; the 9 interface of chip U3 is electrically connected between resistor R13 and bidirectional Zener diode D6, and the 11 interface of chip U3 is electrically connected between the 9 interface of chip U3 and bidirectional Zener diode D6; the 5 interface of chip U3 is electrically connected between the 11 interface of chip U3 and bidirectional Zener diode D6 through resistor R11; the chip U... Interface 4 of chip U1 is electrically connected between resistor R11 and bidirectional Zener diode D6 via capacitor C22; Interface 3 of chip U3 is electrically connected between capacitor C22 and bidirectional Zener diode D6 via resistor R15; Interface 2 of chip U3 is electrically connected between resistor R10 and resistor R15; Interface 2 of chip U3 is electrically connected between resistor R15 and bidirectional Zener diode D6 via capacitor C23; Interface 2 of chip U3 is electrically connected between capacitor C23 and bidirectional Zener diode D6 via electrolytic capacitor C18; the connection point of electrolytic capacitor C18 with chip U3 is externally connected to a 24V-2 terminal; Interface 3 of chip U1... The interface is externally connected to the VCC 5V terminal; the five components of chip U1—interface 2, ferrite bead FB1, capacitor C3, capacitor C2, and interface 3—are connected in series in sequence; the connection lines of capacitors C3 and C2 are grounded; the connection line of ferrite bead FB1 and capacitor C3 is externally connected to the AVDD 33 terminal; a capacitor C7 is connected in parallel outside capacitor C3; one end of capacitor C7 is electrically connected between ferrite bead FB1 and the AVDD 33 terminal; the other end of capacitor C7 is electrically connected between capacitor C3 and capacitor C2; a capacitor C9 is connected in parallel outside capacitor C2; interface 1 of chip U1 is electrically connected between capacitor C7 and capacitor C9.

[0040] The connection line between capacitors C3 and C2 is grounded. Capacitors C5, C6, and electrolytic capacitor C4 are connected in parallel between capacitors C9 and C7. One end of capacitor C5 is electrically connected between one end of electrolytic capacitor C4 and one end of capacitor C6. One end of capacitor C5 is externally connected to the VDD33 terminal. The other end of capacitor C5 is electrically connected between the other end of electrolytic capacitor C4 and the other end of capacitor C6. One end of electrolytic capacitor C4 is electrically connected between interface 2 of chip U1 and capacitor C5. The other end of electrolytic capacitor C4 is electrically connected between interface 1 of chip U1 and capacitor C5. One end of capacitor C6 is electrically connected between capacitor C5 and ferrite bead FB1. The other end of capacitor C6 is electrically connected between capacitor C7 and capacitor C5.

[0041] One end of button KEY1 is connected to VDD33 via resistor R17, and the other end of button KEY1 is grounded. Laser diode LD3 is connected to VDD33 via resistor R18; laser diode LD4 is connected to VDD33 via resistor R19; laser diode LD5 is connected to VDD33 via resistor R21. Figure 13 The power supply connections for each module are as follows: 24V is input from the outside and needs to be stepped down to 5V and 12V. Considering the large voltage difference, in order to improve power efficiency and reduce heat generation, two DC-DC step-down power management chips are selected as the first-level power management. The 24V power supply is also output to the motor driver through the internal traces of the PCB. The DC-DC output above is 5V, and the downstream side needs to be powered by 3.3V. These are all low-power but power-sensitive components. The power supply ripple needs to be small and the accuracy needs to be high. Therefore, LDO step-down is used as the second-level power management.

[0042] At the same time, it directly outputs to the optocoupler of the motor that requires 5V, the single-ended to differential chip, and the differential to single-ended chip of the grating ruler;

[0043] The first LDO steps down to 3.3V to power the core circuit's main control chip, memory, flash memory, crystal oscillator circuit, and reset circuit. The second LDO then steps down to 3.3V to power the network module's network PHY chip. The third and fourth LDOs are used for laser LD driving; one powers the driver chip, and the other directly powers the LD, adjusting the voltage across the LD to achieve a constant current effect. The four LDOs are used for their respective module power management. Although all are 3.3V, their independent operation effectively reduces power crosstalk between different modules, ensuring stable signal transmission. The bottom DC-DC output of 12V is specifically used to power and trigger the external CMOS camera module. Since other components in the CMOS camera consume more power, a separate DC-DC power supply is used here.

[0044] like Figure 2 and Figure 3As shown, the ARM main control module includes chip U13 (main control chip ARM), chip U12 (reset IC chip), crystal oscillator Y2, chip U14 (surface-mount TVS diode), chip U19 (memory chip SDRAM), and chip U20 (flash chip); the 31 interface of chip U13 is connected to the 2 interface of chip U12, the 1 interface of chip U12 is grounded, the 3 interface of chip U12 is electrically connected to capacitor C40, one end of capacitor C40 is grounded, and the connection between capacitor C40 and the 3 interface of chip U12 is grounded; the 29 interface of chip U13, the 3 interface of crystal oscillator Y2, the 1 interface of crystal oscillator Y2, and the 30 interface of chip U13 are connected in series; the crystal oscillator Y2... The 4th interface of the body oscillator Y2 is electrically connected to the 1st interface of the crystal oscillator Y2 through capacitor C50. The connection between the 4th interface of the crystal oscillator Y2 and capacitor C50 is grounded. The 2nd interface of the crystal oscillator Y2 is electrically connected to the 3rd interface of the crystal oscillator Y2 through capacitor C51. The connection between the 2nd interface of the crystal oscillator Y2 and capacitor C51 is grounded. The chip U14 has an external USB interface. The chip U13 includes an FMC bus and is interconnected with the chip U19 through the FMC bus. The 4th interface of the chip U20 is grounded. The 8th interface of the chip U20 is externally connected to the VDD33 terminal. A capacitor C74 is electrically connected between the 8th interface of the chip U20 and the VDD33 terminal. One end of the capacitor C74 is grounded.

[0045] Interface 1 of chip U20 is connected to interface 164 of chip U13; interface 2 of chip U20 is connected to interface 27 of chip U13; interface 3 of chip U20 is connected to interface 25 of chip U13; interface 5 of chip U20 is connected to interface 26 of chip U13; interface 6 of chip U20 is connected to interface 58 of chip U13; and interface 7 of chip U20 is connected to interface 24 of chip U13. Interface 166 of chip U13, resistor R62, resistor R63, resistor R64, and interface 48 of chip U13 are connected in series. The connection of resistor R64 is grounded. The connections of resistors R62 and R63 are connected to interface 2 of socket P6 via BOOT. Interface 1 of socket P6 is externally connected to VDD33. Interface 6 of chip U13 is externally connected to VDD33. The connection between interface 6 of chip U13 and VDD33 is externally connected to capacitor C41, which is grounded. Interface 38 of chip U13 is externally connected to VDDA via resistor R65. The connection between interface 38 of chip U13 and resistor R65 is externally connected to capacitors C43 and C44. One end of each of capacitors C43 and C44 is grounded.

[0046] The 81 interface of the chip U13, capacitor C42, capacitor C45, and the 125 interface of the chip U13 are connected in series, and the connection of capacitor C42 and capacitor C45 is grounded.

[0047] The 39 interface of the chip U13 is externally connected to the VDD33 terminal through resistor R66; the connection between the 39 interface of the chip U13 and resistor R66 is externally connected to capacitors C46 and C47; one end of each of capacitors C46 and C47 is grounded; the 37 interface of the chip U13, resistor R67, and the 171 interface of the chip U13 are connected in series, the connection between the 37 interface of the chip U13 and resistor R67 is grounded, and the connection between resistor R67 and the 171 interface of the chip U13 is externally connected to the VDD33 terminal through resistor R68; the core control part consists of the main control chip ARM, the memory chip SDRAM, and the flash memory chip. The main control chip ARM is STMicroelectronics' STM32F767, which has a main frequency of 220MHz and can realize complex motion control algorithms and high-frequency coded signal capture. Considering that the motor motion control requires a large amount of memory, the built-in RAM of the armf767 is not enough. Therefore, an additional SDRAM memory chip was added to process the motion control algorithm. At the same time, a flash memory chip was added to be used when online upgrade programs need to be loaded and when some parameters need to be saved even when power is off.

[0048] The connections of the various components in this module are as follows: Figure 14 As shown, the main control chip is a 32-bit ARM with a main frequency of 220MHz. It has 512KB of SRAM and 2MB of Flash. However, because we need to control the S-curve acceleration and deceleration of the motor and process high-frequency grating signals, the amount of data is large. Therefore, 32MB of RAM and 32MB of flash memory were added. The RAM used is SDRAM, which balances capacity and communication speed. The ARM processor has an FMC bus, which is used here to interconnect with the SDRAM; -- [A11:A0] 12-bit address bus is used for addressing when the ARM accesses the SDRAM; -- [D15:D0] 16-bit data lines are used for the ARM to read or write data from the SDRAM; -- Clock lines are used to synchronize data writing, reading and writing one bit per clock cycle, provided by the ARM; -- U / LDQM control lines are used when only 8 bits of high / low bytes need to be written or read, masking unnecessary high and low bits; -- WE control lines are used for write enable, allowing data to be written to the SDRAM via the data lines only when enabled, preventing interference and erroneous operations; -- CAS and RAS are the SDRAM row precharge time and address strobe pulses; -- Enable line is used to enable the overall function; The communication timing between the ARM and SDRAM is as follows: Figure 15As shown; the flash memory selected is a 32MB QSPI interface Flash memory. It stores the boot program, application program, and some custom control parameters such as device name, serial number, movement speed, etc.; -- Clock line and read / write data line constitute the basic timing of SPI communication. The ARM and flash memory exchange data through the SPI protocol; -- SPI write enable mainly protects the data in the SPI from accidental writes during the startup and operation phases; -- SPI write protection mainly controls the write of data during the programming phase to prevent accidental writes.

[0049] The communication timing between ARM and Flash is as follows: Figure 16 as follows;

[0050] Reset Circuit: To ensure stable operation of the ARM processor upon power-up and avoid power spikes and external crosstalk causing unsuccessful resets in the RC circuit, we selected a dedicated reset chip. This chip has a clearly defined reset level detection threshold with an accuracy of ±2%, and allows for setting a reset delay, ensuring a successful reset each time the ARM processor powers on, thus enabling stable operation. The connection between the reset chip and the ARM reset pin is as follows: After power-up, when U12 detects the arrival of VDD33, its VOUT pin outputs a high level, resetting the ARM processor.

[0051] Crystal oscillator circuit: The crystal oscillator circuit mainly provides the total reference clock signal for the ARM. This ARM requires a 25M clock, so we chose a passive crystal and connected an external matching capacitor to form the oscillation circuit.

[0052] Capacitors C50 and C51 are matching capacitors. The passive crystal load capacitor is 18pF. The conventional formula for calculating the value of the matching capacitor is:

[0053]

[0054] CL is the load capacitance of the crystal, CdCg are the matching capacitors C50 / C51 in the diagram above, and Cs is the parasitic capacitance on the two crystal lines when routing on the PCB, typically 2-5pF. Taking 5pF, Cd and Cg are calculated as follows:

[0055] Cd=Cg=(18-5)*2=26pF,

[0056] Use standard 22pF capacitors;

[0057] The ARM processor starts by receiving an external power supply, an oscillator clock signal, and a reset signal. It loads the firmware program from the QSPI Flash into the SDRAM to run, completes data exchange, and forms a core self-operating system.

[0058] like Figure 7As shown, the camera trigger module includes a socket P1, with interfaces 1 and 3 of the socket P1 grounded. The socket P1 consists of six components connected in series: interface 2, resistor R35, interface 3 of transistor Q4, interface 1 of transistor Q4, resistor R37, and the CAM_Trigger terminal. The CAM_Trigger terminal is connected to interface 101 of chip U13. Interface 4 of the socket P1 is electrically connected between resistor R35 and interface 3 of transistor Q4. Interface 2 of transistor Q4 is grounded, and resistor R38 is electrically connected between interface 1 and interface 2 of transistor Q4.

[0059] The socket P1's 5th pin, resistor R34, transistor Q3's 1st pin, transistor Q3's 3rd pin, and CAM_Feedback terminal are connected in series. The CAM_Feedback terminal is connected to the chip U13's 100th pin. An external resistor R31 is connected to the connection line between transistor Q3's 3rd pin and the CAM_Feedback terminal. One end of resistor R31 is connected to VDD33. Transistor Q3's 2nd pin is grounded. A resistor R38 is electrically connected between transistor Q3's 1st pin and 2nd pin. The connection line between socket P1's 5th pin and resistor R34 is connected to an external resistor R... 32. One end of resistor R32 is connected to the 12V terminal; the 6th interface of socket P1 is connected to the CAM_IO terminal through resistor R33, and the CAM_IO terminal is connected to the 99th interface of chip U13; the CMOS camera trigger module uses an NPN transistor as the driver, as shown in the figure below. Pin 4 of P1 is connected to the camera's trigger input, and by default it is pulled up to Pin 2 to maintain a 12V high level; when the ARM sends a high level to the base (pin 1) of Q4, the collector (pin 3) of the three lasers is pulled low to a low level. For the camera, a falling edge is obtained at this time, so setting the camera's trigger condition to a falling edge will allow the camera to trigger the image acquisition operation;

[0060] In this design, in order to achieve high-speed triggering, the PCB internal traces are directly connected instead of optocoupler isolation, because the optocoupler signal switching time is too long to meet the 1ms requirement.

[0061] like Figure 5 As shown, the stepper motor drive module includes chip U15 (optical isolation chip), chip U16 (optical isolation chip), chip U17 (single-ended to differential signal chip), and chip U23 (optical isolation chip).

[0062] Interface 1 of chip U15 is connected in series with VDD33 via resistor R73, and interface 3 of chip U15 is connected in series with VDD33 via resistor R72. Interface 2 of chip U15 is connected to MCU_AWO_O, MCU_AWO_O is connected to interface 134 of chip U13, interface 4 of U15 is connected to MCU_CS_O, and MCU_CS_O is connected to interface 132 of chip U13. Interfaces 5 and 7 of chip U15 are grounded. Interface 6 of chip U15 is connected to MOTOR_CS- via fuse F6, and MOTOR_CS- is connected to interface 8 of socket P8. Interface 8 of chip U15 is connected to MOTOR_AWO- via fuse F5, and MOTOR_AWO- is connected to interface 6 of socket P8.

[0063] Both interfaces 5 and 7 of chip U16 are grounded. The following four components of chip U16 are connected in series: interface 6, MCU_ALM_I terminal, resistor R74, and VDD33 terminal. Similarly, the following four components of chip U16 are connected in series: interface 8, MCU_TIM_I terminal, resistor R75, and VDD33 terminal. The MCU_ALM_I terminal is connected to interface 128 of chip U13, and the MCU_TIM_I terminal is connected to interface 129 of chip U13. Interface 1 of chip U16 is connected to the VCC5V terminal via resistor R76, and interface 3 of chip U16 is connected to the VCC5V terminal via resistor R77. Interface 2 of chip U16 is externally connected to the MOTOR_TIM+ terminal, which is connected to interface 11 of socket P8. Interface 4 of chip U16 is externally connected to the MOTOR_ALM+ terminal, which is connected to interface 9 of socket P8.

[0064] The 8th interface of chip U17 is grounded; the 4th interface of chip U17 is connected to the VCC 5V terminal; the 16th interface of chip U17 is also connected to the VCC 5V terminal; the 1st interface of U17 is connected to the MCU_Dir_O terminal, which is connected to the 131st interface of chip U13; the 1st interface of U17 is also connected to the MCU_Pulse_O terminal, which is connected to the 133rd interface of chip U13; the 2nd interface of chip U17 is connected to the MOTOR_Dir+ terminal. The MOTOR_Dir+ terminal is connected to interface 3 of socket P8; interface 3 of chip U17 is externally connected to the MOTOR_Dir- terminal, which is connected to interface 4 of socket P8; interface 14 of U17 is externally connected to the MOTOR_Pulse+ terminal, which is connected to interface 1 of socket P8; interface 13 of U17 is externally connected to the MOTOR_Pulse- terminal, which is connected to interface 2 of socket P8.

[0065] Both interfaces 5 and 7 of chip U23 are grounded; the 6th interface, MCU_END_I terminal, resistor R20, and VDD33 terminal of chip U23 are connected in series; the 8th interface, MCU_ZERO_I terminal, resistor R105, and VDD33 terminal of chip U23 are also connected in series; the MCU_END_I terminal is connected to interface 118 of chip U13; the MCU_ZERO_I terminal is connected to interface 117 of chip U13; interface 2 of chip U23 is connected to interface 3 of socket P11 through the MOTOR_ZERO terminal; interface 4 of chip U23 is connected to interface 4 of socket P11 through the MOTOR_END terminal; the MOTOR... The _ZERO terminal is connected to the interface of chip U13, and the MOTOR_END terminal is also connected to the interface of chip U13. The 1st interface of chip U23, resistor R106, and the 2nd interface of socket P11 are connected in series. Resistors R108 and R109 are externally connected to the connection between resistor R106 and the 2nd interface of socket P11. Resistor R108 is externally connected to the VCC5V terminal, and resistor R109 is externally connected to the 24V_IN terminal. The 3rd interface of chip U23 is electrically connected between resistors R106 and R108 through resistor R107. The 1st interface of socket P11 is grounded, and the 1st interface of socket P11 is electrically connected between resistor R109 and the 2nd interface of socket P11 through capacitor C92.

[0066] The 5th and 7th interfaces of socket P8 are respectively connected to the VCC 5V terminal; the 10th and 12th interfaces of socket P8 are respectively grounded; the 3D white light interference sensor needs to capture N (>300) interference fringe images within a certain height range, which requires a motor to drive a CMOS camera to take pictures at different positions. The smaller the distance between the picture positions, the more accurate the measurement, and the higher the accuracy of the final 3D measurement. This control system uses a motor platform with a 2-micron pulse equivalent (sending a pulse to the motor drives the lead screw to advance 2 microns), and simultaneously detects the feedback signal from a 50-nanometer resolution grating ruler. This allows the motor to move at a minimum 0.4-micron interval and trigger the camera to acquire 350 2D images within 1 second. Finally, a 3D image with an accuracy of 0.1 microns (100nm) can be obtained through software fitting. The relevant working connections of this module are as follows: Figure 17 As shown; Motor signal operation process:

[0067] --AWO brake signal, because our motor is installed vertically inside, when no pulse is given to the motor, in order to prevent the motor from sliding down due to its own weight, a brake signal is needed to stop the motor.

[0068] --CS step angle adjustment signal, used to adjust the angle of each rotation of the stepper motor in order to control the running accuracy of the motor;

[0069] --TIM origin timing signal, used to detect when the motor stops rotating and feed back the number of motor pulses currently sent to the PC;

[0070] --ALM alarm signal: When the motor is in an abnormal state, such as when it has reached the upper or lower limit position but is still sending pulses to the motor, this signal will raise the alarm level.

[0071] The above signals are connected to the stepper motor driver using an optocoupler isolation chip to minimize external interference to the interface and ensure signal accuracy; -- Pulse signal: The ARM sends pulse signals to control the motor rotation. The motor input is a differential signal, so a single-ended to differential converter chip is used here; -- Direction signal: The ARM uses this signal to control the motor to rotate forward and backward to achieve direction changes; When the step angle is 7.2°, the pulse and motor rotation diagram is as follows. Figure 18 As shown;

[0072] The ZERO and END signals are the upper and lower limit signals connecting the ARM and the motor driver, and are also optically isolated. When the motor reaches the upper or lower limit, sending pulses to the motor will prevent it from rotating, thus protecting it from overshoot. In this design, the lower limit of the ZERO signal is also used as the origin, and the motor pulse count and grating ruler count are cleared to 0 here.

[0073] like Figure 6 As shown, the grating ruler encoder receiving module includes a chip U18 (differential to single-ended chip). Interface 8 of chip U18 is grounded; interface 4 of chip U18 is connected to a VCC 5V terminal; interface 12 of chip U18 is grounded; interface 16 of chip U18 is connected to a VCC 5V terminal; and interface 16 and the VCC 5V terminal of chip U18 are directly connected to an external capacitor C94, with one end of capacitor C94 grounded; interface 3 of chip U18, the MCU_EA terminal, and a resistor... R80 and VDD33 terminals, the aforementioned four items are connected in series. The 5th interface, MCU_EB terminal, resistor R79, and VDD33 terminal of chip U18 are connected in series. The 11th interface, MCU_EZ terminal, resistor R79, and VDD33 terminal of chip U18 are connected in series. The MCU_EA terminal is connected to the 87th interface of chip U13. The MCU_EB terminal is connected to the 88th interface of chip U13. The MCU_EZ terminal is connected to the 89th interface of chip U13.

[0074] The U18 chip has the following external connections: Interface 1 is connected to the Extern_EAz- terminal; Interface 2 is connected to the Extern_EAz+ terminal; Interface 6 is connected to the Extern_EBz+ terminal; Interface 7 is connected to the Extern_EBz- terminal; Interface 10 is connected to the Extern_EZz+ terminal; and Interface 9 is connected to the Extern_EZz- terminal. The Extern_EAz+, Extern_EAz-, Extern_EBz+, Extern_EBz-, Extern_EZz+, and Extern_EZz- terminals are all connected to... Socket P10; The 8th pin of socket P10 is grounded, the 7th pin of socket P10 is connected to VCC5V externally, and the 1st pin, Extern_EAz+ terminal, resistor R81, Extern_EAz- terminal, and 2nd pin of socket P10 are connected in series; the 3rd pin, Extern_EBz+ terminal, resistor R110, Extern_EBz- terminal, and 4th pin of socket P10 are connected in series; the 5th pin, Extern_EZz+ terminal, resistor R111, Extern_EZz- terminal, and 6th pin of socket P10 are connected in series; the relevant working connections of this module are as follows. Figure 17 As shown;

[0075] Grating ruler signal: Each pulse of the stepper motor advances 2 micrometers, but for our 3D white light interferometer sensor, an accuracy of 0.1 micrometers is not enough. Therefore, a higher-precision 50-nanometer grating ruler is introduced to provide more accurate feedback signals and control the camera to be in the correct position.

[0076] --The AB phase pulse counting signal is the electronic pulse signal waveform output by the grating ruler reader when it reads changes in the grating light during movement. The A-phase waveform and the B-phase waveform are 90° out of phase, so there are four edge signals (2 rising edges and 2 falling edges) in one cycle. When the grating ruler pitch is 40 micrometers and the subdivision factor is 200, a resolution signal of 40÷200÷4=0.05 (um) can be obtained.

[0077] The ARM side detects the rising and falling edges of the input waveform of each grating ruler through the orthogonal encoding detection input interface, counts them, and uses the count to provide feedback on the current position of the motor.

[0078] --Origin signal: The origin signal is a grid shielding point on the grating ruler. When the reader passes through this grid, the origin signal pulse will be triggered, which is used as the 0 position for counting. This design reserves this position but does not use it.

[0079] like Figure 8 As shown, the laser LD driving module includes chip U6 (LDO power step-down chip), chip U7 (constant current drive chip), chip U8 (LDO power step-down chip), and socket P2; the 1st interface, LD_SCL terminal, and 9th interface of the socket P2 are connected in series; the 2nd interface, LD_SDA terminal, and 8th interface of the chip U7 are connected in series; the 5th interface of the socket P2, capacitor C28, the chip, and the 5th interface of U7 are connected in series; the 4th interface of the chip U7 is electrically connected between the 5th interface of the socket P2 and capacitor C28; an external resistor R49 is connected between the LD_SDA terminal and the 8th interface of the chip U7; an external resistor R50 is connected between the LD_SDA terminal and the 8th interface of the chip U7; and resistors R49, R50, and the 1st interface of the chip U7 are all connected to the VDD33_LDREF terminal.

[0080] The socket P2's 4th interface, LD_EN terminal, and chip U6's 1st interface are connected in series. The socket P2's 6th interface is connected to chip U6's 2nd interface. The connection between the socket P2's 6th interface and chip U6's 2nd interface is externally connected to VCC2_5V. Chip U6's 3rd interface is electrically connected between the socket P2's 5th interface and capacitor C28, and chip U6's 3rd interface is grounded. The chip U6's 4th interface, laser diode LD6's 1st interface, laser diode LD6's 3rd interface, resistor RS1, resistor RS2, and socket P2's 5th interface are connected in series. Resistor R48 is connected in parallel between laser diode LD6's 1st interface and laser diode LD6's 2nd interface. The connection between resistor RS2 and socket P2's 5th interface is grounded. The chip U6's 5th interface, resistor R51, and chip U7's 3rd interface are connected in series. The connection between interface 5 and resistor R51 is externally connected to resistors R52 and R53. One end of resistor R52 is electrically connected between interface 3 of laser diode LD6 and resistor RS1. Resistor R53 is externally connected to the VDD33_LDREF terminal. Resistor R54 is connected in parallel outside resistor R53. The connection between resistors R51 and R52 is externally connected to capacitor C30. One end of capacitor C30 is electrically connected between resistor RS2 and interface 5 of socket P2. The connection between resistor R51 and interface 3 of chip U7 is externally connected to capacitor C29. One end of capacitor C29 is electrically connected between capacitor C30 and interface 5 of socket P2. Interface 2 of chip U7 is electrically connected between capacitor C29 and interface 5 of socket P2. Interface 10 of chip U7 is electrically connected between interface 2 of chip U7 and interface 5 of socket P2. Interface 6 of chip U7 is electrically connected between interface 10 of chip U7 and interface 5 of socket P2.

[0081] The chip U8 has four components connected in series: interface 3, capacitor C33, capacitor C31, and interface 2. The connection between interface 3 of chip U8 and capacitor C33 is externally connected to the VCC2_5V terminal. The connection between capacitor C31 and interface 2 of chip U8 is externally connected to the VDD33_LDREF terminal. The connection between capacitor C33 and capacitor C31 is grounded. Interface 1 of chip U8 is electrically connected between capacitor C33 and capacitor C31. A capacitor C32 is connected in parallel outside capacitor C31.

[0082] The LD_SDA terminal is connected to interface 46 of chip U13, the LD_SCL terminal is connected to interface 45 of chip U13, and the LD_EN terminal is connected to interface 44 of chip U13. The white light interference 3D sensor uses a laser LD emitter as the light source for light interference. This LD needs to be able to adjust its brightness from 0% to 100% and maintain a stable brightness for a long time. A constant current LD driving circuit is designed here. The constant current driving chip is U7. U7 requires a 3.3V power supply, which is obtained by stepping down from 5V using an LDO. The positive terminal of the LD laser is connected to another LDO-U6, and the negative terminal is connected to PIN3 of the constant current driving chip U7.

[0083] Socket P2 is the control interface between the ARM and the constant current driver chip U7. The ARM writes the constant current control value to the register of U7 via the I2C protocol (pins 1 and 2 of socket P2). U7 adjusts the output voltage at pin 3, which changes the voltage drop across the LD (LD6 in the diagram), thus achieving brightness adjustment. When the LD's internal resistance decreases due to heat, causing the voltage across it to rise, U7 can automatically adjust the voltage at the negative terminal of the LD according to the set constant current value, maintaining the voltage across the LD at a fixed value. This ensures a stable constant current through the LD, preventing sudden brightness changes during long-term use.

[0084] like Figures 9-11 As shown, the input / output module includes an input signal circuit, an output signal circuit, and a connector CN1; the white light interferometric 3D sensor can accept external hardware signal input to trigger the entire system to acquire images, generate 3D, and simultaneously provide output results via hardware signals; it supports 2 inputs and 2 outputs, for example, one external input can be designed to be triggered by the rising edge, and the other can be designed to be triggered by the falling edge, and the two outputs can be used to indicate the OK and NG signals of the measurement.

[0085] like Figure 9 and Figure 11As shown, the input signal circuit includes chip U4 (optical isolation chip); interfaces 5 and 7 of chip U4 are grounded, and interfaces 2 and 4 of chip U4 are grounded; interface 6 of chip U4 is connected to the TGR-DSI1 terminal, and interface 8 of chip U4 is connected to the TGR-DSI2 terminal; an external resistor R26 is connected between interface 6 of U4 and the TGR-DSI1 terminal; an external resistor R25 is connected between interface 8 of chip U4 and the TGR-DSI2 terminal; both resistors R26 and R25 are connected to the VDD33 terminal; interface 1 of chip U4, interface 3 of transistor Q1, interface 2 of transistor Q1, and the DSI2 terminal are connected in series, and a resistor R27 is connected in parallel between interface 1 and interface 3 of transistor Q1. A capacitor C24 is connected between interface 1 of chip U4 and interface 2 of chip U4. One end of capacitor C24 is electrically connected between interface 1 of chip U4 and interface 3 of transistor Q1. A resistor R28 and a diode D7 are connected in parallel outside the capacitor C24. The three terminals of chip U4, transistor Q2, transistor Q2, and DSI1 are connected in series. A resistor R29 is connected in parallel between interface 1 and interface 3 of transistor Q2. A capacitor C25 is connected between interface 3 and interface 4 of chip U4. One end of capacitor C25 is electrically connected between interface 3 of chip U4 and interface 3 of transistor Q2. A resistor R30 and a diode D8 are connected in parallel outside the capacitor C25.

[0086] The TGR-DSI1 terminal is connected to the 167 interface of chip U13, and the TGR-DSI2 terminal is connected to the 168 interface of chip U13. The DSI1 terminal is connected to the 7 interface of connector CN1, and the DSI2 terminal is connected to the 6 interface of connector CN1. The 1 and 8 interfaces of connector CN1 are grounded, and the 2 interface of connector CN1 is connected to a 24V_IN terminal. Optical couplers are added between the external input signals DSI1, DSI2 and ARM to prevent damage to the components on the board due to incorrect external wiring or excessive voltage or current. The input signal is driven by the MOSFET and then sent to the optocoupler U4, and then detected by the ARM. The ARM can control the motor movement and the camera to capture images when it detects the input signal.

[0087] like Figure 10 and Figure 11As shown, the output signal circuit includes chip U5 (optical isolation chip). Interfaces 2, 4, and 6 of chip U5 are all grounded. Interface 1 of chip U5 is connected to the TGR-DSO1 terminal via resistor R42. Interface 3 of chip U5 is connected to the TGR-DSO2 terminal via resistor R43. Interface 5 of chip U5 is connected to the TGR-DSO3 terminal via resistor R44. The connection between interface 1 of chip U5 and resistor R42 is externally connected to resistor R47. The connection between interface 3 of chip U5 and resistor R43 is externally connected to resistor R46. The connection between interface 5 of chip U5 and resistor R44 is externally connected to resistor R45. Resistors R45, R46, and R47 are all grounded.

[0088] The following five components are connected in series: chip U5's interface 16, transistor Q5's interface 1, transistor Q5's interface 2, fuse F2, and DSO1. Chip U5's interface 15 is connected to transistor Q5's interface 3. Similarly, chip U5's interface 14, transistor Q6's interface 1, transistor Q6's interface 2, fuse F3, and DSO2 are connected in series. Chip U5's interface 13 is connected to transistor Q6's interface 3. Chip U5's interface 12, transistor Q7's interface 1, transistor Q7's interface 2, fuse F4, and DSO3 are connected in series. Chip U5's interface 11 is connected to transistor Q7's interface 3. The interfaces 3 of transistors Q5, Q6, and Q7 are all grounded. The transistor Q7's... An external resistor R41 is connected to the connection between the 2-pin connector and fuse F4. Resistor R41 is connected to the VCC 5V terminal via diode D9. An external resistor R40 is connected to the connection between the 2-pin connector of transistor Q6 and fuse F3. Resistor R40 is electrically connected between resistor R41 and diode D9. An external resistor R39 is connected to the connection between the 2-pin connector of transistor Q5 and fuse F2. Resistor R39 is electrically connected between resistor R40 and diode D9. An external capacitor C27 is connected to the connection between resistor R39 and diode D9. Capacitor C27 is grounded. An external capacitor C26 is connected to the connection between diode D9 and the VCC 5V terminal. Capacitor C26 is grounded. Fuse F1 is connected between capacitor C26 and capacitor C27. The connection between resistor R39 and diode D9 is externally connected to the VCC_PULL terminal.

[0089] The TGR-DSO1 terminal is connected to interface 174 of chip U13, the TGR-DSO2 terminal is connected to interface 175 of chip U13, the TGR-DSO3 terminal is connected to interface 176 of chip U13, the DSO1 terminal is connected to interface 3 of connector CN1, the DSO2 terminal is connected to interface 4 of connector CN1, and the DSO3 terminal is connected to interface 5 of connector CN1.

[0090] The output signal is processed similarly to the input signal. The high and low level signals output by the ARM are transmitted through optocoupler U5, and then to transistors Q5, Q6, and Q7 to drive external I / O. Because the low voltage is very low, three fuses (F2, F3, and F4) are placed directly at the external interface to prevent overcurrent damage to the internal I / O. Network module: Because the white light interference 3D sensor is an industrial 3D sensor, and the industrial control computer may be located at a relatively far distance, a 100Mbps Ethernet port was chosen for communication. The connection between the network module and the ARM and external components is as follows... Figure 19 As shown; the PHY chip requires a separate 25MHz clock signal to operate, which is provided here by a 25MHz passive crystal oscillator circuit, the same as the 25MHz circuit for the ARM. The ARM provides reset and clock signals to the PHY chip. During power-on initialization, the ARM writes data to the PHY chip's register through the MDC / MDO pin to initialize the PHY chip. Conventional data communication is sent to the PHY chip via the RX, TX differential signal pins. The PHY chip then packages the data according to the TCP protocol and sends it to the computer through the RJ45 network connector. Receiving data from the computer is similar, but the data flow is reversed. For the RJ45 network connector, EMI treatment is performed on the differential data lines to maintain stable data transmission. A 49.9-ohm resistor is connected in series on each line, and a 10pF ceramic capacitor is connected in parallel to ground. This effectively removes some high-frequency glitches, smooths the waveform, and keeps the network transmission stable. In this invention, a power supply module, an ARM main control module, an input / output module, a network module, a camera trigger module, a stepper motor drive module, a laser LD drive module, and a grating encoder receiving module are set up.

[0091] This circuit can collect external signals / communication data, control the motor movement according to instructions, receive counting information from the external encoder grating ruler, and trigger the CMOS camera to acquire images at equal intervals. After the circuit starts working, the PC is configured with working parameters via the network: trigger mode, LED brightness, camera exposure, motor movement parameters, etc. The network module monitors the network trigger signals sent by the PC, and the IO module monitors the hardware trigger signals sent by the external PLC, etc. As long as one is active, the ARM controls the motor to move, and at the same time drives the grating ruler read head to move. Based on the count feedback from the grating ruler, the CMOS camera is triggered at equal intervals to acquire 2D images with interference fringes and send them to the PC, where the 3D image is reconstructed.

[0092] This invention employs a control system consisting of an Arm STM32F767, a 50nm grating ruler decoder, a 2µm stepper motor controller, a laser LD driver, and a high-speed trigger camera. This circuit eliminates the need for specialized motion control cards, ultra-high precision, high-cost motion platforms, servo / linear motors, etc. Through a self-implemented motion control algorithm within the ARM processor, it only requires conventional stepper motors and high-precision grating ruler feedback to achieve rapid image acquisition at the nanometer (100nm) level. This approach also minimizes the requirements for circuit board miniaturization, reduces costs, and increases precision, while minimizing assembly requirements.

Claims

1. A white light interferometric 3D sensor system control circuit, comprising a power supply module, an ARM main control module, an input / output module, a network module, a camera trigger module, a stepper motor drive module, a laser LD drive module, and a grating ruler encoder receiving module, characterized in that: The output terminals of the power module and the grating ruler encoder receiving module are respectively connected to the input terminal of the ARM main control module. The output of the ARM main control module is connected to the input of the input / output module, the network module, the camera trigger module, the stepper motor drive module, and the laser LD drive module, respectively. The power module is connected to an external power adapter; The input / output module is connected to an external signal receiver. The network module is connected to an external computer. The camera trigger module is externally connected to a high-speed CMOS camera; The stepper motor drive module is externally connected to a motor driver and a motor; The grating ruler encoder receiving module is connected to an external grating ruler; The power module includes chip U1, chip U2, chip U3, laser diode LD1, laser diode LD2, laser diode LD3, laser diode LD4, laser diode LD5, and button KEY1; chip U1 is an LDO power step-down chip, chip U2 is a DC-DC power step-down chip, and chip U3 is a DC-DC power step-down chip. The six components of chip U2—interface 1, capacitor C1, inductor L1, capacitor C11, bidirectional Zener diode D3, and interface 2—are connected in series. The connection between capacitor C11 and bidirectional Zener diode D3 is grounded. The 7th interface of the chip U2 is connected between the inductor L1 and the electrolytic capacitor C15 through resistor R1. The 7th interface of the chip U2 is electrically connected between the electrolytic capacitor C15 and the bidirectional Zener diode D3 through resistors R6 and R5. Resistors R6 and R5 are connected in series. The 8-pin interface of chip U2 is electrically connected between resistor R5 and bidirectional Zener diode D3 via capacitor C12; capacitor C8 and resistor R4 are connected in parallel outside capacitor C12; capacitor C8 and resistor R4 are connected in series; capacitor C8 is electrically connected between chip U2 and capacitor C12; resistor R4 is electrically connected between capacitor C12 and bidirectional Zener diode D3; Zener diode D2 is electrically connected between resistor R5 and capacitor C12; Zener diode D2 is electrically connected between capacitor C1 and inductor L1; the 10-pin interface of chip U2 is electrically connected between capacitor C1 and Zener diode D2. The 9th interface of chip U2 is electrically connected between resistor R4 and bidirectional Zener diode D3; the 11th interface of chip U2 is electrically connected between the 9th interface of chip U2 and bidirectional Zener diode D3; the 5th interface of chip U2 is electrically connected between the 11th interface of chip U2 and bidirectional Zener diode D3 through resistor R3; the 4th interface of chip U2 is electrically connected between resistor R3 and bidirectional Zener diode D3 through capacitor C14. The 3rd interface of chip U2 is electrically connected between capacitor C14 and bidirectional Zener diode D3 through resistor R7. The 2nd interface of chip U2 is electrically connected between resistor R2 and resistor R7. The 2nd interface of chip U2 is electrically connected between resistor R7 and bidirectional Zener diode D3 through capacitor C13. The 2nd interface of chip U2 is electrically connected between capacitor C13 and bidirectional Zener diode D3 through electrolytic capacitor C10. The connection point of electrolytic capacitor C10 and chip U2 is externally connected to a 24V-1 terminal.

2. The control circuit for the white light interferometry 3D sensor system according to claim 1, characterized in that: One end of the laser diode LD1 is connected to the VCC5V terminal via resistor R8, and the other end of the laser diode LD1 is grounded. The 2 interface of the chip U2 is connected in series with the 24V_IN terminal through the Zener diode D1; An electrolytic capacitor C15 is connected in parallel to the outside of capacitor C11. One end of the electrolytic capacitor C15 is electrically connected between inductor L1 and capacitor C11, and one end of the electrolytic capacitor C15 is externally connected to VCC5V terminal. The other end of the electrolytic capacitor C15 is electrically connected between capacitor C11 and bidirectional Zener diode D3. One end of the laser diode LD2 is connected to an external 12V terminal through resistor R16, and the other end of the laser diode LD2 is grounded. The 2 interface of the chip U3 is connected in series with the 24V_IN terminal through the Zener diode D4; The six components of chip U3—interface 1, capacitor C16, inductor L2, capacitor C19, bidirectional Zener diode D6, and interface 2—are connected in series. The connection between capacitor C19 and bidirectional Zener diode D6 is grounded. An electrolytic capacitor C21 is connected in parallel to the outside of capacitor C19. One end of the electrolytic capacitor C21 is electrically connected between inductor L2 and capacitor C19, and one end of the electrolytic capacitor C21 is externally connected to a 12V terminal. The other end of the electrolytic capacitor C21 is electrically connected between capacitor C19 and bidirectional Zener diode D6. The 7th interface of the chip U3 is connected between the inductor L2 and the electrolytic capacitor C21 through resistor R9. The 7th interface of the chip U3 is electrically connected between the electrolytic capacitor C21 and the bidirectional Zener diode D6 through resistors R12 and R14. Resistors R12 and R14 are connected in series. The 8-pin interface of chip U3 is electrically connected between resistor R14 and bidirectional Zener diode D6 via capacitor C20; capacitor C17 and resistor R13 are connected in parallel outside capacitor C20; capacitor C17 and resistor R13 are connected in series; capacitor C17 is electrically connected between chip U3 and capacitor C20; resistor R13 is electrically connected between capacitor C20 and bidirectional Zener diode D6; Zener diode D5 is electrically connected between resistor R14 and capacitor C20; Zener diode D5 is electrically connected between capacitor C16 and inductor L2; the 10-pin interface of chip U3 is electrically connected between capacitor C16 and Zener diode D5. The 9th interface of chip U3 is electrically connected between resistor R13 and bidirectional Zener diode D6; the 11th interface of chip U3 is electrically connected between the 9th interface of chip U3 and bidirectional Zener diode D6; the 5th interface of chip U3 is electrically connected between the 11th interface of chip U3 and bidirectional Zener diode D6 through resistor R11; the 4th interface of chip U3 is electrically connected between resistor R11 and bidirectional Zener diode D6 through capacitor C22. The 3rd interface of chip U3 is electrically connected between capacitor C22 and bidirectional Zener diode D6 through resistor R15. The 2nd interface of chip U3 is electrically connected to resistor R15 through resistor R10. The 2nd interface of chip U3 is electrically connected between resistor R15 and bidirectional Zener diode D6 through capacitor C23. The 2nd interface of chip U3 is electrically connected between capacitor C23 and bidirectional Zener diode D6 through electrolytic capacitor C18. The connection point of electrolytic capacitor C18 and chip U3 is externally connected to a 24V-2 terminal. The 3rd interface of the chip U1 is connected to the VCC 5V terminal. The five components of chip U1—interface 2, ferrite bead FB1, capacitor C3, capacitor C2, and interface 3—are connected in series. The connection lines of capacitors C3 and C2 are grounded. The connection line between ferrite bead FB1 and capacitor C3 is externally connected to terminal AVDD33. A capacitor C7 is connected in parallel to the outside of capacitor C3. One end of capacitor C7 is electrically connected between ferrite bead FB1 and terminal AVDD33, and the other end of capacitor C7 is electrically connected between capacitors C3 and C2. A capacitor C9 is connected in parallel to the outside of capacitor C2. Interface 1 of chip U1 is electrically connected between capacitors C7 and C9. The connection line between capacitors C3 and C2 is grounded. Capacitors C5, C6, and electrolytic capacitor C4 are connected in parallel between capacitors C9 and C7. One end of capacitor C5 is electrically connected between one end of electrolytic capacitor C4 and one end of capacitor C6. One end of capacitor C5 is externally connected to the VDD33 terminal. The other end of capacitor C5 is electrically connected between the other end of electrolytic capacitor C4 and the other end of capacitor C6. One end of electrolytic capacitor C4 is electrically connected between interface 2 of chip U1 and capacitor C5. The other end of electrolytic capacitor C4 is electrically connected between interface 1 of chip U1 and capacitor C5. One end of capacitor C6 is electrically connected between capacitor C5 and ferrite bead FB1. The other end of capacitor C6 is electrically connected between capacitor C7 and capacitor C5. One end of the button KEY1 is connected to the VDD33 terminal through resistor R17, and the other end of the button KEY1 is grounded. The laser diode LD3 is connected to the VDD33 terminal through resistor R18; the laser diode LD4 is connected to the VDD33 terminal through resistor R19; and the laser diode LD5 is connected to the VDD33 terminal through resistor R21.

3. The control circuit for the white light interferometry 3D sensor system according to claim 2, characterized in that: The ARM main control module includes chip U13, chip U12, crystal oscillator Y2, chip U14, chip U19, and chip U20; The 31 interface of the chip U13 is connected to the 2 interface of the chip U12. The 1 interface of the chip U12 is grounded. The 3 interface of the chip U12 is electrically connected to the capacitor C40. One end of the capacitor C40 is grounded. The connection between the capacitor C40 and the 3 interface of the chip U12 is grounded. The 29th interface of chip U13, the 3rd interface of crystal oscillator Y2, the 1st interface of crystal oscillator Y2, and the 30th interface of chip U13 are connected in series. The 4th interface of crystal oscillator Y2 is electrically connected to the 1st interface of crystal oscillator Y2 through capacitor C50. The connection between the 4th interface of crystal oscillator Y2 and capacitor C50 is grounded. The 2nd interface of crystal oscillator Y2 is electrically connected to the 3rd interface of crystal oscillator Y2 through capacitor C51. The connection between the 2nd interface of crystal oscillator Y2 and capacitor C51 is grounded. The chip U14 has an external USB interface; The chip U13 includes an FMC bus, and the chip U13 is interconnected with the chip U19 through the FMC bus; The 4th interface of the chip U20 is grounded, the 8th interface of the chip U20 is connected to the VDD33 terminal, and a capacitor C74 is electrically connected between the 8th interface of the chip U20 and the VDD33 terminal, with one end of the capacitor C74 being grounded. Interface 1 of chip U20 is connected to interface 164 of chip U13; interface 2 of chip U20 is connected to interface 27 of chip U13; interface 3 of chip U20 is connected to interface 25 of chip U13; interface 5 of chip U20 is connected to interface 26 of chip U13; interface 6 of chip U20 is connected to interface 58 of chip U13; and interface 7 of chip U20 is connected to interface 24 of chip U13. The 166 interface of the chip U13, resistors R62, R63, R64, and the 48 interface of the chip U13 are connected in series. The connection between resistors R63 and R64 is grounded. The connection between resistors R62 and R63 is connected to interface 2 of socket P6 via BOOT. Interface 1 of socket P6 is externally connected to VDD33. The 6th interface of the chip U13 is externally connected to the VDD33 terminal, and the connection between the 6th interface of the chip U13 and the VDD33 terminal is externally connected to the capacitor C41, which is grounded. The 38 interface of the chip U13 is externally connected to the VDDA terminal through resistor R65; the connection between the 38 interface of the chip U13 and resistor R65 is externally connected to capacitors C43 and C44; one end of each of capacitors C43 and C44 is grounded. The 81 interface of the chip U13, capacitor C42, capacitor C45, and the 125 interface of the chip U13 are connected in series, and the connection of capacitor C42 and capacitor C45 is grounded. The 39 interface of the chip U13 is externally connected to the VDD33 terminal through resistor R66; the connection between the 39 interface of the chip U13 and resistor R66 is externally connected to capacitors C46 and C47; one end of each of capacitors C46 and C47 is grounded. The 37 interface of chip U13, resistor R67, and 171 interface of chip U13 are connected in series. The connection between the 37 interface of chip U13 and resistor R67 is grounded. The connection between resistor R67 and chip U13 interface 171 is externally connected to VDD33 through resistor R68.

4. The control circuit of the white light interferometry 3D sensor system according to claim 3, characterized in that: The camera trigger module includes a socket P1, and the 1 and 3 interfaces of the socket P1 are grounded respectively. The six components of the socket P1 are connected in series: connector 2, resistor R35, connector 3 of transistor Q4, connector 1 of transistor Q4, resistor R37, and CAM_Trigger terminal. The CAM_Trigger terminal is connected to connector 101 of chip U13. Connector 4 of the socket P1 is electrically connected between resistor R35 and connector 3 of transistor Q4. Connector 2 of transistor Q4 is grounded. Resistor R38 is electrically connected between connector 1 and connector 2 of transistor Q4. The socket P1's 5th pin, resistor R34, transistor Q3's 1st pin, transistor Q3's 3rd pin, and CAM_Feedback terminal are connected in series. The CAM_Feedback terminal is connected to the chip U13's 100th pin. The connection line between transistor Q3's 3rd pin and the CAM_Feedback terminal is externally connected to resistor R31, with one end of resistor R31 connected to the VDD33 terminal. Transistor Q3's 2nd pin is grounded. Resistor R38 is electrically connected between transistor Q3's 1st pin and 2nd pin. The connection line between socket P1's 5th pin and resistor R34 is externally connected to resistor R32, with one end of resistor R32 connected to the 12V terminal. The 6-pin connector of socket P1 is connected to the CAM_IO terminal via resistor R33, and the CAM_IO terminal is connected to the 99-pin connector of chip U13.

5. The control circuit for the white light interferometry 3D sensor system according to claim 4, characterized in that: The stepper motor drive module includes chip U15, chip U16, chip U17, and chip U23; Interface 1 of chip U15 is connected in series with VDD33 via resistor R73, and interface 3 of chip U15 is connected in series with VDD33 via resistor R72; interface 2 of chip U15 is connected to MCU_AWO_O, MCU_AWO_O is connected to interface 134 of chip U13, interface 4 of U15 is connected to MCU_CS_O, and MCU_CS_O is connected to interface 132 of chip U13; The 5th and 7th interfaces of the chip U15 are grounded. The 6th interface of the chip U15 is connected to the MOTOR_CS- terminal through fuse F6. The MOTOR_CS- terminal is connected to the 8th interface of the socket P8. The 8th interface of the chip U15 is connected to the MOTOR_AWO- terminal through fuse F5. The MOTOR_AWO- terminal is connected to the 6th interface of the socket P8. Both interface 5 and interface 7 of the chip U16 are grounded; the 6th interface, MCU_ALM_I terminal, resistor R74, and VDD33 terminal of the chip U16 are connected in series; the 8th interface, MCU_TIM_I terminal, resistor R75, and VDD33 terminal of the chip U16 are connected in series; the MCU_ALM_I terminal is connected to interface 128 of the chip U13; and the MCU_TIM_I terminal is connected to interface 129 of the chip U13. Interface 1 of chip U16 is connected to the VCC5V terminal via resistor R76, and interface 3 of chip U16 is connected to the VCC5V terminal via resistor R77; interface 2 of chip U16 is externally connected to the MOTOR_TIM+ terminal, which is connected to interface 11 of socket P8; interface 4 of chip U16 is externally connected to the MOTOR_ALM+ terminal, which is connected to interface 9 of socket P8. The 8th interface of chip U17 is grounded; the 4th interface of chip U17 is connected to the VCC 5V terminal; the 16th interface of chip U17 is also connected to the VCC 5V terminal; the 1st interface of U17 is connected to the MCU_Dir_O terminal, which is connected to the 131st interface of chip U13; the 1st interface of U17 is also connected to the MCU_Pulse_O terminal, which is connected to the 133rd interface of chip U13; the 2nd interface of chip U17 is connected to the MOTOR_Dir+ terminal. The MOTOR_Dir+ terminal is connected to interface 3 of socket P8; interface 3 of chip U17 is externally connected to the MOTOR_Dir- terminal, which is connected to interface 4 of socket P8; interface 14 of U17 is externally connected to the MOTOR_Pulse+ terminal, which is connected to interface 1 of socket P8; interface 13 of U17 is externally connected to the MOTOR_Pulse- terminal, which is connected to interface 2 of socket P8. Both interfaces 5 and 7 of chip U23 are grounded; the 6th interface, MCU_END_I terminal, resistor R20, and VDD33 terminal of chip U23 are connected in series; the 8th interface, MCU_ZERO_I terminal, resistor R105, and VDD33 terminal of chip U23 are also connected in series; the MCU_END_I terminal is connected to interface 118 of chip U13; the MCU_ZERO_I terminal is connected to interface 117 of chip U13; interface 2 of chip U23 is connected to interface 3 of socket P11 through the MOTOR_ZERO terminal; interface 4 of chip U23 is connected to interface 4 of socket P11 through the MOTOR_END terminal; the MOTOR... The _ZERO terminal is connected to the interface of chip U13, and the MOTOR_END terminal is also connected to the interface of chip U13. The 1st interface of chip U23, resistor R106, and the 2nd interface of socket P11 are connected in series. Resistors R108 and R109 are externally connected to the connection between resistor R106 and the 2nd interface of socket P11. Resistor R108 is externally connected to the VCC5V terminal, and resistor R109 is externally connected to the 24V_IN terminal. The 3rd interface of chip U23 is electrically connected between resistors R106 and R108 through resistor R107. The 1st interface of socket P11 is grounded, and the 1st interface of socket P11 is electrically connected between resistor R109 and the 2nd interface of socket P11 through capacitor C92. The 5th and 7th terminals of the socket P8 are respectively connected to the VCC 5V terminal; the 10th and 12th terminals of the socket P8 are respectively grounded.

6. The control circuit for the white light interferometry 3D sensor system according to claim 5, characterized in that: The grating ruler encoder receiving module includes a chip U18. The 8th interface of the chip U18 is grounded, the 4th interface of the chip U18 is connected to the VCC5V terminal, the 12th interface of the chip U18 is grounded, the 16th interface of the chip U18 is connected to the VCC5V terminal, and the 16th interface and the VCC5V terminal of the chip U18 are directly connected to an external capacitor C94, one end of the capacitor C94 is grounded. The following four components of chip U18 are connected in series: interface 3, MCU_EA terminal, resistor R80, and VDD33 terminal; interface 5, MCU_EB terminal, resistor R79, and VDD33 terminal; and interface 11, MCU_EZ terminal, resistor R79, and VDD33 terminal. The MCU_EA terminal is connected to interface 87 of chip U13, the MCU_EB terminal is connected to interface 88 of chip U13, and the MCU_EZ terminal is connected to interface 89 of chip U13. The chip U18 has the following external interfaces: interface 1 is connected to the Extern_EAz- terminal, interface 2 is connected to the Extern_EAz+ terminal, interface 6 is connected to the Extern_EBz+ terminal, interface 7 is connected to the Extern_EBz- terminal, interface 10 is connected to the Extern_EZz+ terminal, and interface 9 is connected to the Extern_EZz- terminal. The Extern_EAz+, Extern_EAz-, Extern_EBz+, Extern_EBz-, Extern_EZz+, and Extern_EZz- terminals are all connected to socket P10. Socket P10's pin 8 is grounded, and its pin 7 is connected to VCC5V. The following five components are connected in series: pin 1, Extern_EAz+, resistor R81, Extern_EAz-, and pin 2 of socket P10. Similarly, the following five components are connected in series: pin 3, Extern_EBz+, resistor R110, Extern_EBz-, and pin 4 of socket P10. Finally, the following five components are connected in series: pin 5, Extern_EZz+, resistor R111, Extern_EZz-, and pin 6 of socket P10.

7. The control circuit for the white light interferometry 3D sensor system according to claim 6, characterized in that: The laser LD driver module includes chip U6, chip U7, chip U8, and socket P2; The socket P2's interface 1, LD_SCL terminal, and chip U7's interface 9 are connected in series. The socket P2's interface 2, LD_SDA terminal, and chip U7's interface 8 are connected in series. The socket P2's interface 5, capacitor C28, chip, and U7's interface 5 are connected in series. The chip U7's interface 4 is electrically connected between the socket P2's interface 5 and capacitor C28. An external resistor R49 is connected between the LD_SDA terminal and chip U7's interface 8. An external resistor R50 is connected between the LD_SDA terminal and chip U7's interface 8. Resistors R49, R50, and chip U7's interface 1 are all connected to the VDD33_LDREF terminal. The socket P2's 4th interface, LD_EN terminal, and chip U6's 1st interface are connected in series. The socket P2's 6th interface is connected to chip U6's 2nd interface. The connection between the socket P2's 6th interface and chip U6's 2nd interface is externally connected to VCC2_5V. Chip U6's 3rd interface is electrically connected between the socket P2's 5th interface and capacitor C28, and chip U6's 3rd interface is grounded. The chip U6's 4th interface, laser diode LD6's 1st interface, laser diode LD6's 3rd interface, resistor RS1, resistor RS2, and socket P2's 5th interface are connected in series. Resistor R48 is connected in parallel between laser diode LD6's 1st interface and laser diode LD6's 2nd interface. The connection between resistor RS2 and socket P2's 5th interface is grounded. The chip U6's 5th interface, resistor R51, and chip U7's 3rd interface are connected in series. The connection between interface 5 and resistor R51 is externally connected to resistors R52 and R53. One end of resistor R52 is electrically connected between interface 3 of laser diode LD6 and resistor RS1. Resistor R53 is externally connected to the VDD33_LDREF terminal. Resistor R54 is connected in parallel outside resistor R53. The connection between resistors R51 and R52 is externally connected to capacitor C30. One end of capacitor C30 is electrically connected between resistor RS2 and interface 5 of socket P2. The connection between resistor R51 and interface 3 of chip U7 is externally connected to capacitor C29. One end of capacitor C29 is electrically connected between capacitor C30 and interface 5 of socket P2. Interface 2 of chip U7 is electrically connected between capacitor C29 and interface 5 of socket P2. Interface 10 of chip U7 is electrically connected between interface 2 of chip U7 and interface 5 of socket P2. Interface 6 of chip U7 is electrically connected between interface 10 of chip U7 and interface 5 of socket P2. The chip U8 has four components connected in series: interface 3, capacitor C33, capacitor C31, and interface 2. The connection between interface 3 of chip U8 and capacitor C33 is externally connected to the VCC2_5V terminal. The connection between capacitor C31 and interface 2 of chip U8 is externally connected to the VDD33_LDREF terminal. The connection between capacitor C33 and capacitor C31 is grounded. Interface 1 of chip U8 is electrically connected between capacitor C33 and capacitor C31. A capacitor C32 is connected in parallel outside capacitor C31. The LD_SDA terminal is connected to interface 46 of chip U13, the LD_SCL terminal is connected to interface 45 of chip U13, and the LD_EN terminal is connected to interface 44 of chip U13.

8. The control circuit for the white light interferometry 3D sensor system according to claim 7, characterized in that: The input / output module includes an input signal circuit, an output signal circuit, and a connector CN1.

9. The control circuit for the white light interferometry 3D sensor system according to claim 8, characterized in that: The input signal circuit includes chip U4; interfaces 5 and 7 of chip U4 are grounded, as are interfaces 2 and 4 of chip U4; interface 6 of chip U4 is connected to the TGR-DSI1 terminal, and interface 8 of chip U4 is connected to the TGR-DSI2 terminal; an external resistor R26 is connected between interface 6 of U4 and the TGR-DSI1 terminal; an external resistor R25 is connected between interface 8 of chip U4 and the TGR-DSI2 terminal; both resistors R26 and R25 are connected to the VDD33 terminal; interface 1 of chip U4, interface 3 of transistor Q1, interface 2 of transistor Q1, and the DSI2 terminal are connected in series; a resistor R27 is connected in parallel between interface 1 and interface 3 of transistor Q1; and interface 1 of chip U4 and... A capacitor C24 is connected between the two interfaces of chip U4. One end of capacitor C24 is electrically connected between the one interface of chip U4 and the three interfaces of transistor Q1. A resistor R28 and a diode D7 are connected in parallel outside the capacitor C24. The three interfaces of chip U4, transistor Q2, transistor Q2, and DSI1 are connected in series. A resistor R29 is connected in parallel between the one interface of transistor Q2 and the three interfaces of transistor Q2. A capacitor C25 is connected between the three interfaces of chip U4 and the four interfaces of chip U4. One end of capacitor C25 is electrically connected between the three interfaces of chip U4 and the three interfaces of transistor Q2. A resistor R30 and a diode D8 are connected in parallel outside the capacitor C25. The TGR-DSI1 terminal is connected to the 167 interface of the chip U13, and the TGR-DSI2 terminal is connected to the 168 interface of the chip U13. The DSI1 terminal is connected to interface 7 of connector CN1, the DSI2 terminal is connected to interface 6 of connector CN1, interfaces 1 and 8 of connector CN1 are grounded, and interface 2 of connector CN1 is connected to a 24V_IN terminal.

10. The control circuit for the white light interferometry 3D sensor system according to claim 9, characterized in that: The output signal circuit includes chip U5. Interfaces 2, 4, and 6 of chip U5 are all grounded. Interface 1 of chip U5 is connected to the TGR-DSO1 terminal via resistor R42. Interface 3 of chip U5 is connected to the TGR-DSO2 terminal via resistor R43. Interface 5 of chip U5 is connected to the TGR-DSO3 terminal via resistor R44. The connection between interface 1 of chip U5 and resistor R42 is externally connected to resistor R47. The connection between interface 3 of chip U5 and resistor R43 is externally connected to resistor R46. The connection between interface 5 of chip U5 and resistor R44 is externally connected to resistor R45. Resistors R45, R46, and R47 are all grounded. The following five components are connected in series: chip U5 (interface 16), transistor Q5 (interface 1), transistor Q5 (interface 2), fuse F2, and DSO1; chip U5 (interface 15) is connected to transistor Q5 (interface 3); chip U5 (interface 14), transistor Q6 (interface 1), transistor Q6 (interface 2), fuse F3, and DSO2; chip U5 (interface 13) is connected to transistor Q6 (interface 3); chip U5 (interface 12), transistor Q7 (interface 1), transistor Q7 (interface 2), fuse F4, and DSO3; chip U5 (interface 11) is connected to transistor Q7 (interface 3); and the three terminals of transistors Q5, Q6, and Q7 are all grounded. The connection between transistor Q7's pin 2 and fuse F4 is externally connected to resistor R41. Resistor R41 is connected to VCC 5V via diode D9. The connection between transistor Q6's pin 2 and fuse F3 is externally connected to resistor R40. Resistor R40 is electrically connected between resistor R41 and diode D9. The connection between transistor Q5's pin 2 and fuse F2 is externally connected to resistor R39. Resistor R39 is electrically connected between resistor R40 and diode D9. The connection between resistor R39 and diode D9 is externally connected to capacitor C27, which is grounded. The connection between diode D9 and VCC 5V is externally connected to capacitor C26, which is grounded. Fuse F1 is connected between capacitor C26 and capacitor C27. The connection between resistor R39 and diode D9 is externally connected to VCC_PULL. The TGR-DSO1 terminal is connected to interface 174 of chip U13, the TGR-DSO2 terminal is connected to interface 175 of chip U13, the TGR-DSO3 terminal is connected to interface 176 of chip U13, the DSO1 terminal is connected to interface 3 of connector CN1, the DSO2 terminal is connected to interface 4 of connector CN1, and the DSO3 terminal is connected to interface 5 of connector CN1.

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