Display panel

Abstract

The present invention relates to the technical field of display panels, and in particular to a display panel. The display panel comprises an array substrate and a color filter substrate arranged relative to each other, wherein the color filter substrate comprises a black matrix layer, and the black matrix layer comprises a plurality of light-blocking strips arranged crosswise; the array substrate comprises: a substrate, a plurality of TFT switching elements located on a surface of the substrate facing the color filter substrate, and a light-shielding layer located on a side of the TFT switching element facing away from the substrate, wherein the light-shielding layer comprises a plurality of light-shielding portions, wherein the orthographic projections of the light-shielding portions on the substrate are located within the orthographic projections of the light-shielding strips on the substrate, and the light-shielding portions and the black matrix layer can jointly block external light from irradiating the channel region of the TFT switching element, thereby preventing external light from irradiating the channel region of the TFT switching element and causing the TFT switching element to generate photo-induced leakage current. The provision of the light-shielding layer can also reduce the width of the light-blocking strips in the black matrix layer, thereby increasing the pixel aperture ratio of the display panel and improving the display effect of the display panel.

Description

Technical Field

[0001] The present invention relates to the technical field of display panels, and in particular to a display panel. Background Art

[0002] TFT-LCDs (TFT-Liquid Crystal Displays) use changes in the intensity of the electric field applied to the liquid crystal layer to alter the degree of rotation of the liquid crystal molecules, thereby controlling the transmittance of the liquid crystal layer to display images. Typically, a liquid crystal display panel includes an array substrate and a color filter substrate arranged relative to each other, and a liquid crystal layer located between the array substrate and the color filter substrate. The array substrate includes a plurality of TFT switches. The color filter substrate has a grid-like black matrix layer, which includes a plurality of light-blocking strips arranged vertically and crosswise. The black matrix layer not only prevents crosstalk between different colors of light but also blocks external light to prevent it from passing through the color filter substrate and irradiating the channel region of the TFT switch, thereby generating photo-induced leakage current in the TFT switch, thereby reducing the impact of photo-induced leakage current on the TFT switching characteristics. However, when the brightness of external light is too high, light will be diffracted by the edges of the light-blocking strips and irradiate the channel region of the TFT switch. To block external light, the width of the light-blocking strips is usually increased, but this also reduces the pixel aperture ratio, affecting the display quality of the display panel, especially for display panels with higher resolution requirements.

[0003] Therefore, current display panels still need to be improved. Summary of the Invention

[0004] The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

[0005] In order to achieve the above-mentioned objectives, the present invention provides a display panel, comprising an array substrate and a color film substrate arranged opposite to each other, and a liquid crystal layer located between the array substrate and the color film substrate, wherein the color film substrate has a black matrix layer, and the black matrix layer includes a plurality of cross-arranged light-blocking strips; the array substrate comprises: a substrate, a plurality of TFT switching elements located on the surface of the substrate facing the color film substrate, and a light-shielding layer located on the side of the TFT switching elements away from the substrate, the light-shielding layer including a plurality of light-shielding portions, and the orthographic projections of the light-shielding portions on the substrate are located within the orthographic projections of the light-blocking strips on the substrate.

[0006] In some embodiments, the display panel includes at least one pixel aperture region, and the TFT switching element is located outside the pixel aperture region; the array substrate further includes: a resin layer located between the light-shielding layer and the TFT switching element, the positive projection of the resin layer on the substrate covers the positive projection of the TFT switching element on the substrate, and at least partially coincides with the positive projection of the pixel aperture region on the substrate, the resin layer has through holes, and the positive projection of the through holes on the substrate is located within the positive projection of the drain of the TFT switching element on the substrate; at least one pixel electrode layer located on a surface of the resin layer facing away from the substrate, the pixel electrode layer is located in the pixel aperture region; a conductive member located within the through hole, and the pixel electrode layer is electrically connected to the drain of the TFT switching element through the conductive member.

[0007] In some embodiments, the light-shielding portion has a hollow region and a light-shielding border surrounding the hollow region, and the positive projection of the channel region of the TFT switching element on the substrate is located within the positive projection of the hollow region on the substrate.

[0008] In some embodiments, the width d of the hollow region satisfies l≤d<l + 2D3×tanθ; where l is the width of the channel region of the TFT switching element, θ is the maximum incident angle of external light on the surface of the display panel, and D3 is the distance between the surface of the light-shielding layer facing away from the substrate and the surface of the drain of the TFT switching element facing away from the substrate;

[0009] The width J of the light-blocking strip n is l + 2D n ×tanθ≤J n <l + 2D2×tanθ; where J n is the width of the light-blocking strip when the width of the hollow region is d n D n is the distance from an intersection position to the black matrix layer, and the intersection is the intersection of the longitudinal vertical line passing through the side edge of the channel region and the external light with an incident angle θ passing through the edge of the hollow region; D2 is the distance between the black matrix layer and the drain of the TFT switching element, and the longitudinal direction is perpendicular to the substrate;

[0010] The width of the light-shielding portion satisfies d n +2a≤L n ≤J n ; where L n is the width of the light-shielding portion when the width of the hollow region is d n a is the lateral width of the light-shielding border, and the lateral direction is parallel to the substrate.

[0011] In some embodiments, the light-shielding portion has a continuous structure. In the width direction of the light-blocking strip, the edge of the light-blocking strip is flush with the edge of the light-shielding portion; the width of the light-shielding portion satisfies l + 2D1×tanθ ≤ L < l + 2D2×tanθ; where L is the width of the light-shielding portion, l is the width of the channel region of the TFT switching element, θ is the maximum incident angle of external light on the surface of the display panel, D1 is the distance between the light-shielding layer and the drain of the TFT switching element, and D2 is the distance between the black matrix layer and the drain of the TFT switching element.

[0012] In some embodiments, the material of the light-shielding layer is metal, and the thickness of the light-shielding layer is

[0013] In some embodiments, the light-shielding layer further includes a plurality of light-blocking strips. One light-blocking strip is connected to at least one light-shielding portion, and the extending direction of the light-blocking strip is parallel to the gate line of the array substrate.

[0014] In some embodiments, the display panel includes a plurality of pixel opening areas, and the TFT switching element is located outside the pixel opening areas; the light-blocking strip is arranged corresponding to the gate line; the width of the light-blocking strip is less than or equal to the width of the gate line, and the orthographic projection of the light-blocking strip on the substrate at least partially overlaps with the orthographic projection of the gate line on the substrate.

[0015] In some embodiments, the display panel includes a plurality of pixel opening areas, and the TFT switching element is located outside the pixel opening areas; the array substrate includes two edge light-blocking strips near the edge of the array substrate, two edge gate lines, an intermediate light-blocking strip located between the two edge light-blocking strips, and an intermediate gate line located between the two edge gate lines; the orthographic projection of the intermediate light-blocking strip on the substrate is located between the orthographic projections of two adjacent intermediate gate lines on the substrate; the width of the edge light-blocking strip is less than or equal to the width of the edge gate line, and the orthographic projection of the edge light-blocking strip on the substrate at least partially overlaps with the orthographic projection of the edge gate line on the substrate.

[0016] In some embodiments, the material of the light-shielding layer is a black insulating material.

[0017] The technical solution of the present invention has the following advantages:

[0018] 1. In the display panel provided by the present invention, the light-shielding layer located in the array substrate and the black matrix layer in the color filter substrate jointly block external light, thereby preventing external light from reaching the channel region of the TFT switching element and generating photo-induced leakage current in the TFT switching element, thereby reducing the impact of photo-induced leakage current on the TFT switching characteristics. Furthermore, the provision of the light-shielding layer can reduce the width of the light-blocking strips in the black matrix layer, thereby increasing the pixel aperture ratio of the display panel and improving the display quality of the display panel.

[0019] 2. In the display panel provided by the present invention, the array substrate also includes a resin layer located between the light-shielding layer and the TFT switch element. The provision of the resin layer increases the distance between the light-shielding layer and the channel region of the TFT switch element. When the material of the light-shielding layer is metal and the light-shielding portion has a continuous structure, it can prevent the channel region of the TFT switch element from coupling with the light-shielding portion located above the channel region.

[0020] 3. In the display panel provided by the present invention, the shading portion has a hollow area and a shading frame surrounding the hollow area. The orthographic projection of the channel area of ​​the TFT switch element on the substrate is located within the orthographic projection of the hollow area on the substrate, so that the channel area of ​​the TFT switch element is exposed in the hollow area, which can prevent the channel area of ​​the TFT switch element from coupling with the metal shading portion located above the channel area. Therefore, there is no need to additionally set a resin layer between the shading layer and the TFT switch element, which not only simplifies the process, but also avoids the influence of the resin layer on the transmittance of the array substrate, thereby improving the transmittance of the array substrate.

[0021] 4. In the display panel provided by the present invention, the material of the shading layer is metal, and the shading layer also includes a plurality of shading strips, one shading strip is connected to at least one shading portion, and the shading strip is suitable for passing common electrode signals to avoid corrosion of the shading portion and extend the service life of the display panel.

[0022] 5. In the display panel provided by the present invention, the array substrate is a single-gateline array substrate, the width of the light-shielding strip is less than or equal to the width of the gateline, and the orthographic projection of the light-shielding strip on the substrate at least partially overlaps with the orthographic projection of the gateline on the substrate. This limitation not only reduces the parasitic capacitance (Cgc) generated between the light-shielding strip and the gateline, but also ensures that the light-shielding strip does not occupy the pixel opening area, thereby facilitating a larger pixel aperture ratio.

[0023] 6. In the display panel provided by the present invention, the array substrate is a dual-gate array substrate, the orthographic projection of the middle light-shielding strip on the substrate is located between the orthographic projections of two adjacent middle gate lines on the substrate; the width of the edge light-shielding strip is less than or equal to the width of the edge gate lines, and the orthographic projection of the edge light-shielding strip on the substrate at least partially overlaps with the orthographic projection of the edge gate lines on the substrate. The above limitation not only reduces the parasitic capacitance (Cgc) generated between the light-shielding strip and the gate lines, but also ensures that the light-shielding strip does not occupy the pixel opening area, which is conducive to obtaining a larger pixel aperture ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0025] Figure 1 A schematic diagram showing the width design of the light-blocking strips in the black matrix layer of a display panel;

[0026] Figure 2 A schematic diagram of the width design of the light-blocking strips in the black matrix layer provided in Example 1;

[0027] Figure 3 A schematic diagram of another design of the width of the light-blocking strips in the black matrix layer provided in Example 1;

[0028] Figure 4 Schematic diagram of the width design of the light-blocking strips in the black matrix layer provided in Example 2;

[0029] Figure 5 A schematic structural diagram of a light shielding layer in a single-grid array substrate when the material of the light shielding layer is metal;

[0030] Figure 6 A schematic structural diagram of a light shielding layer in a dual-gate array substrate when the material of the light shielding layer is metal;

[0031] Reference numerals:

[0032] 1-substrate; 2-TFT switching element; 21-gate; 22-gate insulating layer; 23-active layer; 24-drain; 25-source; 3-light-shielding layer; 31-light-shielding portion; 32-light-shielding strip; 33-edge light-shielding strip; 34-middle light-shielding strip; 4-light-blocking strip; 5-resin layer; 51-through hole; 6-pixel electrode layer; 71-first protective layer; 72-second protective layer; 8-common electrode layer; 9-gate line; 91-edge gate line; 92-middle gate line; 1′-substrate; 2′-TFT switching element; 21′-gate; 22′-gate insulating layer; 23′-active layer; 24′-drain; 25′-source; 6′-pixel electrode layer; 7′-protective layer; 8′-common electrode layer. DETAILED DESCRIPTION

[0033] The following embodiments of the technical solution of the present application are described in detail. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application. All other embodiments obtained by persons of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0034] As described in the background art, in order to block external light, the width of the light-blocking strips is usually increased, but this reduces the pixel aperture ratio and affects the display effect of the display panel.

[0035] For details, see Figure 1 The array substrate in the related art includes: a substrate 1′; a plurality of TFT switching elements 2′ and a plurality of pixel electrode layers 6′ located on the side of the substrate facing the color film substrate, the TFT switching element including a gate electrode 21′, a gate insulating layer 22′ and an active layer 23′ stacked in sequence, a drain electrode 24′ and a source electrode 25′ provided on the surface of the active layer facing away from the substrate, a portion of the gate insulating layer is located on the surface of the gate electrode facing away from the substrate, and another portion is located on the surface of the substrate on the side of the gate electrode, the pixel electrode layer is located outside the TFT switching element and on the surface of the gate insulating layer facing away from the substrate; a protective layer 7′ covering the entire surface of the TFT switching element and the pixel electrode layer; and a common electrode layer 8′ located on the surface of the protective layer facing away from the substrate.

[0036] To prevent external light from reaching the channel region of the TFT switch element, the minimum width of the light-blocking strip located above the TFT switch element must be l + 2D2 × tanθ, where l is the width of the channel region, D2 is the vertical distance between the black matrix layer and the drain electrode of the TFT switch element, and θ is the maximum angle of incidence of external light on the display panel surface. The maximum angle of incidence θ is a constant value within a display panel, and l and D2 have the same unit. The relatively large width of the light-blocking strip affects the size of the pixel opening area, thereby reducing the pixel aperture ratio of the display panel.

[0037] Specifically, a display panel is provided as a comparative example: the display panel provided in this comparative example adopts Figure 1The structure has a sub-pixel size of 21μm*63μm, the spacing between the black matrix layer and the drain electrode in the TFT switch element is 2.71μm to 4.71μm, and the distance from the light-blocking strip in the black matrix layer to the outside of the channel area (i.e., the minimum lateral distance from the edge of the light-blocking strip to the edge of the channel area) is 9.06μm. In this case, the TFT switch element can be prevented from generating light-induced leakage current. When the array substrate in this comparative example is a single-gate array substrate, the aperture ratio of the display panel is 52.3%; when the array substrate in this comparative example is a dual-gate array substrate, the aperture ratio of the display panel is 51.29%.

[0038] Based on this, the present invention provides a display panel, comprising an array substrate and a color filter substrate arranged opposite to each other, and a liquid crystal layer located between the array substrate and the color filter substrate; Figure 2-Figure 4 The color filter substrate has a grid-shaped black matrix layer, and the black matrix layer includes a plurality of light-blocking strips 4 arranged vertically and crosswise; the array substrate includes a substrate 1, a plurality of TFT switch elements 2 spaced apart from each other and located on the surface of the substrate 1 facing the color filter substrate, and a light-shielding layer 3 located on the side of the TFT switch element 2 facing away from the substrate 1, the light-shielding layer 3 includes a plurality of light-shielding portions 31, and the orthographic projection of the light-shielding portion 31 on the substrate 1 is located within the orthographic projection of the light-shielding strip 4 on the substrate 1.

[0039] It should be noted that "the orthographic projection of the light-shielding portion on the substrate is located within the orthographic projection of the light-blocking strip on the substrate" means that the light-shielding portion 31 is arranged opposite to the TFT switch element 2, the width of the light-shielding portion 31 is less than or equal to the width of the light-blocking strip 4, and the width direction of the light-shielding portion is the same as the width direction of the light-blocking strip.

[0040] In the aforementioned display panel, the light-shielding layer in the array substrate and the black matrix layer in the color filter substrate jointly block external light, thereby preventing light from reaching the channel region of the TFT switching elements and generating photo-induced leakage current in the TFT switching elements. This, in turn, reduces the impact of this photo-induced leakage current on the TFT switching characteristics. Furthermore, the provision of the light-shielding layer can reduce the width of the light-blocking strips in the black matrix layer, thereby increasing the pixel aperture ratio of the display panel and enhancing the display quality.

[0041] Specifically, the display panel includes at least one pixel opening area, which corresponds to the area surrounded by the light-blocking strips 4 in the black matrix layer. The pixel opening area is provided with a pixel electrode layer 6, and the TFT switch element 2 is located outside the pixel opening area.

[0042] For details, see Figure 2-Figure 4 , the TFT switch element 2 includes:

[0043] A gate 21 is located on a surface of the substrate 1 facing the color filter substrate and outside the pixel opening area. The gate 21 is suitable for connecting to the gate line 9 in the array substrate.

[0044] a gate insulating layer 22 covering the entire surface, wherein a portion of the gate insulating layer 22 is located on a surface of the gate 21 facing away from the substrate 1 , and another portion of the gate insulating layer 22 is located on a surface of the substrate at a side of the gate;

[0045] an active layer 23 , the active layer 23 being located on a surface of the gate insulating layer 22 facing away from the substrate 1 and outside the pixel opening region;

[0046] a drain electrode 24 , wherein at least a portion of the surface of the drain electrode 24 is located on a surface of the active layer 23 facing away from the substrate 1 , the drain electrode 24 is close to an edge of the active layer 23 and is located outside the pixel opening region, and the drain electrode 24 is electrically connected to the pixel electrode layer 6 ;

[0047] A source electrode 25, at least part of the surface of the source electrode 25 is located on the side surface of the active layer 23 facing away from the substrate 1, the source electrode 25 is close to the edge of the active layer 23 and is located outside the pixel opening area, and the source electrode 25 is suitable for connecting to the data line in the array substrate; the drain electrode 24 and the source electrode 25 are spaced apart from each other, and the orthographic projection of the channel region of the TFT switch element 2 on the surface of the active layer 23 coincides with the orthographic projection of the spacing area between the drain electrode 24 and the source electrode 25 on the surface of the active layer 23, that is, the width of the channel region is equal to the distance between the drain electrode 24 and the source electrode 25.

[0048] The display panel in this embodiment is a liquid crystal display panel, which also includes a backlight module (not shown) located on the surface of the array substrate facing away from the color film substrate; the array substrate is a TFT array substrate, and the substrate 1 in the array substrate is a transparent substrate, such as glass.

[0049] Example 1

[0050] See also Figure 2 The light shielding portion 31 has a continuous structure, that is, the orthographic projection of the light shielding portion 31 on the substrate covers the channel region of the TFT switch element, and in the width direction of the light shielding bar 4, the edge of the light shielding bar 4 is flush with the edge of the light shielding portion 31.

[0051] Specifically, the width L of the light-shielding portion 31 satisfies the condition: l + 2D1×tanθ ≤ L < l + 2D2×tanθ; where L is the width of the light-shielding portion 31, l is the width of the channel region, D1 is the vertical distance between the light-shielding layer 3 and the drain 24 of the TFT switch 2, D2 is the vertical distance between the black matrix layer and the drain 24 of the TFT switch 2, and θ is the maximum incident angle of external light on the surface of the display panel. L, l, D1, and D2 have the same unit. It can be seen that the width of the light-blocking strip 4 in this embodiment is smaller than the minimum width of the light-blocking strip 4 in the related art. Therefore, the size of the pixel aperture region can be increased, thereby improving the pixel aperture ratio of the display panel.

[0052] Optionally, the width L of the light-shielding portion 31 = l + 2D1×tanθ. At this time, the light-blocking strip 4 has a smaller width, and the pixel aperture ratio of the display panel is the largest.

[0053] See Figure 2 , the pixel electrode layer 6 is located on the surface of the gate insulating layer 22 facing away from the substrate 1 and is spaced apart from the active layer 23. Both ends of the drain 24 of the TFT switch 2 cover a part of the surface of the active layer 23 and a part of the surface of the pixel electrode layer 6. The material of the pixel electrode layer 6 is a transparent conductive material, such as indium tin oxide (ITO), etc.

[0054] See Figure 2 , the array substrate further includes:

[0055] A whole-surface first protective layer 71 that covers the TFT switch 2 and the pixel electrode layer 6. The light-shielding layer 3 is located on the surface of the first protective layer 71 facing away from the substrate 1;

[0056] A whole-surface second protective layer 72 that covers the light-shielding layer 3 and the first protective layer 71 on the side of the light-shielding layer 3;

[0057] A common electrode layer 8 that is located on the surface of the second protective layer 72 facing away from the substrate 1. The material of the common electrode layer 8 is a transparent conductive material, such as indium tin oxide (ITO), etc.

[0058] It should be noted that the "coverage" described in this application means that the covering object above directly contacts the covered object below. In this application, the position of the TFT switch 2 corresponds to the positions of the gate 21, the active layer 23, the drain 24, and the source 25, but does not correspond to the position of the gate insulating layer 22.

[0059] In this embodiment, the material of the light-shielding layer is a black insulating material, and the black insulating material includes but is not limited to CrO x、CrN x , black resin material, black resin material includes but is not limited to light plastic black resin polymer; or, the material of the light shielding layer 3 is metal, such as Mo, Mo / Al alloy, Mo / Al / Mo alloy, etc., with a thickness of The metal material of the above thickness can meet the light shielding requirements; for example, the thickness of the light shielding layer 3 can be or

[0060] Optional, see Figure 3 When the light shielding layer 3 is made of metal, the array substrate further includes a resin layer 5 located between the light shielding layer 3 and the TFT switch element 2, with the resin layer 5 at least covering the TFT switch element 2. The provision of the resin layer 5 increases the vertical distance between the light shielding layer 3 and the channel region of the TFT switch element 2, thereby preventing coupling between the channel region of the TFT switch element 2 and the light shielding portion 31 located above the channel region. This protects the channel current from being affected by the common electrode signal in the display panel, thereby preventing insufficient charging from affecting normal display.

[0061] Specifically, the thickness of the resin layer 5 is 1.3 μm to 2.0 μm. For example, the thickness of the resin layer 5 may be 1.3 μm, 1.5 μm, 1.6 μm or 2.0 μm.

[0062] In one embodiment, the orthographic projection of the resin layer 5 on the substrate 1 covers the orthographic projection of the TFT switch element on the substrate, and at least partially overlaps with the orthographic projection of the pixel opening area on the substrate, that is, the resin layer 5 covers the TFT switch element 2 and extends to the pixel opening area. It should be noted that since the resin layer 5 has a relatively large thickness, when the resin layer 5 only covers the TFT switch element 2, the subsequently deposited pixel electrode layer 6 is likely to be disconnected on the side of the resin layer 5, and the normal function of the pixel electrode layer 6 cannot be guaranteed. Extending the resin layer 5 to the pixel opening area can avoid the pixel electrode layer 6 from being disconnected on the side of the resin layer 5, ensuring the normal function of the pixel electrode layer 6, and thus ensuring that the display panel can operate normally. Optionally, the orthographic projection of the area of ​​the resin layer located in the pixel opening area on the substrate overlaps with the orthographic projection of the pixel opening area on the substrate.

[0063] Furthermore, when the resin layer 5 covers the TFT switch element 2 and extends to the pixel opening area, the resin layer 5 has a through hole 51, and the orthographic projection of the through hole on the substrate is located within the orthographic projection of the drain electrode of the TFT switch element on the substrate, that is, the through hole 51 exposes part of the surface of the drain electrode 24 of the TFT switch element 2; at this time, the pixel electrode layer 6 is located on the side surface of the resin layer 5 away from the substrate 1, and the pixel electrode layer 6 is electrically connected to the drain electrode of the TFT switch element through the conductive member in the through hole. The conductive member can be the same material as the pixel electrode layer, and the first protective layer 71 covers the pixel electrode layer 6 and the resin layer 5 located on the surface of the TFT switch element 2.

[0064] In this embodiment, when the light shielding layer 3 is made of a black insulating material, the light shielding portion located above the channel region will not couple with the channel region of the TFT switch element, and therefore the array substrate does not need to include the resin layer 5. In this case, the light shielding portion 31 is closer to the channel region, achieving a light-blocking effect with a shorter length. The width of the light-blocking strips 4 is also shortened, thereby increasing the pixel aperture ratio of the display panel.

[0065] This embodiment provides a specific display panel. The display panel adopts Figure 3 The structure contains a light-shielding portion and a resin layer, and the sub-pixel size, the maximum incident angle of external light on the surface of the display panel, and the distance from the array substrate to the black matrix layer are the same as those in the comparative example. The spacing between the light-shielding layer and the drain electrode in the TFT switch element is 1.3μm to 3.3μm, and the distance from the light-shielding portion to the outside of the channel area (that is, the minimum lateral distance from the edge of the light-shielding portion to the edge of the channel area) is 6.7μm. The edge of the light-blocking strip is flush with the edge of the light-shielding portion. At this time, it is possible to prevent the TFT switch element from generating photo-induced leakage current. When the array substrate in this embodiment is a single-gate array substrate, the aperture ratio of the display panel is 55.1%; when the array substrate in this embodiment is a dual-gate array substrate, the aperture ratio of the display panel is 52.33%. It can be seen that compared with the comparative example, the display panel provided in this embodiment has a larger pixel aperture ratio.

[0066] Example 2

[0067] See also Figure 4 The shading portion 31 has a hollow area and a shading frame surrounding the hollow area. The orthographic projection of the channel area of ​​the TFT switch element on the substrate is located within the orthographic projection of the hollow area on the substrate, that is, the hollow area exposes the channel area of ​​the TFT switch element 2.

[0068] Specifically, the width of the hollow area satisfies l≤d<l + 2D3×tanθ; where d is the width of the hollow area, l is the width of the channel area of the TFT switch 2, θ is the maximum incident angle of external light on the surface of the display panel, and D3 is the vertical distance between the surface of the light shielding layer 3 facing away from the substrate 1 and the surface of the drain 24 of the TFT switch 2 facing away from the substrate 1;

[0069] The width of the light blocking strip 4 satisfies l + 2D n ×tanθ≤J n <l + 2D2×tanθ; where J n is the width of the light blocking strip 4 when the width of the hollow area is d n D is the vertical distance from an intersection point to the black matrix layer, and the intersection point is the intersection of the longitudinal vertical line passing through the side edge of the channel area and the external light with an incident angle θ passing through the edge of the hollow area; D2 is the vertical distance between the black matrix layer and the drain 24 of the TFT switch 2, and the longitudinal direction is perpendicular to the substrate; n [[ID=​​​​​​​​​​​​​​​​​​​​​​​​In this embodiment, the light shielding portion 31 and the light blocking strip 4 need to cooperate with each other to prevent external light from irradiating the channel area from the outside of the light shielding portion 31, and also to prevent external light from irradiating the channel area from the hollow area of ​​the light shielding portion 31. For example, when the width of the hollow area is first determined, the minimum width of the light blocking strip 4 at this time needs to be determined immediately to ensure that external light does not irradiate the channel area from the hollow area. Subsequently, the width of the light shielding portion 31 is determined based on the width of the hollow area and the width of the light blocking strip 4 to ensure that the outer edge of the light shielding portion 31 is located between the edge of the hollow area and the edge of the light blocking strip 4, thereby ensuring the strength of the light shielding frame.

[0073] Furthermore, the lateral width a of the light-shielding frame is 2 μm to 4 μm to ensure the strength of the light-shielding frame. For example, the lateral width a of the light-shielding frame can be 2.0 μm, 2.5 μm, 3.0 μm, 3.5 μm or 4 μm.

[0074] Optionally, the width of the hollow area is the same as the width of the channel area of ​​the TFT switch element 2, and the width of the light-blocking strip 4 is L=l+2D4×tanθ, where D4 is the vertical distance between the light-shielding portion and the black matrix layer. At this time, the light-blocking strip 4 has a smaller width, and the pixel opening ratio of the display panel is maximized.

[0075] See also Figure 4 The pixel electrode layer 6 is located on the surface of the gate insulating layer 22 facing away from the substrate 1, and is spaced apart from the active layer 23. The two ends of the drain electrode 24 of the TFT switch element 2 respectively cover part of the surface of the active layer 23 and part of the surface of the pixel electrode layer 6. The material of the pixel electrode layer 6 is a transparent conductive material, such as indium tin oxide (ITO).

[0076] In this embodiment, the display panel further includes:

[0077] a first protective layer 71 covering the entire surface of the TFT switch element 2 and the pixel electrode layer 6 , wherein the light shielding layer 3 is located on a surface of the first protective layer 71 facing away from the substrate 1 ;

[0078] a second protective layer 72 covering the entire surface of the light shielding layer 3 and the first protective layer 71 on the side of the light shielding layer 3;

[0079] The common electrode layer 8 is located on a surface of the second protective layer 72 facing away from the substrate 1 . The common electrode layer 8 is made of a transparent conductive material, such as indium tin oxide (ITO).

[0080] In this embodiment, the material of the light shielding layer is a black insulating material, which includes but is not limited to CrO x、CrN x , black resin material, black resin material includes but is not limited to light plastic black resin polymer; or, the material of the light shielding layer 3 is metal, such as Mo, Mo / Al alloy, Mo / Al / Mo alloy, etc., with a thickness of The metal material of the above thickness can meet the light shielding requirements; for example, the thickness of the light shielding layer 3 can be or

[0081] This embodiment provides a specific display panel. The display panel adopts Figure 4 The structure is that it contains a light-shielding portion, and the light-shielding portion has a hollow area, and the sub-pixel size, the maximum incident angle of external light on the surface of the display panel, and the distance from the array substrate to the black matrix layer are the same as those in the comparative example. The distance between the black matrix layer and the light-shielding layer is 3.35μm, the lateral distance from the edge of the hollow area to the edge of the channel area is 0.8μm, the minimum lateral distance from the edge of the light-shielding portion to the edge of the channel area is 8μm, and the lateral distance from the edge of the light-blocking strip in the black matrix layer to the edge of the channel area is 9.0μm. At this time, it is possible to avoid the generation of photo-induced leakage current by the TFT switch element. When the array substrate in this embodiment is a single-gate array substrate, the aperture ratio of the display panel is 52.8%; when the array substrate in this embodiment is a dual-gate array substrate, the aperture ratio of the display panel is 52.33%. It can be seen that compared with the comparative example, the display panel provided in this embodiment has a larger pixel aperture ratio.

[0082] In Example 1 and Example 2, when the material of the light-shielding layer 3 is metal, the light-shielding layer also includes at least one light-shielding strip, one of the light-shielding strips is connected to at least one of the light-shielding portions, an extension direction of the light-shielding strip is parallel to the gate line of the array substrate, and the light-shielding strip is suitable for passing common electrode signals to avoid corrosion of the light-shielding portion, thereby enabling the normal operation of the display panel and extending the service life of the display panel.

[0083] Specifically, the width of the light shielding strip is 2 μm to 5 μm. For example, the width of the light shielding strip can be 2.0 μm, 2.5 μm, 3.0 μm, 3.5 μm, 4.0 μm, 4.5 μm or 5.0 μm.

[0084] For further information, see Figure 4 When the array substrate is a single-gate line array substrate, the shading strips are arranged corresponding to the gate lines, the number of the shading strips 32 is the same as the number of the gate lines 9, and a plurality of shading portions 31 are connected to one side of the shading strip 32; the orthographic projection of the shading strip 32 on the substrate 1 can completely overlap, completely not overlap, or partially overlap with the orthographic projection of the gate line 9 on the substrate 1.

[0085] It should be noted that when the width of the shading strip 32 is the same as the width of the gate line 9, the orthographic projection of the shading strip 32 on the substrate 1 completely overlaps with the orthographic projection of the gate line 9 on the substrate 1, and a large parasitic capacitance (Cgc) will be generated between the shading strip 32 and the gate line 9, while the orthographic projection of the shading strip 32 on the substrate 1 does not overlap with the orthographic projection of the gate line 9 on the substrate 1 at all, and the shading strip 32 may occupy the pixel opening area, affecting the pixel aperture ratio of the display panel. Therefore, optionally, the width of the shading strip 32 is less than or equal to the width of the gate line 9, and the orthographic projection of the shading strip 32 on the substrate at least partially overlaps with the orthographic projection of the gate line 9 on the substrate. The above limitation can not only reduce the size of the parasitic capacitance (Cgc) generated between the shading strip 32 and the gate line 9, but also ensure that the shading strip 32 does not occupy the pixel opening area, which is conducive to obtaining a larger pixel aperture ratio.

[0086] Specifically, when the width of the shading strip 32 is the same as the width of the gate line 9, the orthographic projection of the shading strip 32 on the substrate 1 partially overlaps with the orthographic projection of the gate line 9 on the substrate 1, and the shading strip 32 is not located in the pixel opening area; or, the width of the shading strip 32 is smaller than the width of the gate line 9, and the orthographic projection of the shading strip 32 on the substrate 1 is located within the orthographic projection of the gate line 9 on the substrate 1.

[0087] For further information, see Figure 5 When the array substrate is a dual-gate line array substrate, the array substrate includes two edge shading strips 33 close to the edge of the array substrate, two edge gate lines 91, an intermediate shading strip 34 located between the two edge shading strips 33, and an intermediate gate line 92 located between the two edge gate lines 91. One side of the edge shading strip 33 is connected to a plurality of the shading portions 31, and the two opposite sides of the intermediate shading strip 34 are both connected to a plurality of the shading portions 31. The number of shading strips is less than the number of gate lines.

[0088] For the edge shading strip 33, the orthographic projection of the edge shading strip 33 on the substrate 1 can completely overlap, completely not overlap, or partially overlap with the orthographic projection of the edge gate line 91 on the substrate 1. It should be noted that when the width of the edge shading strip 33 is the same as the width of the edge gate line 91, the orthographic projection of the edge shading strip 33 on the substrate 1 completely overlaps with the orthographic projection of the edge gate line 91 on the substrate 1, and a large parasitic capacitance (Cgc) will be generated between the edge shading strip 33 and the edge gate line 91. However, the orthographic projection of the edge shading strip 33 on the substrate 1 does not completely overlap with the orthographic projection of the edge gate line 91 on the substrate 1, and the edge shading strip 33 may occupy the pixel opening area, affecting the pixel aperture ratio of the display panel. Therefore, optionally, the width of the edge shading strip 33 is less than or equal to the width of the edge gate line 91, and the orthographic projection of the edge shading strip 33 on the substrate at least partially overlaps with the orthographic projection of the edge gate line 91 on the substrate. The above definition can not only reduce the parasitic capacitance (Cgc) generated between the edge light shielding strip 33 and the edge gate line 91, but also ensure that the edge light shielding strip 33 does not occupy the pixel opening area, which is conducive to obtaining a larger pixel aperture ratio.

[0089] Specifically, when the width of the edge shading strip 33 is the same as the width of the edge gate line 91, the orthographic projection of the edge shading strip 33 on the substrate 1 partially overlaps with the orthographic projection of the edge gate line 91 on the substrate 1, and the edge shading strip 33 is not located in the pixel opening area; or, the width of the edge shading strip 33 is smaller than the width of the edge gate line 91, and the orthographic projection of the edge shading strip 33 on the substrate 1 is located within the orthographic projection of the edge gate line 91 on the substrate 1.

[0090] For the middle light shielding strip 34, the orthographic projection of the middle light shielding strip 34 on the substrate 1 can be located between the orthographic projections of two adjacent middle grid lines 92 on the substrate 1, or can be located not only between the orthographic projections of two adjacent middle grid lines 92 on the substrate 1, but also within or even overlapped with the orthographic projections of one or two middle grid lines 92 on the substrate 1, and there is no pixel opening area between the two grid lines 9. Optionally, as Figure 5 As shown, the orthographic projection of the intermediate light-shielding strip 34 on the substrate 1 is located between the orthographic projections of two adjacent intermediate gate lines 92 on the substrate 1 , and the intermediate light-shielding strip 34 is not located in the pixel opening area.

[0091] Specifically, the array substrate includes a first gate line to an N-th gate line arranged in sequence along a first direction, N is an even number greater than or equal to 4, and n is an even number greater than or equal to 2 and less than or equal to N-2. The pixel electrode layer and the TFT switch element of the array substrate are both located between the n-1-th gate line and the n-th gate line, and between the N-1-th gate line and the N-th gate line; the light shielding layer includes a first light shielding strip to an M-th light shielding strip arranged in sequence along the first direction, M is an integer greater than or equal to 1, and m is an integer greater than or equal to 2 and less than or equal to M-1; the orthographic projection of the m-th light shielding strip on the substrate is located between the orthographic projection of the n-th gate line on the substrate and the orthographic projection of the n+1-th gate line on the substrate. The above definition can not only reduce the size of the parasitic capacitance (Cgc) generated between the intermediate light shielding strip 34 and the intermediate gate line 92, but also ensure that the intermediate light shielding strip 34 does not occupy the pixel opening area, which is conducive to obtaining a larger pixel aperture ratio.

[0092] It should be noted that, when the array substrate is a dual-grid array substrate, the setting of the shading strips can also be the same as that described for the single-grid array substrate, the number of the shading strips is the same as the number of the gate lines, and a plurality of the shading portions are connected to one side of the shading strip; the orthographic projection of the shading strip on the substrate can completely overlap, completely not overlap, or partially overlap with the orthographic projection of the gate line on the substrate.

[0093] In this embodiment, when the material of the light shielding layer 3 is a black insulating material, the light shielding layer may only include a plurality of light shielding portions without light shielding strips.

[0094] It should be understood that the structure of the display panel includes but is not limited to the above structures provided in Example 1 and Example 2.

[0095] The terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0096] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0097] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A display panel comprising an array substrate and a color filter substrate disposed opposite each other, and a liquid crystal layer located between the array substrate and the color filter substrate, wherein the color filter substrate has a black matrix layer, the black matrix layer comprising a plurality of cross-arranged light-blocking strips; characterized in that: The array substrate includes: a substrate; a plurality of TFT switching elements located on one surface of the substrate facing the color filter substrate; a light-shielding layer located on a side of the TFT switching element背离 the substrate, the light-shielding layer includes a plurality of light-shielding portions, a positive projection of the light-shielding portion on the substrate is located within a positive projection of the light-blocking strip on the substrate, the light-shielding layer further includes a plurality of light-shielding strips, one light-shielding strip is connected to at least one light-shielding portion, and an extending direction of the light-shielding strip is parallel to a gate line of the array substrate; wherein, the display panel includes a plurality of pixel opening areas, the TFT switching elements are located outside the pixel opening areas; the light-shielding strips are correspondingly arranged with the gate lines; a width of the light-shielding strip is less than or equal to a width of the gate line, and a positive projection of the light-shielding strip on the substrate at least partially overlaps with a positive projection of the gate line on the substrate.

2. The display panel according to claim 1, wherein: The array substrate further includes: a resin layer located between the light-shielding layer and the TFT switching element, a positive projection of the resin layer on the substrate covers a positive projection of the TFT switching element on the substrate, and at least partially coincides with a positive projection of the pixel opening area on the substrate, the resin layer has through holes, and a positive projection of the through holes on the substrate is located within a positive projection of a drain electrode of the TFT switching element on the substrate; at least one pixel electrode layer located on a surface of the resin layer背离 the substrate, the pixel electrode layer is located in the pixel opening area; a conductive member located in the through hole, and the pixel electrode layer is electrically connected to the drain electrode of the TFT switching element through the conductive member.

3. The display panel according to claim 1, wherein: The light-shielding portion has a hollow area and a light-shielding border surrounding the hollow area, and a positive projection of a channel area of the TFT switching element on the substrate is located within a positive projection of the hollow area on the substrate.

4. The display panel according to claim 3, wherein: A width d of the hollow area satisfies l≤d<l + 2D3×tanθ; where l is a width of the channel area of the TFT switching element, θ is a maximum incident angle of external light on a surface of the display panel, and D3 is a distance between a surface of the light-shielding layer背离 the substrate and a surface of the drain electrode of the TFT switching element背离 the substrate; The width J of the light blocking strip n is l + 2D n × tanθ ≤ J n < l + 2D2 × tanθ; where J n is the width of the light blocking strip when the width of the hollow area is d n and D n is the distance between an intersection position and the black matrix layer, and the intersection is the intersection of the longitudinal vertical line passing through the side edge of the channel region and the external light with the incident angle θ passing through the edge of the hollow area; D2 is a distance between the black matrix layer and the drain electrode of the TFT switching element, and the longitudinal direction is a direction perpendicular to the substrate; The width of the light shielding portion satisfies d n +2a≤L n ≤J n Where, L n When the width of the hollow area is d n When , a is the width of the light-shielding portion, and a is the lateral width of the light-shielding frame, where the lateral direction is a direction parallel to the substrate.

5. The display panel according to claim 2, wherein: The light-shielding portion has a continuous structure, and in a width direction of the light-blocking strip, an edge of the light-blocking strip is flush with an edge of the light-shielding portion; a width of the light-shielding portion satisfies l + 2D1×tanθ≤L<l + 2D2×tanθ; where L is a width of the light-shielding portion, l is a width of the channel area of the TFT switching element, θ is a maximum incident angle of external light on the surface of the display panel, D1 is a distance between the light-shielding layer and the drain electrode of the TFT switching element, and D2 is a distance between the black matrix layer and the drain electrode of the TFT switching element.

6. The display panel according to any one of claims 2 to 5, characterized in that: The material of the light shielding layer is metal, and the thickness of the light shielding layer is 7. The display panel according to claim 1, wherein: The display panel includes a plurality of pixel opening areas, and the TFT switch elements are located outside the pixel opening areas; the array substrate includes two edge light shielding strips near the edge of the array substrate, two edge gate lines, an intermediate light shielding strip located between the two edge light shielding strips, and an intermediate gate line located between the two edge gate lines; the orthographic projection of the intermediate light shielding strip on the substrate is located between the orthographic projections of two adjacent intermediate gate lines on the substrate; The width of the edge light-shielding strip is less than or equal to the width of the edge gate line, and the orthographic projection of the edge light-shielding strip on the substrate at least partially overlaps with the orthographic projection of the edge gate line on the substrate.

8. The display panel according to any one of claims 1, 3 to 5, characterized in that: The material of the light shielding layer is black insulating material.

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