A liquid crystal grating and a display device

Abstract

Embodiments of the present application provide a liquid crystal grating and a display device. The driving circuit includes a first transistor and is electrically connected to a first electrode. A first signal line and a second signal line are electrically connected to the driving circuit. The change frequency of the signal transmitted by the first signal line is greater than that of the signal transmitted by the second signal line. The minimum distance between the positive projection of the second signal line on the substrate and the driving circuit is less than the minimum distance between the positive projection of the first signal line on the substrate and the positive projection of the driving circuit on the substrate; and / or, the switching frequency of the first transistor is greater than that of at least one other transistor in the transistor group, and the minimum distance between the positive projection of the first transistor on the substrate and the signal line group is greater than the minimum distance between the positive projection of at least one other transistor on the substrate and the signal line group. The liquid crystal grating provided by the present application has a good charging effect and can ensure the performance of the liquid crystal grating.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a liquid crystal grating and a display device.

Background Art

[0002] With the development of computer technology and display technology, virtual reality (VR) technology for experiencing a virtual world through a computer simulation system, augmented reality (AR) technology for integrating display content into a real environment background, mixed reality (MR) technology, and naked-eye three-dimensional and other stereoscopic displays.

[0003] The development of the above technologies depends on the reliability of the display performance of the display device. In the display devices required for the above technologies, a liquid crystal grating module is usually provided to adjust the light propagation direction to form left and right eye images, thereby realizing three-dimensional display. The reliability of the liquid crystal grating affects the experience of stereoscopic display. Among them, an important factor affecting the reliability of the liquid crystal grating is whether the electrodes in the liquid crystal grating are fully charged.

[0004]

Content of the Application

[0005] In view of this, embodiments of this application provide a liquid crystal grating and a display device to solve the above technical problems.

[0006] In a first aspect, embodiments of this application provide a liquid crystal grating, including a substrate, a first electrode, a driving circuit, and a signal line group; the first electrode is disposed on the substrate; the driving circuit is electrically connected to the first electrode and the driving circuit includes a transistor group, and the transistor group includes a first transistor; the signal line group is disposed on the substrate, the signal line group includes a first signal line and a second signal line, and the first signal line and the second signal line are electrically connected to the driving circuit;

[0007] Wherein, in at least one first state, the change frequency of the signal transmitted by the first signal line is greater than the change frequency of the signal transmitted by the second signal line; the minimum distance between the positive projection of the second signal line on the substrate and the driving circuit is less than the minimum distance between the positive projection of the first signal line on the substrate and the positive projection of the driving circuit on the substrate; and / or,

[0008] In at least one first state, the switching frequency of the first transistor is greater than the switching frequency of at least one other transistor in the transistor group; the minimum distance between the positive projection of the first transistor on the substrate and the signal line group is greater than the minimum distance between the positive projection of at least one other transistor on the substrate and the signal line group.

[0009] In a second aspect, an embodiment of the present application provides a display device, including the liquid crystal grating provided in the first aspect.

[0010] The liquid crystal grating and the display device provided by the embodiments of the present application have good charging effects and can ensure the performance of the liquid crystal grating.

Description of the Drawings

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0012] Figure 1 It is a schematic diagram of the working principle of a liquid crystal grating provided by an embodiment of the present application;

[0013] Figure 2 It is a schematic diagram of the structure of a liquid crystal grating provided by an embodiment of the present application;

[0014] Figure 3 For Figure 2 the schematic diagram along the M1-M2 direction in

[0015] Figure 4 It is an equivalent schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0016] Figure 5 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0017] Figure 6 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0018] Figure 7 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0019] Figure 8 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0020] Figure 9 It is an equivalent circuit diagram of a driving circuit in a liquid crystal grating provided by an embodiment of the present application;

[0021] Figure 10 For Figure 9 a timing diagram of the driving circuit shown;

[0022] Figure 11 It is an equivalent circuit diagram of a driving circuit in a liquid crystal grating provided by an embodiment of the present application;

[0023] Figure 12 is Figure 11 a timing diagram of the driving circuit shown;

[0024] Figure 13 is an equivalent circuit diagram of the driving circuit in a liquid crystal grating provided by an embodiment of the present application;

[0025] Figure 14 is Figure 13 a timing diagram of the driving circuit shown;

[0026] Figure 15 is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0027] Figure 16 is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0028] Figure 17 is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0029] Figure 18 is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0030] Figure 19 is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0031] Figure 20 is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0032] Figure 21 is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0033] Figure 22 is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0034] Figure 23 is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0035] Figure 24 is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0036] Figure 25 is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0037] Figure 26 is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0038] Figure 27 is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0039] Figure 28 A partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0040] Figure 29 A partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0041] Figure 30 A partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0042] Figure 31 A partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0043] Figure 32 A partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0044] Figure 33 A partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application;

[0045] Figure 34 Schematic diagram of the arrangement of scan lines in the signal line group;

[0046] Figure 35 Schematic diagram of a display device provided by an embodiment of the present application;

[0047] Figure 36 An application scenario of a display device provided by an embodiment of the present application;

[0048] Figure 37 An application scenario of a display device provided by an embodiment of the present application;

[0049] Figure 38 An application scenario of a display device provided by an embodiment of the present application.

Specific embodiments

[0050] In order to better understand the technical solution of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0051] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0052] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0053] It should be understood that the term "and / or" used herein is merely a description of the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the character " / " in this text generally indicates that the associated objects before and after are in an "or" relationship.

[0054] In the description of this specification, it should be understood that words such as "substantially", "approximately", "about", "around", "roughly", "generally" in the claims and embodiments of this application refer to values that can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0055] It should be understood that although terms such as first, second, third, etc. may be used to describe transistors, etc. in the embodiments of this application, these transistors, etc. should not be limited to these terms. These terms are only used to distinguish transistors, etc. from each other. For example, without departing from the scope of the embodiments of this application, the first transistor can also be referred to as the second transistor, and similarly, the second transistor can also be referred to as the first transistor.

[0056] Through careful and in-depth research, the applicant of this case has provided a solution to the problems existing in the prior art.

[0057] Figure 1 It is a schematic diagram of the working principle of a liquid crystal grating provided for the embodiments of this application. Figure 2 It is a schematic diagram of the structure of a liquid crystal grating provided for the embodiments of this application. Figure 3 is Figure 2 a schematic diagram along the M1 - M2 direction in

[0058] As Figure 1 shown, the liquid crystal grating 01 can control the transmittance of the light it receives to change periodically on the light - emitting surface side of the liquid crystal grating 01. Among them, in the working state of the liquid crystal grating 01, the part that allows light to pass through can be regarded as the light - transmitting part of the liquid crystal grating 01, and the part that does not allow light to pass through can be regarded as the barrier part of the grating 01. The liquid crystal grating 01 can form light rays that are respectively incident on the left eye and the right eye based on the incident light. In this way, the images seen by the human left eye and right eye respectively after passing through the liquid crystal grating 01 have a certain parallax, and thus a three - dimensional image can be perceived.

[0059] Combined with Figure 2 and Figure 3, the liquid crystal grating 01 includes a substrate 10 and a first electrode 20 disposed on the substrate 10. In addition, the liquid crystal grating 01 may further include a second electrode 30, which may be disposed on the substrate 10 or on the counter substrate 10' opposite to the substrate 10. The liquid crystal grating 01 may also include a liquid crystal layer 40. If the electric fields between the first electrode 20 and the second electrode 30 are different, the deflection degrees of the liquid crystal molecules in the liquid crystal layer 40 can be controlled to be different.

[0060] Figure 3 The dotted lines in represent the brightness of light rays with the same brightness passing through the liquid crystal grating 01 and exiting from the liquid crystal grating 01. As Figure 3 shown, when the electric fields between multiple first electrodes 20 and the second electrode 30 change periodically as the voltages received by the multiple first electrodes 20 are different respectively, the deflection degrees of the liquid crystals between the multiple first electrodes 20 and the second electrode 30 are different, and then the liquid crystal grating 01 causes the transmittance of the incident light to change periodically.

[0061] Figure 4 This is an equivalent schematic diagram of a liquid crystal grating provided by an embodiment of the present application.

[0062] In addition, when the deflection degrees of the liquid crystals between multiple first electrodes 20 and the second electrode 30 are different, the light rays incident on the liquid crystal grating 01 are deflected by the liquid crystals with different deflection degrees and then exit from the liquid crystal grating 01, and the optical paths of these light rays are no longer the same. The optical path difference of the light rays exiting from the liquid crystal grating can be controlled by controlling the deflection degrees of the liquid crystals at different positions, so that different light rays interfere, and then an effect similar to refraction can be achieved for the light rays. As Figure 4 shown, at this time, the liquid crystals with different deflection degrees can be analogized to a prism OP, which can cause the light rays to propagate in a specific direction after exiting from the liquid crystal grating 01, so that the light rays can be received by the human eyes at specific positions, and the left eye and the right eye can receive different light rays respectively.

[0063] Among them, the electric fields between different first electrodes 20 and the second electrode 30 can be different, which is mainly determined by the voltages received by the first electrodes 20. Generally, the second electrode 30 can correspond to multiple first electrodes 20. When the voltages received by the multiple first electrodes 20 corresponding to the same second electrode 30 are different, the electric fields between the multiple first electrodes 20 and the second electrode 30 are different.

[0064] Figure 5 This is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application.

[0065] Combined with Figure 2 and Figure 5, the liquid crystal grating 01 provided by the embodiment of the present application further includes a driving circuit 50 and a signal line group 60, and the driving circuit 50 and the signal line group 60 are disposed on the substrate 10.

[0066] The driving circuit 50 is electrically connected to the first electrode 20 and is used to transmit signals to the first electrode 20 to which it is electrically connected. Specifically, the driving circuit 50 can transmit data voltages for controlling the deflection of liquid crystal molecules to the first electrode 20 to which it is electrically connected. The driving circuit 50 includes a transistor group 51, the transistor group 51 includes at least two transistors 510, and at least two transistors 510 included in the transistor group 51 include a first transistor 511.

[0067] The signal line group 60 includes at least a first signal line 61 and a second signal line 62, and both the first signal line 61 and the second signal line 62 are electrically connected to the driving circuit 50.

[0068] In an embodiment of the present application, as Figure 5 shown, in at least one first state of the liquid crystal grating 01, the switching frequency of the first transistor 511 is greater than the switching frequency of at least one other transistor 510 in the transistor group 51. The minimum distance between the orthographic projection of the first transistor 511 on the substrate 10 and the orthographic projection of the signal line group 60 on the substrate 10 is greater than the minimum distance between the orthographic projection of the at least one other transistor 510 on the substrate 10 and the orthographic projection of the signal line group 60 on the substrate 10. That is, the orthographic projection of the first transistor 511 on the substrate 10 is farther from the orthographic projection of the signal line group 60 on the substrate 10 than the orthographic projection of the at least one other transistor 510 on the substrate 10.

[0069] In the same driving circuit 50, the distance between the first transistor 511 and the signal line group 60 is greater than the distance between at least one transistor 510 with a refresh frequency less than that of the first transistor 511 and the signal line group 60. The distance between the first transistor 511 with a higher switching frequency and the signal line group 60 is larger, effectively improving the signal interference problem between the first transistor 511 and the signal lines included in the first signal line group 60, and improving the charging ability of the driving circuit 50 to the first electrode 20.

[0070] Figure 6 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application.

[0071] In an embodiment of the present application, as Figure 6As shown, in at least one first state of the liquid crystal grating 01, the change frequency of the signal transmitted by the first signal line 61 is greater than the change frequency of the signal transmitted by the second signal line 62. The minimum distance between the orthographic projection of the second signal line 62 on the substrate substrate 10 and the orthographic projection of the driving circuit 50 on the substrate substrate 10 is less than the minimum distance between the orthographic projection of the first signal line 61 on the substrate substrate 10 and the orthographic projection of the driving circuit 50 on the substrate substrate 10. That is, the orthographic projection of the second signal line 62 on the substrate substrate 10 is farther from the orthographic projection of the driving circuit 50 on the substrate substrate 10 than the orthographic projection of the first signal line 61 on the substrate substrate 10.

[0072] For example, as Figure 6 shown, both the first signal line 61 and the second signal line 62 extend along the row direction X, and the first signal line 61 and the second signal line 62 are arranged along the column direction Y; and along the column direction Y, the second signal line 62 is located between the first signal line 61 and the driving circuit 50.

[0073] That is to say, along the above-mentioned column direction Y, the first signal line 61 is located on the side of the second signal line 62 away from the transistor group 51.

[0074] Optionally, the driving circuits 50 corresponding to different first electrodes 20 can be commonly formed into a circuit array arranged in an array along the above-mentioned column direction Y and row direction X.

[0075] The minimum distance between the first signal line 61 with a higher change frequency of the transmitted signal and the driving circuit 50 is greater than the minimum distance between the second signal line 62 with a lower change frequency of the transmitted signal and the driving circuit 50. The distance between the first signal line 61 with a higher change frequency of the transmitted signal and the driving circuit 50 is larger, effectively improving the signal interference problem between the first signal line 61 and the devices included in the driving circuit 50, and improving the charging ability of the driving circuit 50 to the first electrode 20.

[0076] Figure 7 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application.

[0077] In an embodiment of the present application, as Figure 7 shown, the minimum distance between the orthographic projection of the first transistor 511 on the substrate substrate 10 and the orthographic projection of the signal line group 60 on the substrate substrate 10 is greater than the minimum distance between the orthographic projection of at least one other transistor 510 in the transistor group 51 on the substrate substrate 10 and the orthographic projection of the signal line group 60 on the substrate substrate 10, and the minimum distance between the orthographic projection of the second signal line 62 on the substrate substrate 10 and the orthographic projection of the driving circuit 50 on the substrate substrate 10 is less than the minimum distance between the orthographic projection of the first signal line 61 on the substrate substrate 10 and the orthographic projection of the driving circuit 50 on the substrate substrate 10.

[0078] The distance between the first transistor 511 with a relatively high switching frequency and the signal line group 60 is relatively large, and the distance between the first signal line 61 with a relatively higher transmission signal change frequency and the driving circuit 50 is relatively large, effectively improving the signal interference problem between the devices in the driving circuit 50 and the signal lines included in the first signal line group 60, and improving the charging ability of the driving circuit 50 for the first electrode 20.

[0079] Figure 8 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application.

[0080] In an embodiment of the present application, as Figure 8 shown, the driving circuit 50 further includes a first capacitor C1, and the first plate of the first capacitor C1 is electrically connected to the first electrode 20. The first capacitor C1 is used to hold the voltage on the first electrode 20. In addition, the presence of the first capacitor C1 can also realize the pull-up or pull-down compensation for the voltage on the first electrode 20.

[0081] The transistor group 51 further includes a second transistor 512, that is, at least two transistors 510 included in the transistor group 51 include the second transistor 512. Among them, the first transistor 511 is electrically connected to the first signal line 61, and the second transistor 512 is electrically connected to the second signal line 62.

[0082] In at least one first state of the liquid crystal grating 01, the switching frequency of the first transistor 511 is greater than the switching frequency of the second transistor 512, and / or, the change frequency of the signal transmitted by the first signal line 61 is greater than the change frequency of the signal transmitted by the second signal line 62.

[0083] Among them, the minimum distance between the orthographic projection of the first transistor 511 on the substrate 10 and the orthographic projection of the first capacitor C1 on the substrate 10 is greater than the minimum distance between the orthographic projection of the second transistor 512 on the substrate 10 and the orthographic projection of the first capacitor C1 on the substrate 10.

[0084] When the switching frequency of the first transistor 511 is greater than the switching frequency of the second transistor 512, the distance between the first transistor 511 and the first capacitor C1 in the same driving circuit 50 is greater than the distance between the second transistor 512 and the first capacitor C1, which can effectively improve the signal interference between the first capacitor C1 and the first transistor 511. For example, it can reduce the influence of the control signal received when the switching state of the first transistor 511 changes on the voltage on the plates of the first capacitor C1, and improve the charging ability of the driving circuit 50 for the first electrode 20.

[0085] When the change frequency of the signal transmitted by the first signal line 61 is greater than the change frequency of the signal transmitted by the second signal line 62, in the same driving circuit 50, the distance between the first transistor 511 electrically connected to the first signal line 61 and the first capacitor C1 is greater than the distance between the second transistor 512 electrically connected to the second signal line 62 and the first capacitor C1. Then, the portion of the first signal line 61 electrically connected to the first transistor 511 is farther from the first capacitor C1 than the portion of the second signal line 62 electrically connected to the second transistor 512, which can effectively improve the signal interference between the first capacitor C1 and the first signal line 61. For example, it can reduce the influence of the signal transmitted by the first signal line 61 on the voltage of the first capacitor C1 and improve the charging ability of the driving circuit 50 for the first electrode 20.

[0086] In a technical solution of the present application, as Figure 8 shown, in a driving circuit 50, the orthographic projection of the first transistor 511 on the substrate 10 is located on the side of the orthographic projection of the second transistor 512 on the substrate 10 that is away from the orthographic projection of the first capacitor C1 on the substrate 10, and the second transistor 512 is located between the first capacitor C1 and the first transistor 511. That is, the orthographic projection of the second transistor 512 on the substrate 10 is located between the orthographic projection of the first transistor 511 on the substrate 10 and the orthographic projection of the first capacitor C1 on the substrate 10.

[0087] For example, as Figure 8 shown, in a driving circuit 50, the first capacitor C1, the first transistor 511, and the second transistor 512 are arranged substantially along the row direction X, and in the row direction X, the second transistor 512 is located between the first capacitor C1 and the first transistor 511.

[0088] This setting method can avoid the problem of a wider border of the liquid crystal grating caused by an increase in the width of the driving circuit 50 along the column direction Y on the premise of effectively improving the signal interference between the first capacitor C1 and the first signal line 61 and / or the first transistor 511.

[0089] In a technical solution of the present application, as Figure 8 shown, the gate of the first transistor 511 is electrically connected to the first signal line 61, and the gate of the second transistor 512 is electrically connected to the second signal line 62. That is, the first signal line 61 is used to transmit a control signal for controlling the transmission switch state of the first transistor 511, and the second signal line 62 is used to transmit a control signal for controlling the switch state of the second transistor 512.

[0090] In at least one first state, the switching frequency of the enable signal and the non-enable signal in the control signal transmitted by the first signal line 61 is greater than the switching frequency of the enable signal and the non-enable signal in the control signal transmitted by the second signal line 62, so the switching frequency of the first transistor 511 is greater than the switching frequency of the second transistor 512.

[0091] It should be noted that the enable signal transmitted by the signal line refers to the signal in the signal transmitted by the signal line that can turn on the transistor electrically connected to the signal line; the non-enable signal transmitted by the signal line refers to the signal in the signal transmitted by the signal line that can turn off the transistor electrically connected to the signal line. For example, if the first signal line 61 is electrically connected to the gate of the first transistor 511, the enable signal in the signal transmitted by the first signal line 61 is the signal that can turn on the first transistor 511, and the non-enable signal in the signal transmitted by the first signal line 61 is the signal that can turn off the first transistor 511. For example, if the second signal line 62 is electrically connected to the gate of the second transistor 512, the enable signal in the signal transmitted by the second signal line 62 is the signal that can turn on the second transistor 512, and the non-enable signal in the signal transmitted by the second signal line 62 is the signal that can turn off the second transistor 512.

[0092] Figure 9 The equivalent circuit diagram of the driving circuit in a liquid crystal grating provided by an embodiment of the present application Figure 10 is Figure 9 a timing diagram of the shown driving circuit.

[0093] As Figure 9 shown, the driving circuit 50 includes a signal writing transistor M1, a reset transistor M2, and a first capacitor C1. Among them, the input end of the signal writing transistor M1 is electrically connected to the data voltage line DL, the output end is electrically connected to the first electrode 20, the gate is electrically connected to the first scan line S1, the input end of the reset transistor M2 is electrically connected to the reset signal line RL, the output end is electrically connected to the first electrode 20, and the gate is electrically connected to the second scan line S2. The first plate of the first capacitor C1 is electrically connected to the first electrode 20.

[0094] When the first scan line S1 transmits an enable signal to control the signal writing transistor M1 to turn on, the signal writing transistor M1 transmits a data voltage to the first electrode 20; when the second scan line S2 transmits an enable signal to control the reset transistor M2 to turn on, the reset transistor M2 transmits a reset voltage to the first electrode 20.

[0095] In a working cycle T0 of the liquid crystal grating, in combination with Figure 9 and Figure 10, to enable the first electrode 20 to obtain a signal of the target voltage, multiple rounds of charging are required for the first electrode 20. Then, the first scan line S1 needs to control the signal writing transistor M1 to turn on multiple times within a working cycle T0. That is, a working cycle T0 includes multiple sub-stages T1, and the signal writing transistor M1 is turned on respectively in each sub-stage T1, and the data voltage transmitted by the data voltage line DL is transmitted to the first electrode 20. Especially when the length of the first electrode 20 is relatively large, since the coupling capacitance of the first electrode 20 is larger, it is more necessary for the first scan line S1 to control the signal writing transistor M1 to turn on multiple times within a working cycle to perform multiple rounds of charging on the first electrode 20.

[0096] The process of resetting the voltage on the first electrode 20 can be performed only at the beginning of a working cycle T0. Then, the signal transmitted by the second scan line S1 can control the reset transistor M2 to turn on once during the reset stage T2 of a working cycle T0, so as to transmit the reset voltage transmitted by the reset signal line RL to the first electrode 20.

[0097] Combined with Figure 9 and Figure 10 , the frequency of the enable signal transmitted by the second scan line S1 is less than the frequency of the enable signal transmitted by the first scan line S2. Correspondingly, the frequency of the signal writing transistor M1 turning on is greater than the frequency of the reset transistor M2 turning on.

[0098] Figure 11 FIG. is an equivalent circuit diagram of a driving circuit in a liquid crystal grating provided by an embodiment of the present application. Figure 12 is Figure 11 a timing diagram of the driving circuit shown in FIG.

[0099] As Figure 11 shown, the driving circuit 50 includes a signal writing transistor M1, a reset transistor M2, a first compensation transistor M3, a second compensation transistor M4, and a first capacitor C1. The connection manner of the first plates of the signal writing transistor M1, the reset transistor M2, and the first capacitor C1 is the same as that in the driving circuit 50 shown in Figure 9 and will not be described in detail here.

[0100] The input end of the first compensation transistor M3 is electrically connected to the first compensation voltage line B1, the output end is electrically connected to the second plate of the first capacitor C1, and the gate is electrically connected to the third scan line S3. The input end of the second compensation transistor M4 is electrically connected to the second compensation voltage line B2, the output end is electrically connected to the second plate of the first capacitor C1, and the gate is electrically connected to the fourth scan line S4.

[0101] When the third scan line S3 transmits an enable signal to control the first compensation transistor M3 to turn on, the first compensation transistor M3 transmits a first compensation voltage to the second electrode plate of the first capacitor C1; when the signal transmitted by the fourth scan line S4 controls the reset transistor M4 to turn on, the second compensation transistor M4 transmits a second compensation voltage to the second electrode plate of the first capacitor C1.

[0102] The first compensation transistor M3 and the second compensation transistor M4 cooperate with the first capacitor C1 to raise or lower the voltage on the first electrode 20, and thus the voltage on the first electrode 20 can be compensated. Combined with Figure 12 For Figure 11 the specific working process of the driving circuit 50 shown is as follows:

[0103] When the first scan line S1 transmits an enable signal or before the first scan line S1 transmits an enable signal, the third scan line S3 transmits an enable signal to the gate of the first compensation transistor M3, and the first compensation transistor M3 turns on to transmit the first compensation voltage transmitted by the first compensation voltage line B1 to the second electrode plate of the first capacitor C1;

[0104] In the compensation stage T3 after the first scan line S1 transmits an enable signal, the fourth scan line S4 transmits an enable signal to the gate of the second compensation transistor M4, and the second compensation transistor M4 turns on to transmit the second compensation voltage transmitted by the second compensation voltage line B2 to the second electrode plate of the first capacitor C1.

[0105] When it is necessary to perform a boosting compensation on the voltage of the first electrode 20, the first compensation voltage is less than the second compensation voltage; when it is necessary to perform a boosting compensation on the voltage of the first electrode 20, the first compensation voltage is greater than the second compensation voltage.

[0106] It should be noted that each working cycle T0 of the liquid crystal grating 01 can include the compensation stage T3; alternatively, some working cycles T0 of the liquid crystal grating 01 can include the compensation stage T3, and some working cycles can not include the compensation stage T3.

[0107] For example, as Figure 12As shown, the liquid crystal grating 01 may include a first working state F1 and a second working state F2, and the liquid crystal grating 01 includes a compensation stage T3 in a plurality of working cycles T0 included in the first working state F1, and the liquid crystal grating 01 does not include the compensation stage T3 in a plurality of working cycles T0 included in the second working state F2. In the plurality of working cycles T0 included in the first working state F1, the third scan line S3 and the fourth scan line S4 transmit an enable signal in a partial period of time to turn on the first compensation transistor M3 and the second compensation transistor M4 in the driving circuit 50; in the plurality of working cycles T0 included in the second working state F2, the third scan line S3 and the fourth scan line S4 always transmit a non-enable signal to keep the first compensation transistor M3 and the second compensation transistor M4 in the driving circuit 50 turned off.

[0108] The refresh frequency of the liquid crystal grating 01 in the first working state F1 may be greater than the refresh frequency in the second working state F2. In the first working state F1, the signal writing transistor M1 in the driving circuit 50 transmits the data voltage to the first electrode 20 for a short time, and the data voltage may not be fully written into the first electrode 20. At this time, the voltage on the first electrode 20 can be compensated by the first compensation transistor M3, the second compensation transistor M4 and the first capacitor C1, so that the voltage on the first electrode 20 is close to the target voltage.

[0109] Figure 13 An equivalent circuit diagram of a driving circuit in a liquid crystal grating provided in an embodiment of the present application, Figure 14 for Figure 13 A timing diagram of the drive circuit shown.

[0110] like Figure 13 As shown, the driving circuit 50 includes a signal writing transistor M1, a reset transistor M2, a composite compensation transistor M34 and a first capacitor C1. The connection method of the signal writing transistor M1, the reset transistor M2 and the first plate of the first capacitor C1 is similar to Figure 9 The driving circuit 50 is the same as that shown and will not be described again.

[0111] The composite compensation transistor M34 has an input terminal electrically connected to the composite compensation voltage line B12 , an output terminal electrically connected to the second plate of the first capacitor C1 , and a gate electrically connected to the compensation control line S34 .

[0112] The compensation control line S34 can transmit the first compensation voltage and the second compensation voltage. The signal transmitted by the compensation control line S34 controls the composite compensation transistor M34 to be turned on in time division to transmit the first compensation voltage and the second compensation voltage to the second plate of the first capacitor C1 respectively.

[0113] The composite compensation transistor M34 and the first capacitor C1 can raise or lower the voltage on the first electrode 20, and thus can compensate for the voltage on the first electrode 20. Combining Figure 13 For Figure 14 the specific working process of the driving circuit 50 shown is as follows:

[0114] When the enable signal is transmitted on the first scan line S1 or before the enable signal is transmitted on the first scan line S1, the compensation control line S34 transmits the enable signal to the gate of the composite compensation transistor M34 and the composite compensation voltage line B12 transmits the first compensation voltage, and the composite compensation transistor M34 is turned on to transmit the first compensation voltage transmitted by the composite compensation voltage line B12 to the second electrode plate of the first capacitor C1;

[0115] In the compensation stage T3 after the enable signal is transmitted on the first scan line S1, the compensation control line S34 transmits the enable signal to the gate of the composite compensation transistor M34 and the composite compensation voltage line B12 transmits the second compensation voltage, and the composite compensation transistor M34 is turned on to transmit the second compensation voltage transmitted by the composite compensation voltage line B12 to the second electrode plate of the first capacitor C1.

[0116] When it is necessary to perform a raise compensation on the voltage on the first electrode 20, the first compensation voltage is less than the second compensation voltage; when it is necessary to perform a raise compensation on the voltage on the first electrode 20, the first compensation voltage is greater than the second compensation voltage.

[0117] It should be noted that each working cycle T0 of the liquid crystal grating 01 can include the compensation stage T3; alternatively, some working cycles T0 of the liquid crystal grating 01 can include the compensation stage T3, and some working cycles can not include the compensation stage T3.

[0118] For example, as Figure 14 shown, the liquid crystal grating 01 can include a first working state F1 and a second working state F2. The liquid crystal grating 01 includes the compensation stage T3 in multiple working cycles T0 included in the first working state F1, and the liquid crystal grating 01 does not include the compensation stage T3 in multiple working cycles T0 included in the second working state F2. In multiple working cycles T0 included in the first working state F1, the compensation control line S34 transmits the enable signal in some time periods to turn on the composite compensation transistor M34 in the driving circuit 50; in multiple working cycles T0 included in the second working state F2, the compensation control line S34 always transmits a non-enable signal to keep the composite compensation transistor M34 in the driving circuit 50 turned off.

[0119] Among them, the refresh frequency of the liquid crystal grating 01 in the first working state F1 can be greater than its refresh frequency in the second working state F2. Then, in the first working state F1, the duration for the signal writing transistor M1 in the driving circuit 50 to transmit the data voltage to the first electrode 20 is shorter, and the data voltage may not be fully written into the first electrode 20. At this time, the voltage on the first electrode 20 can be compensated by the composite compensation transistor M34 and the first capacitor C1, so that the voltage on the first electrode 20 is close to the target voltage.

[0120] Figure 15 A partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application Figure 16 A partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application Figure 17 A partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application.

[0121] In an embodiment of the present application, please refer to Figures 15 to 17 , the output end of the first transistor 511 is electrically connected to the first electrode 20, and the input end of the first transistor 511 is electrically connected to the data voltage line DL. Then, the first transistor 511 can be the signal writing transistor M1. The gate of the first transistor 511 is electrically connected to the first signal line 61. Then, the first signal line 61 can be the first scan line S1.

[0122] Through the above analysis, it can be seen that the switching frequency of the signal writing transistor M1 is greater than the switching frequency of the reset transistor M2 in the driving circuit 50, and the frequency of the first scan line S1 transmitting the enable signal is greater than the frequency of the second scan line S2 transmitting the enable signal.

[0123] Such as Figure 15 and Figure 16 shown, when the first transistor 511 is the signal writing transistor M1, the signal writing transistor M1 is farther away from the signal line group 60 relative to at least one transistor 510 (for example, the reset transistor M2) in the driving circuit 50, which can effectively improve the signal interference problem between the signal writing transistor M1 and the signal lines included in the first signal line group 60, and improve the charging ability of the driving circuit 50 to the first electrode 20.

[0124] Such as Figure 16 and Figure 17 shown, when the first signal line 61 is the first scan line S1, the first scan line S1 is farther away from the driving circuit 50 relative to the second signal line 62, which can effectively improve the signal interference problem between the first scan line S1 and the devices included in the driving circuit 50, and improve the charging ability of the driving circuit 50 to the first electrode 20.

[0125] In a technical solution of the present application, such as Figure 15 and Figure 16As shown, when the first transistor 511 is the signal writing transistor M1 and the transistor group 51 further includes a reset transistor M2, the minimum distance between the orthographic projection of the first transistor 511 on the substrate 10 and the signal line group 60 is greater than the minimum distance between the orthographic projection of the reset transistor M2 on the substrate 10 and the signal line group 60. As Figure 15 and Figure 16 shown, the driving circuit 50 and the signal line group 60 are arranged along the column direction Y, and the signal writing transistor M1 in the driving circuit 50 is farther from the signal line group 60 than the reset transistor M2 in the column direction Y.

[0126] By setting the first transistor 511 to be farther from the signal line group 60 than the reset transistor M2, the signal writing transistor M1 is farther from the signal line group 60 than the reset transistor M2, effectively improving the signal interference problem between the signal writing transistor M1 and the signal lines included in the first signal line group 60.

[0127] In an implementation manner of this technical solution, as Figure 15 shown, the first scan line S1 electrically connected to the signal writing transistor M1 can be located on one side of the second signal line 62 of the driving circuit 50, that is, the orthographic projection of the second signal line 62 on the substrate 10 can be located between the orthographic projection of the first scan line S1 on the substrate 10 and the orthographic projection of the driving circuit 50 on the substrate 10.

[0128] In an implementation manner of this technical solution, as Figure 16 shown, the first scan line S1 electrically connected to the signal writing transistor M1 can be located on the side of the second signal line 62 close to the driving circuit 50, that is, the orthographic projection of the first scan line S1 on the substrate 10 can be located between the orthographic projection of the second signal line 62 on the substrate 10 and the orthographic projection of the driving circuit 50 on the substrate 10.

[0129] In addition, as Figure 16 and Figure 17 shown, when the first transistor 511 is the signal writing transistor M1 and the first signal line 61 is the first scan line S1, the minimum distance between the orthographic projection of the first scan line S1 on the substrate 10 and the orthographic projection of the driving circuit 50 on the substrate can be greater than the minimum distance between the orthographic projection of the second signal line 62 on the substrate 10 and the orthographic projection of the driving circuit 50 on the substrate. As Figure 16 and Figure 17As shown, the orthographic projection of the second signal line 62 on the substrate 10 may be located between the orthographic projection of the first scan line S1 on the substrate 10 and the orthographic projection of the driving circuit 50 on the substrate 10. By making the first scan line S1 farther from the driving circuit 50 than the second signal line 62, the signal interference problem between the first scan line S1 and the devices included in the driving circuit 50 can be effectively improved, and the charging ability of the driving circuit 50 to the first electrode 20 can be enhanced.

[0130] Among them, the second signal line S2 may be the second scan line S2 electrically connected to the gate of the reset transistor M2.

[0131] In one implementation of this technical solution, as Figure 16 shown, the driving circuit 50 and the signal line group 60 are arranged along the column direction Y, and the signal writing transistor M1 in the driving circuit 50 is farther from the signal line group 60 than the reset transistor M2 in the column direction Y. Then, in this implementation, the first scan line S1 is farther from the driving circuit 50 than the second signal line 62, and the signal writing transistor M1 is farther from the signal line group 60 than the reset transistor M2.

[0132] In one implementation of this technical solution, as Figure 17 shown, the distance between the signal writing transistor M1 and the signal line group 60 may be equal to the distance between the reset transistor M2 and the signal line group 60.

[0133] Figure 18 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application. Figure 19 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application. Figure 20 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application. Figure 21 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application.

[0134] In a technical solution of the present application, as Figures 18 - 21 shown, when the driving circuit 50 includes a first capacitor C1 and the transistor group 51 further includes a compensation transistor M0, the minimum distance between the orthographic projection of the reset transistor M2 on the substrate 10 and the orthographic projection of the first signal line 61 on the substrate 10 is greater than or equal to the minimum distance between the orthographic projection of the compensation transistor M30 on the substrate 10 and the orthographic projection of the first signal line 61 on the substrate 10.

[0135] Among them, as Figure 18 and Figure 19 shown, the compensation transistor M0 may be a composite compensation transistor M34; or, as Figure 20 and Figure 21As shown, the compensation transistor M0 may include a first compensation transistor M3 and a second compensation transistor M4.

[0136] In one implementation, as Figure 18 and Figure 20 shown, the minimum distance between the orthographic projection of the reset transistor M2 on the substrate 10 and the orthographic projection of the first signal line 61 on the substrate 10 is equal to the minimum distance between the orthographic projection of the compensation transistor M0 on the substrate 10 and the orthographic projection of the first signal line 61 on the substrate 10. As Figure 18 and Figure 20 shown, the transistor group 51 and the signal line group 60 are arranged along the column direction Y, and the distance between the reset transistor M2 and the signal line group 60 in the column direction Y is equal to the distance between the compensation transistor M0 and the signal line group 60 in the column direction Y.

[0137] In one implementation, as Figure 19 and Figure 21 shown, the minimum distance between the orthographic projection of the reset transistor M2 on the substrate 10 and the orthographic projection of the first signal line 61 on the substrate 10 is greater than the minimum distance between the orthographic projection of the compensation transistor M0 on the substrate 10 and the orthographic projection of the first signal line 61 on the substrate 10. As Figure 19 and Figure 21 shown, the transistor group 51 and the signal line group 60 are arranged along the column direction Y, and the distance between the reset transistor M2 and the signal line group 60 in the column direction Y is greater than the distance between the compensation transistor M0 and the signal line group 60 in the column direction Y.

[0138] In the present technical solution, one of the second scan line S2, the third scan line S3, the fourth scan line S4, and the compensation control line S34 may be the second signal line 62.

[0139] As Figure 18 and Figure 21 shown, the second scan line S2, the third scan line S3, and the fourth scan line S4 are all located between the first signal line S1 and the driving circuit 50.

[0140] When the driving circuit 50 includes the first capacitor C1, the signal writing transistor M1, the reset transistor M2, and the compensation transistor M0, the orthographic projections of the compensation transistor M0 and the reset transistor M2 on the substrate 10 are located between the orthographic projection of the first transistor 511 on the substrate 10 and the orthographic projection of the first capacitor C1 on the substrate 10, that is, the orthographic projections of the compensation transistor M0 and the reset transistor M2 on the substrate 10 are located between the orthographic projection of the signal writing transistor M1 on the substrate 10 and the orthographic projection of the first capacitor C1 on the substrate 10. Through such a design, the problem of crosstalk can be further avoided.

[0141] Further, the compensation transistor M0 can be disposed between the reset transistor M2 and the first capacitor C1, and the reset transistor M2 can be disposed between the signal writing transistor M1 and the compensation transistor M0. For example, as Figures 18 to 21 shown, the first capacitor C1, the compensation transistor M0, the reset transistor M2, and the signal writing transistor M1 are arranged in sequence along the row direction X.

[0142] Wherein, when the compensation transistor M0 is a composite compensation transistor M34, the composite compensation transistor M34 can be disposed between the reset transistor M2 and the first capacitor C1, and the reset transistor M2 can be disposed between the signal writing transistor M1 and the composite compensation transistor M34.

[0143] When the compensation transistor M0 includes a first compensation transistor M3 and a second compensation transistor M4, the first compensation transistor M3 and the second compensation transistor M4 can be disposed between the reset transistor M2 and the first capacitor C1, and the reset transistor M2 can be disposed between the signal writing transistor M1 and the first compensation transistor M3 and the second compensation transistor M4. Through such a design, the problem of crosstalk can be further avoided.

[0144] Figure 22 This is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application. Figure 23 This is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application. Figure 24 This is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application. Figure 25 This is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application. Figure 26 This is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application. Figure 27 This is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application.

[0145] In an embodiment of the present application, as Figures 22 to 27 shown, the transistor group 51 further includes a second transistor 512. The output end of the second transistor 512 is electrically connected to the first electrode 20, the input end of the second transistor 512 is electrically connected to the reset signal line RL, and the gate of the second transistor 512 can be electrically connected to the second signal line 62. Then the second transistor 512 is the reset transistor M2 and the second signal line 62 is the second scan line S2.

[0146] In this embodiment, the first transistor 511 in the transistor group 51 may be a signal writing transistor M1 and the second transistor 512 may be a reset transistor M2. The first signal line 61 may be a first scanning line S1 and the second signal line 62 may be a second scanning line. Then, the position settings of the first transistor 511 and the second transistor 512 may refer to the position settings of the signal writing transistor M1 and the reset transistor M2 in the above embodiment, and the position settings of the first signal line 61 and the second signal line 62 may refer to the position settings of the first scanning line S1 and the second scanning line S2 in the above embodiment, which will not be elaborated here.

[0147] In a technical solution of the present application, the signal line group 60 further includes a third signal line 63, and the transistor group 50 further includes a third transistor 513. The output end of the third transistor 513 is electrically connected to the second electrode plate of the first capacitor C1, and the gate of the third transistor 513 is electrically connected to the third signal line 63. Then, the third transistor 53 may be a first compensation transistor M3, and the third signal line 63 may be a third scanning line S3; alternatively, the third transistor 513 may be a second compensation transistor M4, and the third signal line 63 may be a fourth scanning line S4; alternatively, the third transistor 513 may be a composite compensation transistor M34, and the third signal line 63 may be a compensation control line S34, that is, the third transistor 513 may be at least one of the first compensation transistor M3, the second compensation transistor M4, and the composite compensation transistor M34.

[0148] In an implementation manner of this technical solution, the orthographic projection of the third signal line L3 on the substrate 10 is located between the orthographic projection of the first signal line L1 on the substrate 10 and the orthographic projection of the second signal line L2 on the substrate 10. Then, the second signal line L2 and the third signal line L3 are provided between the first signal line L1 and the first capacitor C1 included in the driving circuit 50, so that there is a large distance between the first signal line L1 and the first capacitor C1, avoiding the influence of the signal transmitted on the first signal line L1 on the performance of the first capacitor C1 charging the first electrode 20.

[0149] In an implementation manner of this technical solution, the orthographic projection of the third signal line L3 on the substrate 10 is located on the side of the orthographic projection of the first signal line L1 on the substrate 10 away from the orthographic projection of the second signal line L2 on the substrate 10. The second signal line L2 is provided between the first signal line L1 and the first capacitor C1 included in the driving circuit 50, so that there is a large distance between the first signal line L1 and the first capacitor C1, avoiding the influence of the signal transmitted on the first signal line L1 on the performance of the first capacitor C1 charging the first electrode 20.

[0150] As Figure 22As shown, when the third transistor 513 is the composite compensation transistor M34 and the third signal line 63 is the compensation control line S34, in one implementation, the orthographic projection of the third signal line 63 on the substrate 10 is located between the orthographic projection of the first signal line 61 on the substrate 10 and the orthographic projection of the second signal line 62 on the substrate 10, that is, the orthographic projection of the compensation control line S34 on the substrate 10 is located between the orthographic projection of the first scan line S1 on the substrate 10 and the orthographic projection of the second scan line S2 on the substrate 10.

[0151] As Figure 23 As shown, when the third transistor 513 is the composite compensation transistor M34 and the third signal line 63 is the compensation control line S34, in one implementation, the orthographic projection of the third signal line 63 on the substrate 10 is located on the side of the orthographic projection of the first signal line 61 on the substrate 10 away from the orthographic projection of the second signal line 62 on the substrate 10, that is, the orthographic projection of the first scan line S1 on the substrate 10 is between the orthographic projection of the compensation control line S34 on the substrate 10 and the orthographic projection of the second scan line S2 on the substrate 10.

[0152] When the third transistor 513 is the first compensation transistor M3 and the third signal line 63 is the third scan line S3, the output terminal of the third transistor 513 is electrically connected to the second electrode plate of the first capacitor C1, the input terminal of the third transistor 513 is electrically connected to the first compensation voltage line B1, and the gate of the third transistor 513 is electrically connected to the third signal line 63.

[0153] In one implementation, as Figure 24 shown, the orthographic projection of the third signal line 63 on the substrate 10 is located between the orthographic projection of the first signal line 61 on the substrate 10 and the orthographic projection of the second signal line 62 on the substrate 10, that is, the orthographic projection of the third scan line S3 on the substrate 10 is located between the orthographic projection of the first scan line S1 on the substrate 10 and the orthographic projection of the second scan line S2 on the substrate 10.

[0154] In one implementation, as Figure 25 shown, the orthographic projection of the third signal line 63 on the substrate 10 is located on the side of the orthographic projection of the first signal line 61 on the substrate 10 away from the orthographic projection of the second signal line 62 on the substrate, that is, the orthographic projection of the first scan line S1 on the substrate 10 is located between the orthographic projection of the third scan line S3 on the substrate 10 and the orthographic projection of the second scan line S2 on the substrate 10.

[0155] When the third transistor 513 is the second compensation transistor M4 and the third signal line 63 is the fourth scan line S4, the output terminal of the third transistor 513 is electrically connected to the second electrode plate of the first capacitor C1, the input terminal of the third transistor 513 is electrically connected to the second compensation voltage line B2, and the gate of the third transistor 513 is electrically connected to the third signal line 63.

[0156] In one implementation, as Figure 26 shown, the orthographic projection of the third signal line 63 on the substrate 10 is located between the orthographic projection of the first signal line 61 on the substrate 10 and the orthographic projection of the second signal line 62 on the substrate 10, that is, the orthographic projection of the fourth scan line S4 on the substrate 10 is located between the orthographic projection of the first scan line S1 on the substrate 10 and the orthographic projection of the second scan line S2 on the substrate 10.

[0157] In one implementation, as Figure 27 shown, the orthographic projection of the third signal line 63 on the substrate 10 is located on the side of the orthographic projection of the first signal line 61 on the substrate 10 away from the orthographic projection of the second signal line 62 on the substrate, that is, the orthographic projection of the first scan line S1 on the substrate 10 is located between the orthographic projection of the fourth scan line S4 on the substrate 10 and the orthographic projection of the second scan line S2 on the substrate 10.

[0158] In a technical solution of the present application, as Figures 24 - 27 shown, the signal line group 60 further includes a fourth signal line 64, and the transistor group 50 further includes a fourth transistor 514. The output terminal of the fourth transistor 514 is electrically connected to the second electrode plate of the first capacitor C1, and the gate of the fourth transistor 514 is electrically connected to the fourth signal line 64. Among the third transistor 513 and the fourth transistor 514, one is the first compensation transistor M3 and the other is the second compensation transistor M4; correspondingly, among the third signal line 63 and the fourth signal line 64, one is the third scan line S3 and the other is the fourth scan line S4.

[0159] In one implementation of this technical solution, as Figure 24 and Figure 26 shown, the orthographic projection of the fourth signal line L4 on the substrate 10 is located between the orthographic projection of the first signal line L1 on the substrate 10 and the orthographic projection of the second signal line L2 on the substrate 10. Then, a second signal line L2 and a fourth signal line L4 are provided between the first signal line L1 and the first capacitor C1 included in the driving circuit 50, so that there is a relatively large distance between the first signal line L1 and the first capacitor C1, avoiding the influence of the signal transmitted on the first signal line L1 on the performance of the first capacitor C1 charging the first electrode 20.

[0160] In this implementation manner, the positive projection of the third signal line L3 and the fourth signal line L4 on the substrate 10 may be located between the positive projection of the first signal line L1 on the substrate 10 and the positive projection of the second signal line L2 on the substrate 10.

[0161] In an implementation manner of this technical solution, as Figure 25 and Figure 27 shown, the positive projection of the fourth signal line L4 on the substrate 10 is located on the side of the positive projection of the first signal line L1 on the substrate 10 away from the positive projection of the second signal line L2 on the substrate 10. A second signal line L2 is provided between the first signal line L1 and the first capacitor C1 included in the driving circuit 50, so there is a relatively large distance between the first signal line L1 and the first capacitor C1, avoiding the signal transmitted on the first signal line L1 from affecting the performance of the first capacitor C1 to charge the first electrode 20.

[0162] In this implementation manner, the positive projections of the third signal line L3 and the fourth signal line L4 on the substrate 10 may both be located on the side of the positive projection of the first signal line L1 on the substrate 10 away from the positive projection of the second signal line L2 on the substrate 10.

[0163] Taking the third transistor 513 as the first compensation transistor M3 and the fourth transistor 514 as the second compensation transistor M4 as an example, and the third signal line 63 as the third scan line S3 and the fourth signal line 64 as the fourth scan line S4 as an example for illustration.

[0164] In an implementation manner, as Figure 24 and Figure 26 shown, the positive projection of the fourth signal line 64 on the substrate 10 is located between the positive projection of the first signal line 61 on the substrate 10 and the positive projection of the second signal line 62 on the substrate 10, that is, the positive projection of the fourth scan line S4 on the substrate 10 is located between the positive projection of the first scan line S1 on the substrate 10 and the positive projection of the second scan line S2 on the substrate 10.

[0165] In this implementation manner, the positive projection of the third signal line 63 on the substrate 10 may also be located between the positive projection of the first signal line 61 on the substrate 10 and the positive projection of the second signal line 62 on the substrate 10, that is, the positive projections of the third scan line S3 and the fourth scan line S4 on the substrate 10 are located between the positive projection of the first scan line S1 on the substrate 10 and the positive projection of the second scan line S2 on the substrate 10.

[0166] In an implementation manner, as Figure 25 and Figure 27As shown, the orthographic projection of the fourth signal line 64 on the substrate 10 is located on the side of the orthographic projection of the first signal line 61 on the substrate 10 that is far from the orthographic projection of the second signal line 62 on the substrate 10, that is, the orthographic projection of the first scan line S1 on the substrate 10 is located between the orthographic projection of the fourth scan line S4 on the substrate 10 and the orthographic projection of the second scan line S2 on the substrate 10.

[0167] In this implementation, the orthographic projection of the third signal line 63 on the substrate 10 can also be located on the side of the orthographic projection of the first signal line 61 on the substrate 10 that is far from the orthographic projection of the second signal line 62 on the substrate 10, that is, the orthographic projection of the first scan line S1 on the substrate 10 is located between the orthographic projections of the third scan line S3 and the fourth scan line S4 on the substrate 10 and the orthographic projection of the second scan line S2 on the substrate 10.

[0168] Figure 28 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application. Figure 29 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application. Figure 30 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application.

[0169] In an embodiment of the present application, as Figures 28 - 30 shown, the driving circuit 50 further includes a first capacitor C1, and the first electrode plate of the first capacitor C1 is electrically connected to the first electrode 20. The transistor group 51 further includes a second transistor 512, the output end of the second transistor 512 is electrically connected to the second electrode plate of the first capacitor C1, and the gate of the second transistor 512 is electrically connected to the second signal line 62. Then the second transistor 512 can be a compensation transistor M0. Specifically, the second transistor 512 can be one of a first compensation transistor M3, a second compensation transistor M4, and a composite compensation transistor M34.

[0170] As Figure 28 shown, when the second transistor 512 is the first compensation transistor M3, the second signal line L2 is the third scan line S3, then the third scan line S3 can be arranged between the first scan line S1 and the driving circuit 50. At least the third scan line S3 is arranged between the first scan line S1 and the first capacitor C1 included in the driving circuit 50, reducing the signal interference between the first scan line S1 and the first capacitor C1 included in the driving circuit 50.

[0171] As Figure 29As shown, when the second transistor 512 is the second compensation transistor M4, the second signal line 62 is the fourth scan line S4, and the fourth scan line S4 can be disposed between the first scan line S1 and the driving circuit 50. At least the fourth scan line S4 is disposed between the first scan line S1 and the first capacitor C1 included in the driving circuit 50, reducing the signal interference between the first scan line S1 and the first capacitor C1 included in the driving circuit 50.

[0172] As Figure 30 shown, when the second transistor 512 is the composite compensation transistor M34, the second signal line 62 is the compensation control line S34, and the compensation control line S34 can be disposed between the first scan line S1 and the driving circuit 50. At least the compensation control line S34 is disposed between the first scan line S1 and the first capacitor C1 included in the driving circuit 50, reducing the signal interference between the first scan line S1 and the first capacitor C1 included in the driving circuit 50.

[0173] In a technical solution corresponding to this embodiment, the signal line group 60 further includes a third signal line 63 and the transistor group 51 further includes a third transistor 513. The output end of the third transistor 513 is electrically connected to the first electrode 20, the input end of the third transistor 513 is electrically connected to the reset signal line RL, and the gate of the third transistor 513 is electrically connected to the third signal line 63. Then the third transistor 513 can be the reset transistor M2 and the third signal line 63 can be the second scan line S2.

[0174] In an implementation manner of this technical solution, as Figures 28 - 30 shown, the orthographic projection of the third signal line 63 on the substrate 10 is located between the orthographic projection of the first signal line 61 on the substrate 10 and the orthographic projection of the second signal line 62 on the substrate. That is, the orthographic projection of the second scan line S2 on the substrate 10 is located between the orthographic projection of the first scan line S1 on the substrate 10 and the orthographic projection of the third scan line S3 / the fourth scan line S4 / the compensation control line S34 on the substrate 10.

[0175] Figure 31 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application. Figure 32 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application. Figure 33 It is a partial schematic diagram of a liquid crystal grating provided by an embodiment of the present application.

[0176] In an implementation manner of this technical solution, as Figures 31 - 33As shown, the orthographic projection of the third signal line 63 on the substrate 10 is located on the side of the orthographic projection of the first signal line 61 on the substrate 10 that is away from the orthographic projection of the second signal line 62 on the substrate 10. That is, the orthographic projection of the first scan line S1 on the substrate 10 is located between the orthographic projection of the second scan line S2 on the substrate 10 and the orthographic projection of the third scan line S3 / fourth scan line S4 / compensation control line S34 on the substrate 10.

[0177] Figure 34 It is a schematic diagram of the arrangement of scan lines in the signal line group.

[0178] As Figure 34 shown, when the signal line group 60 simultaneously includes the first scan line S1, the second scan line S2, the third scan line S3, and the fourth scan line S4, the distance between the third scan line S3 and the fourth scan line can be less than the distance between the first scan line S1 and the adjacent scan line. As Figure 34 shown, the first scan line S1 is adjacent to the second scan line S2, then the distance between the first scan line S1 and the second scan line S2 is greater than the distance between the third scan line S3 and the fourth scan line S4; or, the first scan line S1 is adjacent to the second scan line S2 and the third scan line S3 respectively, the distance between the first scan line S1 and the second scan line S2 is greater than the distance between the third scan line S3 and the fourth scan line S4, and the distance between the first scan line S1 and the third scan line S3 is greater than the distance between the third scan line S3 and the fourth scan line S4.

[0179] Figure 35 It is a schematic diagram of a display device provided by an embodiment of the present application, Figure 36 It is an application scenario of a display device provided by an embodiment of the present application, Figure 37 It is an application scenario of a display device provided by an embodiment of the present application, Figure 38 It is an application scenario of a display device provided by an embodiment of the present application.

[0180] As Figure 35 shown, the display device 001 provided by an embodiment of the present application includes the liquid crystal grating 01 and the light emitting module 02 provided by any one of the above embodiments, and there is parallax in the image light that enters the human eye after the light emitted by the light emitting module 02 passes through the liquid crystal grating 01.

[0181] The embodiment of the present application also provides that the display device 001 can be used in, for example, Figure 36 the head-up display device shown, for example, Figure 37 the near-eye display device shown, for example, Figure 38 the autostereoscopic display device shown, etc., and can achieve virtual reality display, augmented reality display, holographic projection display, etc.

[0182] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present application shall be included within the scope of protection of the present application.

Claims

1. A liquid crystal grating, characterized in that, Comprising: A substrate; A first electrode disposed on the substrate; A driving circuit electrically connected to the first electrode; The driving circuit includes a transistor group, and the transistor group includes a first transistor; A signal line group disposed on the substrate; the signal line group includes a first signal line and a second signal line, and the first signal line and the second signal line are electrically connected to the driving circuit; Wherein, in at least one first state, the change frequency of the signal transmitted by the first signal line is greater than the change frequency of the signal transmitted by the second signal line; the minimum distance between the positive projection of the second signal line on the substrate and the driving circuit is less than the minimum distance between the positive projection of the first signal line on the substrate and the positive projection of the driving circuit on the substrate; And / or In at least one first state, the switching frequency of the first transistor is greater than the switching frequency of at least one other transistor in the transistor group; the minimum distance between the positive projection of the first transistor on the substrate and the signal line group is greater than the minimum distance between the positive projection of the at least one other transistor on the substrate and the signal line group.

2. The liquid crystal grating according to claim 1, wherein The driving circuit further includes a first capacitor, and a first electrode plate of the first capacitor is electrically connected to the first electrode; The transistor group further includes a second transistor, the first transistor is electrically connected to the first signal line, and the second transistor is electrically connected to the second signal line; in at least one first state, the change frequency of the signal transmitted by the first signal line is greater than the change frequency of the signal transmitted by the second signal line, and / or, the switching frequency of the first transistor is greater than the switching frequency of the second transistor; Wherein, the minimum distance between the positive projection of the first transistor on the substrate and the positive projection of the first capacitor on the substrate is greater than the minimum distance between the positive projection of the second transistor on the substrate and the positive projection of the first capacitor on the substrate.

3. The liquid crystal grating according to claim 2, wherein, The positive projection of the second transistor on the substrate is located between the positive projection of the first transistor on the substrate and the positive projection of the first capacitor on the substrate.

4. The liquid crystal grating according to claim 2, wherein The gate of the first transistor is electrically connected to the first signal line, and the gate of the second transistor is electrically connected to the second signal line.

5. The liquid crystal grating according to claim 1, wherein The output end of the first transistor is electrically connected to the first electrode, and the input end of the first transistor is electrically connected to the data voltage line; the gate of the first transistor is electrically connected to the first signal line.

6. The liquid crystal grating according to claim 5, wherein The transistor group further includes a reset transistor, the output end of the reset transistor is electrically connected to the first electrode, and the input end of the reset transistor is electrically connected to the reset signal line; The minimum distance between the positive projection of the first transistor on the substrate and the signal line group is greater than the minimum distance between the positive projection of the reset transistor on the substrate and the signal line group.

7. The liquid crystal grating according to claim 6, wherein The driving circuit further includes a first capacitor, and a first electrode plate of the first capacitor is electrically connected to the first electrode; The transistor group further includes a compensation transistor, and an output end of the compensation transistor is electrically connected to a second electrode plate of the first capacitor; A minimum distance between a positive projection of the reset transistor on the substrate and the first signal line is greater than a minimum distance between a positive projection of the compensation transistor on the substrate and the first signal line.

8. The liquid crystal grating according to claim 7, wherein Positive projections of the compensation transistor and the reset transistor on the substrate are located between a positive projection of the first transistor on the substrate and a positive projection of the first capacitor on the substrate.

9. The liquid crystal grating according to claim 5, wherein The transistor group further includes a second transistor; an output end of the second transistor is electrically connected to the first electrode, an input end of the second transistor is electrically connected to a reset signal line, and a gate of the second transistor is electrically connected to the second signal line.

10. The liquid crystal grating according to claim 9, wherein The driving circuit further includes a first capacitor, and a first electrode plate of the first capacitor is electrically connected to the first electrode; the signal line group further includes a third signal line; The transistor group further includes a third transistor, and an output end of the third transistor is electrically connected to the second electrode plate of the first capacitor, and a gate of the third transistor is electrically connected to the third signal line; Wherein, a positive projection of the third signal line on the substrate is located between a positive projection of the first signal line on the substrate and a positive projection of the second signal line on the substrate; or, a positive projection of the third signal line on the substrate is located on a side of the positive projection of the first signal line on the substrate away from the positive projection of the second signal line on the substrate.

11. The liquid crystal grating according to claim 10, wherein The driving circuit further includes a first capacitor, and a first electrode plate of the first capacitor is electrically connected to the first electrode; the signal line group further includes a fourth signal line; The transistor group further includes a fourth transistor, and an output end of the fourth transistor is electrically connected to the second electrode plate of the first capacitor, and a gate of the fourth transistor is electrically connected to the fourth signal line; Wherein, a positive projection of the fourth signal line on the substrate is located between a positive projection of the first signal line on the substrate and a positive projection of the second signal line on the substrate; or, a positive projection of the fourth signal line on the substrate is located on a side of the positive projection of the first signal line on the substrate away from the positive projection of the second signal line on the substrate.

12. The liquid crystal grating according to claim 5, characterized in that The driving circuit further includes a first capacitor, and a first electrode plate of the first capacitor is electrically connected to the first electrode; the transistor group further includes a second transistor; An output end of the second transistor is electrically connected to the second electrode plate of the first capacitor, and a gate of the second transistor is electrically connected to the second signal line.

13. The liquid crystal grating according to claim 12, characterized in that The signal line group further includes a third signal line; the transistor group further includes a third transistor; An output end of the third transistor is electrically connected to the first electrode, an input end of the third transistor is electrically connected to a reset signal line, and a gate of the third transistor is electrically connected to the third signal line; Wherein, a positive projection of the third signal line on the substrate is located between a positive projection of the first signal line on the substrate and a positive projection of the second signal line on the substrate; or, the positive projection of the third signal line on the substrate is located on a side of the positive projection of the first signal line on the substrate away from the positive projection of the second signal line on the substrate.

14. A display device, characterized in that, Comprising the liquid crystal grating according to any one of claims 1-13.

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