A low dropout linear regulator

Abstract

The present invention discloses a low dropout linear regulator, belonging to the field of power management. The low dropout linear regulator of the present invention includes the following parts: a differential amplifier A1, a PMOS adjustment transistor MP2, a pole adjustment module, a resistor R21 and a resistor R22, and a compensation capacitor CM2; wherein, the resistor R21 and the resistor R22 are connected in series between the drain of the PMOS adjustment transistor MP2 and the ground, the positive input terminal of the differential amplifier A2 is connected between the resistor R21 and the resistor R22, the negative input terminal of the differential amplifier A2 is externally connected to a reference voltage, the pole adjustment module is connected between the output terminal of the differential amplifier A2 and the gate of the PMOS adjustment transistor MP2, the compensation capacitor CM2 is connected between the pole adjustment module and the drain of the PMOS adjustment transistor MP2, and the output terminal of the low dropout linear regulator is connected to the drain of the PMOS adjustment transistor MP2. By adding a pole adjustment module, the present invention enables the main pole to follow the secondary pole and move simultaneously with the change of the load current by using a current mirror, thereby improving the stability.

Description

Technical Field

[0001] The present invention relates to the technical field of power management, and particularly relates to a low dropout linear regulator. Background Art

[0002] A low dropout linear regulator (LDO) can provide a stable output voltage close to the input voltage to supply power to a chip, and is currently widely used in power management chips. A traditional low dropout linear regulator generally consists of a differential amplifier, a MOS regulating transistor, a resistor feedback loop, etc.; in addition, a traditional low dropout linear regulator also includes a bypass capacitor, a compensation capacitor for achieving a compensation effect, etc., so as to achieve the stability of the circuit.

[0003] As Figure 1 shown is a schematic diagram of a common LDO circuit structure with a compensation capacitor, which specifically includes a differential amplifier A1, a PMOS regulating transistor MP1, a compensation capacitor CM1, a load capacitor CL1, a resistor R11, and a resistor R12; wherein, the source of the PMOS regulating transistor MP1 is connected to the power supply voltage VDD, the resistor R11 and the resistor R12 are connected in series between the drain of the PMOS regulating transistor MP1 and the ground, the positive input terminal of the differential amplifier A1 is connected between the resistor R11 and the resistor R12, the negative input terminal of the differential amplifier A1 is connected to the reference voltage VREF1, the output terminal of the differential amplifier A1 is connected to the gate of the PMOS regulating transistor MP1, the compensation capacitor CM1 is connected between the gate and the drain of the PMOS regulating transistor MP1, the output terminal VOUT of the LDO circuit is connected to one end of the drain of the PMOS regulating transistor MP1 and the load capacitor CL1, the other end of the load capacitor CL1 is connected to the ground, and the capacitance value of the load capacitor CL1 can be 0.

[0004] The traditional LDO circuit separates the main pole and the secondary pole in a pole splitting manner through the compensation capacitor CM1. The main pole is determined by the output impedance of the differential amplifier A1, the compensation CM1 capacitor, and the parasitic capacitance, and the secondary pole is determined by the output impedance and the output capacitor C L1 determined. Usually, the secondary pole is designed outside the loop bandwidth. However, when the load current gradually increases, the secondary pole moves towards high frequency with the increase of the current, while the main pole fails to follow the secondary pole well, thus resulting in poor loop stability of the LDO circuit. Summary of the Invention

[0005] The purpose of the present invention is to provide a low dropout linear regulator to solve the problem that the existing LDO circuit is unstable when the load current becomes large.

[0006] To solve the above technical problems, the present invention provides a low dropout linear regulator, which includes a differential amplifier A2, a PMOS adjustment transistor MP2, a pole adjustment module, a compensation capacitor CM2, a load capacitor CL2, a resistor R21, and a resistor R22; wherein,

[0007] The source of the PMOS adjustment transistor MP2 is connected to the power supply voltage VDD, and the resistors R21 and R22 are connected in series between the drain of the PMOS adjustment transistor MP2 and the ground;

[0008] The positive input terminal of the differential amplifier A2 is connected between the resistors R21 and R22, and the negative input terminal is connected to the reference voltage VREF2;

[0009] The pole adjustment module is connected between the output terminal of the differential amplifier A2 and the gate of the PMOS adjustment transistor MP2. The first end of the compensation capacitor CM2 is connected to the pole adjustment module, and the second end is connected to the drain of the PMOS adjustment transistor MP2. The output terminal VOUT of the low dropout linear regulator is connected to the drain of the PMOS adjustment transistor MP2 and the first end of the load capacitor CL2, and the second end of the load capacitor CL2 is connected to the ground.

[0010] In an embodiment, the pole adjustment module includes a PMOS transistor MP21, a PMOS transistor MP22, a PMOS transistor MP23, an NMOS transistor MN21, and an NMOS transistor MN22; wherein,

[0011] The sources of the PMOS transistors MP21, MP22, and MP23 are all connected to the power supply voltage VDD, and the sources of the NMOS transistors MN21 and MN22 are all connected to the ground;

[0012] The gate and drain of the PMOS transistor MP21 are short-circuited and connected together with the output terminal VA2 of the differential amplifier A2 and the gate of the PMOS transistor MP22; the PMOS transistors MP21 and MP22 form a current mirror structure;

[0013] The gate and drain of the NMOS transistor MN21 are short-circuited and connected together with the drain of the PMOS transistor MP22 and the gate of the NMOS transistor MN22 to form a node Q1; the NMOS transistors MN21 and MN22 form a current mirror structure;

[0014] The gate and drain of the PMOS transistor MP23 are short-circuited and connected together with the drain of the NMOS transistor MN22, the gate of the PMOS adjustment transistor MP2, and the first end of the compensation capacitor CM2 to form a node Q2; the node Q2 controls the gate voltage of the PMOS adjustment transistor MP2, thereby controlling the load current.

[0015] In one embodiment, the PMOS transistors MP21 and PMOS transistor PMOS tube MP22 have the same size.

[0016] In one embodiment, the size of the PMOS transistor MP23 is much smaller than the size of the PMOS adjustment transistor MP2.

[0017] In one embodiment, the sizes of the NMOS transistors MN21 and MN22 are proportional.

[0018] In one embodiment, the capacitance value of the load capacitor CL2 is 0.

[0019] In one embodiment, the low dropout linear regulator is a capacitorless LDO circuit.

[0020] In a low dropout linear regulator provided by the present invention, when the load current changes, the impedance of the main pole corresponding to the gate of the PMOS adjustment transistor MP2 changes with the change of the load current, so that the main pole and the secondary pole move simultaneously with the change of the load current, thereby improving the loop stability of the low dropout linear regulator; at the same time, when the load current increases, the NMOS transistor MN22 in the pole adjustment module controls the gate voltage of the PMOS adjustment transistor MP2 to further decrease, which also ensures the stability of the output current. Description of the Drawings

[0021] Figure 1 is a schematic diagram of a conventional LDO circuit structure with a compensation capacitor.

[0022] Figure 2 is a schematic diagram of a low dropout linear regulator proposed by the present invention. Detailed Embodiments

[0023] The following further describes in detail a low dropout linear regulator proposed by the present invention with reference to the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention.

[0024] The present invention provides a low dropout linear regulator, the structure of which is as Figure 1As shown in the figure, it includes a differential amplifier A2, a PMOS regulating transistor MP2, a pole adjustment module, a compensation capacitor CM2, a load capacitor CL2, a resistor R21, and a resistor R22. Among them, the source of the PMOS regulating transistor MP2 is connected to the power supply voltage VDD, and the resistors R21 and R22 are connected in series between the drain of the PMOS regulating transistor MP2 and the ground. The positive input terminal of the differential amplifier A2 is connected between the resistors R21 and R22, and the negative input terminal is connected to the reference voltage VREF2. The pole adjustment module is connected between the output terminal of the differential amplifier A2 and the gate of the PMOS regulating transistor MP2. The first end of the compensation capacitor CM2 is connected to the pole adjustment module, and the second end is connected to the drain of the PMOS regulating transistor MP2. The output terminal VOUT of the low-dropout linear regulator is connected to the drain of the PMOS regulating transistor MP2 and the first end of the load capacitor CL2. The second end of the load capacitor CL2 is connected to the ground. The capacitance value of the load capacitor CL2 can be 0. Therefore, the low-dropout linear regulator of the present invention can be called a capacitorless LDO circuit.

[0025] Please continue to refer to Figure 2 , the pole adjustment module 20 includes a PMOS transistor MP21, a PMOS transistor MP22, a PMOS transistor MP23, an NMOS transistor MN21, and an NMOS transistor MN22. Among them, the sources of the PMOS transistors MP21, MP22, and MP23 are all connected to the power supply voltage VDD, and the sources of the NMOS transistors MN21 and MN22 are all connected to the ground. The gate and drain of the PMOS transistor MP21 are short-circuited and connected together with the output terminal VA2 of the differential amplifier A2 and the gate of the PMOS transistor MP22. The PMOS transistors MP21 and MP22 form a current mirror structure. The gate and drain of the NMOS transistor MN21 are short-circuited and connected together with the drain of the PMOS transistor MP22 and the gate of the NMOS transistor MN22 to form a node Q1. The NMOS transistors MN21 and MN22 form a current mirror structure. The gate and drain of the PMOS transistor MP23 are short-circuited and connected together with the drain of the NMOS transistor MN22, the gate of the PMOS regulating transistor MP2, and the first end of the compensation capacitor CM2 to form a node Q2. The node Q2 controls the gate voltage of the PMOS regulating transistor MP2, and further controls the load current.

[0026] Among them, the sizes (i.e., width-to-length ratios) of the PMOS transistors MP21 and MP22 in the pole adjustment module 20 are the same, that is, (W / L) MP21 =(W / L) MP22 . The sizes of the NMOS transistors MN21 and MN22 maintain a certain proportional relationship to ensure sufficient gain, that is, (W / L) MN22 / (W / L) MN21= K. For example, K is taken as 25. In addition, the size of the PMOS transistor MP23 is designed to be much smaller than that of the PMOS regulating transistor MP2, that is, (W / L) MP23 << (W / L) MP2 .

[0027] In this embodiment, the specific working principle of the low dropout linear regulator is as follows: The voltage VOUT output by the low dropout linear regulator is divided by the resistors R21 and R22, and the expression of the voltage VFB2 is obtained as:

[0028]

[0029] When the load current increases, the voltage VFB2 at the positive input terminal of the differential amplifier A2 is compared with the reference voltage VREF2 at the negative input terminal, and the output voltage VA2 decreases. The voltage VA2 passes through the current mirror formed by the PMOS transistors MP21 and MP22 to obtain the node Q1 voltage and the current I1 flowing through the drain-source of the NMOS transistor MN21. The node Q1 voltage increases, and after passing through the current mirror formed by the NMOS transistors MN21 and MN22, the node Q2 voltage and the current I2 flowing through the drain-source of the NMOS transistor MN22 are obtained. The node Q2 voltage decreases, and then the gate voltage of the PMOS regulating transistor MP2 is adjusted, finally stabilizing the load current.

[0030] When the load current of the low dropout linear regulator gradually increases, the corresponding secondary pole at the output terminal gradually moves from low frequency to high frequency. At this time, according to the increase of the node Q1 voltage, it can be known that the current I2 flowing through the NMOS transistor MN22 increases. And because the output impedance r out is:

[0031]

[0032] where λ is the channel length modulation coefficient, μ P represents the hole mobility, C ox is the gate capacitance per unit area, and the output impedance r out decreases. And because the PMOS transistor MP23 and the PMOS regulating transistor MP2 form a current mirror structure, the current I2 and the load current satisfy a linear proportional relationship. Therefore, the main pole frequency corresponding to the node Q2 moves to high frequency as the load current increases.

[0033] In summary, in the low dropout linear regulator proposed in the present invention, as the load current gradually increases, the secondary pole gradually moves to high frequency, and at the same time, through the current mirror, the main pole also follows the change of the load and moves to high frequency, thus ensuring the stability of the low dropout linear regulator.

[0034] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the scope of protection of the claims.

Claims

1. A low dropout linear regulator, characterized in that, It includes a differential amplifier A2, a PMOS regulating transistor MP2, a pole adjustment module, a compensation capacitor CM2, a load capacitor CL2, a resistor R21, and a resistor R22. Among them, the source of the PMOS regulating transistor MP2 is connected to the power supply voltage VDD, and the resistors R21 and R22 are connected in series between the drain of the PMOS regulating transistor MP2 and the ground; the positive input terminal of the differential amplifier A2 is connected between the resistors R21 and R22, and the negative input terminal is connected to the reference voltage VREF2; the pole adjustment module is connected between the output terminal of the differential amplifier A2 and the gate of the PMOS regulating transistor MP2. The first end of the compensation capacitor CM2 is connected to the pole adjustment module, and the second end is connected to the drain of the PMOS regulating transistor MP2. The output terminal VOUT of the low dropout linear regulator is connected to the drain of the PMOS regulating transistor MP2 and the first end of the load capacitor CL2, and the second end of the load capacitor CL2 is connected to the ground; the pole adjustment module includes a PMOS transistor MP21, a PMOS transistor MP22, a PMOS transistor MP23, an NMOS transistor MN21, and an NMOS transistor MN22. Among them, the sources of the PMOS transistors MP21, MP22, and MP23 are all connected to the power supply voltage VDD, and the sources of the NMOS transistors MN21 and MN22 are all connected to the ground; the gate and drain of the PMOS transistor MP21 are short-circuited and connected together with the output terminal VA2 of the differential amplifier A2 and the gate of the PMOS transistor MP22. The PMOS transistor MP21 and the PMOS transistor MP22 form a current mirror structure; the gate and drain of the NMOS transistor MN21 are short-circuited and connected together with the drain of the PMOS transistor MP22 and the gate of the NMOS transistor MN22 to form a node Q1. The NMOS transistor MN21 and the NMOS transistor MN22 form a current mirror structure; the gate and drain of the PMOS transistor MP23 are short-circuited and connected together with the drain of the NMOS transistor MN22, the gate of the PMOS regulating transistor MP2, and the first end of the compensation capacitor CM2 to form a node Q2. The node Q2 controls the gate voltage of the PMOS regulating transistor MP2, thereby controlling the load current.

2. The low dropout linear regulator according to claim 1, characterized in that, The PMOS transistor MP21 and the PMOS transistor MP22 have the same size.

3. The low dropout linear regulator according to claim 1, characterized in that, The NMOS transistor MN21 and the NMOS transistor MN22 are in proportion in size.

4. The low dropout linear regulator according to claim 1, wherein The capacitance value of the load capacitor CL2 is 0.

5. The low dropout linear regulator according to claim 1, characterized in that, The low dropout linear regulator is a capacitorless LDO circuit.

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