Display panel and laser signal generating circuit thereof

Abstract

A display panel and a laser signal generating circuit therefor are provided. The laser signal generating circuit includes an output stage circuit, a first control signal generator, a second control signal generator, a switch, and a first capacitor. The output stage circuit generates a laser signal based on the first control signal and the second control signal. The first control signal generator generates a first control signal at a first control terminal. The second control signal generator generates a second control signal at a second control terminal. The switch is coupled between the first control terminal and the output stage circuit. The first capacitor is coupled to the first control terminal.

Description

Technical Field

[0001] The present invention relates to a display panel and a laser signal generating circuit, and in particular to a display panel and a laser signal generating circuit capable of improving reliability. Background Art

[0002] In current LED display devices, the activation period of the laser signal that illuminates the LEDs is shortened. This shortened activation period prolongs the stabilization period of the laser signal generation circuit, and the generated laser signal maintains a high voltage for a longer period of time. Consequently, some components in the laser signal generation circuit are subject to a high voltage bias for extended periods of time, accelerating component degradation and reducing the reliability of the display device. Summary of the Invention

[0003] The present invention provides a display panel and a laser signal generating circuit, which can effectively improve the reliability of a display device.

[0004] The laser signal generating circuit of the present invention includes an output stage circuit, a first control signal generator, a second control signal generator, a switch and a first capacitor. The output stage circuit generates a laser signal according to the first control signal and the second control signal. The first control signal generator is coupled to the output stage circuit and the first control terminal, and generates a first control signal at the first control terminal according to a reference laser signal, a first clock signal, a first reference voltage and a second reference voltage. The second control signal generator is coupled to the output stage circuit and the second control terminal, and generates a second control signal at the second control terminal according to the reference laser signal, the first clock signal, the first reference voltage and the second reference voltage. The switch is coupled between the first control terminal and the output stage circuit, and the control terminal of the switch receives the second reference voltage. The first capacitor has a first end coupled to the first control terminal, and a second end of the first capacitor receives a third reference voltage.

[0005] The display panel of the present invention includes a laser driver, which includes a plurality of laser signal generating circuits as described above.

[0006] Based on the above, the laser signal generating circuit of the present invention comprises a switch and a first capacitor disposed between the output stage circuit and the first control terminal. The switch can be used to disconnect or connect the connection path between the first control terminal and the output stage circuit. When the switch is turned on, the first capacitor can form a voltage divider circuit with the capacitor in the output stage circuit, thereby reducing the voltage applied to the output stage circuit and thereby reducing the risk of damage to the output stage circuit. When the switch is turned off, the voltage at the first control terminal is not affected by the jitter of the clock signal, thereby reducing the risk of damage to the circuit components of the first control signal generator and the second control signal generator. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram showing a laser signal generating circuit according to an embodiment of the present invention is shown.

[0008] Figure 2 A circuit diagram showing a laser signal generating circuit according to another embodiment of the present invention is shown.

[0009] Figures 3A to 3C The following illustrates the implementation of the laser signal generating circuit according to the embodiment of the present invention during the stabilization period.

[0010] Figure 4 The following shows how the laser signal generating circuit according to the embodiment of the present invention operates during output.

[0011] Figure 5 A schematic diagram showing a display panel according to an embodiment of the present invention.

[0012] Description of reference numerals:

[0013] 100, 200, 511~51A: Laser signal generation circuit

[0014] 110, 210: Output stage circuit

[0015] 120, 130, 220, 230: Control signal generator

[0016] 121, 122: Partial circuit

[0017] 240: Signal selector

[0018] 500: Display panel

[0019] 510: Laser Driver

[0020] C1, C2, C3: capacitors

[0021] CTS1, CTS2: control signals

[0022] ED: Ending signal

[0023] EM, EM1~EMA: laser signal

[0024] EMN: post-stage laser signal

[0025] EMP: Pre-laser signal

[0026] EMR: Reference laser signal

[0027] Q0: First control terminal

[0028] Q3: Second control terminal

[0029] RST: Reset voltage

[0030] ST: Start signal

[0031] SW1: switch

[0032] T1~T11:Transistors

[0033] U2D, D2U: Select signal

[0034] VGH, VGL: reference voltage

[0035] XCK, CK: clock signal DETAILED DESCRIPTION

[0036] Please refer to Figure 1 , Figure 1 A schematic diagram of a laser signal generating circuit according to an embodiment of the present invention is shown. Laser signal generating circuit 100 includes an output stage circuit 110, control signal generators 120 and 130, a switch SW1, and a capacitor C3. Output stage circuit 110 generates laser signal EM based on control signals CTS1 and CTS2, and a clock signal CK. Output stage circuit 110 can pull laser signal EM down to a reference voltage VGL based on control signal CTS1, or pull laser signal EM up to a reference voltage VGH based on control signal CTS2. Reference voltage VGH is higher than reference voltage VGL.

[0037] The control signal generator 120 is coupled to the first control terminal Q0 and the output stage circuit 110. In this embodiment, the control signal generator 120 includes a first circuit section 121 and a second circuit section 122. The control signal generator 120 can generate a control signal CTS1 at the first control terminal Q0 based on the reference laser signal EMR, the clock signal XCK, and the reference voltages VGH and VGL, and provide the control signal CTS1 to the output stage circuit 110 via the switch SW1. The clock signal XCK is an inverted signal of the clock signal CK.

[0038] The control signal generator 130 is coupled to the second control terminal Q3 and the output stage circuit 110. The control signal generator 130 generates a control signal CTS2 at the second control terminal Q3 according to the reference laser signal EMR, the clock signal XCK, and the reference voltages VGH and VGL, and provides the control signal CTS2 to the output stage circuit 110.

[0039] It is worth noting that a first terminal of capacitor C3 is coupled to the first control terminal Q0, and a second terminal of capacitor C3 can receive a reference voltage VG3. Reference voltage VG3 is a constant voltage, such as reference voltage VGH, or any voltage lower than reference voltage VGH. In addition, switch SW1 is coupled between the first control terminal Q0 and the output stage circuit 110. The control terminal of switch SW1 receives reference voltage VGL. When switch SW1 is turned on, control signal generator 120 can provide control signal CTS1 to output stage circuit 110. When switch SW1 is turned off, the connection path between the first control terminal Q0 and output stage circuit 110 can be cut off.

[0040] In this embodiment of the present invention, when the laser signal generating circuit 100 is operating in the output phase, the switch SW1 can be disconnected. Simultaneously, because the connection between the first control terminal Q0 and the output stage circuit 110 is disconnected, the voltage at the first control terminal Q0 is not affected by the periodic transitions of the clock signal CK in the output stage circuit 110 and can be maintained at a fixed voltage level. This can slow down the aging of circuit components in the second circuit portion 122 of the control signal generator 120, and ensure that the output stage circuit 110 has relatively stable driving capabilities.

[0041] On the other hand, when the laser signal generating circuit 100 is operating in a stable state, the switch SW1 can be turned on. Under these conditions, the capacitor C3 can be coupled to a capacitor within the output stage circuit 110 via the switch SW1, thereby forming a voltage divider circuit. As a result, the voltage at the terminal of the output stage circuit 110 that receives the control signal CTS1 can reduce fluctuations caused by the periodic transitions of the clock signal CK due to the voltage divider effect of the voltage divider circuit, thereby increasing the stability of the output stage circuit 110.

[0042] For details about the laser signal generating circuit of the present invention, please refer to Figure 2 FIG. 1 is a circuit diagram of a laser signal generating circuit according to another embodiment of the present invention. Figure 2 In the embodiment, the laser signal generating circuit 200 includes an output stage circuit 210 , control signal generators 220 and 230 , a switch SW1 , a capacitor C3 , and a signal selector 240 .

[0043] In this embodiment, the signal selector 240 includes transistors T9 and T10. The first end of transistor T9 receives the front-stage laser signal EMP, and the second end of transistor T9 is coupled to the second end of transistor T10. The first end of transistor T10 receives the rear-stage laser signal EMN. The control ends of transistors T9 and T10 receive selection signals U2D and D2U, respectively. When the laser signal generating circuit 200 is implemented in a display panel, the laser signal generating circuit 200 can be configured in the same display panel with multiple laser signal generating circuits of the same circuit architecture. The selection signals U2D and D2U are used to set the scanning direction of the multiple laser signal generating circuits in the display panel. The selection signals U2D and D2U are complementary. In this embodiment, when the selection signal U2D is a logic low voltage (the selection signal D2U is a logic high voltage), the signal selector 240 selects to output the front-stage laser signal EMP as the reference laser signal EMR. In contrast, when the selection signal U2D is at a logic high voltage (the selection signal D2U is at a logic low voltage), the signal selector 240 selects and outputs the subsequent laser signal EMN as the reference laser signal EMR.

[0044] Furthermore, the control signal generator 220 includes transistors T1 and T4. One terminal of transistor T1 receives the reference laser signal EMR, while the other terminal of transistor T1 is coupled to the first control terminal Q0 and to the switch SW1. One terminal of transistor T4 is coupled to the first control terminal Q0, while the other terminal of transistor T4 receives the reference voltage VGH. The control terminal of transistor T1 receives the clock signal XCK, while the control terminal of transistor T4 is coupled to the second control terminal Q3 to receive the second control signal CTS2.

[0045] In this embodiment, the transistor T1 can be periodically turned on or off according to the clock signal XCK. When the transistor T1 is turned on, the transistor T1 can transmit the reference laser signal EMR as a basis for generating the first control signal CTS1.

[0046] The control signal generator 230 includes transistors T5 to T8 and a capacitor C1. A first terminal of transistor T5 receives a reference voltage VGL, a control terminal of transistor T5 is coupled to the coupling terminal of capacitor C1 and transistor T7, and a second terminal of transistor T5 is coupled to a second control terminal Q3. Transistor T8 is coupled in parallel with transistor T5, and a control terminal of transistor T8 receives a reset voltage RST. A first terminal of transistor T6 is coupled to a second terminal of transistor T5, a second terminal of transistor T6 receives a reference voltage VGH, and a control terminal of transistor T6 is coupled to a first control terminal Q0. In this embodiment, when transistor T6 is turned on, it is configured to pull a second control signal CTS2 high according to the reference voltage VGH. Each of transistors T5 and T8 can pull a second control signal CTS2 low according to the reference voltage VGH when turned on.

[0047] Furthermore, a first terminal of transistor T7 is coupled to capacitor C1 and the control terminal of transistor T5. A second terminal of transistor T7 receives a reference voltage VGH, and a control terminal of transistor T7 receives a reference laser signal EMR. The other terminal of capacitor C1 receives a clock signal XCK. When the reference laser signal EMR is at a logic low voltage, transistor T7 can be turned on. The signal at the control terminal of transistor T5 can be maintained equal to the reference voltage VGH. When the reference laser signal EMR is at a logic high voltage, transistor T7 can be turned off. The signal at the control terminal of transistor T5 can be a periodic clock signal based on the clock signal XCK.

[0048] One terminal of capacitor C3 is coupled to the first control terminal Q0. In this embodiment, the other terminal of capacitor C3 can receive a reference voltage VGH. Switch SW1 is implemented by transistor T11. One terminal of transistor T11 is coupled to the first control terminal Q0, the other terminal of transistor T11 is coupled to the output stage circuit 210, and the control terminal of transistor T11 receives the reference voltage VGL.

[0049] In this embodiment, the output stage circuit 210 includes transistors T2 and T3, and a capacitor C2. A first terminal of transistor T2 receives a reference voltage VGL, a second terminal of transistor T2 is used to generate a laser signal EM, and a control terminal of transistor T2 is coupled to switch SW1 and receives a first control signal CTS1. A first terminal of transistor T3 receives a reference voltage VGH, a second terminal of transistor T3 is coupled to the second terminal of transistor T2, and is used to generate the laser signal EM. A control terminal of transistor T3 is coupled to a second control terminal Q3 and receives a second control signal CTS2.

[0050] For details on the operation of the laser signal generating circuit 200, please refer to the following Figures 3A to 4 Implementation method. Figures 3A to 3C FIG. 4 shows an implementation of the laser signal generating circuit according to an embodiment of the present invention during a stable period. Figure 4 FIG. 1 shows an implementation of the laser signal generating circuit during output according to an embodiment of the present invention. Figure 3A In the example, the laser signal generating circuit 200 operates during a stable period. When transistor T1 is turned on according to the clock signal XCK, for example, transistor T9 is turned on (transistor T10 is turned off), the preceding laser signal EMP can be transmitted to the first control terminal Q0 via transistor T1. When the preceding laser signal EMP is at a logic high voltage, transistor T7 is turned off. Since the clock signal XCK is at a logic low voltage, the voltage at the control terminal of transistor T5 is a logic low voltage, turning on transistor T5. Therefore, the second control signal CTS2 at the second control terminal Q3 can be equal to the reference voltage VGL, turning on transistor T3. Correspondingly, transistor T4 can be turned on.

[0051] With transistor T4 turned on, the voltage at the first control terminal Q0 can be equal to the reference voltage VGH and reach a logic high voltage. At this point, transistor T11, acting as a switch, is turned on, causing the first control signal CTS1 to be equal to the voltage at the first control terminal Q0 (equal to the reference voltage VGH). Consequently, transistor T2 can be turned off.

[0052] It can be seen from the above description that the laser signal generating circuit 200 can generate the laser signal EM substantially equal to the reference voltage VGH by turning on the transistor T3 and turning off the transistor T2.

[0053] exist Figure 3B In the embodiment of FIG. 2 , the laser signal generating circuit 200 continues to operate in a stable period. However, because the clock signal XCK transitions to a logic high voltage, transistor T1 is turned off. At this time, transistor T11 remains in an on state, and capacitors C3 and C2 are connected in series through transistor T11 to form a voltage divider circuit. The voltage divider circuit formed by capacitors C3 and C2 can divide the voltage difference between the reference voltage VGH and the clock signal CK to generate the first control signal CTS1. In this case, the clock signal CK is equal to the reference voltage VGL. In other words, the voltage value of the first control signal CTS1 is, for example, equal to VGH + (VGH – VGL) * C2 / (C2 + C3).

[0054] Incidentally, the capacitance of capacitor C3 may be equal to that of capacitor C2. In other embodiments of the present invention, the capacitance of capacitor C3 may also be (slightly) larger than that of capacitor C2 to effectively reduce the voltage of the first control signal CTS1.

[0055] In addition, according to Figure 3C The corresponding Figure 3A When transistor T1 is turned on, the reference laser signal EMR, which is a logic low voltage, can be provided to the first control terminal Q0 through transistor T1. Since one end of capacitor C2 receives the clock signal CK, the first control signal CTS1 can correspond to the coupling effect generated by the clock signal CK through capacitor C2, and become a signal with multiple ripples. Here, based on the series structure of capacitors C3 and C2, this coupling amount is prevented from being fed back to the signal on the first control terminal Q0. In other words, the gate-source voltage difference borne by transistor T6 will not be amplified, effectively reducing the aging rate of transistor T6. Similarly, the source-drain voltage difference of transistor T4 will not increase due to the above-mentioned coupling phenomenon, reducing the risk of leakage current.

[0056] On the other hand, in Figure 4In the embodiment, the laser signal generating circuit 200 operates during the output period. During this period, transistor T1 is turned off in response to a clock signal equal to the reference voltage VGH, and the voltage at the first control terminal Q0 is equal to the reference voltage VGL plus the absolute value of the threshold voltage of transistor T1. Correspondingly, the voltage value of the first control signal CTS1 can be equal to the reference voltage VGL plus the absolute value of the threshold voltage of transistor T11, plus the difference between the threshold voltages VGL and VGH. The difference between the threshold voltages VGL and VGH contributes to the coupling generated by capacitor C2 in response to the clock signal CK (transitioning between the threshold voltages VGL and VGH). Accordingly, transistor T11, acting as a switch, is in the off state.

[0057] Because transistor T11 is turned off, the periodic fluctuations in the first control signal CTS1 due to the coupling of the clock signal CK through capacitor C2 do not affect the voltage at the first control terminal Q0. Consequently, the gate-source voltage of transistor T6 is not increased, effectively slowing the aging rate. Furthermore, the source-drain voltage of transistor T4 is also not increased due to the coupling of the clock signal CK through capacitor C2, reducing potential leakage current and maintaining a stable output capability for transistor T2.

[0058] Incidentally, in this embodiment, transistors T1 and T11 may have the same threshold voltage. Furthermore, the second control signal CTS2 is equal to the reference voltage VGH, and the voltage at the control terminal of transistor T5 may also be equal to the reference voltage VGH. During the output period, transistor T2 is turned on, while transistor T3 is turned off. Laser signal generating circuit 200 can generate laser signal EM equal to reference voltage VGL.

[0059] Please refer to the following Figure 5 , Figure 5 A schematic diagram of a display panel according to an embodiment of the present invention is shown. Display panel 500 includes a laser driver 510. Laser driver 510 is configured to generate a plurality of laser signals EM1-EMA. Laser signals EM1-EMA are configured to drive corresponding light-emitting diodes. Laser driver 510 includes a plurality of laser signal generators 511-51A, which can be coupled to shift registers. Each laser signal generator 511-51A can be implemented using any of the laser signal generators described in the aforementioned embodiments, and the detailed operation thereof will not be elaborated upon.

[0060] In this embodiment, the first-stage laser signal generator 511 may receive reference voltages VGH and VGL, clock signals XCK and CK, selection signals U2D and D2U, a start signal ST, and a laser signal EM2 generated by the first-stage laser signal generator 512. The first-stage laser signal generator 511 may select the start signal ST or the laser signal EM2 as a reference laser signal according to the selection signals U2D and D2U, and generate the laser signal EM1 based on the reference voltages VGH and VGL and the clock signals XCK and CK.

[0061] Furthermore, in this embodiment, the intermediate (second) stage laser signal generator 512 may receive reference voltages VGH and VGL, clock signals XCK and CK, selection signals U2D and D2U, laser signal EM1 generated by the first (previous) stage laser signal generator 511, and laser signal EM3 generated by the third (latter) stage laser signal generator. The first stage laser signal generator 512 may select either laser signal EM1 or laser signal EM3 as a reference laser signal based on selection signals U2D and D2U, and generate laser signal EM2 based on reference voltages VGH and VGL and clock signals XCK and CK.

[0062] The laser signal generator 51A of the last stage (stage A) receives reference voltages VGH and VGL, clock signals XCK and CK, selection signals U2D and D2U, laser signal EMA-1 generated by the laser signal generator of the previous stage (stage A-1), and end signal ED. The laser signal generator 512 of the first stage selects laser signal EMA-1 or end signal ED as the reference laser signal based on selection signals U2D and D2U, and generates laser signal EMA based on reference voltages VGH and VGL and clock signals XCK and CK.

[0063] In this embodiment, the laser signals EM1 -EMA may be enabled in sequence. In this embodiment, each of the laser signals EM1 -EMA is enabled when it is equal to the reference voltage VGL.

[0064] In summary, the laser signal generating circuit of the present invention sets a switch between the output stage circuit and the first control terminal. By cutting off the switch, the voltage coupling generated by the transition phenomenon of the clock signal on the output stage circuit can be prevented from interfering with the operation of other circuit components. The laser signal generating circuit of the present invention sets a capacitor on the first control terminal, so that the above-mentioned capacitor and the capacitor in the output stage circuit produce a voltage divider effect, which can effectively reduce the voltage value on the first control terminal during the stable period, and reduce the influence of the voltage coupling generated by the transition phenomenon of the clock signal. In this way, the aging rate of the components of the laser signal generating circuit can be reduced, and its output stability can be improved, effectively improving the reliability of the laser signal generating circuit and the corresponding display panel.

Claims

1. A laser signal generating circuit, comprising: an output stage circuit for generating a laser signal according to a first control signal and a second control signal; a first control signal generator coupled to the output stage circuit and a first control terminal, generating the first control signal at the first control terminal according to a reference laser signal, a first clock signal, a first reference voltage, and a second reference voltage; a second control signal generator coupled to the output stage circuit and a second control terminal, for generating the second control signal at the second control terminal according to the reference laser signal, the first clock signal, the first reference voltage, and the second reference voltage; a switch coupled between the first control terminal and the output stage circuit, wherein the control terminal of the switch receives the second reference voltage; and a first capacitor having a first terminal coupled to the first control terminal, and a second terminal of the first capacitor receiving a third reference voltage; During an output period, the switch is turned off to isolate the output stage circuit from the first control terminal. 2 . The laser signal generating circuit as claimed in claim 1 , wherein the first reference voltage is higher than the second reference voltage.

3. The laser signal generating circuit as claimed in claim 1 , wherein the output stage circuit comprises: a first transistor having a first terminal receiving the second reference voltage, a control terminal of the first transistor coupled to the switch, and a second terminal of the first transistor generating the laser signal; a second capacitor having a first terminal for receiving a second clock signal, and a second terminal of the second capacitor coupled to the control terminal of the first transistor; as well as a second transistor having a first terminal receiving the first reference voltage, a control terminal of the second transistor coupled to the second control terminal, and a second terminal of the second transistor coupled to the second terminal of the first transistor; The first clock signal is an inverted signal of the second clock signal. 4 . The laser signal generating circuit as claimed in claim 3 , wherein a capacitance value of the second capacitor is greater than or equal to a capacitance value of the first capacitor. 5 . The laser signal generating circuit as claimed in claim 3 , wherein during a stable operation period, the switch is turned on so that the first capacitor and the second capacitor form a voltage divider circuit.

6. The laser signal generating circuit as claimed in claim 1 , wherein the first control signal generator comprises: a first transistor having a first terminal for receiving a reference laser signal, a control terminal of the first transistor for receiving the first clock signal, and a second terminal of the first transistor coupled to the first control terminal; as well as A second transistor has a first terminal coupled to the first control terminal, a control terminal of the second transistor coupled to the second control terminal, and a second terminal of the second transistor receiving the second reference voltage.

7. The laser signal generating circuit as claimed in claim 1 , wherein the second control signal generator comprises: a first transistor having a first terminal for receiving the second reference voltage, and a second terminal of the first transistor coupled to the second control terminal; a second transistor having a first terminal coupled to the second terminal of the first transistor, a control terminal of the second transistor coupled to the first control terminal, and a second terminal of the second transistor receiving the second reference voltage; a third transistor having a first terminal coupled to the control terminal of the first transistor, the control terminal of the third transistor receiving the reference laser signal, and a second terminal of the third transistor receiving the second reference voltage; as well as A second capacitor has a first terminal for receiving the first clock signal, and a second terminal of the second capacitor is coupled to the control terminal of the first transistor.

8. The laser signal generating circuit as claimed in claim 7, wherein the second control signal generator further comprises: A fourth transistor is coupled in parallel with the first transistor and is controlled by a reset voltage.

9. The laser signal generating circuit according to claim 1 , further comprising: A signal selector selects a front-stage laser signal or a rear-stage laser signal to generate the reference laser signal.

10. A display panel comprising: A laser driver includes a plurality of laser signal generating circuits, each of the laser signal generating circuits including: an output stage circuit for generating a laser signal according to a first control signal and a second control signal; a first control signal generator coupled to the output stage circuit and a first control terminal, generating the first control signal at the first control terminal according to a reference laser signal, a first clock signal, a first reference voltage, and a second reference voltage; a second control signal generator coupled to the output stage circuit and a second control terminal, for generating the second control signal at the second control terminal according to the reference laser signal, the first clock signal, the first reference voltage, and the second reference voltage; a switch coupled between the first control terminal and the output stage circuit, wherein the control terminal of the switch receives the second reference voltage; and a first capacitor having a first terminal coupled to the first control terminal, and a second terminal of the first capacitor receiving a third reference voltage; During an output period, the switch is turned off to isolate the output stage circuit from the first control terminal.

11. The display panel as claimed in claim 10, wherein the output stage circuit comprises: a first transistor having a first terminal receiving the second reference voltage, a control terminal of the first transistor coupled to the switch, and a second terminal of the first transistor generating the laser signal; a second capacitor having a first terminal for receiving a second clock signal, and a second terminal of the second capacitor coupled to the control terminal of the first transistor; as well as A second transistor has a first terminal receiving the first reference voltage, a control terminal of the second transistor coupled to the second control terminal, and a second terminal of the second transistor coupled to the second terminal of the first transistor. 12 . The display panel as claimed in claim 11 , wherein a capacitance value of the second capacitor is greater than or equal to a capacitance value of the first capacitor. 13 . The display panel as claimed in claim 11 , wherein during a stable operation period, the switch is turned on so that the first capacitor and the second capacitor form a voltage divider circuit. 14 . The display panel as claimed in claim 10 , wherein the reference laser signal is a preceding laser signal, a succeeding laser signal, or a start signal.

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