Pixel driving circuit and driving method thereof, display panel

Abstract

The application discloses a pixel driving circuit and a driving method thereof and a display panel. The pixel driving circuit comprises a driving transistor, a storage capacitor, a writing sub-circuit, a first reset sub-circuit, a second reset sub-circuit and a first threshold control sub-circuit. The first reset sub-circuit is used for providing a voltage of a first reset signal end to a second end of the driving transistor in response to control of a first scan signal. The second reset sub-circuit is used for providing a voltage of a second reset signal end to a control end of the driving transistor and the storage capacitor in response to control of a third scan signal. The writing sub-circuit is used for providing a voltage of a data signal end to a first end of the driving transistor in response to control of a fourth scan signal. The first threshold control sub-circuit is used for turning on a connection between the control end of the driving transistor and the second end of the driving transistor in response to control of a second scan signal. The voltage of the first reset signal end and the voltage of the second reset signal end are opposite in polarity.

Description

TECHNICAL FIELD

[0001] The present application generally relates to the technical field of display, and in particular to a pixel driving circuit, a driving method thereof and a display panel. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) display panel has gradually occupied the vast majority of market share in recent years. OLED display panel is widely concerned due to its advantages such as lightness, excellent display effect, high contrast, wide color gamut, flexibility and the like, and is considered as a next generation display scheme expected to replace liquid crystal.

[0003] With the increasing demand for screen display diversification, improving screen utilization has become a new development demand. At present, the screen refresh frequency is mainly reduced to meet the demand in some displays to reduce power consumption. For example, a driving mode with a higher refresh rate is used to drive the display of dynamic pictures (such as sports events or game scenes) to ensure the smoothness of the display picture; a driving mode with a lower refresh rate is used to drive the display of slow-motion images or static pictures to reduce power consumption.

[0004] However, while the OLED display product realizes low power consumption and adaptive dynamic refresh rate driving, there are problems such as low-frequency flicker, refresh frequency switching flicker and first-frame response flicker. SUMMARY

[0005] In view of the above defects or deficiencies in the prior art, it is desirable to provide a pixel driving circuit, a driving method thereof and a display panel, which can improve the problems of low-frequency flicker, refresh frequency switching flicker and first-frame response flicker.

[0006] In a first aspect, the present application provides a pixel driving circuit, comprising a driving transistor, a storage capacitor, a writing sub-circuit, a first reset sub-circuit, a second reset sub-circuit, a first threshold control sub-circuit,

[0007] The driving transistor is configured to generate a driving current on a conduction path from a first end to a second end in response to a control of a control end signal voltage;

[0008] The first reset sub-circuit is connected to the second end of the driving transistor and is configured to provide a voltage of a first reset signal end to the second end of the driving transistor in response to a control of a first scan signal;

[0009] The second reset sub-circuit is connected to the control end of the driving transistor, the storage capacitor and the first end of the first threshold control sub-circuit, and is configured to provide a voltage of a second reset signal end to the control end of the driving transistor and the storage capacitor in response to a control of a third scan signal.

[0010] The write sub-circuit is connected with the first end of the driving transistor, and is configured to provide a voltage of a data signal end to the first end of the driving transistor in response to control of a fourth scan signal;

[0011] The second end of the first threshold control sub-circuit is connected with the second end of the driving transistor, and is configured to turn on the connection between the control end of the driving transistor and the second end of the driving transistor in response to control of a second scan signal;

[0012] The voltage of the first reset signal end is opposite in polarity to the voltage of the second reset signal end.

[0013] Optionally, the display panel further comprises a light emitting element, a first light emitting sub-circuit, a second light emitting sub-circuit and a third reset sub-circuit, wherein,

[0014] The first light emitting sub-circuit is connected with a first power supply end and the first end of the driving transistor, and is configured to provide a voltage of the first power supply end to the driving transistor in response to control of a light emitting signal;

[0015] The second light emitting sub-circuit is connected with the second end of the driving transistor and the first end of the light emitting element, and is configured to provide a driving current of the driving transistor to the light emitting element in response to control of the light emitting signal, and the second end of the light emitting element is connected with a second power supply end;

[0016] The third reset sub-circuit is connected with the second end of the second light emitting sub-circuit and the first end of the light emitting element, and is configured to provide a voltage of the third reset signal end to the second end of the second light emitting sub-circuit and the first end of the light emitting element in response to control of the first scan signal.

[0017] Optionally, the first reset sub-circuit comprises a first transistor, the first end of the first transistor is connected with the first reset signal end, the second end of the first transistor is connected with the second end of the driving transistor, and the control end of the first transistor is connected with a first scan line providing the first scan signal;

[0018] The second reset sub-circuit comprises a fifth transistor, the first end of the fifth transistor is connected with the second reset signal end, the second end of the fifth transistor is connected with the control end of the driving transistor and the storage capacitor, and the control end of the fifth transistor is connected with a third scan line providing the third scan signal;

[0019] The write sub-circuit comprises a fourth transistor, the first end of the fourth transistor is connected with the data signal end, the second end of the fourth transistor is connected with the first end of the driving transistor, and the control end of the fourth transistor is connected with a fourth scan line providing the fourth scan signal.

[0020] The first threshold control sub-circuit includes a second transistor, the first end of which is connected to the control terminal of the driving transistor and the storage capacitor, the second end of which is connected to the second terminal of the driving transistor, and the control terminal of the second transistor is connected to the second scan line that provides the second scan signal.

[0021] Optionally, the first light-emitting sub-circuit includes a seventh transistor, the first terminal of which is connected to the first power supply terminal, the second terminal of which is connected to the first terminal of the driving transistor, and the control terminal of which is connected to a light-emitting control line that provides a light-emitting signal.

[0022] The second light-emitting sub-circuit includes an eighth transistor, the first terminal of which is connected to the second terminal of the driving transistor, the second terminal of which is connected to the first terminal of the light-emitting element, and the control terminal of which is connected to the light-emitting control line.

[0023] The third reset sub-circuit includes a sixth transistor, the first end of which is connected to the first end of the light-emitting element, the second end of which is connected to the third reset signal terminal, and the control terminal of which is connected to the first scan line.

[0024] Optionally, it further includes a second threshold control sub-circuit, the first end of which is connected to the storage capacitor and the control terminal of the driving transistor, and the second end of which is connected to the second reset sub-circuit.

[0025] The second threshold control sub-circuit is used to control the connection between the control terminal of the driving transistor and the first threshold control sub-circuit in response to the fifth scan signal.

[0026] Optionally, the second threshold control sub-circuit includes a ninth transistor, the first terminal of which is connected to the control terminal of the driving transistor and the storage capacitor, the second terminal of which is connected to the first terminal of the second transistor, and the control terminal of the ninth transistor is connected to the fifth scan line that provides the fifth scan signal.

[0027] Optionally, the first scan signal and the third scan signal share the same scan line, and / or the second scan signal and the fourth scan signal share the same scan line.

[0028] Secondly, this application provides a driving method for a pixel driving circuit, applied to any of the pixel driving circuits described above. The refresh driving cycle of the driving method includes a first reset phase, a write phase, a first bias phase, and a first light emission phase.

[0029] During the first reset phase, the first reset sub-circuit responds to the control of the first scan signal to provide a voltage to the second terminal of the driving transistor for the first reset signal terminal;

[0030] During the writing phase, the writing sub-circuit provides a voltage to the first terminal of the driving transistor in response to the control of the fourth scan signal, and the first threshold control sub-circuit connects the control terminal of the driving transistor to the second terminal of the driving transistor in response to the second scan signal.

[0031] During the first bias phase, the first reset sub-circuit provides a voltage to the second terminal of the driving transistor in response to the control of the first scan signal, and the first threshold control sub-circuit disconnects the control terminal of the driving transistor from the second terminal of the driving transistor in response to the second scan signal.

[0032] In the first light-emitting phase, the light-emitting element emits light in response to the driving current of the driving transistor.

[0033] Optionally, the holding drive cycle of the driving method includes a second reset phase, a holding phase, a second bias phase, and a second light emission phase.

[0034] During the second reset phase, the first reset sub-circuit responds to the control of the first scan signal by providing a voltage to the second terminal of the driving transistor for the first reset signal terminal;

[0035] During the holding phase, the write sub-circuit disconnects from the first terminal of the drive transistor in response to the control of the fourth scan signal;

[0036] During the second bias phase, the first reset sub-circuit provides a voltage to the first reset signal terminal of the driving transistor in response to the control of the first scan signal; the first threshold control sub-circuit disconnects the control terminal of the driving transistor from the second terminal of the driving transistor in response to the second scan signal.

[0037] In the second light-emitting stage, the light-emitting element emits light in response to the driving current of the driving transistor.

[0038] Optionally, the first reset phase includes a first reset sub-phase, a second reset sub-phase, and a third reset sub-phase:

[0039] During the first reset stage, the first reset circuit provides a voltage to the second terminal of the driving transistor in response to the control of the first scan signal; the first threshold control circuit connects the control terminal of the driving transistor to the second terminal of the driving transistor in response to the second scan signal.

[0040] During the second reset phase, the second reset circuit provides a voltage at the second reset signal terminal to the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control circuit disconnects the connection between the control terminal of the driving transistor and the second terminal of the driving transistor in response to the second scan signal.

[0041] In the third reset stage, the second reset circuit provides a voltage at the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control circuit connects the second terminal of the driving transistor to the control terminal of the driving transistor in response to the second scan signal.

[0042] Optionally, the first reset phase further includes a reset maintenance sub-phase located between the first reset sub-phase and the second reset sub-phase.

[0043] During the reset sustaining sub-stage, the first reset sub-circuit provides a voltage to the second terminal of the driving transistor in response to the control of the first scan signal; the first threshold control sub-circuit disconnects the control terminal of the driving transistor from the second terminal of the driving transistor in response to the second scan signal.

[0044] Optionally, the first reset phase includes a first reset sub-phase and a second reset sub-phase.

[0045] During the first reset phase, the first reset sub-circuit provides a voltage to the second terminal of the driving transistor in response to the control of the first scan signal; the first threshold control sub-circuit disconnects the control terminal of the driving transistor from the second terminal of the driving transistor in response to the second scan signal.

[0046] During the second reset phase, the second reset sub-circuit provides a voltage at the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control sub-circuit disconnects the connection between the control terminal of the driving transistor and the second terminal of the driving transistor in response to the second scan signal.

[0047] Optionally, the refresh driving cycle of the driving method further includes:

[0048] During the first reset phase, the first reset sub-circuit provides a voltage to the second terminal of the driving transistor in response to the control of the first scan signal, the second reset sub-circuit provides a voltage to the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal, and the first threshold control sub-circuit disconnects the connection between the control terminal of the driving transistor and the second terminal of the driving transistor in response to the second scan signal.

[0049] Thirdly, this application provides a display panel including the pixel driving circuit as described in any of the above.

[0050] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0051] The pixel driving circuit provided in this embodiment resets the second terminal and control terminal of the driving transistor through a first reset circuit and a second reset circuit, respectively. This allows the bias state of the driving transistor to be adjusted to a negative or positive bias state before screen switching, making the driving transistor unaffected by the previous frame's image data and enabling rapid screen switching to the preset switching image. This helps to reduce flickering during screen switching and improves display quality. By having the first reset circuit start the light-emitting phase from a fixed bias conduction state, the recovery process of the driving transistor's threshold voltage during the hold driving cycle is made more consistent with the recovery process during the refresh driving cycle. This reduces the brightness difference between the refresh driving cycle and the hold driving cycle, improving VRR (Vibration Reduction). Attached Figure Description

[0052] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0053] Figures 1-2 A schematic diagram of a pixel driving circuit provided for an embodiment of this application;

[0054] Figure 3 A connection diagram of a pixel driving circuit provided for an embodiment of this application;

[0055] Figures 4-9 A schematic diagram of the state of a pixel driving circuit provided for an embodiment of this application;

[0056] Figures 10-11 A timing diagram of a pixel driving circuit driving method provided for an embodiment of this application;

[0057] Figures 12-13 A schematic diagram of the state of a pixel driving circuit provided for an embodiment of this application;

[0058] Figures 14-15 A timing diagram of a pixel driving circuit driving method provided for an embodiment of this application;

[0059] Figure 16 A connection diagram of a pixel driving circuit provided for an embodiment of this application;

[0060] Figure 17 A schematic diagram of the state of a pixel driving circuit provided for an embodiment of this application;

[0061] Figures 18-19 A timing diagram of a pixel driving circuit driving method provided for an embodiment of this application. Detailed Implementation

[0062] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0063] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0064] In a pixel driving circuit, the driving transistor generates a driving current, and the light-emitting element responds to this driving current to emit light. The driving current generated by the driving transistor is related to the potential of its gate, which is connected to a storage capacitor. Due to the inherent characteristics of the driving transistor, during screen switching in a display device, the driving transistor is affected by the data from the previous frame, causing the displayed image to fail to switch quickly to the preset image, resulting in flickering. This phenomenon is known as first-frame response flicker (FFR). For example, a gray screen (between black and white) may appear before the transition from a black screen to a white screen, affecting the display quality.

[0065] When switching the driving method of existing pixel circuits to a lower frequency, for example, under normal driving, the refresh rate is 60Hz, divided into 60 frames, with 60 refresh driving cycles per second. Under a lower frequency, the refresh rate is reduced, taking 1Hz as an example, to refresh one frame per second (one frame has only one refresh driving cycle).

[0066] Specifically, during the first refresh drive cycle, data is written normally. During the remaining 59 hold drive cycles, no data is written; instead, the data written in the previous frame is used to continue emitting light from the OLED. In this drive mode, a single frame needs to be held for a relatively long time. However, holding the same image for an extended period causes the threshold voltage to shift, affecting the characteristics of the thin-film transistor. This results in a difference in brightness between the refresh frame and the hold frame, creating a brightness difference that is perceptible to the human eye. This phenomenon can be called refresh rate switching flicker (VRR).

[0067] Please see details. Figure 1 This application provides a pixel driving circuit, including a driving transistor T3, a storage capacitor C, a write sub-circuit 900, a first reset sub-circuit 100, a second reset sub-circuit 200, and a first threshold control sub-circuit 300.

[0068] The driving transistor T3 is used to generate a driving current in the conduction path from the first terminal to the second terminal in response to the control terminal signal voltage.

[0069] The first reset sub-circuit 100 is connected to the second terminal of the driving transistor T3 and is used to provide the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3 in response to the control of the first scan signal G1.

[0070] The second reset sub-circuit 200 is connected to the control terminal of the driving transistor T3, the storage capacitor C, and the first terminal of the first threshold control sub-circuit 300, and is used to provide the voltage of the second reset signal terminal Vinit2 to the control terminal of the driving transistor T3 and the storage capacitor C in response to the control of the third scan signal G3.

[0071] The write sub-circuit 900 is connected to the first terminal of the drive transistor T3 and is used to provide the voltage of the data signal terminal Vdata to the first terminal of the drive transistor T3 in response to the control of the fourth scan signal G4.

[0072] The second terminal of the first threshold control sub-circuit 300 is connected to the second terminal of the driving transistor T3, and is used to turn on the connection between the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3 in response to the control of the second scan signal G2.

[0073] The voltage of the first reset signal terminal Vinit1 has the opposite polarity to the voltage of the second reset signal terminal Vinit2.

[0074] like Figure 2 As shown, the pixel driving circuit also includes a light-emitting element 800, a first light-emitting sub-circuit 500, a second light-emitting sub-circuit 600, and a third reset sub-circuit 700.

[0075] The first light-emitting sub-circuit 500 is connected to the first power supply terminal VDD and the first terminal of the driving transistor T3, and is used to provide the voltage of the first power supply terminal VDD to the driving transistor T3 in response to the control of the light-emitting signal EM.

[0076] The second light-emitting sub-circuit 600 is connected to the second terminal of the driving transistor T3 and the first terminal of the light-emitting element 800, and is used to provide the driving current of the driving transistor T3 to the light-emitting element 800 in response to the control of the light-emitting signal EM. The second terminal of the light-emitting element 800 is connected to the second power supply terminal VSS.

[0077] The third reset sub-circuit 700 is connected to the second terminal of the second light-emitting sub-circuit 600 and the first terminal of the light-emitting element 800, and is used to provide the voltage of the third reset signal terminal Vinit3 to the second terminal of the second light-emitting sub-circuit 600 and the first terminal of the light-emitting element 800 in response to the control of the first scan signal G1.

[0078] It should be noted that, in the embodiments of this application, the light-emitting element 800 can be a current-driven light-emitting device, including LEDs (Light Emitting Diodes) or OLEDs (Organic Light Emitting Diodes), which are existing technologies. The light-emitting element 800 can also be a micro-LED (Micro-LED: MicroLight Emitting Diode). A micro-LED refers to an ultra-small inorganic light-emitting element 800 with a size of less than 100 micrometers (μm) that emits light independently without backlighting or filters. The following embodiments are described using micro-LEDs as an example. It should be noted that the light-emitting element 800 can be various types of LEDs, such as those emitting red, green, blue, or white light, and the embodiments of this application do not limit this.

[0079] "Control terminal" specifically refers to the gate of the transistor, "first terminal" specifically refers to the source of the transistor, and "second terminal" specifically refers to the drain of the transistor. Of course, those skilled in the art should know that the "first terminal" and "second terminal" are interchangeable, that is, the "first terminal" specifically refers to the drain of the transistor, and the "second terminal" specifically refers to the source of the transistor.

[0080] In the embodiments of this application, the first power supply terminal VDD can be a high-level input DC signal, referred to as the first voltage. The second power supply terminal VSS can be a low-level input DC signal, referred to as the second voltage, which is lower than the first voltage. The following embodiments are the same and will not be described again.

[0081] Furthermore, based on their semiconductor characteristics, transistors can be classified into N-type transistors and P-type transistors. When used as switching transistors, N-type switching transistors are turned on by a high-level switching control signal (Gate) and turned off by a low-level switching control signal (Gate). P-type switching transistors are turned on by a low-level switching control signal (Gate) and turned off by a high-level switching control signal (Gate).

[0082] It is worth noting that the pixel circuits in this application embodiment are applicable to pixel driving circuits of various structures (e.g., 8T1C, 9T1C, 12T1C, or 8T2C, etc.). The following will provide exemplary descriptions of 8T1C and 9T1C pixel driving circuits. It is understood that different pixel circuit structures are selected for different application scenarios.

[0083] In this embodiment, the pixel driving circuit uses an LTPO circuit, which is fabricated using low-temperature polycrystalline silicon (LTPS) technology and in-gas oxide (IGZO). Low-temperature polycrystalline silicon thin-film transistors (LTPS) utilize polycrystalline silicon deposition to form the active layer. LTPS exhibits high electron mobility, fast response speed, and advantages such as high brightness, high resolution, and low power consumption.

[0084] Oxide thin-film transistors (OTTFTs), such as those using oxide semiconductors as the active layer of the TFT, like indium gallium zinc oxide (IGZO), have high electron mobility and good turn-off characteristics. Compared to LTPS, oxide semiconductors have simpler manufacturing processes and higher compatibility with amorphous silicon processes.

[0085] Of course, oxide thin-film transistors can also be other metal oxide semiconductors, such as indium zinc tin oxide (IZTO) or indium gallium zinc tin oxide (IGZTO). Using oxide thin-film transistors can effectively reduce transistor size and prevent leakage current, thereby making the pixel circuit suitable for low-frequency driving while also increasing the resolution of the display substrate.

[0086] In various embodiments of this application, the control terminal of the driving transistor T3 is connected to the storage capacitor C at the first node N1, the first terminal of the driving transistor T3 is connected to the second node N2, and the second terminal of the driving transistor T3 is connected to the third node N3. It should be noted that in the description of the embodiments of this application, the first node N1, the second node N2, and the third node N3 do not represent actual existing components, but rather represent the junction points of related circuit connections in the circuit diagram.

[0087] It should be noted that, in the embodiments of this application, a valid signal (level) refers to a signal (level) used to turn on the corresponding switching element, and an invalid signal (level) refers to a signal (level) used to turn off the corresponding switching element. Similarly, this interpretation applies to other embodiments of this application. Valid level and invalid level only represent that the signal level has two state quantities, and do not mean that the valid level or invalid level has a specific value throughout the text.

[0088] The pixel driving circuit provided in this embodiment resets the second terminal and control terminal of the driving transistor T3 through the first reset sub-circuit 100 and the second reset sub-circuit 200, respectively. This allows the bias state of the driving transistor T3 to be adjusted to a negative bias state or a positive bias state before screen switching, making the driving transistor T3 unaffected by the previous frame's image data and enabling rapid screen switching to the preset switching image. This helps to reduce flickering during screen switching and improves the display effect. By having the first reset sub-circuit 100 start the driving transistor T3 from a fixed bias conducting state to the light-emitting stage before the light-emitting stage, the recovery process of the threshold voltage of the driving transistor T3 in the hold driving cycle t200 is made more consistent with the recovery process of the threshold voltage of the driving transistor T3 in the refresh driving cycle t100. This reduces the brightness difference between the refresh driving cycle t100 and the hold driving cycle t200, improving VRR (Vibration Reduction).

[0089] In this application embodiment, an exemplary description of adjusting the negative bias state of the transistor is provided. In this application embodiment, the exemplary 8T1C circuit includes eight thin-film transistors (T1-T8), where T2 and T5 are N-type thin-film transistors (NMOS) using oxide TFTs; the rest are P-type thin-film transistors (PMOS) using LTPS TFTs. The exemplary 9T1C circuit includes eight thin-film transistors (T1-T9), where T9 is an N-type thin-film transistor (NMOS) using oxide TFTs; the rest are P-type thin-film transistors (PMOS) using LTPS TFTs.

[0090] Example 1

[0091] In this embodiment, the pixel driving circuit uses an 8T1C, such as Figure 3 As shown, the first reset sub-circuit 100 includes a first transistor T1. The first terminal of the first transistor T1 is connected to the first reset signal terminal Vinit1. The second terminal of the first transistor T1 is electrically connected to the second terminal of the driving transistor T3 at the third node N3. The control terminal of the first transistor T1 is connected to the first scan line that provides the first scan signal G1.

[0092] The second reset sub-circuit 200 includes a fifth transistor T5. The first terminal of the fifth transistor T5 is connected to the second reset signal terminal Vinit2. The second terminal of the fifth transistor T5 is electrically connected to the control terminal of the driving transistor T3 at the first node N1 and the storage capacitor C. The control terminal of the fifth transistor T5 is connected to the third scan line that provides the third scan signal G3.

[0093] The write sub-circuit 900 includes a fourth transistor T4, the first terminal of which is connected to the data signal terminal Vdata, the second terminal of which is electrically connected to the first terminal of the drive transistor T3 at the second node N2, and the control terminal of the fourth transistor T4 is connected to the fourth scan line that provides the fourth scan signal G4.

[0094] The first threshold control sub-circuit 300 includes a second transistor T2. The first terminal of the second transistor T2 is electrically connected to the control terminal of the driving transistor T3 at a first node N1 and to the storage capacitor C. The second terminal of the second transistor T2 is electrically connected to the second terminal of the driving transistor T3 at a third node N3. The control terminal of the second transistor T2 is connected to a second scan line that provides the second scan signal G2.

[0095] The first light-emitting sub-circuit 500 includes a seventh transistor T7. The first terminal of the seventh transistor T7 is connected to the first power supply terminal VDD. The second terminal of the seventh transistor T7 is electrically connected to the first terminal of the driving transistor T3 at the second node N2. The control terminal of the seventh transistor T7 is connected to the light-emitting control line that provides the light-emitting signal EM.

[0096] The second light-emitting sub-circuit 600 includes an eighth transistor T8. The first terminal of the eighth transistor T8 is electrically connected to the second terminal of the driving transistor T3 at a third node N3. The second terminal of the eighth transistor T8 is connected to the first terminal of the light-emitting element 800. The control terminal of the eighth transistor T8 is connected to the light-emitting control line.

[0097] The third reset sub-circuit 700 includes a sixth transistor T6. The first terminal of the sixth transistor T6 is connected to the first terminal of the light-emitting element 800, the second terminal of the sixth transistor T6 is connected to the third reset signal terminal Vinit3, and the control terminal of the sixth transistor T6 is connected to the first scan line.

[0098] In this embodiment, T2 and T5 are N-type thin-film transistors (NMOS), and the rest are P-type thin-film transistors (PMOS) for illustrative purposes. The voltage of the first reset signal terminal Vinit1 is positive, the voltage of the second reset signal terminal Vinit2 is negative, and the voltage of the third reset signal terminal Vinit3 is negative. The voltage value of the first reset signal terminal Vinit1 is greater than the voltage value of the second signal terminal, i.e., |Vinit1|>|Vinit2|. This setting allows the driving transistor T3 to form a large negative bias voltage between the first node N1 and the third node N3 during the reset process, which will accelerate the capture of charge carriers on the gate of the driving transistor T3 and eliminate the influence of the previous frame of display.

[0099] The voltages of Vinit2 and Vinit3 can be the same or different. Vinit2 is responsible for resetting the control terminal of the driving transistor T3, while Vinit3 is responsible for resetting the anode of the light-emitting element 800. The advantage is that the two processes do not interfere with each other. Vinit3, which is used to reset the anode of the light-emitting element 800, can perform a lower voltage reset to eliminate positive charge, which is more beneficial for improving lifespan.

[0100] This application provides a driving method for a pixel driving circuit, such as... Figures 4-10 As shown, applied to any of the pixel driving circuits described above, the refresh driving cycle t100 of the driving method includes a first reset phase t110, a write phase t120, a first bias phase t130, and a first light emission phase t140.

[0101] During the first reset phase t110, the first reset sub-circuit 100 responds to the control of the first scan signal G1 by providing the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3.

[0102] Specifically, the first reset stage t110 includes a first reset sub-stage t101, a second reset sub-stage t102, and a third reset stage t103:

[0103] In the first reset sub-stage t101, the first reset sub-circuit 100, in response to the control of the first scan signal G1, provides the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3. The first threshold control sub-circuit 300, in response to the second scan signal G2, connects the control terminal of the driving transistor T3 to the second terminal of the driving transistor T3, as shown below. Figure 4 and Figure 10 As shown.

[0104] In the first reset stage t101, the first scan signal G1 is low, the first transistor T1 is turned on, the second scan signal G2 is high, and the second transistor T2 is turned on; the third scan signal G3 is low, and the fifth transistor T5 is turned off; the fourth scan signal G4 and the light emission signal EM are high, and the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off; the control terminal of the sixth transistor T6 reuses the first scan signal G1, the first scan signal G1 is low, and the sixth transistor T6 is turned on. During this stage, the driving transistor T3 is turned on, and the voltage of the first reset signal terminal Vinit1 is applied to the control terminal of the driving transistor T3 through the first transistor T1 and the second transistor T2, resetting the control terminal of the driving transistor T3 until the driving transistor T3 is turned off. During this stage, the voltage at the first node N1 is Vinit1, the voltage at the second node N2 is Vinit1-Vth, and the voltage at the third node N3 is Vinit1, where Vth is the threshold voltage of the driving transistor T3. For the PMOS driving transistor T3, Vth < 0.

[0105] In the second reset sub-stage t102, the second reset sub-circuit 200, in response to the control of the third scan signal G3, provides the voltage of the second reset signal terminal Vinit2 to the control terminal of the driving transistor T3 and the storage capacitor C. The first threshold control sub-circuit 300, in response to the second scan signal G2, disconnects the connection between the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3, as shown below. Figure 5 and Figure 10 As shown.

[0106] In the second reset stage t102, the third scan signal G3 is high, and the fifth transistor T5 is turned on; the second scan signal G2 is low, and the second transistor T2 is turned off; the first scan signal G1, the fourth scan signal G4, and the light emission signal EM are high, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. The voltage of the second reset signal terminal Vinit2 is applied to the second terminal of the driving transistor T3 through the fifth transistor T5. In this stage, the driving transistor T3 is turned on, and the control terminal of the driving transistor T3 is connected to the storage capacitor C. The voltage at the first node N1 is Vinit2, the voltage at the second node N2 is Vinit1, and the voltage at the third node N3 is Vinit1.

[0107] In the second reset stage t102, a large negative bias is formed between nodes N1-N3 of the driving transistor T3. This accelerates the capture of gate-captured carriers, allowing the driving transistor T3 to generate the drive current corresponding to the preset switching screen, unaffected by the previous frame's image data. This enables the screen to switch quickly to the preset switching screen, thus improving the FFR flicker phenomenon that occurs during screen switching and enhancing the display effect. However, in the second reset stage t102, the deep negative bias on the driving transistor T3 causes the release of saturated carriers within the frame, resulting in threshold drift and brightness changes in the driving transistor T3. This has little effect on improving VRR.

[0108] In the third reset sub-stage t103, the second reset sub-circuit 200, in response to the control of the third scan signal G3, provides the voltage of the second reset signal terminal Vinit2 to the control terminal of the driving transistor T3 and the storage capacitor C. The first threshold control sub-circuit 300, in response to the second scan signal G2, connects the second terminal of the driving transistor T3 to the control terminal of the driving transistor T3, as shown below. Figure 6 and Figure 10 As shown.

[0109] In the third reset stage t103, the second scan signal G2 and the third scan signal G3 are at high levels, and the second transistor T2 and the fifth transistor T5 are turned on; the first scan signal G1, the fourth scan signal G4, and the light emission signal EM are at high levels, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. In this stage, the voltage of the second reset signal terminal Vinit2 is applied to the control terminal of the driving transistor T3 through the fifth transistor T5 and the second transistor T2, resetting the gate of the driving transistor T3. The driving transistor T3 is turned on under the control of the voltage of the second reset signal terminal Vinit2, and the voltage of the first reset signal terminal Vinit1 is applied to the first and second terminals of the driving transistor T3 through the fifth transistor T5. In this stage, the voltage at the first node N1 is Vinit2, the voltage at the second node N2 is Vinit2-Vth, and the voltage at the third node N3 is Vinit2, where Vth is the threshold voltage of the driving transistor T3.

[0110] During this stage, due to the large negative bias voltage between the gate and source of the driving transistor T3 in the second reset stage t102, the threshold voltage of the driving transistor T3 drifts to a certain extent. In this embodiment, N1 / N2 / N3 are all positive voltages in the first reset stage t101, and N1 / N2 / N3 become negative voltages in the third reset stage t103. By performing multiple charging and discharging operations on the driving transistor T3 in the first reset stage t110, the voltage of the three nodes of the driving transistor T3 is flipped at least once. During this process, the light emission control line is not turned on to emit light. After the driving transistor T3 stabilizes, it emits light, thereby improving the drift and hysteresis characteristics of the driving transistor T3 and improving the short-term afterimage problem.

[0111] In some other embodiments of this application, in order to improve the state of the large bias negative voltage formed between the gate and source of the driving transistor T3 in the second reset sub-stage t102, the first reset stage t110 further includes a reset maintenance sub-stage tt102 located between the first reset sub-stage t101 and the second reset stage t102, such as... Figure 7 and Figure 10 As shown.

[0112] During the reset sustaining sub-stage tt102, the first reset sub-circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3 in response to the control of the first scan signal G1; the first threshold control sub-circuit 300 disconnects the connection between the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3 in response to the second scan signal G2.

[0113] During this stage, the first scan signal G1 is low, the first transistor T1 is turned on, the second scan signal G2 and the third scan signal G3 are low, and the second transistor T2 and the fifth transistor T5 are turned off; the fourth scan signal G4 and the light emission signal EM are high, and the fourth transistor T4, the seventh transistor T7 and the eighth transistor T8 are turned off; the control terminal of the sixth transistor T6 reuses the first scan signal G1, the first scan signal G1 is low, and the sixth transistor T6 is turned on. During this stage, the driving transistor T3 is turned on, and the first and second terminals of the driving transistor T3 are reset by the first scan signal G1. The voltage at the first node N1 is Vinit2, the voltage at the second node N2 is Vinit1, and the voltage at the third node N3 is Vinit1.

[0114] By maintaining the positive voltage charging of the first reset circuit 100 in the reset maintenance sub-stage t102 for the second node N2 and the third node N3, the large bias negative voltage formed between the gate and source of the driving transistor T3 in the second reset sub-stage t102 is maintained, further eliminating the influence of the previous frame image data, and enabling the image to switch quickly to the preset switching image. Therefore, it is beneficial to improve the FFR flickering phenomenon that occurs during the image switching process and improve the display effect.

[0115] During the write phase t120, the write sub-circuit 900, in response to the control of the fourth scan signal G4, provides a voltage to the data signal terminal Vdata at the first terminal of the driving transistor T3. The first threshold control sub-circuit 300, in response to the second scan signal G2, connects the control terminal of the driving transistor T3 to the second terminal of the driving transistor T3. Figure 8 and Figure 10 As shown.

[0116] During the writing phase t120, the fourth scan signal G4 is low, the fourth transistor T4 is turned on, the second scan signal G2 is high, and the second transistor T2 is turned on; the third scan signal G3 is low, and the fifth transistor T5 is turned off; the first scan signal G1 and the light emission signal EM are high, and the first transistor T1, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. During this phase, the driving transistor T3 is turned on, and the voltage of the data signal terminal Vdata is applied to the control terminal of the driving transistor T3 through the fourth transistor T4 and the second transistor T2, realizing the writing of the data signal and providing voltage compensation to the control terminal of the driving transistor T3. During this phase, the voltage at the first node N1 is Vdata + Vth, the voltage at the second node N2 is Vdata, and the voltage at the third node N3 is Vdata, where Vth is the threshold voltage of the driving transistor T3.

[0117] During the first bias phase t130, the first reset sub-circuit 100, in response to the control of the first scan signal G1, provides the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3. The first threshold control sub-circuit 300, in response to the second scan signal G2, disconnects the connection between the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3. Figure 9 and Figure 10 As shown.

[0118] During the first biasing phase t130, the first scan signal G1 is low, turning on the first transistor T1 and the sixth transistor T6; the second scan signal G2 is low, turning off the second transistor T2; the third scan signal G3 is low, turning off the fifth transistor T5; and the fourth scan signal G4 and the light emission signal EM are high, turning off the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8. During this phase, the driving transistor T3 is turned on, applying the voltage of the first reset signal terminal Vinit1 to the second and third terminals of the driving transistor T3 through the first transistor T1. During this phase, the voltage at the first node N1 is Vdata + Vth, the voltage at the second node N2 is Vinit1, and the voltage at the third node N3 is Vinit1, where Vth is the threshold voltage of the driving transistor T3.

[0119] During this stage, the first transistor T1 resets the second node N2 and the third node N3 to a high voltage, which is equivalent to applying a negative bias voltage to the gate and source of the driving transistor T3. This will change the recovery process of the threshold voltage of the driving transistor T3 during the light-emitting stage.

[0120] During the first light-emitting stage t140, the light-emitting element 800 emits light in response to the driving current of the driving transistor T3. When the light-emitting signal EM is low, the seventh transistor T7 and the eighth transistor T8 are turned on, and the driving transistor T3 is turned on; the other transistors are all in the off state under the control of the corresponding switching control signals.

[0121] The driving transistor T3DN operates in saturation. According to the saturation current characteristics, the saturation current I flowing through the driving transistor T3DN and used to drive the light-emitting element 80030 satisfies the following formula:

[0122] I=1 / 2*μ*Cox*W / L*(Vgs-Vth)^2

[0123] =K(Vdata+Vth-VDD–Vth)^2

[0124] =K(Vdata-VDD)^2

[0125] Where K is a structural parameter, and this value is relatively stable in the same structure and can be considered a constant.

[0126] Where K is a structural parameter, and this value is relatively stable in the same structure and can be considered a constant. It can be seen that the operating current of the light-emitting element 800 is no longer affected by the threshold voltage Vth of the driving transistor T3DN, completely solving the drift of the threshold voltage Vth of the driving transistor T3DN caused by the manufacturing process and long-term operation, effectively improving problems such as low-frequency flicker, and thus improving the non-uniformity of the panel display.

[0127] like Figure 11 As shown, the holding drive cycle t200 of the driving method includes a second reset phase t210, a holding phase t220, a second bias phase t230, and a second light emission phase t240.

[0128] During the second reset phase t210, the first reset sub-circuit 100 responds to the control of the first scan signal G1 by providing the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3.

[0129] During the hold phase t220, the write sub-circuit 900 disconnects from the first terminal of the drive transistor T3 in response to the control of the fourth scan signal G4. This hold phase t220 corresponds to the write phase t120 in the refresh drive cycle t100, during which no data signal voltage is written.

[0130] It is understandable that during the light-emitting phase of the refresh drive cycle t100, a voltage signal is written to the control terminal of the drive transistor T3; during the hold drive cycle t200, since no data signal is written, the voltage written to the control terminal of the drive transistor T3 during the write phase t120 of the refresh drive cycle t100 is the same as the voltage written to the control terminal of the drive transistor T3 during the light-emitting phase of the hold drive cycle, so as to control the drive current during the light-emitting phase of the hold drive cycle.

[0131] During the second bias phase t230, the first reset sub-circuit 100, in response to the control of the first scan signal G1, provides a voltage to the first reset signal terminal Vinit1 at the second terminal of the driving transistor T3. The first threshold control sub-circuit 300, in response to the second scan signal G2, disconnects the control terminal of the driving transistor T3 from the second terminal of the driving transistor T3.

[0132] During the second light-emitting stage t240, the light-emitting element 800 emits light in response to the driving current of the driving transistor T3.

[0133] In this embodiment, the driving timing of the first scan signal G1 in the hold driving cycle t200 is the same as that of the first scan signal G1 in the refresh driving cycle t100, while the driving timing of the remaining scan signals in the hold driving cycle t200 is such that the corresponding transistor can remain off at each stage of the hold driving cycle t200.

[0134] In this embodiment, by using the first bias stage t130 of the refresh driving cycle t100 and the second bias stage t230 of the hold driving cycle t200, the pixel driving circuit is kept in a fixed bias conduction state. This ensures that regardless of whether the data signal of the previous frame is black or white, the driving transistor T3 will start from the fixed bias conduction state and enter the light-emitting stage. This makes the recovery process of the threshold voltage of the driving transistor T3 in the hold driving cycle t200 consistent with the recovery process of the threshold voltage of the driving transistor T3 in the refresh driving cycle t100, thus reducing the brightness difference between the refresh driving cycle t100 and the hold driving cycle t200 and improving VRR.

[0135] In this embodiment of the application, the anode potential of the light-emitting element 800EL is reset multiple times by the third reset sub-circuit 700 during the reset phase, so as to control the light-emitting element 800EL not to emit light and avoid the influence of the charge remaining on the anode of the light-emitting element 800 on the brightness of the light emission.

[0136] Example 2

[0137] In this embodiment, the pixel driving circuit uses an 8T1C. Based on Embodiment 1, the arrangement of the scan signal lines is optimized. In Embodiment 2, which uses 5 groups of GOAs (Gate Driver on Array) to drive each gate control signal, the number of GOAs is reduced. In this embodiment, the second scan signal G2 and the fourth scan signal G4 share the same scan line, meaning their driving timing is identical. Four groups of GOAs are used to control the pixel driving circuit in this embodiment. The technical solution in this embodiment saves GOA space and pixel space, reduces GOA power consumption, and is suitable for products with narrow bezels and high pixel density.

[0138] In this embodiment, as Figures 12-14 As shown, the refresh driving cycle t100 of the driving method includes a first reset stage t110, a write stage t120, a first bias stage t130, and a first light emission stage t140.

[0139] During the first reset phase t110, the first reset sub-circuit 100 responds to the control of the first scan signal G1 by providing the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3.

[0140] In this embodiment, the first reset stage t110 includes a first reset sub-stage t111 and a second reset sub-stage t112. Specifically:

[0141] In the first reset phase t111, the first reset sub-circuit 100, in response to the control of the first scan signal G1, provides the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3. The first threshold control sub-circuit 300, in response to the second scan signal G2, disconnects the connection between the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3, as shown below. Figure 12 and Figure 14 As shown.

[0142] In the first reset stage t111, the second transistor T2 is turned off, and the second node N2 and the third node N3 of the driving transistor T3 are reset by the first reset sub-circuit 100, so that the voltage of the second node N2 and the third node N3 is reset to Vinit1.

[0143] In the second reset phase t112, the second reset sub-circuit 200, in response to the control of the third scan signal G3, provides the voltage of the second reset signal terminal Vinit2 to the control terminal of the driving transistor T3 and the storage capacitor C. The first threshold control sub-circuit 300, in response to the second scan signal G2, disconnects the connection between the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3, as shown below. Figure 13 and Figure 14 As shown.

[0144] In the second reset stage t112, the second transistor T2 is turned off, and the first node N1 of the driving transistor T3 is reset through the second reset sub-circuit 200, so that the voltage of the first node N1 is reset to Vinit2. By forming a negative bias voltage between the gate and source of the driving transistor T3 in the first reset stage t110, the FFR can be effectively improved. It is understood that in this embodiment, since the large negative bias voltage between the gate and source of the driving transistor T3 in Embodiment 1 is not formed, the improvement effect on FFR in this embodiment is weaker than that in Embodiment 2, but it can greatly improve FFR and improve the display effect compared with the existing technology.

[0145] During the write phase t120, the write sub-circuit 900, in response to the control of the fourth scan signal G4, provides a voltage to the data signal terminal Vdata at the first terminal of the driving transistor T3. The first threshold control sub-circuit 300, in response to the second scan signal G2, connects the control terminal of the driving transistor T3 to the second terminal of the driving transistor T3. Figure 8 and Figure 14 As shown.

[0146] During the first bias phase t130, the first reset sub-circuit 100, in response to the control of the first scan signal G1, provides the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3. The first threshold control sub-circuit 300, in response to the second scan signal G2, disconnects the connection between the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3. Figure 9 and Figure 14 As shown.

[0147] During the first light-emitting phase t140, the light-emitting element 800 emits light in response to the driving current of the driving transistor T3.

[0148] Optionally, such as Figure 15 As shown, the holding drive cycle t200 of the driving method includes a second reset phase t210, a holding phase t220, a second bias phase t230, and a second light emission phase t240.

[0149] During the second reset phase t210, the first reset sub-circuit 100 responds to the control of the first scan signal G1 by providing the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3.

[0150] During the holding phase t220, the write sub-circuit 900 disconnects from the first terminal of the drive transistor T3 in response to the control of the fourth scan signal G4.

[0151] During the second bias phase t230, the first reset sub-circuit 100, in response to the control of the first scan signal G1, provides a voltage to the first reset signal terminal Vinit1 at the second terminal of the driving transistor T3. The first threshold control sub-circuit 300, in response to the second scan signal G2, disconnects the control terminal of the driving transistor T3 from the second terminal of the driving transistor T3.

[0152] During the second light-emitting stage t240, the light-emitting element 800 emits light in response to the driving current of the driving transistor T3.

[0153] In this embodiment, the timing of the first scan signal G1 during the hold drive cycle t200 is the same as that during the refresh drive cycle t100. The driving timing of the remaining scan signals during the hold drive cycle t200 allows the responding transistor to remain off at each stage of the hold drive cycle t200. Through the second bias stage t230, the recovery process of the threshold voltage of the driving transistor T3 in the hold drive cycle t200 is made to be consistent with the recovery process of the threshold voltage of the driving transistor T3 in the refresh drive cycle t100, thus reducing the brightness difference between the refresh drive cycle t100 and the hold drive cycle t200 and improving VRR.

[0154] It is understood that in this embodiment, since no large negative bias voltage is formed between the gate and source of the driving transistor T3 during the refresh driving cycle t100, the shift of the threshold voltage during the refresh driving cycle t100 is mainly determined by the positive bias voltage on N2 and N3 of the driving transistor T3. Therefore, both the holding driving cycle t200 and the refresh driving cycle t100 use the first reset circuit 100 to positively bias N2 and N3 of the driving transistor T3, so that the threshold voltage drift of the driving transistor T3 during the holding driving cycle t200 and the refresh driving cycle t100 is basically the same. In addition, the recovery process of the threshold voltage of the driving transistor T3 is also similar, so that the brightness difference between the refresh driving cycle t100 and the holding driving cycle t200 is small, and the VRR is significantly improved.

[0155] Example 3

[0156] In this embodiment, the pixel driving circuit uses a 9T1C. Based on Embodiment 1, the pixel driving circuit further includes a second threshold control sub-circuit 400, such as... Figure 16 As shown, the first terminal of the second threshold control sub-circuit 400 is connected to the storage capacitor C and the control terminal of the driving transistor T3, and the second terminal of the second threshold control sub-circuit 400 is connected to the second reset sub-circuit 200; the second threshold control sub-circuit 400 is used to control the connection between the control terminal of the driving transistor T3 and the first threshold control sub-circuit 300 in response to the control of the fifth scan signal G5.

[0157] Specifically, the second threshold control sub-circuit 400 includes a ninth transistor T9, the first terminal of the ninth transistor T9 is electrically connected to the control terminal of the driving transistor T3 at the first node N1 and the storage capacitor C, the second terminal of the ninth transistor T9 is connected to the first terminal of the second transistor T2, and the control terminal of the ninth transistor T9 is connected to the fifth scan line that provides the fifth scan signal G5.

[0158] In this embodiment, T9 is an N-type thin-film transistor (NMOS), and the rest are P-type thin-film transistors (PMOS) for illustrative purposes.

[0159] In this embodiment, the driving transistor T3 is a P-type transistor. Since P-type transistors have relatively large leakage current, low-frequency driving can cause flickering and other phenomena, thus limiting the use of this pixel circuit. In this embodiment, adding a ninth transistor T9 to the pixel circuit can further reduce the leakage current of the first node N1. For specific driving methods, please refer to the description of the 8T1C driving method; this application will not repeat it further.

[0160] In Embodiment 1, five groups of Gate Arrays (GOAs) are used to drive the gate control signals. This embodiment adds a ninth transistor, therefore normally six GOAs are needed to drive the pixel driving circuit. To optimize the arrangement of the scan signal lines, in this embodiment, the second scan signal G2 and the fourth scan signal G4 share the same scan line, and the first scan signal G1 and the third scan signal G3 share the same scan line. That is, the driving timing of the second scan signal G2 and the fourth scan signal G4 is the same, and the driving timing of the first scan signal G1 and the third scan signal G3 is the same. Using four GOAs to control the pixel driving circuit in this embodiment saves GOA space and pixel space, reduces GOA power consumption, and is suitable for products with narrow bezels and high pixel density.

[0161] In this embodiment, as Figures 17-18 As shown, the refresh driving cycle t100 of the driving method includes a first reset phase t110, a write phase t120, a first bias phase t130, and a first light emission phase t140.

[0162] During the first reset phase t110, the first reset sub-circuit 100, in response to the control of the first scan signal G1, provides a voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3. The second reset sub-circuit 200, in response to the control of the third scan signal G3, provides a voltage of the second reset signal terminal Vinit2 to the control terminal of the driving transistor T3 and the storage capacitor C. The first threshold control sub-circuit 300, in response to the second scan signal G2, disconnects the connection between the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3.

[0163] In this embodiment, the first reset circuit 100 performs a positive voltage reset on the second node N2 and the third node N3 of the driving transistor T3, and the second reset circuit 200 performs a negative voltage reset on the first node N1 of the driving transistor T3. A large negative bias voltage is formed between the gate and source of the driving transistor T3, which can significantly improve the FFR of the refresh driving cycle t100.

[0164] During the write phase t120, the write sub-circuit 900, in response to the control of the fourth scan signal G4, provides a voltage to the data signal terminal Vdata at the first terminal of the driving transistor T3. The first threshold control sub-circuit 300, in response to the second scan signal G2, connects the control terminal of the driving transistor T3 to the second terminal of the driving transistor T3. Figure 8 and Figure 18 As shown.

[0165] During the first bias phase t130, the first reset sub-circuit 100, in response to the control of the first scan signal G1, provides the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3. The first threshold control sub-circuit 300, in response to the second scan signal G2, disconnects the connection between the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3. Figure 9 and Figure 18 As shown.

[0166] During the first light-emitting phase t140, the light-emitting element 800 emits light in response to the driving current of the driving transistor T3.

[0167] Optionally, such as Figure 19 As shown, the holding drive cycle t200 of the driving method includes a second reset phase t210, a holding phase t220, a second bias phase t230, and a second light emission phase t240.

[0168] During the second reset phase t210, the first reset sub-circuit 100 responds to the control of the first scan signal G1 by providing the voltage of the first reset signal terminal Vinit1 to the second terminal of the driving transistor T3.

[0169] During the holding phase t220, the write sub-circuit 900 disconnects from the first terminal of the drive transistor T3 in response to the control of the fourth scan signal G4.

[0170] During the second bias phase t230, the first reset sub-circuit 100, in response to the control of the first scan signal G1, provides a voltage to the first reset signal terminal Vinit1 at the second terminal of the driving transistor T3. The first threshold control sub-circuit 300, in response to the second scan signal G2, disconnects the control terminal of the driving transistor T3 from the second terminal of the driving transistor T3.

[0171] During the second light-emitting stage t240, the light-emitting element 800 emits light in response to the driving current of the driving transistor T3.

[0172] In this embodiment, the driving timing of the first scan signal G1 in the hold driving cycle t200 is the same as that of the first scan signal G1 in the refresh driving cycle t100. The driving timing of the remaining scan signals in the hold driving cycle t200 is such that the corresponding transistors can remain off during each stage of the hold driving cycle t200. In the second reset stage t210 of the hold driving cycle t200, the ninth transistor T9 remains off, and nodes N2 and N3 are reset only through the first reset sub-circuit 100; node N1 cannot be reset through the second reset sub-circuit 200.

[0173] Through the first bias stage t130 and the second bias stage t230, the first reset sub-circuit 100 performs a positive voltage reset on the second node N2 and the third node N3 of the driving transistor T3, making the recovery process of the threshold voltage of the driving transistor T3 in the refresh driving cycle t100 and the hold driving cycle t200 more consistent. This can reduce the brightness difference between the refresh driving cycle t100 and the hold driving cycle t200, thereby improving VRR.

[0174] It is understandable that in this embodiment, a large negative bias voltage is formed between the gate and source of the driving transistor T3 during the refresh drive cycle t100, which effectively improves FRR, but causes a certain drift in the threshold voltage of the driving transistor T3. During the hold drive cycle t200, only high levels are applied to the second node N2 and the third node N3 of the driving transistor T3. There is no N1 point reset process during the hold drive cycle t200; only the Vinit1 voltage bias process. Therefore, compared to the scheme in Embodiment 2, the improvement effect on VRR is weaker through only the first bias stage t130 and the second bias stage t230. However, compared to the prior art, it has a stronger FRR improvement effect and also achieves VRR improvement.

[0175] Based on the same inventive concept, this application provides a display panel including the pixel driving circuit as described above. This display panel can be applied to any product or component with display functionality, such as OLED display devices, AMOLED display devices, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.

[0176] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0177] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0178] Unless otherwise defined, the technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used herein is for descriptive purposes only and is not intended to limit the invention. Terms such as “set” appearing herein can refer to either a component being directly attached to another component or a component being attached to another component via an intermediary. A feature described in one embodiment herein may be applied, alone or in combination with other features, to another embodiment, unless that feature is not applicable in that other embodiment or is otherwise stated.

[0179] The present invention has been described through the above embodiments; however, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the present invention to the described embodiments. Those skilled in the art will understand that many variations and modifications can be made based on the teachings of the present invention, and all such variations and modifications fall within the scope of protection claimed by the present invention.

Claims

1. A pixel driving circuit, characterized in that, This includes a driving transistor, a storage capacitor, a write sub-circuit, a first reset sub-circuit, a second reset sub-circuit, and a first threshold control sub-circuit. The driving transistor is used to generate a driving current in the conduction path from the first terminal to the second terminal in response to the control signal voltage at the control terminal. The first reset sub-circuit is connected to the second terminal of the driving transistor and is used to provide a voltage to the second terminal of the driving transistor in response to the control of the first scan signal; The second reset sub-circuit is connected to the control terminal of the driving transistor, the storage capacitor, and the first terminal of the first threshold control sub-circuit, and is used to provide the voltage of the second reset signal terminal to the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal; The writing sub-circuit is connected to the first terminal of the driving transistor and is used to provide a voltage to the first terminal of the driving transistor in response to the control of the fourth scan signal; The second terminal of the first threshold control sub-circuit is connected to the second terminal of the driving transistor, and is used to control the connection between the control terminal of the driving transistor and the second terminal of the driving transistor in response to the control of the second scan signal; Wherein, the voltage at the first reset signal terminal has the opposite polarity to the voltage at the second reset signal terminal; The pixel driving circuit is driven through a writing stage, a first bias stage, a first light emission stage, a first reset stage, a second reset stage, and a third reset stage. During the writing phase, the writing sub-circuit provides a voltage to the first terminal of the driving transistor in response to the control of the fourth scan signal, and the first threshold control sub-circuit connects the control terminal of the driving transistor to the second terminal of the driving transistor in response to the second scan signal. During the first bias phase, the first reset sub-circuit provides a voltage to the first reset signal terminal of the driving transistor in response to the control of the first scan signal, and the first threshold control sub-circuit disconnects the control terminal of the driving transistor from the second terminal of the driving transistor in response to the second scan signal. In the first light-emitting stage, the light-emitting element emits light in response to the driving current of the driving transistor; During the first reset stage, the first reset circuit provides a voltage to the second terminal of the driving transistor in response to the control of the first scan signal; the first threshold control circuit connects the control terminal of the driving transistor to the second terminal of the driving transistor in response to the second scan signal. During the second reset phase, the second reset circuit provides a voltage at the second reset signal terminal to the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control circuit disconnects the connection between the control terminal of the driving transistor and the second terminal of the driving transistor in response to the second scan signal. In the third reset stage, the second reset circuit provides a voltage at the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control circuit connects the second terminal of the driving transistor to the control terminal of the driving transistor in response to the second scan signal.

2. The pixel driving circuit according to claim 1, characterized in that, It also includes a light-emitting element, a first light-emitting sub-circuit, and a second light-emitting sub-circuit, wherein, The first light-emitting sub-circuit is connected to the first power supply terminal and the first terminal of the driving transistor, and is used to provide the voltage of the first power supply terminal to the driving transistor in response to the control of the light-emitting signal; The second light-emitting sub-circuit is connected to the second terminal of the driving transistor and the first terminal of the light-emitting element, and is used to provide the driving current of the driving transistor to the light-emitting element in response to the control of the light-emitting signal. The second terminal of the light-emitting element is connected to the second power supply terminal.

3. The pixel driving circuit according to claim 2, characterized in that, The first reset sub-circuit includes a first transistor, a first terminal of the first transistor is connected to the first reset signal terminal, a second terminal of the first transistor is connected to the second terminal of the driving transistor, and a control terminal of the first transistor is connected to the first scan line that provides the first scan signal. The second reset sub-circuit includes a fifth transistor, the first terminal of which is connected to the second reset signal terminal, the second terminal of which is connected to the control terminal of the driving transistor and the storage capacitor, and the control terminal of the fifth transistor is connected to the third scan line that provides the third scan signal; The write sub-circuit includes a fourth transistor, the first terminal of which is connected to the data signal terminal, the second terminal of which is connected to the first terminal of the drive transistor, and the control terminal of which is connected to the fourth scan line that provides the fourth scan signal. The first threshold control sub-circuit includes a second transistor, the first end of which is connected to the control terminal of the driving transistor and the storage capacitor, the second end of which is connected to the second terminal of the driving transistor, and the control terminal of the second transistor is connected to the second scan line that provides the second scan signal.

4. The pixel driving circuit according to claim 3, characterized in that, The first light-emitting sub-circuit includes a seventh transistor, the first terminal of which is connected to the first power supply terminal, the second terminal of which is connected to the first terminal of the driving transistor, and the control terminal of which is connected to a light-emitting control line that provides a light-emitting signal. The second light-emitting sub-circuit includes an eighth transistor, the first terminal of which is connected to the second terminal of the driving transistor, the second terminal of which is connected to the first terminal of the light-emitting element, and the control terminal of which is connected to the light-emitting control line. The third reset circuit includes a sixth transistor, the first terminal of which is connected to the first terminal of the light-emitting element, the second terminal of which is connected to the third reset signal terminal, and the control terminal of which is connected to the first scan line.

5. The pixel driving circuit according to claim 3, characterized in that, It also includes a second threshold control sub-circuit, the first end of which is connected to the storage capacitor and the control terminal of the driving transistor, and the second end of which is connected to the second reset sub-circuit. The second threshold control sub-circuit is used to control the connection between the control terminal of the driving transistor and the first threshold control sub-circuit in response to the fifth scan signal.

6. The pixel driving circuit according to claim 5, characterized in that, The second threshold control sub-circuit includes a ninth transistor, the first terminal of which is connected to the control terminal of the driving transistor and the storage capacitor, the second terminal of which is connected to the first terminal of the second transistor, and the control terminal of the ninth transistor is connected to the fifth scan line that provides the fifth scan signal.

7. The pixel driving circuit according to claim 1, characterized in that, The first scan signal and the third scan signal share the same scan line, and / or the second scan signal and the fourth scan signal share the same scan line.

8. A driving method for a pixel driving circuit, characterized in that, Applied to the pixel driving circuit as described in any one of claims 1-7, the refresh driving cycle of the driving method includes a first reset phase, a write phase, a first bias phase, and a first light emission phase. During the first reset phase, the first reset sub-circuit responds to the control of the first scan signal to provide a voltage to the second terminal of the driving transistor for the first reset signal terminal; During the writing phase, the writing sub-circuit provides a voltage to the first terminal of the driving transistor in response to the control of the fourth scan signal, and the first threshold control sub-circuit connects the control terminal of the driving transistor to the second terminal of the driving transistor in response to the second scan signal. During the first bias phase, the first reset sub-circuit provides a voltage to the first reset signal terminal of the driving transistor in response to the control of the first scan signal, and the first threshold control sub-circuit disconnects the control terminal of the driving transistor from the second terminal of the driving transistor in response to the second scan signal. In the first light-emitting stage, the light-emitting element emits light in response to the driving current of the driving transistor; The first reset phase includes a first reset sub-phase, a second reset phase, and a third reset phase. During the first reset stage, the first reset circuit provides a voltage to the second terminal of the driving transistor in response to the control of the first scan signal; the first threshold control circuit connects the control terminal of the driving transistor to the second terminal of the driving transistor in response to the second scan signal. During the second reset phase, the second reset circuit provides a voltage at the second reset signal terminal to the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control circuit disconnects the connection between the control terminal of the driving transistor and the second terminal of the driving transistor in response to the second scan signal. In the third reset stage, the second reset circuit provides a voltage at the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control circuit connects the second terminal of the driving transistor to the control terminal of the driving transistor in response to the second scan signal.

9. The driving method for the pixel driving circuit according to claim 8, characterized in that, The driving method's holding driving cycle includes a second reset phase, a holding phase, a second bias phase, and a second light emission phase. During the second reset phase, the first reset sub-circuit responds to the control of the first scan signal by providing a voltage to the second terminal of the driving transistor for the first reset signal terminal; During the holding phase, the write sub-circuit disconnects from the first terminal of the drive transistor in response to the control of the fourth scan signal; During the second bias phase, the first reset sub-circuit provides a voltage to the first reset signal terminal of the driving transistor in response to the control of the first scan signal; the first threshold control sub-circuit disconnects the control terminal of the driving transistor from the second terminal of the driving transistor in response to the second scan signal. In the second light-emitting stage, the light-emitting element emits light in response to the driving current of the driving transistor.

10. The driving method for the pixel driving circuit according to claim 8, characterized in that, The first reset phase further includes a reset maintenance sub-phase located between the first reset sub-phase and the second reset sub-phase. During the reset sustaining sub-stage, the first reset sub-circuit provides a voltage to the second terminal of the driving transistor in response to the control of the first scan signal; the first threshold control sub-circuit disconnects the control terminal of the driving transistor from the second terminal of the driving transistor in response to the second scan signal.

11. The driving method for the pixel driving circuit according to claim 8, characterized in that, The first reset phase includes a first reset sub-phase and a second reset sub-phase. During the first reset phase, the first reset sub-circuit provides a voltage to the second terminal of the driving transistor in response to the control of the first scan signal; the first threshold control sub-circuit disconnects the control terminal of the driving transistor from the second terminal of the driving transistor in response to the second scan signal. During the second reset phase, the second reset sub-circuit provides a voltage at the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control sub-circuit disconnects the control terminal of the driving transistor from the second terminal of the driving transistor in response to the second scan signal.

12. The driving method for the pixel driving circuit according to claim 8, characterized in that, The refresh driving cycle of the driving method also includes: During the first reset phase, the first reset sub-circuit provides a voltage to the second terminal of the driving transistor in response to the control of the first scan signal, the second reset sub-circuit provides a voltage to the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal, and the first threshold control sub-circuit disconnects the connection between the control terminal of the driving transistor and the second terminal of the driving transistor in response to the second scan signal.

13. A display panel comprising a pixel driving circuit as described in any one of claims 1-7.

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