Timing driving circuit, method and display device

Abstract

The application relates to a timing driving circuit, a method and a display device. The timing driving circuit comprises a master control module, a switch module, a first clock signal output module and a second clock signal output module. The master control module is used for outputting a first clock control signal, a second clock control signal, a first scanning start signal and a second scanning start signal. The switch module is used for transmitting the first clock control signal and the second clock control signal to the first clock signal output module under the control of the first scanning start signal, and transmitting the first clock control signal and the second clock control signal to the second clock signal output module under the control of the second scanning start signal. The first clock signal output module is used for outputting a first clock signal group corresponding to the first scanning start signal according to the first clock control signal and the second clock control signal. The second clock signal output module is used for outputting a second clock signal group corresponding to the second scanning start signal according to the first clock control signal and the second clock control signal. The clock control signal is multiplexed, and the TCON port of the SOC is saved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a timing driving circuit, method and display device. Background Technology

[0002] In recent years, with the widespread adoption of Hardware Super Resolution (HSR) panels, the requirements for peripheral drivers of display panels have also increased. Currently, HSR display panels mainly use 12 clock signals. Some display panels also require gate row scan array (GOA) input signals such as scan start signals or pull-down sustain unit control signals. The large number of GOA signals necessitates a significant number of timing control (TCON) ports on the System on Chip (SOC). Since ordinary input / output (IO) ports cannot be used to replace the SOC's TCON ports, there is a problem that the number of SOC TCON ports is insufficient to meet the usage requirements of HSR panels. Summary of the Invention

[0003] This application provides a timing drive circuit, method, and display device to address the problem that the limited number of TCON ports cannot meet the usage requirements of HSR panels.

[0004] In a first aspect, this application provides a timing drive circuit, including: a main control module, a switch module, a first clock signal output module, and a second clock signal output module;

[0005] The main control module is used to output a first clock control signal, a second clock control signal, a first scan start signal, and a second scan start signal;

[0006] The switch module is used to transmit the first clock control signal and the second clock control signal to the first clock signal output module under the control of the first scan start signal, and to transmit the first clock control signal and the second clock control signal to the second clock signal output module under the control of the second scan start signal.

[0007] The first clock signal output module is used to receive the first clock control signal and the second clock control signal, and output at least one first clock signal group according to the first clock control signal and the second clock control signal;

[0008] The second clock signal output module is used to receive the first clock control signal and the second clock control signal, and output at least one second clock signal group according to the first clock control signal and the second clock control signal.

[0009] Optionally, the switching module includes: a first transistor unit and a second transistor unit;

[0010] The main control module has a first clock control signal terminal, a second clock control signal terminal, a first scan start signal terminal, and a second scan start signal terminal;

[0011] The first clock control signal terminal is used to output the first clock control signal;

[0012] The second clock control signal terminal is used to output the second clock control signal;

[0013] The first scan start signal terminal is used to output the first scan start signal;

[0014] The second scan start signal terminal is used to output the second scan start signal;

[0015] The first terminal of the first transistor unit and the first terminal of the second transistor unit are both electrically connected to the first clock control signal terminal of the main control module. The second terminal of the first transistor unit and the second terminal of the second transistor unit are both electrically connected to the second clock control signal terminal of the main control module. The third terminal of the first transistor unit and the fourth terminal of the first transistor unit are both electrically connected to the first clock signal output module. The control terminal of the first transistor unit is electrically connected to the first scan start signal terminal of the main control module. The third terminal of the second transistor unit and the fourth terminal of the second transistor unit are both electrically connected to the second clock signal output module. The control terminal of the second transistor unit is electrically connected to the second scan start signal terminal of the main control module.

[0016] The first transistor unit is configured to transmit the first clock control signal and the second clock control signal to the first clock signal output module under the control of the first scan start signal;

[0017] The second transistor unit is used to transmit the first clock control signal and the second clock control signal to the second clock signal output module under the control of the second scan start signal.

[0018] Optionally, the first transistor unit includes: a first transistor and a second transistor;

[0019] Both the control terminals of the first transistor and the second transistor are electrically connected to the first scan start signal terminal. The first terminal of the first transistor is electrically connected to the first clock control signal terminal, and the second terminal of the first transistor is electrically connected to the first input terminal of the first clock signal output module.

[0020] The first terminal of the second transistor is electrically connected to the second clock control signal terminal, and the second terminal of the second transistor is electrically connected to the second input terminal of the first clock signal output module.

[0021] Optionally, the second transistor unit includes: a third transistor and a fourth transistor;

[0022] The control terminals of the third transistor and the fourth transistor are both electrically connected to the second scan start signal terminal. The first terminal of the third transistor is electrically connected to the first clock control signal terminal, and the second terminal of the third transistor is electrically connected to the first input terminal of the second clock signal output module.

[0023] The first terminal of the fourth transistor is electrically connected to the second clock control signal terminal, and the second terminal of the fourth transistor is electrically connected to the second input terminal of the second clock signal output module.

[0024] Optionally, the first clock signal output module includes: a first level conversion circuit;

[0025] The first terminal of the first level conversion circuit is electrically connected to the second terminal of the first transistor, and the second terminal of the first level conversion circuit is electrically connected to the second terminal of the second transistor.

[0026] Optionally, the second clock signal output module includes: a second level conversion circuit;

[0027] The first terminal of the second level conversion circuit is electrically connected to the second terminal of the third transistor, and the second terminal of the second level conversion circuit is electrically connected to the second terminal of the third transistor.

[0028] Optionally, the liquid crystal panel is used to display images based on the first clock signal group and the second clock signal group.

[0029] Optionally, the main control module includes: a main chip;

[0030] The first clock control signal terminal of the main chip is electrically connected to the first terminal and the second terminal of the switch module, and the second clock control signal terminal of the main chip is electrically connected to the third terminal and the fourth terminal of the switch module.

[0031] The first scan start signal terminal of the main chip is electrically connected to the first control terminal of the switch module, and the second scan start signal terminal of the main chip is electrically connected to the second control terminal of the switch module.

[0032] Secondly, this application provides a timing-driven method, characterized in that it includes:

[0033] The main control module outputs a first clock control signal, a second clock control signal, and a scan start signal to the switch module. The scan start signal includes the first scan start signal and the second scan start signal. The first scan start signal is used to control the switch module to transmit the first clock control signal and the second clock control signal to the first clock signal output module. The second scan start signal is used to control the switch module to transmit the first clock control signal and the second clock control signal to the second clock signal output module.

[0034] Based on the first clock control signal and the second clock control signal, at least one first clock signal group is output through the first clock signal output module;

[0035] Based on the first clock control signal and the second clock control signal, at least one second clock signal group is output through the second clock signal output module.

[0036] Optionally, the switching module includes: a first transistor unit and a second transistor unit; the main control module alternately outputs a first scan start signal of the target level signal and a first scan start signal of the non-target level signal according to a preset output frequency;

[0037] When the first scan start signal is a target level signal and the second scan control signal is a non-target level signal, the first transistor unit is turned on according to the first scan start signal and provides the first clock control signal and the second clock control signal to the first clock signal output module. The first clock signal output module receives the first clock control signal and the second clock control signal and outputs at least one first clock signal group according to the first clock control signal and the second clock control signal.

[0038] The main control module alternately outputs a second scan start signal of a non-target level signal and a second scan start signal of a target level signal according to a preset output frequency.

[0039] When the first scan control signal is a non-target level signal and the second scan control signal is a target level signal, the second transistor unit is turned on according to the second scan start signal and provides the first clock control signal and the second clock control signal to the second clock signal output module. The second clock signal output module receives the first clock control signal and the second clock control signal and outputs at least one second clock signal group according to the first clock control signal and the second clock control signal.

[0040] Thirdly, this application also provides a display device including a timing drive circuit as described in any of the first aspects.

[0041] In this embodiment, the main control module outputs a first clock control signal, a second clock control signal, and a scan start signal to the switch module. The scan start signal includes the first scan start signal and the second scan start signal. The first scan start signal controls the switch module to transmit the first clock control signal and the second clock control signal to the first clock signal output module. The second scan start signal controls the switch module to transmit the first clock control signal and the second clock control signal to the second clock signal output module. Based on the first clock control signal and the second clock control signal, the first clock signal output module outputs the first clock signal group corresponding to the first scan start signal, and the second clock signal output module outputs the second clock signal group corresponding to the second scan start signal. This achieves multiplexing of clock control signals, reduces the input of clock control signals, and saves TCON ports. Attached Figure Description

[0042] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A schematic diagram of the structure of an HSR panel with 8 TCON ports is provided for the prior art;

[0045] Figure 2 A schematic diagram of the structure of an HSR panel with 9 TCON ports provided for the prior art;

[0046] Figure 3 A timing diagram of an HSR panel is provided for the prior art;

[0047] Figure 4 This is a schematic diagram of a timing drive circuit provided in an embodiment of this application;

[0048] Figure 5 A schematic diagram of a timing drive circuit provided in an optional embodiment of this application;

[0049] Figure 6 The timing diagram corresponding to the timing drive circuit provided in the optional example of this application;

[0050] Figure 7 This is a timing diagram corresponding to the timing drive circuit provided in another optional embodiment of this application;

[0051] Figure 8 This is a flowchart illustrating a timing-driven method provided in an embodiment of this application. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0053] In related technologies, the TCON port of the SOC is mainly used as an I / O port to generate the screen GOA input timing. The number of GOA signals and their input timing vary between different displays, such as scan start signals STV0 / STV1 / STV2, clock signals CK1-CK12, pull-down sustain unit control signals LC1 / LC2, etc. The GOA control signals required by these screens are jointly generated and controlled by the level shifter IC. Since the level shifter IC channel logic includes one input and one output, and one input and multiple outputs (one input and one output means that one STV_in input generates two STV1A and STV1B, and one LC_in input generates LC1 and LC2), the required SOC TCON port also varies. The SOC TCON port is different from ordinary I / O ports. Due to the differences in SOC hardware and software configurations, the number of TCON ports generally varies from SOC to SOC. Moreover, due to the need to generate specific timings (such as CPV1 / CPV2 / CPV3 / CPV4 timings, which have relatively high frequencies), the TCON port resources of the SOC are very limited and often cannot be replaced by ordinary IO ports. Even TCON ports cannot be used interchangeably. For example, a CPV1 port can only be used for CPV1 and cannot be used for CPV2 or STV TCON port resources.

[0054] Traditional non-HSR panels typically require four TCON ports: scan start signal STV_in, pull-down sustain unit control signal LC_in, and clock control signals CPV1 / CPV2. If the Level Shifter IC used has a one-in-one-out channel for both the scan start signal and the pull-down sustain unit control signal LC, i.e., one input to STV_in generates two STV1A and STV1B, and one input to LC_in generates LC1 and LC2, then at most six TCON ports are needed. However, if... Figure 1 As shown, an HSR panel typically requires an SOC to provide 8 TCON ports, including 3 scan start signals STV0, STV1, and STV2, 1 pull-down sustain unit control signal LC1_in, and 4 clock control signals CPV1, CPV2, CPV3, and CPV4. If the selected Level Shifter IC has a one-in-one-out LC channel, then as follows... Figure 2 As shown, an LC2_in is also needed, requiring at least 9 TCON ports from the SOC. Existing technology typically uses two Level Shifter ICs, which, in addition to generating STV and LC signals, also generate the CK signal. Generating CK1-CK12 with two Level Shifter ICs requires four CPV inputs from the SOC, namely CPV1-CPV4. For example... Figure 3As shown, by simply controlling the CPV input time, the functions of CPV1-CPV4 can be achieved using only CPV1 and CPV2.

[0055] Therefore, one of the core technical concepts of this application is to propose a timing drive circuit that realizes the multiplexing of CPV1 and CPV2, eliminating the need to input the timing control signals CPV3 and CPV4, thus saving the TCON port and addressing the problem that the limited number of TCON ports cannot meet the usage requirements of HSR panels.

[0056] Figure 4 This is a schematic diagram of a timing drive circuit provided in an embodiment of this application; specifically, as shown... Figure 4 As shown, the timing drive circuit provided in this application embodiment may specifically include: a main control module 41, a switch module 42, a first clock signal output module 43, and a second clock signal output module 44; wherein, the main control module 41 is used to output a first clock control signal CPV1, a second clock control signal CPV2, and a scan start signal ST, the scan start signal including the first scan start signal ST_ODD and the second scan start signal ST_EVEN; the switch module 42 is used to transmit the first clock control signal CPV1 and the second clock control signal CPV2 to the first clock signal output module 43 under the control of the first scan start signal ST_ODD, and to transmit the first clock control signal CPV1 and the second clock control signal CPV2 to the second clock signal output module 44 under the control of the first scan start signal ST_EVEN; the first clock signal output module 43 is used to output at least one first clock signal group according to the first clock control signal CPV1 and the second clock control signal CPV2; the second clock signal output module 44 is used to output at least one second clock signal group according to the first clock control signal CPV1 and the second clock control signal CPV2.

[0057] Specifically, in this embodiment, the main control module 41 can output a first clock control signal CPV1, a second clock control signal CPV2, a first scan start signal ST_ODD, and a first scan start signal ST_EVEN to the switch module 42. This allows the switch module 42 to transmit the first clock control signal CPV1 and the second clock control signal CPV2 to the first clock signal output module 43 under the control of the first scan start signal ST_ODD. The first clock signal output module 43 can then output a first clock signal group corresponding to the first scan start signal ST_ODD based on the first clock control signal CPV1 and the second clock control signal CPV2. Furthermore, the switch module 42 can provide the first clock control signal CPV1 and the second clock control signal CPV2 to the second clock signal output module 44 under the control of the first scan start signal ST_EVEN. This allows the clock signal output module to output a second clock signal group corresponding to the first scan start signal ST_EVEN based on the first clock control signal CPV1 and the second clock control signal CPV2, thereby achieving the multiplexing of clock control signals.

[0058] The timing drive circuit provided in this application can be applied to a display panel, such as a timing drive circuit for a display panel. This application does not impose specific limitations on this.

[0059] As can be seen, in this embodiment, the main control module outputs a first clock control signal, a second clock control signal, and a scan start signal to the switch module. The scan start signal includes the first scan start signal and the second scan start signal. The first scan start signal controls the switch module to transmit the first clock control signal and the second clock control signal to the first clock signal output module. The second scan start signal controls the switch module to transmit the first clock control signal and the second clock control signal to the second clock signal output module. Thus, based on the first clock control signal and the second clock control signal, the first clock signal output module outputs the first clock signal group corresponding to the first scan start signal, and based on the first clock control signal and the second clock control signal, the second clock signal output module outputs the second clock signal group corresponding to the second scan start signal. This achieves multiplexing of clock control signals, reduces the input of clock control signals, and saves TCON ports.

[0060] Figure 5 This application provides a schematic diagram of the structure of a timing drive circuit in an optional embodiment, as shown below. Figure 5As shown, the switching module 42 in this embodiment includes: a first transistor M1 unit 21 and a second transistor M2 unit 22; wherein, the first terminal of the first transistor M1 unit 21 and the first terminal of the second transistor M2 unit 22 are both electrically connected to the first clock control signal CPV1 terminal of the main control module 41, the second terminal of the first transistor M1 unit 21 and the second terminal of the second transistor M2 unit 22 are both electrically connected to the second clock control signal CPV2 terminal of the main control module 41, the third terminal and the fourth terminal of the first transistor M1 unit 21 are both electrically connected to the first clock signal output module 43, the control terminal of the first transistor M1 unit 21 is electrically connected to the first scan start signal ST_ODD terminal of the main control module 41, the third terminal and the fourth terminal of the second transistor M2 unit 22 are both electrically connected to the second clock signal output module 44, and the control terminal of the second transistor M2 unit 22 is electrically connected to the first clock signal output module 43. The first scan start signal ST_EVEN terminal of the control module 41 is electrically connected; the first clock control signal CPV1 terminal is used to output the first clock control signal CPV1; the second clock control signal CPV2 terminal is used to output the second clock control signal CPV2; the first scan start signal ST_ODD terminal is used to output the first scan start signal ST_ODD; the first scan start signal ST_EVEN terminal is used to output the first scan start signal ST_EVEN; the first transistor M1 unit 21 is used to transmit the first clock control signal CPV1 and the second clock control signal CPV2 to the first clock signal output module 43 under the control of the first scan start signal ST_ODD; the second transistor M2 unit 22 is used to transmit the first clock control signal CPV1 and the second clock control signal CPV2 to the second clock signal output module 44 under the control of the first scan start signal ST_EVEN.

[0061] Specifically, in this embodiment, the control terminal of the first transistor M1 unit 21 is electrically connected to the first scan start signal ST_ODD terminal of the main control module 41, and the first terminal of the first transistor M1 unit 21 is electrically connected to the first clock control signal CPV1 terminal of the main control module 41. The second terminal of the first transistor M1 unit 21 is electrically connected to the second clock signal group terminal of the main control module 41. The third and fourth terminals of the first transistor M1 unit 21 are both electrically connected to the first clock signal output module 43. This allows the first transistor M1 unit 21 to provide the first clock control signal CPV1 output from the first clock control signal CPV1 terminal and the second clock control signal CPV2 output from the second clock control signal CPV2 terminal of the main control module 41 to the first clock signal output module 43 under the control of the first scan start signal ST_ODD terminal of the main control module 41. Furthermore, the control terminal of the second transistor M2 unit 22 is electrically connected to the first scan start signal ST_ODD terminal of the main control module 41. The _EVEN terminal is electrically connected. The first terminal of the second transistor M2 unit 22 is electrically connected to the first clock control signal CPV1 terminal of the main control module 41. The second terminal of the second transistor M2 unit 22 is electrically connected to the second clock signal group terminal of the main control module 41. The third and fourth terminals of the second transistor M2 unit 22 are both electrically connected to the second clock signal output module 44. This allows the second transistor M2 unit 22 to provide the first clock control signal CPV1 output from the first clock control signal CPV1 terminal and the second clock control signal CPV2 output from the second clock control signal CPV2 terminal of the main control module 41 to the first and second clock signal output modules under the control of the first scan start signal ST_EVEN terminal of the main control module 41. Thus, the first clock signal group is output through the first clock signal output module 43, and the second clock signal group is output through the second clock signal output module 44, thereby realizing the multiplexing of clock control signals and saving the TCON port of the SOC.

[0062] Furthermore, the first transistor M1 unit 21 in this embodiment includes: a first transistor M1 and a second transistor M2; wherein, the control terminals of the first transistor M1 and the second transistor M2 are both electrically connected to the first scan start signal ST_ODD terminal, the first terminal of the first transistor M1 is electrically connected to the first clock control signal CPV1 terminal, and the second terminal of the first transistor M1 is electrically connected to the first input terminal of the first clock signal output module 43; the first terminal of the second transistor M2 is electrically connected to the second clock control signal CPV2 terminal, and the second terminal of the second transistor M2 is electrically connected to the second input terminal of the first clock signal output module 43, so that the first transistor M1, under the control of the first scan start signal ST_ODD, provides the first clock control signal CPV1 to the first clock signal output module 43, and the second transistor M2, under the control of the first scan start signal ST_ODD, provides the second clock control signal CPV2 to the first clock output module, thereby enabling the first clock output module to output a first clock signal group according to the first clock control signal CPV1 and the second clock control signal CPV2.

[0063] Furthermore, the second transistor M2 unit 22 in this embodiment includes a third transistor M3 and a fourth transistor M4; wherein the control terminals of the third transistor M3 and the fourth transistor M4 are both electrically connected to the first scan start signal ST_EVEN terminal, the first terminal of the third transistor M3 is electrically connected to the first clock control signal CPV1 terminal, and the second terminal of the third transistor M3 is electrically connected to the first input terminal of the second clock signal output module 44; the first terminal of the fourth transistor M4 is electrically connected to the second clock control signal CPV2 terminal, and the second terminal of the fourth transistor M4 is electrically connected to the second input terminal of the second clock signal output module 44, so that the third transistor M3, under the control of the first scan start signal ST_ODD, provides the first clock control signal CPV1 to the first clock signal output module 43, and the fourth transistor M4, under the control of the first scan start signal ST_ODD, provides the second clock control signal CPV2 to the second clock output module, thereby enabling the second clock output module to output a second clock signal group according to the first clock control signal CPV1 and the second clock control signal CPV2.

[0064] Optionally, the first clock signal output module 43 in this embodiment includes: a first level conversion circuit; wherein, the first terminal of the first level conversion circuit is electrically connected to the second terminal of the first transistor M1, and the second terminal of the first level conversion circuit is electrically connected to the second terminal of the second transistor M2, so that the first level conversion circuit outputs a first clock signal group according to the first clock control signal CPV1 provided by the first transistor M1 and the second clock control signal CPV2 provided by the second transistor M2.

[0065] Furthermore, the second clock signal output module 44 in this embodiment includes: a second level conversion circuit; the first terminal of the second level conversion circuit is electrically connected to the second terminal of the third transistor M3, and the second terminal of the second level conversion circuit is electrically connected to the second terminal of the third transistor M3, so that the second level conversion circuit outputs a second clock signal group according to the first clock control signal CPV1 and the second clock control signal CPV2 provided by the third transistor M3.

[0066] Optionally, embodiments of this application may further include: a liquid crystal panel; wherein the open cell of the liquid crystal panel can be used to display images based on the first clock signal group and the second clock signal group.

[0067] Optionally, the main control module 41 in this embodiment may include: a main chip; wherein, the first clock control signal CPV1 terminal of the main chip is electrically connected to the first terminal and the second terminal of the switch module 42, the second clock control signal CPV2 terminal of the main chip is electrically connected to the third terminal and the fourth terminal of the switch module 42; the first scan start signal ST_ODD terminal of the main chip is electrically connected to the first control terminal of the switch module 42, and the first scan start signal ST_EVEN terminal of the main chip is electrically connected to the second control terminal of the switch module 42.

[0068] Specifically, the first clock control signal CPV1 terminal of the main chip is electrically connected to the first terminal and the second terminal of the switch module 42, so that the main chip can provide the first clock control signal CPV1 to the first terminal and the second terminal of the switch module 42 through the first clock control signal CPV1 terminal; the second clock control signal CPV2 terminal of the main chip is electrically connected to the third terminal and the fourth terminal of the switch module 42, so that the main chip can provide the second clock control signal CPV2 to the third terminal and the fourth terminal of the switch module 42 through the second clock control signal CPV2 terminal; the first scan start signal ST_ODD terminal of the main chip is electrically connected to the first control terminal of the switch module 42, and the first scan start signal ST_EVEN terminal of the main chip is electrically connected to the second control terminal of the switch module 42, so that the main chip can provide the first scan start signal ST_ODD to the first control terminal of the switch module 42 through the first scan start signal ST_ODD terminal, and provide the first scan start signal ST_EVEN to the second control terminal of the switch module 42 through the first scan start signal ST_EVEN terminal.

[0069] It should be noted that the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can be switching transistors, transistors, or field-effect transistors. Specifically, they can be N-type transistors or P-type transistors. This application does not impose specific limitations on these aspects in the embodiments.

[0070] As an example of this application, when the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all N-type transistors, and the first scan start signal ST_ODD is high, both the first transistor M1 and the second transistor M2 are in a conducting state under the control of the first scan start signal ST_ODD. This allows the SOC to provide the first clock control signal CPV1 and the second clock control signal CPV2 to the Level shifter IC1 through the first transistor M1 and the second transistor M2, respectively, so that the Level shifter IC1 outputs the first clock signal group. When the first scan start signal ST_EVEN is high, both the third transistor M3 and the fourth transistor M4 are in a conducting state under the control of the first scan start signal ST_EVEN. This allows the third transistor M3 to provide the first clock control signal CPV1 to the Level shifter IC2, and the fourth transistor M4 to provide the second clock control signal CPV2 to the Level shifter IC2, so that the Level shifter... IC2 can output a second clock signal group based on the first clock control signal CPV1 and the second clock control signal CPV2. The first clock signal group may include CK1, CK2, CK3, CK4, CK5 and CK6, and the second clock signal group may include CK7, CK8, CK9, CK10, CK11 and CK12. The first scan start signal ST_ODD terminal and the first scan start signal ST_EVEN terminal can be ordinary I / O ports.

[0071] Figure 6 The timing diagram provided here is an optional example of the timing drive circuit in this application; specifically, as shown in the figure. Figure 6As shown, when the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all N-type transistors, the first scan start signal ST_ODD and the first scan start signal ST_EVEN change between high and low levels within a preset time interval. For example, in the first half of a frame, the first scan start signal ST_ODD is at a high level. Under the control of the first scan start signal ST_ODD, the first clock control signal CPV1 and the second clock control signal CPV2 are provided to the Level shifter IC1, and the first clock signal group is output. Since the first scan start signal ST_EVEN is at a low level at this time, the third transistor M3 and the fourth transistor M4 are both in the off state, and the first clock control signal CPV1 and the second clock control signal CPV2 cannot be input to the Level shifter IC2. At this time, the Level shifter IC2 does not work and does not output the first clock signal group. However, in the second half of a frame, the first scan start signal ST_ODD is at a low level, and the first clock control signal CPV1 and the second clock control signal CPV2 cannot be input to the Level shifter IC1. At this time, the Level shifter IC2 does not work and does not output the first clock signal group. Level shifter IC1 is not working, and there is no first clock signal group output. At this time, since the first scan start signal ST_EVEN is high, both the third transistor M3 and the fourth transistor M4 are in the conducting state. The first clock control signal CPV1 and the second clock control signal CPV2 are input to Level shifter IC2 through the third transistor M3 and the fourth transistor M4, respectively. This allows Level shifter IC2 to work according to the first clock control signal CPV1 and the second clock control signal CPV2 and output the second clock signal group. By making Level shifter IC1 and Level shifter IC2 alternately output the first clock signal group and the second clock signal group, the timing output of one frame of image driving GOA is completed. Thus, by controlling the conduction and disconnection of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, the first clock control signal CPV1 and the second clock control signal CPV2 are provided to the first clock signal output module 43 and the second clock signal group clock module. This achieves the multiplexing of the first clock control signal CPV1 and the second clock signal group, requiring only two clock control signal interfaces and saving the TCON port of the SOC.

[0072] Figure 7 The timing diagram corresponds to the timing drive circuit provided in another optional embodiment of this application. Specifically, as shown... Figure 7As shown, when the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all P-type transistors, the first scan start signal ST_ODD and the first scan start signal ST_EVEN change between high and low levels within a preset time interval. For example, in the first half of a frame, the first scan start signal ST_ODD is low. Under the control of the first scan start signal ST_ODD, the first clock control signal CPV1 and the second clock control signal CPV2 are provided to the Level shifter IC1, and the first clock signal group is output. Since the first scan start signal ST_EVEN is high at this time, the third transistor M3 and the fourth transistor M4 are both in the off state, and the first clock control signal CPV1 and the second clock control signal CPV2 cannot be input to the Level shifter IC2. At this time, the Level shifter IC2 does not work and does not output the second clock signal group. However, in the second half of a frame, the first scan start signal ST_ODD is high, and the first clock control signal CPV1 and the second clock control signal CPV2 cannot be input to the Level shifter IC1. At this time, the Level shifter IC2 does not work and does not output the second clock signal group. Level shifter IC1 is not working, and there is no first clock signal group output. At this time, since the first scan start signal ST_EVEN is low, both the third transistor M3 and the fourth transistor M4 are in the on state. The first clock control signal CPV1 and the second clock control signal CPV2 are input to Level shifter IC2 through the third transistor M3 and the fourth transistor M4, respectively, so that Level shifter IC2 can work according to the first clock control signal CPV1 and the second clock control signal CPV2 and output the second clock signal group. By controlling the on and off states of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, Level shifter IC1 and Level shifter IC2 alternately output the first clock signal group and the second clock signal group, thereby completing the GOA timing output driven by one frame of image. This realizes the provision of the first clock control signal CPV1 and the second clock control signal CPV2 to the first clock signal output module 43 and the second clock signal group clock module, thus realizing the multiplexing of the first clock control signal CPV1 and the second clock signal group. Only two clock control signal interfaces are needed, saving the TCON port of the SOC.

[0073] In summary, this embodiment of the application can output a first clock control signal CPV1, a second clock control signal CPV2, and a scan start signal to the switch module 42 via the main control module 41. The scan start signal includes the first scan start signal and the second scan start signal. The first scan start signal is used to control the switch module 42 to transmit the first clock control signal CPV1 and the second clock control signal CPV2 to the first clock signal output module 43. The second scan start signal is used to control the switch module 42 to transmit the first clock control signal CPV1 and the second clock control signal CPV2 to the second clock signal output module 44. Thus, based on the first clock control signal CPV1 and the second clock control signal CPV2, the first clock signal output module 43 outputs the first clock signal group corresponding to the first scan start signal, and based on the first clock control signal CPV1 and the second clock control signal CPV2, the second clock signal output module 44 outputs the second clock signal group corresponding to the second scan start signal. This achieves multiplexing of clock control signals, reduces the input of clock control signals, and saves TCON ports.

[0074] Figure 8 This is a flowchart illustrating a timing-driven method provided in an embodiment of this application. Specifically, as shown... Figure 8 As shown, the timing-driven method provided in this application includes the following steps:

[0075] Step 81: The main control module outputs a first clock control signal, a second clock control signal, and a scan start signal to the switch module. The scan start signal includes the first scan start signal and the second scan start signal. The first scan start signal is used to control the switch module to transmit the first clock control signal and the second clock control signal to the first clock signal output module. The second scan start signal is used to control the switch module to transmit the first clock control signal and the second clock control signal to the second clock signal output module.

[0076] Step 82: Based on the first clock control signal and the second clock control signal, output at least one first clock signal group through the first clock signal output module;

[0077] Step 83: Based on the first clock control signal and the second clock control signal, output at least one second clock signal group through the second clock signal output module.

[0078] Specifically, in this embodiment, the main control module can output a first clock control signal, a second clock control signal, a first scan start signal, and a second scan start signal to the switch module. Under the control of the first scan start signal, the switch module can transmit the first clock control signal and the second clock control signal to the first clock signal output module, and under the control of the second scan start signal, transmit the first clock control signal and the second clock control signal to the second clock signal output module. This allows the first clock signal output module to output a first clock signal group based on the first clock control signal and the second clock control signal, and the second clock signal output module to output a second clock signal group based on the first clock control signal and the second clock control signal, thereby completing the display of one frame of the image. This achieves the multiplexing of clock control signals, reduces the number of clock control signals that need to be input, and saves the TCON port of the SOC.

[0079] Optionally, the switching module includes: a first transistor unit and a second transistor unit; the main control module alternately outputs a first scan start signal of a target level signal and a first scan start signal of a non-target level signal according to a preset output frequency; when the first scan start signal is a target level signal and the second scan control signal is a non-target level signal, the first transistor unit is turned on according to the first scan start signal and provides the first clock control signal and the second clock control signal to the first clock signal output module, the first clock signal output module is connected to the first clock control signal and the second clock control signal, and outputs at least one first clock signal group according to the first clock control signal and the second clock control signal; the main control module alternately outputs a second scan start signal of a non-target level signal and a second scan start signal of a target level signal according to a preset output frequency; when the first scan control signal is a non-target level signal and the second scan control signal is a target level signal, the second transistor unit is turned on according to the second scan start signal and provides the first clock control signal and the second clock control signal to the second clock signal output module, the second clock signal output module is connected to the first clock control signal and the second clock control signal, and outputs at least one second clock signal group according to the first clock control signal and the second clock control signal.

[0080] In actual processing, the first scan start signal and the first scan start signal can change between high and low levels within a preset time interval. For example, in the first half of a frame, the first scan start signal is low, allowing the first transistor unit to provide the first clock control signal and the second clock control signal to Level shifter IC1 under the control of the first scan start signal, and output the first clock signal group. Since the first scan start signal is high at this time, the second transistor unit is in the off state, and the first clock control signal and the second clock control signal cannot be input to Level shifter IC2. At this time, Level shifter IC2 does not work and does not output the second clock signal group. In the second half of a frame, the first scan start signal is high, and the first clock control signal and the second clock control signal cannot be input to Level shifter IC1. At this time, Level shifter IC1 does not work and there is no first clock signal group output. Since the first scan start signal terminal is low, the second transistor unit is in the on state, and the first clock control signal and the second clock control signal are respectively input to Level shifter IC2 through the second transistor unit, allowing Level shifter IC2 to work according to the first clock control signal and the second clock control signal, and output the second clock signal group. By controlling the on and off states of the first and second transistor units, Level shifter IC1 and Level shifter IC2 alternately output the first clock signal group and the second clock signal group, thereby completing the GOA timing output driven by one frame of image. This realizes the provision of the first clock control signal and the second clock control signal to the first clock signal output module and the second clock signal group clock module, thus realizing the multiplexing of the first clock control signal and the second clock signal group. Only two clock control signal interfaces are needed, saving the TCON port of the SOC.

[0081] This application also provides a display device comprising a timing drive circuit as described above.

[0082] The display device in this application embodiment can be an HSR display panel, or it can be other display panels with different resolutions or different refresh rates. This application embodiment does not impose specific limitations on this.

[0083] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0084] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A timing drive circuit, characterized in that, include: Main control module, switch module, first clock signal output module, and second clock signal output module; The main control module is used to output a first clock control signal, a second clock control signal, a first scan start signal, and a second scan start signal; The switching module is used to transmit the first clock control signal and the second clock control signal to the first clock signal output module under the control of the first scan start signal, and to transmit the first clock control signal and the second clock control signal to the second clock signal output module under the control of the second scan start signal. The first clock signal output module is used to receive the first clock control signal and the second clock control signal, and output at least one first clock signal group according to the first clock control signal and the second clock control signal; The second clock signal output module is used to receive the first clock control signal and the second clock control signal, and output at least one second clock signal group according to the first clock control signal and the second clock control signal.

2. The timing drive circuit according to claim 1, characterized in that, The switching module includes: a first transistor unit and a second transistor unit; The main control module has a first clock control signal terminal, a second clock control signal terminal, a first scan start signal terminal, and a second scan start signal terminal; The first clock control signal terminal is used to output the first clock control signal; The second clock control signal terminal is used to output the second clock control signal; The first scan start signal terminal is used to output the first scan start signal; The second scan start signal terminal is used to output the second scan start signal; The first terminal of the first transistor unit and the first terminal of the second transistor unit are both electrically connected to the first clock control signal terminal of the main control module. The second terminal of the first transistor unit and the second terminal of the second transistor unit are both electrically connected to the second clock control signal terminal of the main control module. The third terminal of the first transistor unit and the fourth terminal of the first transistor unit are both electrically connected to the first clock signal output module. The control terminal of the first transistor unit is electrically connected to the first scan start signal terminal of the main control module. The third terminal of the second transistor unit and the fourth terminal of the second transistor unit are both electrically connected to the second clock signal output module. The control terminal of the second transistor unit is electrically connected to the second scan start signal terminal of the main control module. The first transistor unit is configured to transmit the first clock control signal and the second clock control signal to the first clock signal output module under the control of the first scan start signal; The second transistor unit is used to transmit the first clock control signal and the second clock control signal to the second clock signal output module under the control of the second scan start signal.

3. The timing drive circuit according to claim 2, characterized in that, The first transistor unit includes: a first transistor and a second transistor; Both the control terminals of the first transistor and the second transistor are electrically connected to the first scan start signal terminal. The first terminal of the first transistor is electrically connected to the first clock control signal terminal, and the second terminal of the first transistor is electrically connected to the first input terminal of the first clock signal output module. The first terminal of the second transistor is electrically connected to the second clock control signal terminal, and the second terminal of the second transistor is electrically connected to the second input terminal of the first clock signal output module.

4. The timing drive circuit according to claim 2, characterized in that, The second transistor unit includes: a third transistor and a fourth transistor; The control terminals of the third transistor and the fourth transistor are both electrically connected to the second scan start signal terminal. The first terminal of the third transistor is electrically connected to the first clock control signal terminal, and the second terminal of the third transistor is electrically connected to the first input terminal of the second clock signal output module. The first terminal of the fourth transistor is electrically connected to the second clock control signal terminal, and the second terminal of the fourth transistor is electrically connected to the second input terminal of the second clock signal output module.

5. The timing drive circuit according to claim 3, characterized in that, The first clock signal output module includes: a first level conversion circuit; The first terminal of the first level conversion circuit is electrically connected to the second terminal of the first transistor, and the second terminal of the first level conversion circuit is electrically connected to the second terminal of the second transistor.

6. The timing drive circuit according to claim 4, characterized in that, The second clock signal output module includes: a second level conversion circuit; The first terminal of the second level conversion circuit is electrically connected to the second terminal of the third transistor, and the second terminal of the second level conversion circuit is electrically connected to the second terminal of the third transistor.

7. The timing drive circuit according to claim 1, characterized in that, Also includes: LCD panel; The liquid crystal panel is used to display images based on the first clock signal group and the second clock signal group.

8. The timing drive circuit according to claim 2, characterized in that, The main control module includes: a main chip; The first clock control signal terminal of the main chip is electrically connected to the first terminal and the second terminal of the switch module, and the second clock control signal terminal of the main chip is electrically connected to the third terminal and the fourth terminal of the switch module. The first scan start signal terminal of the main chip is electrically connected to the first control terminal of the switch module, and the second scan start signal terminal of the main chip is electrically connected to the second control terminal of the switch module.

9. A timing-driven method, characterized in that, include: The main control module outputs a first clock control signal, a second clock control signal, a first scan start signal, and a second scan start signal to the switch module. The first scan start signal is used to control the switch module to transmit the first clock control signal and the second clock control signal to the first clock signal output module. The second scan start signal is used to control the switch module to transmit the first clock control signal and the second clock control signal to the second clock signal output module. Based on the first clock control signal and the second clock control signal, at least one first clock signal group is output through the first clock signal output module; Based on the first clock control signal and the second clock control signal, at least one second clock signal group is output through the second clock signal output module.

10. The timing-driven method according to claim 9, characterized in that, The switching module includes: a first transistor unit and a second transistor unit; The main control module alternately outputs the first scan start signal of the target level signal and the first scan start signal of the non-target level signal according to a preset output frequency. When the first scan start signal is a target level signal and the second scan control signal is a non-target level signal, the first transistor unit is turned on according to the first scan start signal and provides the first clock control signal and the second clock control signal to the first clock signal output module. The first clock signal output module receives the first clock control signal and the second clock control signal and outputs at least one first clock signal group according to the first clock control signal and the second clock control signal. The main control module alternately outputs a second scan start signal of a non-target level signal and a second scan start signal of a target level signal according to a preset output frequency. When the first scan control signal is a non-target level signal and the second scan control signal is a target level signal, the second transistor unit is turned on according to the second scan start signal and provides the first clock control signal and the second clock control signal to the second clock signal output module. The second clock signal output module receives the first clock control signal and the second clock control signal and outputs at least one second clock signal group according to the first clock control signal and the second clock control signal.

11. A display device, characterized in that, Includes the timing drive circuit as described in any one of claims 1-8.

Images