Switch chip and high-speed signal pin packaging method of switch chip
By reserving space in the switch chip package to arrange high-speed signal pins and optimizing the placement of SerDes IP modules, the signal integrity bottleneck in traditional designs is solved, enabling lower-cost PCB fabrication.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEAL CORE SEMICON (NANJING) CO LTD
- Filing Date
- 2023-04-10
- Publication Date
- 2026-06-09
AI Technical Summary
The high-speed trace design of traditional switch chips leads to signal integrity performance bottlenecks and increases PCB manufacturing costs.
During the packaging process of the switch chip, space is reserved for the placement of Tx and Rx high-speed signal pins, the placement of the SerDes IP module is optimized, the trace length is reduced, and cheaper PCB materials are used.
It effectively reduces trace loss, lowers production costs, and improves signal integrity performance.
Smart Images
Figure CN116389396B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip packaging technology, and in particular to a switch chip and a method for packaging high-speed signal pins of the switch chip. Background Technology
[0002] Currently, traditional switch chips use a four-sided routing method for high-speed traces to the front port of the switch to reduce the density of traces on each side. However, as signal speeds increase, the longest trace away from the front port becomes the bottleneck for the signal integrity performance of the entire system. This necessitates the use of lower loss materials for the PCB, thereby increasing the system's manufacturing cost.
[0003] Therefore, how to reduce the wire length during switch chip packaging is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0004] This application provides a switch chip and a method for packaging high-speed signal pins of the switch chip. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general description, nor is it intended to identify key / important components or describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.
[0005] In a first aspect, embodiments of this application provide a high-speed signal pin packaging method for a switch chip, including:
[0006] The Tx high-speed signal pin pair is located outside the reserved space in the middle of the first, second, third, and fourth sides of the chip edge;
[0007] The Rx high-speed signal pin pair is located outside the reserved space in the middle of the first, second, third, and fourth sides of the chip edge;
[0008] The length of the reserved space in the middle is less than or equal to the length of the fourth side.
[0009] In an optional embodiment, it further includes:
[0010] Place the Rx high-speed signal pin pair inside the Tx high-speed signal pin pair, and place all Tx high-speed signal pin pairs outside the Rx high-speed signal pin pairs; or,
[0011] A first number of Tx high-speed signal pin pairs are set outside the Rx high-speed signal pin pairs, and a second number of Tx high-speed signal pin pairs and Rx high-speed signal pin pairs are interspersed inside the first number of Tx high-speed signal pin pairs.
[0012] In an optional embodiment, it further includes:
[0013] Set the Tx high-speed signal pin pair inside the Rx high-speed signal pin pair, and place all Rx high-speed signal pin pairs outside the Tx high-speed signal pin pairs; or,
[0014] A first number of preset Rx high-speed signal pin pairs are set outside the Tx high-speed signal pin pairs, and a second number of preset Rx high-speed signal pin pairs and Tx high-speed signal pin pairs are interspersed inside the first number of Rx high-speed signal pin pairs.
[0015] In an optional embodiment, when the length of the intermediate reserved space is equal to the length of the fourth side, the method further includes:
[0016] When the number of high-speed signals at the switching port of the switching chip is x128 channels, 48 Tx high-speed signal pin pairs are set from bottom to top on the first and third sides of the chip edge, and 32 Tx high-speed signal pin pairs are set from any point in the middle of the preset range on the second side of the chip edge to the left and right.
[0017] In an optional embodiment, when the length of the intermediate reserved space is equal to the length of the fourth side, the method further includes:
[0018] When the number of high-speed signals at the switching port of the switching chip is x256 channels, 96 Tx high-speed signal pin pairs are set from bottom to top on the first and third sides of the chip edge, and 64 Tx high-speed signal pin pairs are set from any point in the middle of the preset range on the second side of the chip edge to the left and right.
[0019] In an optional embodiment, when the length of the intermediate reserved space is equal to the length of the fourth side, the method further includes:
[0020] When the number of high-speed signals at the switching port of the switching chip is x128 channels, 48 Rx high-speed signal pin pairs are set from bottom to top on the first and third sides of the chip edge, and 32 Rx high-speed signal pin pairs are set from any point in the middle of the preset range on the second side of the chip edge to the left and right.
[0021] In an optional embodiment, when the length of the intermediate reserved space is equal to the length of the fourth side, the method further includes:
[0022] When the number of high-speed signals at the switching port of the switching chip is x256 channels, 96 Rx high-speed signal pin pairs are set from bottom to top on the first and third sides of the chip edge, and 64 Rx high-speed signal pin pairs are set from any point in the middle of the preset range on the second side of the chip edge to the left and right.
[0023] In an optional embodiment, the P pin and N pin of each pair of Tx high-speed signals are adjacent and separated by a preset first distance;
[0024] The shortest distance between the P and N pins of one pair of Tx high-speed signals and the P and N pins of another pair of Tx high-speed signals is a preset second distance;
[0025] The shortest distance between the P and N pins of a pair of Tx high-speed signals and the P and N pins of another pair of Rx high-speed signals is a preset third distance;
[0026] Specifically, when the highest baud rate of a single channel is less than or equal to 29Gsym / s, the minimum preset second distance is √2 times the preset first distance; when the highest baud rate of a single channel is greater than 29Gsym / s, the minimum preset second distance is twice the preset first distance.
[0027] The minimum preset third distance is twice the preset first distance.
[0028] In an optional embodiment, the P pin and N pin of each pair of Rx high-speed signals are adjacent and separated by a preset first distance;
[0029] The shortest distance between the P and N pins of one pair of Rx high-speed signals and the P and N pins of another pair of Rx high-speed signals is a preset second distance;
[0030] The minimum preset second distance is twice the preset first distance.
[0031] In an optional embodiment, it further includes:
[0032] When the number of high-speed signal channels on the switch chip's switching ports is x128, the number of SerDes IP modules in the kernel area is determined according to the following formula:
[0033] 4X + 8Y = 128
[0034] Where X represents the number of SerDes IP modules with x4 channels, Y represents the number of SerDes IP modules with x8 channels, the sum of X and Y is even, and X and Y are greater than or equal to 0;
[0035] Multiple SerDes IP modules are positioned on the first, second, third, and fourth sides of the kernel region, symmetrical about the central axis of the kernel region.
[0036] In an optional embodiment, it further includes:
[0037] When the number of high-speed signal channels on the switch chip's switching ports is x256, the number of SerDes IP modules in the kernel area is determined according to the following formula:
[0038] 4X + 8Y = 256
[0039] Where X represents the number of SerDes IP modules with x4 channels, Y represents the number of SerDes IP modules with x8 channels, the sum of X and Y is even, and X and Y are greater than or equal to 0;
[0040] Multiple SerDes IP modules are positioned on the first, second, third, and fourth sides of the kernel region, symmetrical about the central axis of the kernel region.
[0041] Secondly, embodiments of this application provide a switch chip, including:
[0042] Tx high-speed signal pin pair and Rx high-speed signal pin pair;
[0043] The Tx high-speed signal pin pair and the Rx high-speed signal pin pair adopt the high-speed signal pin packaging method provided in the above embodiments.
[0044] The technical solutions provided in this application embodiment may include the following beneficial effects:
[0045] The switch chip provided in this application provides space on one side when designing high-speed signal pins, which helps to effectively shorten the longest line length when building the switch chip. This allows the switch to be manufactured using cheaper PCB materials, effectively saving the production cost of the switch chip.
[0046] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description
[0047] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.
[0048] Figure 1 This is a schematic diagram of a switch chip packaging structure according to an exemplary embodiment;
[0049] Figure 2 This is a schematic diagram of a chip pin design scheme in the existing technology;
[0050] Figure 3 This is a schematic diagram of the chip pin design provided in an embodiment of this application;
[0051] Figure 4 This is a schematic diagram illustrating the arrangement of high-speed signal pins of a chip Tx according to an exemplary embodiment;
[0052] Figure 5This is a schematic diagram illustrating the arrangement of high-speed signal pins (Rx) of a chip according to an exemplary embodiment.
[0053] Figure 6 This is a schematic diagram illustrating the pin arrangement of a 12.8T bandwidth chip high-speed signal pins according to an exemplary embodiment;
[0054] Figure 7 This is a schematic diagram illustrating the arrangement of high-speed signal pins of a chip with a bandwidth of 25.6T according to an exemplary embodiment. Detailed Implementation
[0055] The following description and accompanying drawings fully illustrate specific embodiments of the invention to enable those skilled in the art to practice them.
[0056] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0057] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of systems and methods consistent with some aspects of the invention as detailed in the appended claims.
[0058] like Figure 2 As shown, traditional switch chips use a four-sided outgoing trace to reach the front port of the switch in order to reduce the density of traces on each side. However, as signal speeds increase, the longest trace away from the front port becomes the bottleneck for the signal integrity performance of the entire system. This necessitates the use of a PCB board with lower loss material, thereby increasing the system's manufacturing cost.
[0059] Based on this, this application breaks away from the constraints of traditional design and, based on a thorough study of system design, proposes a joint design scheme that combines the placement of SerDes IP modules on the die region (core region) with high-speed signal pins, such as... Figure 3 As shown, this application reserves space on one side when designing high-speed signal pins, which can effectively reduce trace loss under the same system design, making it possible to use cheaper materials for PCB board and helping to effectively save costs in the switch system.
[0060] The packaging design method for the high-speed signal pins of the switch chip provided in this application will be described in detail below with reference to the accompanying drawings.
[0061] This application provides a method for packaging high-speed signal pins of a switch chip, including: setting a Tx high-speed signal pin pair in an area outside the middle reserved space of the first, second, third, and fourth sides of the chip edge; setting an Rx high-speed signal pin pair in an area outside the middle reserved space of the first, second, third, and fourth sides of the chip edge; wherein the length of the middle reserved space is less than or equal to the length of the fourth side.
[0062] The high-speed signal pin packaging method provided in this application provides space on one side, which helps to effectively shorten the longest line length when constructing a switch chip. In one embodiment, high-speed signal pins can be set on the first, second, and third sides of the chip edge, with a reserved space in the middle of the fourth side. Alternatively, high-speed signal pins can be set only on the first, second, and third sides, with no high-speed signal pins on the entire fourth side. The reserved space on the fourth side can be the top, bottom, left, or right side of the chip. Since the chip can be flipped up, down, left, or right, this application does not limit which side the fourth side specifically refers to. It can be determined according to actual needs.
[0063] In one embodiment, the Tx high-speed signal pin pair and the Rx high-speed signal pin pair are located outside the left, right, and bottom edges of the chip, as well as the middle reserved space on the top edge. The upper reserved space is preferably located in the middle area of the top edge; its specific position and length can be determined according to actual needs, and this embodiment does not impose specific limitations.
[0064] like Figure 1 As shown, when the length of the reserved space is equal to the length of the fourth side, no high-speed signal pins are set on the entire fourth side, such as... Figure 1 As shown, the Tx high-speed signal pins are positioned on both sides and the bottom edge of the chip, and the Rx high-speed signal pins are also positioned on both sides and the bottom edge of the chip. The top edge is left unused.
[0065] In an optional embodiment, when arranging the Tx high-speed signal pins and Rx high-speed signal pins, the method further includes: placing the Rx high-speed signal pin pair inside the Tx high-speed signal pin pair, and placing all of the Tx high-speed signal pin pairs outside the Rx high-speed signal pin pair.
[0066] Alternatively, a first predetermined number of Tx high-speed signal pin pairs can be positioned outside the Rx high-speed signal pin pairs, and a second predetermined number of Tx high-speed signal pin pairs can be interspersed with the Rx high-speed signal pin pairs inside the first predetermined number of Tx high-speed signal pin pairs. The specific values of the first and second predetermined numbers are not specifically limited in this embodiment. In this embodiment, some Tx high-speed signal pins can be positioned outside, while other Tx high-speed signal pins can be interspersed with the Rx high-speed signal pins inside.
[0067] In an alternative embodiment, the Tx high-speed signal pin pair may be located inside the Rx high-speed signal pin pair, and all Rx high-speed signal pin pairs may be located outside the Tx high-speed signal pin pair.
[0068] Alternatively, a first predetermined number of Rx high-speed signal pin pairs can be positioned outside the Tx high-speed signal pin pairs, and a second predetermined number of Rx high-speed signal pin pairs can be interspersed with the Tx high-speed signal pin pairs inside the first predetermined number of Rx high-speed signal pin pairs. The specific values of the first and second predetermined numbers are not specifically limited in this embodiment. In this embodiment, some Rx high-speed signal pins can be positioned outside, while other Rx high-speed signal pins and Tx high-speed signal pins can be interspersed inside.
[0069] Furthermore, the number of Rx high-speed signal pin pairs and Tx high-speed signal pin pairs will be explained.
[0070] When the length of the reserved space in the middle is equal to the length of the fourth side, pins are only provided on the first, second, and third sides of the chip edge. In one embodiment, the first side is the right side of the chip, the second side is the bottom side of the chip, the third side is the left side of the chip, and the fourth side is the top side of the chip. Because the chip can also be flipped up, down, left, and right, this application does not limit which side the first, second, third, and fourth sides specifically refer to.
[0071] Specifically, when the number of high-speed signals at the switching port of the switching chip is x128 channels, 48 Tx high-speed signal pin pairs are set from bottom to top on the first and third sides of the chip edge, and 32 Tx high-speed signal pin pairs are set from any point in the middle of the preset range on the second side of the chip edge to the left and right.
[0072] When the number of high-speed signals at the switching port of the switching chip is x128 channels, it also includes 48 Rx high-speed signal pin pairs arranged from bottom to top on the first and third sides of the chip edge, and 32 Rx high-speed signal pin pairs arranged from any point in the middle of the preset range on the second side of the chip edge to the left and right.
[0073] In an exemplary scenario, the first side and the third side refer to the left and right sides. When setting high-speed signal pin pairs on the left and right sides, they should be arranged as close to the bottom as possible from bottom to top, leaving as much space as possible on the top side. When setting high-speed signal pin pairs on the bottom side, they should be arranged symmetrically to the left and right sides, starting from the middle point. Alternatively, they can be arranged to the left and right sides from any point within a preset range in the middle. The specific value of the middle range is not specifically limited in this application.
[0074] In an optional embodiment, when the length of the middle reserved space is equal to the length of the fourth side, the method further includes: when the number of high-speed signals of the switching port of the switching chip is x256 channels, 96 Tx high-speed signal pin pairs are respectively set from bottom to top on the first and third sides of the chip edge, and 64 Tx high-speed signal pin pairs are set from any point in the middle preset range on the second side of the chip edge to the left and right sides.
[0075] When the length of the reserved space in the middle is equal to the length of the fourth side, it also includes: when the number of high-speed signals of the switching port of the switching chip is x256 channels, 96 Rx high-speed signal pin pairs are set from bottom to top on the first and third sides of the chip edge, and 64 Rx high-speed signal pin pairs are set from any point in the middle preset range on the second side of the chip edge to the left and right sides.
[0076] When the number of high-speed signal pins increases, the setting principle remains unchanged. When setting high-speed signal pin pairs on the left and right sides, they should be set as close to the bottom as possible from bottom to top, leaving as much space as possible on the top side. When setting high-speed signal pin pairs on the bottom side, they should be set symmetrically to the left and right sides, starting from the middle point. Alternatively, they can be set to the left and right sides from any point within a preset range in the middle. The specific value of the middle range is not specifically limited in this application.
[0077] Furthermore, the distance between the pins is explained. Figure 6 This is a schematic diagram illustrating the arrangement of high-speed signal pins of a chip with a bandwidth of 12.8T or less, according to an exemplary embodiment. Figure 7 This is a schematic diagram illustrating the pin arrangement of a high-speed signal chip with a bandwidth of 25.6T or higher, according to an exemplary embodiment. Figure 6 and 7 As shown, both the Tx high-speed signal pin pairs and the Rx high-speed signal pin pairs are arranged in an equally spaced array. During arrangement, the Tx and Rx high-speed signal pin pairs should be arranged from bottom to top as much as possible, leaving as much space as possible at the top. They can also be arranged slightly towards the center, but when arranging them towards the center, care must be taken to maintain a certain distance from the core area. This bottom-up approach can further reduce the length of the system traces. Figure 4 This is a schematic diagram illustrating the arrangement of high-speed signal pins of a chip Tx according to an exemplary embodiment; Figure 5 This is a schematic diagram illustrating the arrangement of high-speed signal pins (Rx) of a chip according to an exemplary embodiment.
[0078] like Figure 4 As shown, the P and N pins of each pair of Tx high-speed signals are adjacent and separated by a preset first distance; the shortest distance between the P and N pins of one pair of Tx high-speed signals and the P and N pins of another pair of Tx high-speed signals is a preset second distance; the shortest distance between the P and N pins of one pair of Tx high-speed signals and the P and N pins of another pair of Rx high-speed signals is a preset third distance.
[0079] Specifically, when the highest baud rate of a single channel is less than or equal to 29 Gsym / s, the minimum preset second distance is √2 times the minimum preset first distance; when the highest baud rate of a single channel is greater than 29 Gsym / s, the minimum preset second distance is twice the minimum preset first distance. The minimum preset third distance is twice the minimum preset first distance.
[0080] The preset first distance can be 1 mm. This application does not limit the specific value of the preset first distance and can set it according to the actual situation. In an exemplary scenario, the preset second distance is 2 times or √2 times the preset first distance. When the bandwidth is 3.2T or 12.8T, the second distance is √2 times the preset first distance. When the bandwidth is 25.6T, the second distance is 2 times the preset first distance. The preset third distance is 2 times the preset first distance.
[0081] like Figure 5 As shown, the P and N pins of each pair of Rx high-speed signals are adjacent and separated by a preset first distance; the shortest distance between the P and N pins of one pair of Rx high-speed signals and the P and N pins of another pair of Rx high-speed signals is a preset second distance; wherein the preset second distance is at least twice the preset first distance. A return ground via must be present in between to isolate the two high-speed signal pin pairs from different Rx signals. Similarly, the preset first distance can be 1 mm; this application does not limit the specific value of the preset first distance and it can be set according to actual conditions.
[0082] In one alternative embodiment, such as Figure 1 As shown, it also includes setting a preset number of SerDesIP modules within the core region, which is connected via metal bumps and a package layer. A combined design scheme integrating the placement of SerDes IP modules on the die region (core region) and high-speed signal pins is proposed, which can effectively reduce trace losses in equivalent system designs.
[0083] In one possible implementation, when the number of high-speed signal channels on the switch chip's switching ports is x128, the number of SerDes IP modules in the kernel region is determined according to the following formula:
[0084] 4X + 8Y = 128
[0085] Where X represents the number of x4-channel SerDes IP modules, Y represents the number of x8-channel SerDes IP modules, the sum of X and Y is even, and X and Y are both greater than or equal to 0, and are integers greater than or equal to 0. Multiple SerDes IP modules are positioned on the first, second, third, and fourth sides of the kernel region, symmetrically about the central axis of the kernel region.
[0086] In an exemplary scenario, when the number of high-speed signal channels on the switch chip's switching ports is x128, only x4-channel SerDes IP modules need to be configured in the kernel region. In this case, a total of 32 x4-channel SerDes IP modules are required. These 32 x4-channel SerDes IP modules are located on the first, second, third, and fourth sides of the kernel region, and are symmetrical about the central axis. For example... Figure 1 As shown, four SerDes IP modules can be placed on the top, six on the bottom, and then eleven SerDes IP modules can be placed on the left and right sides respectively. Each Tx high-speed signal pin pair corresponds to one Tx module; therefore, the left side is as follows... Figure 1 There are 48 / 4 = 12 Tx modules, and the corresponding 4 Rx high-speed signal pin pairs constitute one Rx module. Therefore, as shown on the left... Figure 1 There are 48 / 4 = 12 Rx modules. Below that, there are 32 / 4 = 8 Tx modules and Rx modules respectively.
[0087] In an exemplary scenario, when the number of high-speed signal channels on the switch chip's switching ports is x128, only x8-channel SerDes IP modules need to be configured in the kernel region. In this case, a total of 16 x8-channel SerDes IP modules are required. The 16 x8-channel SerDes IP modules are located on the first, second, third, and fourth sides of the kernel region and are symmetrical about the central axis.
[0088] In an exemplary scenario, when the number of high-speed signal channels on the switch chip's switching ports is x128, x8-channel SerDes IP modules and x4-channel SerDes IP modules can be configured in the kernel area. In this case, the specific number of these modules is not limited, as long as the formula described above is satisfied. For example, two x8-channel SerDes IP modules and 28 x4-channel SerDes IP modules can be configured.
[0089] In an optional embodiment, when the number of high-speed signal channels on the switch chip's switching ports is x256, the number of SerDes IP modules in the kernel region is determined according to the following formula:
[0090] 4X + 8Y = 256
[0091] Where X represents the number of SerDes IP modules in x4 channels, Y represents the number of SerDes IP modules in x8 channels, the sum of X and Y is even, and X and Y are greater than or equal to 0, and are integers greater than or equal to 0. Multiple SerDes IP modules are set on the first, second, third and fourth sides of the kernel region, and are symmetrical about the central axis of the kernel region.
[0092] In an exemplary scenario, when the number of high-speed signal channels on the switch chip's switching ports is x256, only x4-channel SerDes IP modules need to be configured in the kernel region. In this case, a total of 64 x4-channel SerDes IP modules are required. The 64 x4-channel SerDes IP modules are located on the first, second, third, and fourth sides of the kernel region and are symmetrical about the central axis.
[0093] In an exemplary scenario, when the number of high-speed signal channels on the switch chip's switching ports is x256, it is possible to configure only x8-channel SerDes IP modules in the kernel region. In this case, a total of 32 x8-channel SerDes IP modules are required. The 32 x8-channel SerDes IP modules are located on the first, second, third, and fourth sides of the kernel region and are symmetrical about the central axis.
[0094] In an exemplary scenario, when the number of high-speed signal channels on the switch chip's switching ports is x256, x8-channel SerDes IP modules and x4-channel SerDes IP modules can be configured in the kernel area. The specific number of these modules is not limited, as long as the formula described above is satisfied. For example, 10 x8-channel SerDes IP modules or 44 x4-channel SerDes IP modules can be configured.
[0095] Secondly, embodiments of this application provide a switch chip, including:
[0096] Tx high-speed signal pin pair and Rx high-speed signal pin pair;
[0097] The Tx high-speed signal pin pair and the Rx high-speed signal pin pair adopt the high-speed signal pin packaging method provided in the above embodiments.
[0098] Specifically, a switch chip includes:
[0099] The Tx high-speed signal pin pair is located outside the reserved space in the middle of the first, second, third, and fourth sides of the chip edge;
[0100] The Rx high-speed signal pin pair is located outside the reserved space in the middle of the first, second, third, and fourth sides of the chip edge;
[0101] The length of the reserved space in the middle is less than or equal to the length of the fourth side.
[0102] In an optional embodiment, it further includes:
[0103] The Rx high-speed signal pin pair is located inside the Tx high-speed signal pin pair, and all Tx high-speed signal pin pairs are located outside the Rx high-speed signal pin pair; or, a first number of Tx high-speed signal pin pairs are located outside the Rx high-speed signal pin pair, and a second number of Tx high-speed signal pin pairs are interspersed with the Rx high-speed signal pin pairs inside the first number of Tx high-speed signal pin pairs.
[0104] In an optional embodiment, it further includes:
[0105] The Tx high-speed signal pin pair is located inside the Rx high-speed signal pin pair, and all Rx high-speed signal pin pairs are located outside the Tx high-speed signal pin pair; or, a first number of Rx high-speed signal pin pairs are located outside the Tx high-speed signal pin pair, and a second number of Rx high-speed signal pin pairs are interspersed with the Tx high-speed signal pin pairs inside the first number of Rx high-speed signal pin pairs.
[0106] In an optional embodiment, the method further includes: when the number of high-speed signals at the switching port of the switching chip is x128 channels, 48 Tx high-speed signal pin pairs are arranged from bottom to top on the first and third sides of the chip edge, and 32 Tx high-speed signal pin pairs are arranged from any point in the middle of the preset range on the second side of the chip edge to the left and right sides.
[0107] In an optional embodiment, the method further includes: when the number of high-speed signals at the switching port of the switching chip is x256 channels, 96 Tx high-speed signal pin pairs are arranged from bottom to top on the first and third sides of the chip edge, and 64 Tx high-speed signal pin pairs are arranged from any point in the middle of the preset range on the second side of the chip edge to the left and right sides.
[0108] In an optional embodiment, the method further includes: when the number of high-speed signals at the switching port of the switching chip is x128 channels, 48 Rx high-speed signal pin pairs are arranged from bottom to top on the first and third sides of the chip edge, and 32 Rx high-speed signal pin pairs are arranged from any point in the middle of the preset range on the second side of the chip edge to the left and right sides.
[0109] In an optional embodiment, the method further includes: when the number of high-speed signals at the switching port of the switching chip is x256 channels, 96 Rx high-speed signal pin pairs are disposed on the first and third sides of the chip edge, and 64 Rx high-speed signal pin pairs are disposed on the second side of the chip edge from any point within a preset range in the middle to the left and right sides.
[0110] In an optional embodiment, the P pins and N pins of each pair of Tx high-speed signals are adjacent and separated by a preset first distance; the shortest distance between the P pins and N pins of one pair of Tx high-speed signals and the P pins and N pins of another pair of Tx high-speed signals is a preset second distance; the shortest distance between the P pins and N pins of one pair of Tx high-speed signals and the P pins and N pins of another pair of Rx high-speed signals is a preset third distance; wherein, when the highest baud rate of a single channel is less than or equal to 29 Gsym / s, the preset second distance is at least √2 times the preset first distance; when the highest baud rate of a single channel is greater than 29 Gsym / s, the preset second distance is at least twice the preset first distance; and the preset third distance is at least twice the preset first distance.
[0111] In an optional embodiment, the P pins and N pins of each pair of Rx high-speed signals are adjacent and separated by a preset first distance; the shortest distance between the P pins and N pins of one pair of Rx high-speed signals and the P pins and N pins of another pair of Rx high-speed signals is a preset second distance; wherein the preset second distance is at least twice the preset first distance.
[0112] In an optional embodiment, the chip further includes a kernel region, the number of SerDes IP modules in the kernel region being determined according to the following formula when the number of high-speed signal channels on the switch chip's switching ports is x128:
[0113] 4X + 8Y = 128
[0114] Where X represents the number of SerDes IP modules with x4 channels, Y represents the number of SerDes IP modules with x8 channels, the sum of X and Y is even, and X and Y are greater than or equal to 0;
[0115] Multiple SerDes IP modules are located on the first, second, third, and fourth sides of the kernel region, and are symmetrical about the central axis of the kernel region.
[0116] In an optional embodiment, when the number of high-speed signal channels on the switch chip's switching ports is x256, the number of SerDes IP modules in the kernel region is determined according to the following formula:
[0117] 4X + 8Y = 256
[0118] Where X represents the number of SerDes IP modules with x4 channels, Y represents the number of SerDes IP modules with x8 channels, the sum of X and Y is even, and X and Y are greater than or equal to 0;
[0119] Multiple SerDes IP modules are located on the first, second, third, and fourth sides of the kernel region, and are symmetrical about the central axis of the kernel region.
[0120] The switch chip and the packaging method of the switch chip provided in this application belong to the same inventive concept. For detailed technical features and implementation methods, please refer to the method embodiment, which will not be repeated here. The two have the same technical effect.
[0121] The switch chip provided in this application breaks away from the constraints of traditional design by designing high-speed signal pin pairs along the first, second, and third sides of the chip package and reserving space on the fourth side. Based on a thorough study of system design, a joint design scheme combining the placement of SerDes IP modules on the core area and high-speed signal pin pairs is designed. This can effectively reduce trace losses under the same system design, making it possible to use cheaper materials for PCB boards and helping to effectively save costs in the switch system.
[0122] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0123] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.
Claims
1. A method for packaging high-speed signal pins of a switch chip, characterized in that, include: The Tx high-speed signal pin pair is located outside the reserved space in the middle of the first, second, third, and fourth sides of the chip edge; The Rx high-speed signal pin pair is located outside the reserved space in the middle of the first, second, third, and fourth sides of the chip edge; wherein the length of the reserved space in the middle is less than or equal to the length of the fourth side. It also includes: placing the Rx high-speed signal pin pair inside the Tx high-speed signal pin pair, and placing all the Tx high-speed signal pin pairs outside the Rx high-speed signal pin pair; or, placing a preset first number of Tx high-speed signal pin pairs outside the Rx high-speed signal pin pair, and interleaving a preset second number of Tx high-speed signal pin pairs with the Rx high-speed signal pin pairs inside the first number of Tx high-speed signal pin pairs; When the number of high-speed signal channels on the switch chip's switching ports is x128, the number of SerDes IP modules in the kernel area is determined according to the following formula: Where X represents the number of x4 channel SerDes IP modules, Y represents the number of x8 channel SerDes IP modules, the sum of X and Y is even, and X and Y are greater than or equal to 0; the multiple SerDes IP modules are set on the first, second, third and fourth sides of the kernel region, and are symmetrical about the central axis of the kernel region.
2. The method according to claim 1, characterized in that, Also includes: The Tx high-speed signal pin pair is positioned inside the Rx high-speed signal pin pair, and all Rx high-speed signal pin pairs are located outside the Tx high-speed signal pin pair; or, A first number of Rx high-speed signal pin pairs are arranged outside the Tx high-speed signal pin pairs, and a second number of Rx high-speed signal pin pairs are interspersed with the Tx high-speed signal pin pairs inside the first number of Rx high-speed signal pin pairs.
3. The method according to claim 1, characterized in that, When the length of the intermediate reserved space is equal to the length of the fourth side, it also includes: When the number of high-speed signals at the switching port of the switching chip is x128 channels, 48 Tx high-speed signal pin pairs are set from bottom to top on the first and third sides of the chip edge, and 32 Tx high-speed signal pin pairs are set from any point in the middle of the preset range on the second side of the chip edge to the left and right.
4. The method according to claim 1, characterized in that, When the length of the intermediate reserved space is equal to the length of the fourth side, it also includes: When the number of high-speed signals on the switching port of the switching chip is x256 channels, 96 Tx high-speed signal pin pairs are set from bottom to top on the first and third sides of the chip edge, and 64 Tx high-speed signal pin pairs are set from any point in the middle of the preset range on the second side of the chip edge to the left and right.
5. The method according to claim 1, characterized in that, When the length of the intermediate reserved space is equal to the length of the fourth side, it also includes: When the number of high-speed signals at the switching port of the switching chip is x128 channels, 48 Rx high-speed signal pin pairs are set from bottom to top on the first and third sides of the chip edge, and 32 Rx high-speed signal pin pairs are set from any point in the middle of the preset range on the second side of the chip edge to the left and right.
6. The method according to claim 1, characterized in that, When the length of the intermediate reserved space is equal to the length of the fourth side, it also includes: When the number of high-speed signals on the switching chip's switching port is x256 channels, 96 Rx high-speed signal pin pairs are set from bottom to top on the first and third sides of the chip edge, and 64 Rx high-speed signal pin pairs are set from any point in the middle of the preset range on the second side of the chip edge to the left and right.
7. The method according to any one of claims 1-6, characterized in that, The P pin and N pin of each pair of Tx high-speed signals are adjacent and separated by a preset first distance; The shortest distance between the P and N pins of one pair of Tx high-speed signals and the P and N pins of another pair of Tx high-speed signals is a preset second distance; The shortest distance between the P and N pins of a pair of Tx high-speed signals and the P and N pins of another pair of Rx high-speed signals is a preset third distance; Wherein, when the highest baud rate of a single channel is less than or equal to 29Gsym / s, the minimum preset second distance is √2 times the preset first distance; when the highest baud rate of a single channel is greater than 29Gsym / s, the minimum preset second distance is twice the preset first distance. The minimum preset third distance is twice the preset first distance.
8. The method according to any one of claims 1-6, characterized in that, The P and N pins of each pair of Rx high-speed signals are adjacent and separated by a preset first distance; The shortest distance between the P and N pins of one pair of Rx high-speed signals and the P and N pins of another pair of Rx high-speed signals is a preset second distance; The minimum of the preset second distance is twice the preset first distance.
9. The method according to claim 1, characterized in that, Also includes: When the number of high-speed signal channels on the switch chip's switching ports is x256, the number of SerDes IP modules in the kernel area is determined according to the following formula: Where X represents the number of x4 channel SerDes IP modules, Y represents the number of x8 channel SerDes IP modules, the sum of X and Y is even, and X and Y are greater than or equal to 0; Multiple SerDes IP modules are positioned on the first, second, third, and fourth sides of the kernel region, and are symmetrical about the central axis of the kernel region.
10. A switch chip, characterized in that, include: Tx high-speed signal pin pair and Rx high-speed signal pin pair; The Tx high-speed signal pin pair and the Rx high-speed signal pin pair adopt any one of the high-speed signal pin packaging methods of claims 1-9.