A method for solving shallow erase in SSD master control and SSD unit

Abstract

The present invention designs an SSD unit. The unit receives partially written blocks that need to be erased during the operation of the SSD through a NAND shallow erase information unit and a NAND shallow erase operation unit. The unit writes the partially written blocks that need to be erased due to various reasons during the operation of the SSD. After determination, the unit writes or erases the blocks to complete the shallow erase operation. In this way, the software algorithm only needs to write the blocks that need to be shallow erased into the information unit FIFO of the hardware module, thereby reducing the involvement and complexity of software design and achieving the effect of using a small amount of hardware resources to complete the design purpose.

Description

Technical Field

[0001] The present invention relates to the field of SSD hardware module design, and in particular to a method for solving shallow erasure in an SSD master control and an SSD unit. Background Art

[0002] A shallow erase operation is an erroneous erase of a NAND block. This occurs when a block is not fully written. Because the block is not fully written, the memory cells within the written word lines (WordLines) and the memory cells within the unwritten word lines (WordLines) are in an unstable state. Performing an erase operation at this time will cause physical damage to these word lines. If these shallow erases accumulate a certain number of times, the block will be irreparably damaged, manifesting as errors exceeding the correctable error range during reads.

[0003] During normal operation of the SSD, many incomplete blocks are inevitable. The existing solution is to have the software fill the blocks during background recycling. This consumes a lot of software resources, but the filling and erasing operations do not actually require the software to constantly schedule and monitor their status. Summary of the Invention

[0004] The purpose of the present invention is to provide a dedicated hardware module to perform a series of operations such as filling and erasing, so as to solve the hidden danger of shallow erasing by hardware.

[0005] To achieve the above-mentioned purpose, the present invention is implemented through the following technical solutions:

[0006] A method for solving shallow erase in an SSD master controller includes the following steps:

[0007] (1) Write the Block information that needs to be shallowly erased during the operation of the SSD into the NAND shallow erase information unit, and start the shallow erase operation unit to read the Block information;

[0008] (2) The NAND shallow erase operation unit polls the block information in the NAND shallow erase information unit and reads it as long as there is information;

[0009] (3) The NAND shallow erase operation unit organizes the information of the block and determines whether to generate a write operation or an erase operation. After generating a response command, it writes the command into the command buffer of the corresponding channel;

[0010] (4) The NAND shallow erase operation unit monitors the status of the operation commands sent to each channel in real time and updates the status to the NAND information unit in real time;

[0011] (5) If the write operation is completed, the NAND shallow erase operation unit determines whether the operation status is successful. If it fails, it performs the write operation again. If it succeeds, it calculates whether the block has been fully written. If the block is fully written, the NAND shallow erase operation unit generates an erase command and stores it in the command buffer of the corresponding channel;

[0012] (6) If the erase operation is completed, the NAND shallow erase operation unit determines whether the operation status is successful. If successful, the erased block is placed in the system's list of blocks to be used. If failed, another erase operation is performed.

[0013] Block information includes channel number, CE, LUN, number of written word lines, etc.

[0014] The conditions for determining whether to generate a write operation or an erase operation are as follows: the number of word lines is analyzed to determine whether to generate a write operation or an erase operation. When the number of written word lines is equal to the total number of word lines in the block, only an erase operation is required; otherwise, a write operation must be performed first.

[0015] The NAND shallow erase operation unit reads multiple blocks of information located in different LUNs at the same time, and processes up to 64 blocks in parallel.

[0016] The present invention also discloses an SSD unit for solving shallow erasure in an SSD master control, comprising:

[0017] NAND shallow erase information unit, used to receive the partially written blocks that need to be erased during SSD operation;

[0018] The NAND shallow erase operation unit is used to generate corresponding NAND operation commands according to the Block information and write them into the corresponding command buffer, while detecting the operation status of each command.

[0019] The NAND shallow erase information unit includes a FIFO and several registers, including a start register and a status register. The FIFO is used to write block information. The start register is used to inform the NAND shallow erase operation unit that it can read the block information to be processed from the FIFO. The status register is used to display the block information currently being processed, the corresponding operation, and the operation status.

[0020] The advantages of the present invention lie in the design of a hardware module within the main control system that handles shallow erase blocks independently of software. Software designers configure hardware unit registers, and software algorithms simply write blocks requiring shallow erase into the hardware module's information unit FIFO. Hardware then completes tasks such as filling and erasing partially filled blocks, thus preventing shallow erase operations. This reduces software design involvement and complexity, achieving the desired design objectives with minimal hardware resources. By analyzing NAND management tasks within the SSD layer by layer, the present invention separates weakly coupled operations and has them completed independently by hardware units. This leverages the combined strengths of hardware and software, freeing up main control resources and simplifying software design. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a flow chart of the method of Example 1 of the present invention;

[0022] Figure 2 This is a schematic diagram of the SSD unit structure according to embodiment 2 of the present invention. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0024] Example 1

[0025] The present invention discloses a method for solving shallow erasure in SSD master control. Figure 1 flow chart.

[0026] First, during the operation of the SSD, a block that is not fully written but needs to be erased, i.e., a shallow erase block, is generated. The system writes the block information into the NAND shallow erase information unit in the shallow erase module and sets the start register in the unit to 1. When the start register in the NAND shallow erase information unit is set to 1, it indicates that a block that needs to be shallow erased is generated in the SSD system, and the NAND shallow erase operation unit reads the block information in the information unit FIFO.

[0027] Second, the NAND shallow erase operation unit starts working and keeps polling the FIFO of the information unit, reading as long as there is information.

[0028] Third, the NAND shallow erase operation unit organizes block information: channel number, CE, LUN, block, and the number of written wordlines. This unit analyzes the number of wordlines and determines whether to generate a write or erase operation. When the number of written wordlines equals the total number of wordlines in the block, only an erase operation is required. After generating the corresponding command, it is written to the command buffer of the corresponding channel.

[0029] Fourth, the NAND shallow erase operation unit detects the status of the operation command sent to each channel in real time, and updates the status to the status register of the information unit in real time.

[0030] Fifth, if the write operation is completed, the NAND shallow erase operation unit calculates whether the block has been fully written based on the operation status. If it succeeds, it calculates whether the block has been fully written. If it fails, it performs another write operation.

[0031] Sixth, if the block is full, the next step is to perform an erase operation. The NAND shallow erase operation unit generates an erase command and stores it in the command buffer of the corresponding channel.

[0032] Seventh, if the erase operation is completed, the NAND shallow erase operation unit determines the operation status. If successful, the erased block is placed in the system's list of blocks to be used; if unsuccessful, the erase operation is performed again.

[0033] Example 2

[0034] The method introduced in the present invention includes two main functional units, namely a NAND shallow erase information unit and a NAND shallow erase operation unit.

[0035] Among them, the main function of the NAND shallow erase information unit is to receive the partially written blocks that need to be erased during the operation of the SSD; this unit mainly consists of a FIFO and several registers.

[0036] During SSD operation, blocks that need to be erased but are not fully written may occur due to various reasons. Information about these partially written blocks, such as the channel number, CE, LUN, and number of occupied word lines, is written to the FIFO of the NAND shallow erase information unit. The registers primarily include a start register and a status register. The start register tells the NAND shallow erase operation unit to read the block information to be processed from the FIFO. The status register displays the block information currently being processed, the corresponding operation, and the operation status (success or failure).

[0037] The main function of the NAND shallow erase operation unit is to generate corresponding NAND operation commands according to the Block information, write these commands into the corresponding command buffer, and detect the operation status of each command.

[0038] When the start register in the NAND shallow erase information unit is set to 1, the NAND shallow erase operation unit reads the block information in the information unit FIFO and determines whether the block requires a write or erase operation based on the number of occupied word lines in the information. The NAND shallow erase operation unit simultaneously reads multiple block information located in different LUNs, processing up to 64 blocks in parallel. The unit detects each generated write or erase operation. If it fails, it executes the same operation again. If it succeeds, it proceeds to the next operation based on the block status. For example, if the block is full, an erase operation is performed. If the block is successfully erased, it is placed in the system's list of blocks to be used.

[0039] The system can detect the real-time status of the shallow erase operation by reading the NAND shallow erase information unit status register. To solve the shallow erase hardware unit design, it only needs to write the block information that needs to be shallow erased into the hardware unit module at the software algorithm level, which simplifies the software design and SSD master control resources.

[0040] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for solving shallow erase in SSD master controller, characterized in that: Including steps: (1) Write the Block information that needs to be shallowly erased during the operation of the SSD into the NAND shallow erase information unit, and start the shallow erase operation unit to read the Block information; (2) The NAND shallow erase operation unit polls the block information in the NAND shallow erase information unit and reads it as long as there is information; (3) The NAND shallow erase operation unit organizes the information of the block and determines whether to generate a write operation or an erase operation. After generating a response command, it writes the command into the command buffer of the corresponding channel; (4) The NAND shallow erase operation unit monitors the status of the operation commands sent to each channel in real time and updates the status to the NAND information unit in real time; (5) If the write operation is completed, the NAND shallow erase operation unit determines whether the operation status is successful. If it fails, it performs the write operation again. If it succeeds, it calculates whether the block has been fully written. If the block is fully written, the NAND shallow erase operation unit generates an erase command and stores it in the command buffer of the corresponding channel; (6) If the erase operation is completed, the NAND shallow erase operation unit determines whether the operation status is successful. If successful, the erased block is placed in the system's waiting block list. If failed, another erase operation is performed. NAND shallow erase information unit, used to receive the partially written blocks that need to be erased during SSD operation; NAND shallow erase operation unit, used to generate corresponding NAND operation commands according to Block information and write them into the corresponding command buffer, while detecting the operation status of each command; The NAND shallow erase information unit includes a FIFO and several registers, wherein the registers include a start register and a status register. The FIFO is used to write block information, the start register is used to inform the NAND shallow erase operation unit to read the block information to be processed from the FIFO, and the status register is used to display the block information currently being processed, the corresponding operation, and the operation status.

2. The method for solving shallow erase in SSD master controller according to claim 1, characterized in that: The block information includes the number of written word lines.

3. The method for solving shallow erase in SSD master controller according to claim 2, characterized in that: The condition for determining whether to generate a write operation or an erase operation is: analyzing the number of word lines to determine whether to generate a write operation or an erase operation; when the number of written word lines is equal to the total number of word lines in the block, only an erase operation is required; otherwise, a write operation must be performed first.

4. The method for solving shallow erase in SSD master controller according to claim 1, characterized in that: The NAND shallow erase operation unit reads multiple blocks of information located in different LUNs at the same time, and processes up to 64 blocks in parallel.

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