A switchable precision floating point multiplier-adder

Abstract

The application discloses a switchable precision floating-point multiplier-adder, which comprises a four-stage pipeline, a first-stage pipeline, a second-stage pipeline, a third-stage pipeline and a fourth-stage pipeline; the first-stage pipeline comprises a distribution processing module, a multiplier array module, an adder array adding module and an exponent comparison module; the second-stage pipeline comprises an exponent difference module, an alignment shift module, an addition tree module and a compression module; the third-stage pipeline comprises a leading zero prediction module, a leading zero coding module, a sign prediction module and an advance calculation module; and the fourth-stage pipeline comprises a sum and rejection module and an exponent normalization module. The floating-point multiplier-adder combines double-precision multiplication and addition to complete double-precision floating-point operation in the form of A+BxC, and the combination can greatly reuse the components in the multiplier-adder compared with a simple multiplier-adder combined with an adder. The application can be widely applied in the field of hardware operation devices.

Description

Technical Field

[0001] This invention relates to the field of hardware computing devices, and more particularly to a floating-point multiply-accumulator with switchable precision. Background Technology

[0002] Existing polynomial floating-point multiply-accumulators generally have similar structures. They typically multiply corresponding mantissas, add corresponding exponents, and compare them to obtain the maximum exponent sum. The difference between each exponent sum and the maximum exponent sum is then calculated to obtain the exponent difference. The mantissa products are then aligned and shifted according to the corresponding exponent differences. An adder tree composed of 3:2 or 4:2 compressors is used to compress all mantissas, resulting in two rows of partial products: `sum` and `carry`. These two partial products are then added together by an adder to obtain a result. Since this involves adding and subtracting multiple numbers, the final result is not standardized (i.e., the decimal point is not necessarily after the first significant digit). Therefore, leading zero detection is needed, i.e., calculating how many zeros precede the first significant digit and standardizing it by left shifting. To reduce critical timing paths, leading zero prediction is usually performed on `sum` and `carry` before the result is obtained. Prediction and addition are performed simultaneously, allowing the result to be shifted immediately after calculation, or the result can be shifted first based on the prediction result before addition. The final result is then standardized. Finally, the result is rounded down. Since rounding may result in a carry-over to the highest bit, it needs to be shifted and standardized at the end.

[0003] Configurable precision floating-point multipliers and accumulators are designed to reuse the functionality of device modules. Since the method for multiplying and adding floating-point numbers of different precisions is the same, the same module can be configured to perform floating-point operations of different precisions based on the desired precision mode. However, the bit width of the corresponding data segments differs. Therefore, to adapt to different bit widths and achieve a higher reuse rate (i.e., high utilization of the same module across different precision modes), module adjustments are necessary. Since the mantissa multiplier is the most resource-intensive module in the floating-point multiplier and accumulator, adjustments are focused on the multiplier. A minimum redundancy mantissa partitioning method is used to subdivide the mantissa portion: since half-precision mantissas have 11 bits, single-precision mantissas have 24 bits, and double-precision mantissas have 53 bits, the mantissa of single-precision floating-point numbers is divided into two 12-bit data segments, and the mantissa of double-precision numbers is divided into one 5-bit and four 12-bit data segments. This partitioning allows multiple low-precision multipliers to be combined into a high-precision multiplier. The drawback of existing technology is that double precision only performs multiplication and not addition. Therefore, when this multiply-accumulator is used in high-performance computing or neural network inference, it must be paired with a double precision adder. Secondly, double precision requires two cycles to complete one multiplication, which is slower than single precision and half precision. In addition, some components only operate in one cycle, such as leading zero encoding. In the first clock cycle, the low data segments of sum and carry are calculated, and leading zero prediction is meaningless. Prediction can only begin after the high bits of sum and carry are calculated in the second clock cycle. Summary of the Invention

[0004] In order to at least partially solve one of the technical problems existing in the prior art, the present invention aims to provide a floating-point multiply-accumulator with switchable precision.

[0005] The technical solution adopted in this invention is:

[0006] A switchable precision floating-point multiply-accumulator includes a four-stage pipeline:

[0007] The first-stage pipeline includes an allocation processing module, a multiplier array module, an adder array summing module, and an exponent comparison module. The allocation processing module allocates the input data to obtain n pairs of mantissas, which are then fed into the multiplier array module. The multiplier array module multiplies the n pairs of mantissas to obtain n partial products of mantissas. The exponent pairs in the input data are fed into the adder array summing module to obtain multiple exponent sums, which are then fed into the exponent comparison module to obtain the maximum exponent sum.

[0008] The second-stage pipeline includes an exponent difference module, an alignment and shift module, an addition tree module, and a compression module. The exponent difference module is used to subtract the sum of the largest exponent from each exponent to obtain the exponent difference. The alignment and shift module is used to align and shift the n mantissa partial products obtained by the multiplier array module according to the exponent difference. After the n partial products are shifted, they are compressed into two rows of numbers by the addition tree module. The compression module is used to further process these two rows of numbers to obtain one row of sum data and one row of carry data.

[0009] The third-stage pipeline includes a leading zero prediction module, a leading zero encoding module, a sign prediction module, and an advance calculation module. The leading zero prediction module obtains a leading zero sequence based on the sum and carry data, and the leading zero encoding module encodes the number of leading zeros in the leading zero sequence. The advance calculation module performs calculations on the sum and carry data to obtain a carry propagation signal p and a carry generation signal g. The sign prediction module predicts whether the final calculation result is positive or negative and feeds the prediction result back to the advance calculation module.

[0010] The fourth-stage pipeline includes an addition and rounding module and an exponent standardization module; the addition and rounding module is used to perform addition calculations based on the carry signal and to round the calculation results; the exponent standardization module is used to perform exponent standardization.

[0011] Furthermore, the input data includes two 320-bit data inputs in1 and in2, and a 2-bit mode input mode;

[0012] If it is in 00 mode, the allocation processing module will interpret the data as a 20-pair precision floating-point number;

[0013] If it is in 01 mode, the allocation processing module interprets the lower 160 bits of the two data as 5 pairs of single-precision floating-point numbers;

[0014] In mode 10, the allocation processing module interprets the data as three double-precision floating-point numbers A, B, and C; the multiplier array module multiplies double-precision floating-point numbers B and C, with double-precision floating-point number A as the addend; the first-stage pipeline also includes an exponent calculation module and a mantissa equalization shift module; the exponent calculation module is used to calculate the exponent difference d, and the calculation formula is as follows:

[0015]

[0016] In the formula, EA, EB, and EC are the exponents of the double-precision floating-point numbers A, B, and C, respectively.

[0017] The mantissa equal shift module is used to equal shift the mantissa of the double-precision floating-point number A according to the exponent difference d after inverting the mantissa.

[0018] Furthermore, the compression module further processes the two lines of data in the following manner:

[0019] If it is in 10 mode, the two rows of numbers and the mantissa of the double-precision floating-point number A after shifting are input into a 3:2 compressor for further compression, resulting in one row of sum data and one row of carry data.

[0020] In other modes, the mantissa of the double-precision floating-point number A is set to 0, and then compressed using a 3:2 compressor to obtain one row of sum data and one row of carry data.

[0021] Furthermore, the addition tree module includes six 48-bit 4:2 compressors and six 48-bit 3:2 compressors;

[0022] The alignment shift module is implemented using a 48-bit shifter.

[0023] Furthermore, the sign prediction module is used to determine whether the final mantissa result is positive or negative;

[0024] In double-precision mode, since the mantissa of A is inverted and the result of B multiplied by the mantissa of C is positive, the only possible case for the mantissa result to be negative is when the exponent difference d is greater than 0. When the exponent difference d is greater than 2, it is definitely negative. When d = 0 or 1, due to the possibility of overflow when adding the mantissas, it may not be negative. In this case, it is necessary to compare the sum data and the carry data.

[0025] For single-precision and half-precision, directly compare the sum data and carry data.

[0026] Furthermore, the exponent comparison module selects the corresponding input according to the mode. In double precision mode, S and C are selected to be input in segments of 6 bits each, resulting in 18 comparison results. These results are then input into the second-stage comparator to obtain the final comparison size. Here, S represents the compressed sum and C represents the compressed carry.

[0027] Furthermore, the leading zero prediction module performs prediction calculations using the following formula:

[0028]

[0029] in, This represents the predicted sequence of leading zeros; It is the XOR of the sum and carry data, representing carry propagation; It is a bitwise AND operation between the sum and carry data to indicate the carry-out. It is a bitwise OR of the sum and carry data, representing that both are 0.

[0030] Furthermore, the adder in the addition and rounding module is a square root adder, which is composed of multiple carry-selection adders cascaded together, and the bit width of each carry-selection adder increases progressively.

[0031] The rounding unit in the addition and rounding module determines the numbers Rd and Rd1 to be added to the rounding position R based on the sticky bit and the rounding mode.

[0032] Furthermore, the index standardization module performs index standardization in the following manner:

[0033] The exponents are added directly using the IEEE 754 offset code format. Therefore, for double-precision mode, subtract 1023; for single-precision mode, subtract 127; and for half-precision mode, subtract 15.

[0034] Furthermore, since half-precision and single-precision involve multiplying and adding multiple numbers, the decimal point is not located between the highest and second-highest digits of the mantissa. To move the decimal point to that position, the exponent plus the corresponding number of bits to be moved is required.

[0035] Finally, the mantissa of the leading zero is normalized by shifting the exponent by subtracting the corresponding shift number.

[0036] Furthermore, the multiplier array module includes The multiplier adds a positive or negative signal to the result encoding on the basis of the original common encoding, so that it can be inverted according to the positive or negative sign of the calculation result.

[0037] The beneficial effects of the present invention are: the floating-point multiply-accumulator of the present invention combines double-precision multiplication and addition to complete double-precision floating-point operations of the form A+B×C. Compared with a simple multiply-accumulator paired with an adder, this combination can reuse the components in the multiply-accumulator more. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a diagram of the compressor structure;

[0040] Figure 2 This is a schematic diagram of the improved Booth coding process.

[0041] Figure 3 This is an overall structural diagram of a switchable precision floating-point multiplier-accumulator according to an embodiment of the present invention;

[0042] Figure 4 This is an addition tree structure diagram in an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of the double-precision mode of the addition tree in an embodiment of the present invention;

[0044] Figure 6 This is a structural diagram of the index comparison module in an embodiment of the present invention;

[0045] Figure 7 This is a structural diagram of the addition and rejection module in an embodiment of the present invention;

[0046] Figure 8 This is a structural diagram of a 55-bit carry generator in an embodiment of the present invention;

[0047] Figure 9 This is a structural diagram of a 12-bit multiplier in an embodiment of the present invention;

[0048] Figure 10 This is a schematic diagram of the partial product processing and Wallace tree compression process in an embodiment of the present invention.

[0049] Figure 1 The attached diagrams are labeled as follows: 1-Assignment processing module; 2-Adder array addition module; 3-Exponent calculation module; 4-Mantissa alignment shift module; 5-Multiplier array module; 6-Exponent difference module; 7-Alignment shift module; 8-Addition tree module; 9-Exponent comparison module; 10-Compression module; 12-Sign prediction module; 13-Advance calculation module; 14-Leading zero prediction module; 15-Standardized shift module; 16-Leading zero encoding module; 17-Exponent standardization module; 18-Summation and rounding module. Detailed Implementation

[0050] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0051] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0052] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0053] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0054] Terminology Explanation:

[0055] Switchable precision floating-point multiply-accumulator: According to the IEEE 754 standard, floating-point numbers are represented in three ways: double precision, single precision, and half precision. Their representation method is consistent, consisting of a sign bit, an exponent bit, and a mantissa bit, similar to representing a number using scientific notation. The exponent and mantissa bit widths differ for each of these three precisions. The bit widths are shown in Table 1 below:

[0056] Table 1. Distribution of sign bit, exponent bit, and mantissa bits for three precision floating-point numbers.

[0057]

[0058] Floating-point multiplication is similar to scientific notation multiplication, involving multiplying the mantissas and adding the exponents. When implementing multipliers of various precisions using hardware description languages, the required multiplier bit width varies depending on the bit width, corresponding to multiplication of numbers with different precisions. A multiply-adder, on the other hand, refers to a multiplication-addition operation implemented as A+B*C or A1×B1+ A2×B2+ A3×B4+…, involving the multiplication and addition of multiple pairs of numbers. Since a multiplier is essentially also an addition of multiple partial products, multiple small-bit-width multipliers can be combined to form a large multiplier, or a large-bit-width multiplier can be split into multiple small-bit-width multipliers. This allows the same components to handle the multiplication of the mantissas of floating-point numbers with different bit widths, i.e., module reuse. This is the basic idea behind switchable-precision multiply-adders.

[0059] CSA: Carry-Save Adder: A single-bit-width carry-save adder is also called a full adder. A multi-bit-width carry-save adder consists of multiple single-bit-width carry-save adders, and the carries are not cascaded. Because it has three inputs and two outputs, it is also called a 3:2 compressor. There is also a 4:2 compressor, which is composed of multiple single-bit-width 5:3 compressors. The structure of a 5:3 compressor is as follows... Figure 1 As shown, the input bits are p0, p1, p2, p3 and carry_in, and the output bits are sum, carry and carry_out. By connecting n compressors together, that is, by connecting two adjacent compressors carry_in and carry_out, the input becomes 4n+1 bits and the output becomes 2n+1 bits, thus achieving an approximate compression ratio of 4:2.

[0060] Improved Booth coding: The principle of improved Booth coding is essentially to treat the multiplier as a base-4 number to generate a partial product with the multiplicand. Figure 2 As shown in the example, the multiplier is binary with 12 bits (0-11). A 0 is added to the least significant bit and two 0s to the most significant bit (represented by blue dots). Then, each group of three adjacent bits is grouped to generate a partial product. For example, 1, 2, and 3 form a group called mb2, and 3, 4, and 5 form a group called mb4. If we generate a partial product for each bit in the most basic way, the middle two bits of these two groups, bit2 and bit4, each generate a row of partial products (as shown in the second and third rows of dots in the diagram). The partial product of bit4 is four times that of bit2, which is the multiplicand shifted two bits to the left. For bit3, since it exists in both groups, it generates two partial products. The sum of these two partial products should be twice that of bit2. The solution is that bit3 generates a partial product of -2 times that of bit2 in the mb2 group, and a partial product of equal value to bit4 in the mb4 group. In summary, bit3 generates two partial products, and the sum of these two is exactly (4 + (-2)) = 2 times the partial product relative to bit2. Therefore, the booth encoding algorithm generates a partial product of (-2 times multiplicand × b2i+1) + (1 times multiplicand × b2i) + (1 times multiplicand × b2i-1) for each multiplier group (b2i+1, b2i, b2i-1). The advantage of this is that the number of partial product rows is reduced by nearly half, with only 7 rows of partial products generated for 12 bits multiplied by 12 bits.

[0061] The drawback of existing methods is that double-precision computing only performs multiplication, not addition. Therefore, when this multiply-accumulator is used in high-performance computing or neural network inference, it must be paired with a double-precision adder. To address this, this invention incorporates double-precision addition, completing a double-precision floating-point operation of the form A + B × C. This combination, compared to a simple multiply-accumulator paired with an adder, allows for greater reuse of components within the multiply-accumulator, such as the leading zero prediction component, standard shifting component, and rounding component. Secondly, double-precision computing requires two cycles to complete one multiplication, which is slower than single-precision and half-precision computing. Furthermore, some components only operate in one cycle, such as leading zero encoding. In the first clock cycle, the low-order data segments of sum and carry are calculated, and leading zero prediction is meaningless; prediction can only begin after the high-order bits of sum and carry are calculated in the second clock cycle. There is also the rounding module. Theoretically, the adder module could calculate the low-order bits first, then the high-order bits, but the approach used in this paper, with a 66-bit adder width, indicates that this is not done; instead, addition is completed only after both high and low-order bits arrive in the second cycle. From a time perspective, the utilization rate of this multiply-accumulator is not as high as expected. Therefore, although designing a single-cycle multiply-accumulator requires more multipliers, the overall utilization rate is improved, and it is simpler than a two-cycle design. For example, in the addition tree, with adjustments to bit width and compression strategy, the compressor usage can be reduced by 20% for the same performance in a single-cycle configuration. In addition, some components can be optimized, such as the adder, simultaneous leading zero encoding and shifting, etc.

[0062] like Figure 3 As shown, this embodiment provides a floating-point multiply-accumulator with switchable precision, including a four-stage pipeline. The specific workflow of each pipeline stage is as follows:

[0063] The first-stage pipeline includes a distribution processing module 1, a multiplier array module 5, an adder array addition module 2, an exponent comparison module 9, an exponent calculation module 3, and a mantissa shifting module 4.

[0064] Allocation processing module 1 performs allocation processing on the input data. Figure 3In the input module, in1 and in2 are two 320-bit data inputs, mode is the calculation mode, and valid indicates that the input data is valid. The allocation processing module 1 receives two 320-bit data inputs in1 and in2, and a 2-bit mode input mode. In mode 00, the data is interpreted as 20 pairs (40) of half-precision floating-point numbers; in mode 01, the lower 160 bits of the two data points are interpreted as 5 pairs of single-precision floating-point numbers; and in mode 10, the data is interpreted as three double-precision floating-point numbers A, B, and C. After mode selection, the 20 pairs of mantissas are sent to a 20-12-bit multiplier array module 5, where they are multiplied to obtain 20 mantissa partial products. The exponent pairs are then sent to an adder array addition module 2, and after obtaining multiple exponent sums, they are sent to an exponent comparison module 9 to obtain the largest exponent sum.

[0065] Furthermore, since the multiplier array only performs B×C operations on double-precision numbers, the mantissa of A also needs to be processed. Based on the valid subtraction case (i.e., the product of A and BC, where one is positive and the other is negative), the mantissa of the double-precision addend A needs to be inverted (converted to two's complement; the addition of 1 is performed later). The exponent calculation module 3 calculates the exponent difference according to the following formula:

[0066]

[0067] The mantissa equalization shift module 4, after inverting the mantissa of the double-precision floating-point number A, shifts the mantissa of A according to the exponent difference d. Here, EA, EB, and EC are the exponent parts of A, B, and C, respectively.

[0068] The second-stage pipeline includes the exponential difference module 6, the alignment shift module 7, the addition tree module 8, and the compression module 10.

[0069] The exponent difference module 6 subtracts the sum of the largest exponents obtained from the comparator from each exponent to obtain the exponent difference. The alignment and shift module 7 aligns and shifts the 20 mantissa partial products obtained from the multiplier array according to the exponent difference. After shifting, the 20 partial products are compressed into two rows of numbers by the addition tree module 8. These two rows of numbers are then compressed with the mantissa of A after alignment by a 3:2 compression module 10, resulting in two more rows of numbers: one row of sum data and one row of carry data (if not in double-precision mode, the mantissa of A is set to 0). That is, the mantissa of A is shifted in the first stage pipeline. This shifted result and the result obtained from the addition tree are passed to the 3:2 compressor for further compression. In double-precision mode, the multiplier array and the addition tree calculate the mantissa of B multiplied by the mantissa of C, but it does not directly obtain a single row of final results. Instead, it is compressed into two rows of partial products because it implements A + B * C. These two rows of partial products need to be added to the mantissa of A, so further compression is performed to obtain the sum and carry.

[0070] The third-level pipeline includes a leading zero prediction module 14, a leading zero encoding module 16, a symbol prediction module 12, and an advance calculation module 13.

[0071] The sum and carry data are sent to the leading zero prediction module 14, the sign prediction module 12, and the advance calculation module 13, respectively. The leading zero prediction module 14 derives a leading zero sequence from the sum and carry data. The leading zero encoding module 16 encodes the number of leading zeros in the sequence using a coding tree with a total of 7 bits. Timing-wise, the encoding is performed sequentially from the most significant bit to the least significant bit, shifting the data once for each bit. Therefore, encoding and shifting occur simultaneously. The advance calculation module 13 performs partial addition on the sum and carry data during the leading zero sequence generation process, reducing the timing path of the final adder circuit. This partial operation generates the carry propagation signal p and the carry generation signal g. The sign prediction module 12 predicts whether the final result is positive or negative. Because two's complement is inconvenient for subsequent rounding modules, it converts the p and g signals from two's complement to original code in advance based on the sign of the final result.

[0072] The fourth-level pipeline includes the addition and rounding module 18 and the exponential standardization module 17.

[0073] The addition and rounding module 18 performs addition and rounding of the last digit. The addition uses a square root double-ended adder, and the rounding is performed differently depending on the rounding mode, such as rounding to the nearest whole number or truncating. The exponent standardization module 17 is used to perform exponent standardization.

[0074] The following sections will provide a detailed explanation of each of the modules mentioned above.

[0075] (1) Addition Tree Module

[0076] Figure 4 This is the overall architecture diagram of the addition tree. Figure 4 In CSA (Carry-Saving Adder), also known as a compressor, S represents sum and C represents carry. A 3:2 CSA can compress a three-row partial product into a two-row multiplication, and a 4:2 CSA can compress a four-row partial product into a two-row multiplication. Timing-wise, a 3:2 CSA requires approximately two XOR gates, and a 4:2 CSA requires approximately three XOR gates. The number of compressed rows varies: 20 rows, 12 rows, 6 rows, 4 rows, and 2 rows.

[0077] Figure 5The compression process in double-precision mode is described. The red boxes represent compressors, the black boxes represent 24-bit partial products, and the blue boxes represent bits with a value of 0. B0-B4 and C0-C4 represent different data segments of the mantissas of the double-precision numbers B and C, respectively, with each segment consisting of 12 bits. The highest segments, B4 and C4, are 5 bits each. Different data segments are multiplied in a multiplier array to obtain 20 rows of partial products, which are then compressed through four stages to obtain the final result. It can be seen that the first-level partial products are not all aligned to the left or right of the compressor. For example, in the compressor containing B1×C3, all four partial products are placed in the middle. This is to allow the second-level compressor to directly send the compression result from the first level without shifting. The shifting before the first level is placed can be done by the shifters originally provided for single-precision and half-precision. From the second to the third level, data selectors or shifters are inevitably needed to shift the compressed result before feeding it into the next level, but the number of such shifters is small. For double precision, some lower bits are already compressed in the second stage, while some higher bits require the carry from the previous bits to be moved to the most significant bit using a half-adder. For half precision and single precision, since the mantissa is only 24 bits and 11 bits wide respectively, a 48-bit compressor is sufficient. For example, in single precision, the lower 24 bits are only used for rounding operations. If the exponent difference is greater than 24 bits, the number exceeding the bit width needs to be discarded, which has little impact on precision. The results from all higher-level compressors can be directly passed to the next level.

[0078] The addition tree designed in this embodiment uses approximately six 48-bit 4:2 compressors and six 48-bit 3:2 compressors to complete the operation in one cycle, while the prior art uses approximately three 60-bit 4:2 compressors and three 60-bit 3:2 compressors to complete the operation in two cycles. Therefore, under the same performance comparison, the compressor utilization rate of this embodiment is reduced by approximately 20%.

[0079] (2) Symbol prediction module

[0080] The sign detection module is used to determine whether the final mantissa result is positive or negative. In double-precision mode, since the mantissa of A is inverted by effective subtraction (SA=1 or SB XOR SC=1), and the result of multiplying the mantissa of B by the mantissa of C is positive (the multiplier outputs in sign-magnitude mode in double precision), the only possible negative mantissa result is d=EA-(EB+EC) greater than 0. When d is greater than 2, it is definitely negative. When d=0 or 1, due to the possibility of overflow during mantissa addition, it may not be negative, requiring comparison of sum and carry. Since d=0 or 1, the mantissa of A is shifted right by 55 or 56 bits, so the high 55 bits must be sign extension bits. Therefore, only the last 108 bits need to be compared, requiring a 108-bit comparator (i.e., exponent comparison modulus). For single-precision and half-precision, sum and carry are directly compared because their effective bit width is only 48 bits.

[0081] (3) Alignment and shifting module

[0082] The 20 aligned shifters employ 48-bit shifters. Taking half-precision mode as an example, 20 6-bit subtractors are used. Each exponent is subtracted from the largest exponent, resulting in 20 exponent differences. The outputs of the 20 multipliers are then right-shifted according to each exponent difference. Since the subtraction operation generates the least significant bit first and then the most significant bit, each shifter shifts from least significant to most significant bit according to the exponent difference. This allows the subtraction and shifting operations to occur almost simultaneously, shortening the timing. For single precision, since the exponent difference will be greater than 48, exponent differences exceeding 48 are shifted according to the maximum value of 48. In addition, for some partial products, the exponent difference needs to be added by 12 or 24. This is because multiplying the mantissas of the same pair of single-precision numbers requires four 12-bit multipliers to generate four partial products. One partial product is the multiplication of two most significant bits, two partial products are the multiplication of one least significant bit and one most significant bit, and one partial product is the multiplication of two least significant bits. Therefore, compared to multiplying the most significant bits, the latter requires a right shift of 12 bits and 24 bits respectively. For double precision, simply shift the corresponding partial product by a multiple of 12 bits. The specific number of bits to shift can be found in [the relevant documentation / resource]. Figure 5 I saw it in the middle.

[0083] (4) Index Comparison Module

[0084] like Figure 6 As shown, Figure 6 This is a structural diagram of the index comparison module. Figure 6In this module, LT represents less than, GT represents greater than, S represents the compressed sum, and C represents the compressed carry. This module reconstructs the 18 6-bit modules of the exponent comparison. The corresponding input is selected according to the mode. In double-precision mode, S and C are input in 6-bit segments to obtain 18 comparison results. These results are then input into the second-stage comparator to obtain the final comparison size. The second and third-stage comparators do not use the exponent comparator array because this would increase the multi-input selector and timing, thus requiring additional comparators.

[0085] Another function of the exponent comparison module is to compare the 20 exponents in single-precision and half-precision exponents to find the maximum value, using a cascaded exponent comparison method. Taking half-precision as an example, firstly, the first level of 20 exponents are divided into 10 pairs and compared pairwise to obtain 10 larger values. Then, the second level of 10 larger values ​​are divided into three groups: 3, 3, and 4. The method for comparing multiple numbers simultaneously to find the maximum value is to compare pairwise. Taking three numbers E1, E2, and E3 as an example, any two numbers are selected for comparison, i.e., C3. 2 The first stage uses three comparators: E1 and E2, E2 and E3, and E3 and E1. It then calculates the maximum value based on these three comparisons. Assuming 1 represents greater than and 0 represents less than, a comparison result of 110 indicates that E1 is the largest, and so on. The third stage performs a final comparison on the three largest values ​​from the second stage to determine the maximum value. In summary, the first stage comparator requires 10 comparators, and the second stage comparator requires C3 comparators. 2 +C3 2 +C4 2 =3 + 3 + 6 = 12, and the last stage needs 3, for a total of 25 6-bit comparators. The advantage of this maximum value method is that it minimizes the use of comparators while meeting timing requirements. If a larger number of simultaneous comparisons are used, although the timing will be optimized a little, the hardware cost will increase exponentially.

[0086] (5) Leading zero prediction module

[0087] Generally, floating-point multiplication and addition involve adding numbers with different signs. The mantissas after the multiplier are represented in two's complement. The sum and carry obtained after passing these mantissas through the addition tree are also in two's complement, and they can be positive or negative. If one is positive and the other is negative, they may cancel each other out during addition, resulting in multiple leading zeros or 1s in the result. For example, 15 + (-14) = 1 in two's complement: 01111 + 10010 = 00001; 13 + (-15) = -2 in two's complement: 01101 + 10001 = 11110.

[0088] At this point, the result needs to be standardized, which requires calculating the number of leading zeros and then shifting the result to the standard mantissa format. This can be achieved through the standardization shift module 15. Calculating the number of leading zeros after the result is obtained will increase the delay of the critical path. Therefore, we consider using sum and carry to directly calculate the number of leading zeros, and then adding sum and carry together. This strategy is called leading zero prediction to reduce the delay of the critical path. The calculation method for leading zero prediction is shown in the following formula (1):

[0089] (1)

[0090]

[0091] in This represents the predicted sequence, which begins with several zeros, and these zeros are called leading zeros. It is the XOR of sum and carry, representing carry propagation; It's a bitwise AND operation of sum and carry, indicating carry-out. This represents the bitwise OR of sum and carry, where both bits are 0. i is an integer from 0 to 108.

[0092] When obtained After the sequence, the number of leading zeros in the f sequence needs to be encoded, using a binary search method. This is done using 16 bits. Sequence bit example, first The sequence is multiplied into two parts. If bits 0 to 7 are all 0, then the code s1 = 1. Then, bits 8 to 15 are divided into two parts, and it is checked whether bits 8 to 11 are all 0. If they are, then s2 = 1. If s1 = 0, then bits 0 to 7 are divided into two parts, and it is checked whether bits 0 to 3 are all zero. If they are, then s2 = 1. This process is repeated until the final code bits are s1s2s3s4.

[0093] (6) Addition and discard module

[0094] See Figure 7 , Figure 7 Here is a structural diagram of the addition and discard module. Figure 7Y0 and Y1 in the equation represent the results corresponding to input carry-in bits of 0 and 1, respectively. The actual input carry-inc selects the module to receive the two rows of partial products after normalization and shifting by leading zeros. OVF indicates the overflow condition, and the final summation result is selected as either bits 0-52 or bits 1-53. Finally, the two rows of partial products need to be added together and then truncated and rounded. Taking a double-precision bit width as an example, the high 54 bits are the final result, and the low 55-161 bits are the part to be discarded. It is necessary to calculate whether there is a carry-in to 54 bits for the discarded part, and at the same time, it is necessary to calculate the sticky bit. The sticky bit is whether there is a residual 1 after adding the discarded parts except for the carry-in bit of the highest bit. However, it is not necessary to add them directly; it can be calculated according to the following formula 2), where, and , This is an intermediate result, where i represents the number of bits, ranging from 55 to 161.

[0095]

[0096]

[0097]

[0098] (2)

[0099] The adder in the addition and rounding module uses a square root adder. The square root adder is composed of multiple cascaded carry-select adders, but the bit width of each carry-select adder increases progressively. A total of eight carry-select adders are cascaded, with bit widths of 3, 4, 5, 6, 7, 8, 9, and 10 bits respectively, forming a total of 52 bits. Since the timing path of a carry-select adder is approximately the delay of one selector multiplied by the bit width, each adder can independently calculate two results simultaneously and then select the actual result based on the carry from the previous stage. Therefore, as the bit width of the adder increases, more bits can be calculated in the stages before and after the previous stage has finished calculating the result. For example, the first-stage adder calculates two results after delays through three selectors, then selects the actual result through another selector. At this point, the second-stage multiplier has also calculated two results, and the actual carry from the previous stage is used to select the actual result in this stage, and so on. This minimizes timing complexity.

[0100] The rounding unit in the addition and rounding module determines the numbers Rd and Rd1 to be added to the rounding bit R based on the sticky bit and rounding mode. The calculation formula is as follows (3), where r[0] and r[1] are the input rounding modes, with a default of 11. The sign bit is the result of the sign detection. There are three rounding modes: RI means rounding to infinity, RZ means truncation rounding, and RN means rounding to the nearest even number. After Rd and Rd1 are calculated, they are compressed into two parts by a 3:2 compressor, and then added to the highest carry c53 from the discarded part by a 2-bit adder to obtain the result of the least significant bit and the carry inc to be added to the square root adder.

[0101]

[0102]

[0103]

[0104]

[0105] (3)

[0106] Least significant bit correction is used to correct errors in rounding to the nearest even number. The rounding formula follows the rounding method, which leads to a situation where the least significant bit L=0, the rounding bit is 1, and the sticky bit is 0, resulting in a rounding error where L=1. The correct rounding should keep L as an even number, 0.

[0107] Therefore, least significant bit error correction will detect this situation and change L to 0.

[0108] Figure 8 The structure diagram for C53 carry selection is as follows: First, a 5m-bit carry-lookahead adder is constructed by cascading m 5-carry-lookahead adders. Then, a 5n-bit carry-lookahead adder is constructed by cascading n 5-carry-lookahead adders. Finally, a 5m+n-bit carry-select adder is constructed using two 5m-bit adders and one 5n-bit adder. Figure 8 As shown, the two 5m-bit adders on the left have one input carry fixed at 0 and the other at 1. The final output carry of both is determined by the output carry of the 5n-bit adder. A 55-bit carry output is constructed using three adders with different m and n parameters. See [link to documentation]. Figure 8 The first one has m=4, n=1, the second one has m=3, n=1, and the third one has m=1, n=1. After such reconstruction, 19 5-bit adders are needed, which requires a timing path of approximately 4 cascaded 5-bit carry-lookahead adders.

[0109] (7) Index Standardization Module

[0110] The above exponent addition is performed directly using the IEEE 754 offset format. Therefore, a offset needs to be subtracted: 1023 for double precision, 127 for single precision, and 15 for half precision. Furthermore, since half precision and single precision involve multiplying and adding multiple numbers, in single precision, adding five numbers causes the mantissa width to continuously increase (each level of the adder tree increases in width). Therefore, the decimal point is not located between the highest and second-highest bits of the mantissa. To shift the decimal point to that position, the exponent needs to be added with the corresponding shift number. Finally, for the mantissa normalization shift with leading zeros, the exponent also needs to be subtracted from the corresponding shift number.

[0111] (8) Multiplier array module

[0112] The multiplier array module includes 12 One multiplier and eight fused multipliers. See also Figure 9 , Figure 9 For a single The diagram shows the structure of a multiplier. The multiplier takes two's complement inputs A and B as inputs and the product result (signed SAB) as the symbol, and outputs the two's complement result (in double-precision mode, the input is the two's complement result). Since the multiplier is currently used for IEEE 754 operations, the input is in two's complement, but we want the two's complement result (because we will be adding the results of multiple multipliers later, and two's complement is most suitable for addition). Generally, multipliers using improved booth encoding algorithms require two two's complement inputs. Then, based on the booth encoding of the multiplier, the multiplicand is multiplied by 2, -2, 1, -1, or converted to 0 (i.e., left-shifting, inverting, or decrementing the multiplicand). Then, all the two's complement partial products are added to obtain the result. Converting the original code to two's complement before performing these operations inevitably increases timing, especially the inversion and addition operations. However, observation shows that if the multiplier result is positive, the two's complement input is equivalent to the original code input. And if the multiplier result is negative, the encoding is reversed. For example, if the multiplier has a booth encoding of 2, then multiplying the multiplicand by -2 is equivalent to inverting and left-shifting (adding 1 is reserved for later). If the booth encoding is -2, then multiplying the multiplicand by 2 is equivalent to left-shifting, and so on. In this way, the partial product can be obtained directly from the original code input, the booth encoding, and the sign of the product. The timing difference compared to two's complement input only adds an XOR operation on the product sign.

[0113] Figure 10 This diagram illustrates the partial product preprocessing and Wallace tree compression process for a 12-bit multiplier. The specific process is as follows:

[0114] First, eliminate the effect of sign bit extension. Since the partial product is in two's complement form, each partial product must be extended to the same bit width for addition. A 12*12 bit product has a maximum of 24 bits, and including the sign bit, it has 25 bits. Figure 10The white dots and the calculation of the sign bits are undoubtedly a waste of resources. Research shows that these sign bits can be calculated in advance. The calculation principle is to first assume that all the extended sign bits (white dots and the blue dots on the left) are 1 and add them together. This will result in a special sequence of partial products (101010...1011). The least significant bit of the sequence is aligned with the sign bit of the first row of partial products. Then, every two bits of this sequence are placed at the end of the corresponding partial product. Since this sequence is obtained by assuming that all sign bits are 1, if in reality some rows of extended sign bits are not 1, such as the first row of sign bits S0 being 0, it means that an extra row of 1s has been added. The solution is to add the opposite of the sign bit ~S0=1, directly causing this row of 1s to overflow. Discarding the overflow bit will return it to 0. In this way, all partial products are transformed into a parallelogram shape, eliminating the need to compress the sign bits using a compressor.

[0115] Next, by pre-compiling the partial product by inverting and adding 1 using the encoding of A, B, and booth, the sign bit of the last row of the partial product is eliminated. This reduces the number of partial products by one row, and the partial products form a regular parallelogram, thus reducing the final number of compressors used.

[0116] The above three steps are all processed simultaneously with the partial product generation, corresponding to the special partial product generation module in the multiplier. Therefore, they do not increase timing but add a small amount of logic circuitry.

[0117] Next, following the idea of ​​Wallace trees, we compress the 7-row partial product into 4 rows. Figure 10 The red boxes indicate the following: those with two rows of dots are half-adders, those with three rows are full adders (3:2 compressors), and those with four rows of dots are 4:2 compressors. After the first compression, the result is the four-row partial product shown at the bottom of the diagram. The second compression follows the same process, producing two rows of partial products, which are then added together using adders.

[0118] Through the aforementioned techniques, the timing and area of ​​the multiplier have been greatly optimized, and it meets the specific requirements of the overall design.

[0119] In summary, the floating-point multiply-accumulator of the present invention has at least the following advantages and beneficial effects compared with the prior art:

[0120] 1) The functionality is more complete. For double precision, the original single-number multiplication has been changed to an operation of the form A + B × C. In use, the output result can be returned to A to continuously complete the multiplication and accumulation function. Alternatively, A can be set to 0 to perform a separate multiplication, or B can be set to 1 to perform a separate addition. This is more suitable for high-performance computing or convolution operations in neural networks.

[0121] 2) Higher reuse rate. Compared to adding an additional double-precision adder, double-precision addition reuses the leading zero prediction unit, the normalization shift unit, and the final adder unit. Existing solutions use two-cycle computation in both double-precision and single-precision modes. The first cycle calculates the low-order multiplication, and the second cycle calculates the high-order multiplication. However, some components only operate in one cycle, such as the leading zero encoding, addition, and rounding modules. This solution changes to single-cycle computation, and the number of multipliers is increased from 10 to 20, calculating all mantissa multiplications at once. From a time perspective, the utilization rate of each module is also higher.

[0122] 3) Key timing paths have been optimized. Exponential subtraction and mantissa alignment shift are performed simultaneously, as are leading zero encoding and shifting. The final adder has been changed from an average-distribution double-ended adder to a square-root adder, shortening the timing path without increasing the area.

[0123] 4) The area of ​​the addition tree has been optimized, and the addition tree of this design can only be used under the premise of single-cycle calculation. Under the same performance comparison, the number of compressors has been reduced by about 20%.

[0124] In the foregoing description of this specification, references to terms such as "one embodiment," "another embodiment," or "some embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0125] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0126] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A floating-point multiply-accumulator with switchable precision, characterized in that, Includes a four-stage production line: The first-stage pipeline includes an allocation processing module, a multiplier array module, an adder array summing module, and an exponent comparison module. The allocation processing module allocates the input data to obtain n pairs of mantissas, which are then fed into the multiplier array module. The multiplier array module multiplies the n pairs of mantissas to obtain n partial products of mantissas. The exponent pairs in the input data are fed into the adder array summing module to obtain multiple exponent sums, which are then fed into the exponent comparison module to obtain the maximum exponent sum. The second-stage pipeline includes an exponential difference module, an alignment shift module, an addition tree module, and a compression module; The exponential difference module is used to subtract the sum of the largest exponent from each exponent to obtain the exponential difference; The alignment and shift module is used to align and shift the n mantissa partial products obtained by the multiplier array module according to the exponent difference. After the shifted n partial products are compressed by the addition tree module, they become two rows of numbers. The compression module is used to further process the two rows of numbers to obtain a row of sum data and a row of carry data. The third-level pipeline includes a leading zero prediction module, a leading zero encoding module, a symbol prediction module, and an advance calculation module; The leading zero prediction module is used to obtain a leading zero sequence based on the sum data and carry data, and the leading zero encoding module encodes the number of leading zeros in the leading zero sequence. The advance calculation module is used to perform calculations on the sum and carry data to obtain the carry propagation signal p and the carry generation signal g; the sign prediction module is used to predict whether the final calculation result is positive or negative and feeds the prediction result back to the advance calculation module. The fourth-stage pipeline includes an addition and rounding module and an exponent standardization module; the addition and rounding module is used to perform addition calculations based on the carry signal and to round the calculation results; the exponent standardization module is used to perform exponent standardization.

2. The switchable precision floating-point multiply-accumulator according to claim 1, characterized in that, The input data includes two 320-bit data inputs in1 and in2, and a 2-bit mode input mode; If it is in 00 mode, the allocation processing module will interpret the data as a 20-pair precision floating-point number; If it is in 01 mode, the allocation processing module interprets the lower 160 bits of the two data as 5 pairs of single-precision floating-point numbers; In mode 10, the allocation processing module interprets the data as three double-precision floating-point numbers A, B, and C; the multiplier array module multiplies double-precision floating-point numbers B and C, with double-precision floating-point number A as the addend; the first-stage pipeline also includes an exponent calculation module and a mantissa equalization shift module; the exponent calculation module is used to calculate the exponent difference d, and the calculation formula is as follows: In the formula, EA, EB, and EC are the exponents of the double-precision floating-point numbers A, B, and C, respectively. The mantissa equal shift module is used to equal shift the mantissa of the double-precision floating-point number A according to the exponent difference d after inverting the mantissa.

3. A switchable precision floating-point multiply-accumulator according to claim 2, characterized in that, The compression module further processes the two lines of data in the following way: If it is in 10 mode, the two rows of numbers and the mantissa of the double-precision floating-point number A after shifting are input into a 3:2 compressor for further compression, resulting in one row of sum data and one row of carry data; In other modes, the mantissa of the double-precision floating-point number A is set to 0, and then compressed using a 3:2 compressor to obtain one row of sum data and one row of carry data.

4. A switchable precision floating-point multiply-accumulator according to claim 2, characterized in that, The addition tree module includes six 48-bit 4:2 compressors and six 48-bit 3:2 compressors; The alignment shift module is implemented using a 48-bit shifter.

5. A switchable precision floating-point multiply-accumulator according to claim 2, characterized in that, The sign prediction module is used to determine whether the final mantissa result is positive or negative. In double-precision mode, since the mantissa of A is inverted and the result of B multiplied by the mantissa of C is positive, the only possible case for the mantissa result to be negative is when the exponent difference d is greater than 0. When the exponent difference d is greater than 2, it is definitely negative. When d = 0 or 1, due to the possibility of overflow when adding the mantissas, it may not be negative. In this case, it is necessary to compare the sum data and the carry data. For single-precision and half-precision, directly compare the sum data and carry data.

6. A switchable precision floating-point multiply-accumulator according to claim 2, characterized in that, The exponent comparison module selects the corresponding input according to the mode. In double precision mode, S and C are selected to be input in 6-bit segments to obtain 18 comparison results. These results are then input into the second-stage comparator to obtain the final comparison size. Where S represents the sum obtained from compression, and C represents the carry obtained from compression.

7. A switchable precision floating-point multiply-accumulator according to claim 1, characterized in that, The leading zero prediction module performs prediction calculations using the following formula: in, This represents the predicted sequence of leading zeros; It is the XOR of the sum and carry data, representing carry propagation; It is a bitwise AND operation between the sum and carry data to indicate the carry-out. It is a bitwise OR of the sum and carry data, representing that both are 0.

8. A switchable precision floating-point multiply-accumulator according to claim 1, characterized in that, The adder in the summation and rounding module is a square root adder, which is composed of multiple carry-select adders cascaded together, and the bit width of each carry-select adder increases progressively. The rounding unit in the addition and rounding module determines the numbers Rd and Rd1 to be added to the rounding position R based on the sticky bit and the rounding mode.

9. A switchable precision floating-point multiply-accumulator according to claim 1, characterized in that, The index standardization module performs index standardization in the following ways: The exponents are added directly using the IEEE 754 offset code format. Therefore, for double-precision mode, subtract 1023; for single-precision mode, subtract 127; and for half-precision mode, subtract 15. Furthermore, since half-precision and single-precision involve multiplying and adding multiple numbers, the decimal point is not located between the highest and second-highest digits of the mantissa. To move the decimal point to that position, the exponent plus the corresponding number of bits to be moved is required. Finally, the mantissa of the leading zero is normalized by shifting the exponent by subtracting the corresponding shift number.

10. A switchable precision floating-point multiply-accumulator according to claim 1, characterized in that, The multiplier array module includes The multiplier adds a positive or negative signal to the result encoding on the basis of the original common encoding, so that it can be inverted according to the positive or negative sign of the calculation result.

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