Scalar engine processing method and apparatus for artificial intelligence chips

Abstract

The application relates to a scalar engine processing method and device for an artificial intelligence chip. The method comprises the following steps: an upper module in the chip acquires an artificial neural network model to be deployed in the chip; the upper module performs conversion processing on the artificial neural network model based on an instruction set built in a scalar engine in the chip, obtains a plurality of target instructions corresponding to the artificial neural network model, and sends the plurality of target instructions to the scalar engine; and the scalar engine executes the plurality of target instructions to realize the compilation processing corresponding to the artificial neural network model in the chip. The method can improve the flexibility of the in-chip compilation processing of the artificial intelligence chip on the artificial neural network model.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a scalar engine processing method and apparatus for artificial intelligence chips. Background Technology

[0002] Currently, artificial intelligence chips have been applied to computational processing in the field of artificial neural networks, and with the continuous development of the field of artificial neural networks, the types of artificial neural networks are becoming increasingly diverse.

[0003] Traditional AI chips often only support applications that accelerate the computation of a single neural network model. For each AI neural network model, if it needs to be compiled and computed in the AI ​​chip, the data flow and circuit layout of the AI ​​chip need to be designed accordingly. Therefore, current AI chips have a low degree of flexibility in on-chip compilation and computation of artificial neural networks. Summary of the Invention

[0004] Therefore, it is necessary to provide a scalar engine processing method and apparatus for artificial intelligence chips that can improve the flexibility of on-chip compilation processing of artificial neural network models, in order to address the above-mentioned technical problems.

[0005] Firstly, this application provides an on-chip compilation method for a model. Applied to a chip, the method includes:

[0006] The upper-layer module in this chip acquires the artificial neural network model to be deployed in this chip;

[0007] The upper-layer module performs transformation processing on the artificial neural network model based on the instruction set built into the scalar engine in the chip, obtains multiple target instructions corresponding to the artificial neural network model, and sends the multiple target instructions to the scalar engine;

[0008] The scalar engine executes the multiple target instructions to implement the compilation process corresponding to the artificial neural network model within the chip.

[0009] In one embodiment, the instruction set includes a vector computation instruction set for implementing vector computation, an artificial neural network computation instruction set for implementing operations corresponding to various artificial neural networks, and a cross-module scheduling dedicated instruction set for the scalar engine to schedule other modules within the chip to perform target operation processing.

[0010] In one embodiment, the vector computation instruction set includes multiple function instructions and multiple operation instructions.

[0011] In one embodiment, the instruction set built into the scalar engine is developed based on the RISCV architecture, and each instruction set is identified by a different field.

[0012] In one embodiment, the first bit range of the target instruction is used to characterize the instruction set to which the target instruction belongs; the second bit range of the target instruction is used to characterize the target register address; the third bit range of the target instruction is used to characterize whether it is necessary to write to the target register and whether it is necessary to read from the source register; the fourth bit range of the target instruction is used to characterize the first source register address; the fifth bit range of the target instruction is used to characterize the second source register address; and the sixth bit range of the target instruction is used to characterize the opcode of the target instruction.

[0013] In one embodiment, the method further includes: determining the target type of the operation processing corresponding to the target instruction currently being executed by the scalar engine; if the target type is different from the type of operation processing currently corresponding to the reconfigurable array in the scalar engine, then reconfiguring the reconfigurable array; and using the reconfigurable array after reconfiguration to perform operation processing on the currently executed target instruction; wherein the type of operation processing corresponding to the reconfigurable array includes at least addition and multiplication operations.

[0014] In one embodiment, the method further includes: if the operation processing corresponding to the target instruction currently being executed by the scalar engine meets the preset adjustment conditions, then the pipeline number of the scalar engine executing the target instruction is changed from the first pipeline number to the second pipeline number; wherein the second pipeline number is less than the first pipeline number.

[0015] Secondly, this application also provides an on-chip compilation device for a model. Applied in a chip, the device includes:

[0016] An acquisition module is used by the upper-layer module in the chip to acquire the artificial neural network model to be deployed in the chip;

[0017] The conversion module is used by the upper-layer module to perform conversion processing on the artificial neural network model based on the instruction set built into the scalar engine in the chip, to obtain multiple target instructions corresponding to the artificial neural network model, and to send the multiple target instructions to the scalar engine;

[0018] An execution module is used by the scalar engine to execute the plurality of target instructions to implement the compilation process corresponding to the artificial neural network model within the chip.

[0019] In one embodiment, the instruction set includes a vector computation instruction set for implementing vector computation, an artificial neural network computation instruction set for implementing operations corresponding to various artificial neural networks, and a cross-module scheduling dedicated instruction set for the scalar engine to schedule other modules within the chip to perform target operation processing.

[0020] In one embodiment, the vector computation instruction set includes multiple function instructions and multiple operation instructions.

[0021] In one embodiment, the instruction set built into the scalar engine is developed based on the RISCV architecture, and each instruction set is identified by a different field.

[0022] In one embodiment, the first bit range of the target instruction is used to characterize the instruction set to which the target instruction belongs; the second bit range of the target instruction is used to characterize the target register address; the third bit range of the target instruction is used to characterize whether it is necessary to write to the target register and whether it is necessary to read from the source register; the fourth bit range of the target instruction is used to characterize the first source register address; the fifth bit range of the target instruction is used to characterize the second source register address; and the sixth bit range of the target instruction is used to characterize the opcode of the target instruction.

[0023] In one embodiment, the device further includes:

[0024] The reconfiguration module is used to determine the target type of the operation processing corresponding to the target instruction currently being executed by the scalar engine; if the target type is different from the type of operation processing currently corresponding to the reconfigurable array in the scalar engine, the reconfigurable array is reconfigured; the reconfigurable array after reconfiguration is used to process the currently executed target instruction; wherein, the type of operation processing corresponding to the reconfigurable array includes at least addition and multiplication operations.

[0025] In one embodiment, the device further includes:

[0026] The modification module is used to change the pipeline number of the scalar engine executing the target instruction from the first level to the second level if the operation processing corresponding to the target instruction currently being executed by the scalar engine meets the preset adjustment conditions; wherein the second level is less than the first level.

[0027] Thirdly, this application also provides a chip including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method described in any of the first aspects above.

[0028] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any one of the first aspects above.

[0029] Fifthly, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the method described in any one of the first aspects above.

[0030] The aforementioned scalar engine processing method and apparatus for artificial intelligence chips involves an upper-layer module within the chip acquiring an artificial neural network model to be deployed on the chip. This upper-layer module then performs conversion processing on the artificial neural network model based on the instruction set built into the scalar engine within the chip, obtaining multiple target instructions corresponding to the artificial neural network model. These target instructions are then sent to the scalar engine. Furthermore, the scalar engine executes these multiple target instructions to perform the compilation processing corresponding to the artificial neural network model within the chip. Thus, because the scalar engine has a built-in instruction set that supports the conversion of artificial neural network models, for different types of artificial neural network models, the chip can directly convert the artificial neural network model to be processed into a data stream supported by the chip on-chip for subsequent compilation processing, without requiring an additional processor to perform data conversion. Furthermore, it eliminates the need to redesign the chip's circuit layout for different types of artificial neural network models, enabling the artificial intelligence chip to effectively support multiple artificial neural network mappings and on-chip compilation, effectively improving the flexibility of current artificial intelligence chips in mapping artificial neural network models and increasing the efficiency of on-chip compilation of artificial neural network models. Attached Figure Description

[0031] Figure 1 This is a flowchart illustrating the on-chip compilation method for a model in one embodiment;

[0032] Figure 2 This is a flowchart illustrating the reconstruction process in one embodiment;

[0033] Figure 3 This is a flowchart illustrating a chip architecture scheme that is compatible with flexible mapping of multiple artificial neural networks in one embodiment.

[0034] Figure 4 This is a block diagram of the on-chip compilation device of a model in one embodiment;

[0035] Figure 5 This is a structural block diagram of another model on-chip compilation device in one embodiment;

[0036] Figure 6 This is a diagram of the internal structure of a chip in one embodiment. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0038] First, before introducing the technical solutions of the embodiments of this application in detail, we will first introduce the technical background or technical evolution on which the embodiments of this application are based.

[0039] Since its formal inception, artificial intelligence (AI) has undergone half a century of accumulation, ushering in revolutionary development and attracting the attention of researchers across various fields. Driven by a significant increase in computing power and data volume, AI has achieved major breakthroughs in machine learning, particularly in deep learning dominated by neural networks. Deep learning algorithms have become synonymous with AI algorithms. Therefore, the term "AI chip" currently used typically refers to a deep learning algorithm chip, which utilizes innovative computing architectures to optimize deep learning algorithms in hardware, achieving optimizations in computing power, power consumption, and cost for AI applications.

[0040] In pursuit of improved performance in artificial intelligence chips, several typical design schemes are currently employed, including the following.

[0041] The Eyeris deep learning processor prioritizes energy efficiency and is based on a dataflow architecture. It employs a proprietary row-stationary (RS) computation rule for its Processing Element (PE) units. The second-generation Eyeris V2, built upon this foundation, offers sparsity and more flexible network structures. Researchers in 2017 introduced ENVISION, proposing various data reuse methods, including convolution reuse, image reuse, and convolution kernel reuse, to improve chip energy efficiency. Subsequently, the DNPU, UNPU, LNPU, and GANPU series of AI chips were launched. The DNPU primarily relies on heterogeneous architecture, hybrid load partitioning methods, dynamically adaptive fixed-point computation, and quantized table-based multipliers to achieve configurability and low power consumption. The UNPU is a fully variable weight bit precision DNN accelerator that can adjust the optimal bit precision according to different accuracy / performance requirements. The LNPU utilizes direct feedback alignment for fast online learning and features a built-in direct error propagation mechanism based on a pseudo-random number generator. GANPU proposes an adaptive spatiotemporal workload reuse method for generative adversarial network processing units to maintain high utilization when accelerating multiple DNNs in a single GAN model. It also utilizes a dual sparsity architecture to skip redundant computations caused by zeros in input and output features, and proposes an exponential-only ReLU inference algorithm and its lightweight processing element architecture.

[0042] An APU (Acceleration Processing Unit) is a heterogeneous computing architecture that integrates a traditional CPU and a GPU on a single chip. It flexibly distributes tasks between the CPU and GPU based on the nature of the computation, assigning AI-related operations to the GPU to improve the efficiency of data parallel processing. Xilinx's DPU (Deep-Learning Processing Unit) is a configurable computing engine based on an FPGA, used to accelerate deep learning algorithms such as convolutional neural networks. Google's TPU (Tensor Processing Unit) is also a dedicated chip for accelerating neural network computations, achieving 15-30 times the performance and 30-80 times the energy efficiency compared to contemporary CPUs and GPUs.

[0043] In addition, there is the multimodal AI chip Thinker, which can balance the resource conflicts between CNN and RNN in terms of computation and bandwidth. It also designed the Evolver, an evolvable AI chip that supports on-chip training and reinforcement learning, ReDCIM for general cloud AI scenarios, TranCIM, which is accelerated based on the in-memory computing self-attention neural network Transformer, and another Transformer acceleration chip based on approximate computation and asymptotic sparsity.

[0044] The STICKER-T AI chip proposes an implementation path combining block loop algorithms and unified frequency domain acceleration. The DianNao series of neural network accelerators supports accelerated processing of large-scale deep neural networks such as CNNs and is one of the world's earliest neural network accelerators specifically designed for artificial intelligence computing. The BPU (Brain Processing Unit) AI chip, fabricated using TSMC's 40nm process, is applied in data-intensive computing scenarios including autonomous driving, smart living, and smart cities.

[0045] The central processing unit (CPU), as the core of a computer system's computation and control, is the final execution unit for information processing and program execution. The von Neumann architecture is the foundation of modern computers. In this architecture, programs and data are stored uniformly, instructions and data must be accessed from the same memory space and transmitted via the same bus, preventing overlapping execution. According to the von Neumann architecture, the CPU's operation is divided into the following five stages: instruction fetch, instruction decoding, instruction execution, memory access, and result write-back.

[0046] The Central Processing Unit (CPU) is one of the main components of an electronic computer, a core part of the computer. Its primary function is to interpret computer instructions and process data in the computer software. The CPU is the core component responsible for reading, decoding, and executing instructions. The CPU mainly consists of two parts: the control unit and the arithmetic logic unit (ALU), which also includes high-speed cache memory and the data and control buses that connect them. The three core components of an electronic computer are the CPU, internal memory, and input / output devices. The CPU's main functions are processing instructions, executing operations, controlling timing, and processing data. In computer architecture, the CPU is the core hardware unit that controls and allocates all the computer's hardware resources (such as memory and input / output units) and performs general-purpose calculations. The CPU is the core of the computer's computation and control. All software operations in a computer system are ultimately mapped to CPU operations through the instruction set.

[0047] A graphics processing unit (GPU), also known as a display core, visual processor, or display chip, is a microprocessor specifically designed for performing image and graphics-related calculations on personal computers, workstations, game consoles, and some mobile devices (such as tablets and smartphones).

[0048] GPUs reduce the reliance of graphics cards on CPUs and perform some of the tasks that were originally handled by the CPU. Especially in 3D graphics processing, the core technologies used by GPUs include hardware T&L (geometry transformation and lighting processing), cubic environment material mapping and vertex blending, texture compression and bump mapping, dual-texture four-pixel 256-bit rendering engines, etc. Hardware T&L technology can be said to be the hallmark of GPUs.

[0049] A neural network processor (Antififcial Intelligence), also known as a neural network accelerator or computing card, or deep learning processor, is a module specifically designed to handle the massive computational tasks in intelligent applications (other non-computational tasks are still handled by the CPU). Much of the data processing in neural networks involves matrix multiplication and addition. GPUs, which perform massively parallel operations, offer a cost-effective approach, but at the cost of higher power consumption. FPGAs, with their built-in DSP modules and local memory, are more energy-efficient, but they are typically more expensive. Deep learning refers to multi-layered neural networks and the methods used to train them. In simple terms, a neural network processor uses deep neural networks to simulate the mechanisms of the human brain for learning, judgment, and decision-making.

[0050] A multi-core processor integrates two or more complete computing engines (cores) into a single processor. This allows the processor to support multiple processors on the system bus, with all bus control and command signals provided by the bus controller. The development of multi-core technology stemmed from engineers' realization that simply increasing the speed of a single-core chip would generate excessive heat without providing a corresponding performance improvement, as was the case with previous processors. They recognized that at those speeds, processors generated excessive heat. Even without the heat issue, the cost-effectiveness was unacceptable; slightly faster processors were significantly more expensive. The advantages of multi-core technology in applications are twofold: providing users with more powerful computing performance; and more importantly, meeting the requirements of users performing simultaneous multitasking and multi-tasking computing environments.

[0051] Heterogeneous computing refers to the ability of computing units using different instruction sets and architectures to "collaborate and accelerate each other," thereby breaking through the development bottlenecks of single processor architectures and effectively solving problems such as energy consumption and scalability. Common processor chips used in heterogeneous processors include CPUs, DSPs, GPUs, FPGAs, and ASICs. CPUs and GPUs require software support, while FPGAs and ASICs are integrated hardware and software architectures, where the software is the hardware. In terms of energy efficiency: ASIC > FPGA > GPU > CPU. The fundamental reason for this is that for computationally intensive algorithms, higher data transfer and computation efficiency result in higher energy efficiency. ASICs and FPGAs are closer to the underlying I / O, hence their high computational and data transfer efficiency. However, FPGAs have redundant transistors and interconnects, and operate at lower frequencies, thus their energy efficiency is not as high as ASICs. GPUs and CPUs are general-purpose processors that require instruction fetching, decoding, and execution. This process shields the underlying I / O, decoupling the hardware and software, but it limits the efficiency of data transfer and computation, resulting in lower energy efficiency compared to ASICs and FPGAs. The difference in energy efficiency between GPUs and CPUs is mainly due to the fact that a large portion of the transistors in a CPU are used for cache and control logic units. Therefore, for computationally intensive algorithms with low computational complexity, redundant transistors cannot be utilized, resulting in a lower energy efficiency for CPUs compared to GPUs.

[0052] Over their long development, processor chips have developed distinct characteristics in terms of usage and market presence. The CPU and GPU fields boast a wealth of open-source software and applications. Any new technology is initially implemented using CPU algorithms, making CPU programming resources abundant and readily available, resulting in low development costs and short development cycles. FPGA implementations utilize low-level hardware description languages ​​such as Verilog / VHDL, requiring developers to have a deep understanding of FPGA chip characteristics. However, their high parallelism often leads to orders-of-magnitude performance improvements. Furthermore, FPGAs are dynamically reconfigurable. Once deployed in a data center, different logic can be configured to implement different hardware acceleration functions based on business needs. For example, the FPGA board currently deployed on a server might be handling image compression logic for QQ services. If real-time advertising prediction requires expansion to obtain more FPGA computing resources, a simple FPGA reconfiguration process can transform the FPGA board into "new" hardware to serve real-time advertising prediction, making it ideal for batch deployment. ASIC chips can achieve optimal performance, namely high area utilization, high speed, and low power consumption; however, neural network SC development is extremely risky, requires a sufficiently large market to guarantee cost, and has a long time cycle from R&D to market, making it unsuitable for fields where algorithms such as deep learning CNN are rapidly iterating.

[0053] Based on the aforementioned background regarding artificial intelligence chips and artificial neural networks, the applicant, through long-term research and the collection and verification of experimental data, discovered that traditional artificial neural network mapping relies on external CPUs and compilers to map the network into the data flow mode supported by the AI ​​chip hardware. In other words, traditional AI chips often only support applications that accelerate the computation of a single neural network model. For each artificial neural network model, if compilation and computation are required within the AI ​​chip, corresponding designs for the chip's data flow and circuit layout are necessary. Therefore, current AI chips suffer from low flexibility in on-chip compilation and computation of artificial neural networks.

[0054] The technical solutions involved in the embodiments of this application will be described below in conjunction with the application scenarios.

[0055] It should be noted that the on-chip compilation method for models provided in this application can be executed by an on-chip compilation device, which can be implemented as part or all of the chip through software, hardware, or a combination of both. The chip can be an artificial intelligence chip, such as a CPU, DSP, GPU, FPGA, or ASIC. The chip may include upper-layer modules, a scalar engine, a vector engine, and an intelligent engine, which can be hardware components or components combining software and hardware. This chip can be applied to various smart devices, such as personal computers, laptops, smartphones, tablets, and IoT devices. This application does not specifically limit the application device of the chip. In the following method embodiments, the execution subject is always described as a chip.

[0056] In one embodiment, such as Figure 1 As shown, an on-chip compilation method for a model is provided and applied to the aforementioned chip, including the following steps:

[0057] Step 101: The upper-layer module in the chip obtains the artificial neural network model to be deployed in the chip.

[0058] This chip can be an artificial intelligence chip. It can include multiple modules, such as a scalar engine, an intelligent engine, a vector engine, and an upper-layer module. The scalar engine primarily controls the overall operation of the various modules within the chip. The vector engine performs batch processing on parallel data within the chip. The intelligent engine performs specific calculations on the data currently being processed by the chip. The upper-layer module is located above the scalar engine. For the artificial neural network model to be deployed on the chip for mapping, the upper-layer module can obtain the artificial neural network model and then perform on-chip compilation processing based on the scalar engine.

[0059] Step 102: The upper-layer module performs conversion processing on the artificial neural network model based on the instruction set built into the scalar engine in the chip, obtains multiple target instructions corresponding to the artificial neural network model, and sends the multiple target instructions to the scalar engine.

[0060] The scalar engine can be a RISCV (Reduced Instruction Set Computing V) processor. RISCV is an open-source instruction set architecture based on the principle of reduced instruction set computing. Based on this, the scalar engine incorporates pre-developed instruction sets for various artificial neural network models, which are essentially AI-specific vector instruction sets. Once executed, these target instructions can be used to perform compilation mapping, parameter revision, and model mapping calibration for artificial neural networks.

[0061] The upper-layer module can obtain multiple target instructions for compiling and processing the artificial neural network based on the artificial neural network to be deployed. The upper-layer module can send each target instruction to the scalar engine, which can then directly execute each target instruction, thereby realizing the compilation and processing of the artificial neural network to be processed by the chip.

[0062] Step 103: The scalar engine executes multiple target instructions to implement the compilation process corresponding to the artificial neural network model within the chip.

[0063] During chip operation, the scalar engine can receive target instructions. Optionally, the scalar engine can execute target instructions sent by the upper-layer module in sequence, or execute target instructions of the same type synchronously based on the type of each target instruction.

[0064] After executing the target instruction, the scalar engine performs the corresponding operation processing, thereby implementing the compilation processing of the artificial neural network model. Optionally, when the scalar engine executes the target instruction, the corresponding operation processing may include related vector calculations, mapping of the artificial neural network, parameter adjustment of the artificial neural network, scheduling of other modules in the chip, etc.

[0065] The aforementioned scalar engine processing method and apparatus for artificial intelligence chips involves an upper-layer module within the chip acquiring an artificial neural network model to be deployed on the chip. This upper-layer module then performs conversion processing on the artificial neural network model based on the instruction set built into the scalar engine within the chip, obtaining multiple target instructions corresponding to the artificial neural network model. These target instructions are then sent to the scalar engine. Furthermore, the scalar engine executes these multiple target instructions to perform the compilation processing corresponding to the artificial neural network model within the chip. Thus, because the scalar engine has a built-in instruction set that supports the conversion of artificial neural network models, for different types of artificial neural network models, the chip can directly convert the artificial neural network model to be processed into a data stream supported by the chip on-chip for subsequent compilation processing, without requiring an additional processor to perform data conversion. Furthermore, it eliminates the need to redesign the chip's circuit layout for different types of artificial neural network models, enabling the artificial intelligence chip to effectively support multiple artificial neural network mappings and on-chip compilation, effectively improving the flexibility of current artificial intelligence chips in mapping artificial neural network models and increasing the efficiency of on-chip compilation of artificial neural network models.

[0066] In one embodiment, the instruction set built into the scalar engine is developed based on the RISCV architecture, and each instruction set is identified by a different field.

[0067] As mentioned above, this scalar engine can be a RISC-CV processor, which supports various artificial neural network mappings and on-chip compilation, as well as on-chip instruction compilation and multi-level operations. Optionally, this scalar engine can be a single-processor 64-bit six-stage pipelined RV64GC application-level RISC-CV processor. Here, a single-processor 64-bit six-stage pipeline means that a single instruction is 64 bits long and the execution of a single instruction involves six steps.

[0068] Specifically, the RISC-CV architecture includes four basic instruction sets: RV32I, RV32E, RV64I, and RV128I, and dozens of extended instruction sets such as M, A, F, D, and C. Based on this, the embodiments of this application customize and extend a dedicated instruction set for vector computation and optimized artificial neural network compilation processing in artificial intelligence applications, and integrate it into the scalar engine.

[0069] Considering the open-source design characteristics of CPUs, this application uses RISC-V as the built-in processor. Leveraging the open-source, concise, and efficient nature of the RISC-V instruction set, a modular instruction set design approach is adopted, dividing instructions that implement different functions into blocks to obtain the various instruction sets supported by the scalar engine. Each instruction set may include a basic instruction set and extended instruction sets.

[0070] Since the scalar engine has multiple instruction sets built-in and is located inside the chip, the CPU processing and compilation process in the conventional technology can be built into the artificial intelligence chip in the embodiments of this application.

[0071] Furthermore, since the instruction set is built into the scalar engine and is specifically developed for the compilation and processing of artificial neural networks, and the operations implemented by the instructions included in different instruction sets belong to different types, in this embodiment, different fields are used to identify each instruction set. For example, a specified bit in each instruction is the field corresponding to the instruction set to which the instruction belongs, thereby making each instruction identified and easy to execute.

[0072] In this embodiment, the open-source RISCV is integrated into the chip to implement vector computation and support for scheduling instructions of other modules in the chip, as well as on-chip program compilation for different artificial neural networks, thereby achieving performance and flexibility optimization.

[0073] The format of each instruction in each instruction set is explained below.

[0074] In one embodiment, the first bit range of the target instruction is used to characterize the instruction set to which the target instruction belongs; the second bit range of the target instruction is used to characterize the target register address; the third bit range of the target instruction is used to characterize whether it is necessary to write to the target register and whether it is necessary to read from the source register; the fourth bit range of the target instruction is used to characterize the first source register address; the fifth bit range of the target instruction is used to characterize the second source register address; and the sixth bit range of the target instruction is used to characterize the opcode of the target instruction.

[0075] The target instructions belong to various instruction sets. Optionally, in this embodiment, the instructions in each instruction set can be in 32-bit encoding format. In this way, the instruction set can directly support the instructions already developed in the RISC-CV architecture, improving the efficiency of instruction set development. The format of the target instructions is shown in Table 1.

[0076] (Table 1)

[0077] 31 25 24 20 19 15 14 13 12 11 7 6 0 funct7 rs2 rs1 xd xs1 xs2 rd opcode

[0078] The first bit range is the opcode, used to characterize the instruction set to which the target instruction belongs. For example, a specific field for a vector computation instruction set is 000001, a specific field for an artificial neural network computation instruction set is 000010, and a specific field for a cross-module scheduling instruction set is 000011. It should be noted that other fields can also be used; the embodiments shown in this application are merely one example. Optionally, the first bit range includes bits 0 to 6 as shown in Table 1.

[0079] The second bit range, rd, represents the address of the target register corresponding to the target instruction, or it can be the number of the target register. Optionally, there are 32 registers, from 0 to register 31. Optionally, the second bit range includes bits 7 to 11 as shown in Table 1.

[0080] The third bit range, consisting of xs1, xs2, and xd, is used to indicate whether it is necessary to write to the destination register and whether it is necessary to read from the source register. Optionally, the third bit range may include 12 to 14 bits as shown in Table 1. Among them, xd is used to indicate whether it is necessary to write to the destination register rd; xs1 is used to indicate whether it is necessary to read from the source register rs1; and xs2 is used to indicate whether it is necessary to read from the source register rs2.

[0081] The fourth bit range is rs1, used to represent the address of the first source register, or it can be the number of the first source register. Optionally, there are 32 registers, from 0 to register 31. Optionally, the fourth bit range includes bits 15 to 19 as shown in Table 1.

[0082] The fifth bit range is rs2, used to represent the address of the second source register, or it can be the number of the first source register. Optionally, there are 32 registers, from 0 to register 31. Optionally, the fifth bit range includes bits 20 to 24 as shown in Table 1.

[0083] The sixth bit range, funct7, is used to represent the opcode of the target instruction. Based on this sixth bit range, more custom operations can be identified; optionally, a maximum of 512 custom instructions can be defined. For example, the sixth bit range includes bits 25 to 31 as shown in Table 1.

[0084] In this embodiment of the application, by setting the encoding format of the instruction set, the scalar engine can construct multiple instruction sets based on the existing conventional vector instructions, thereby effectively supporting various operations in the compilation process of artificial neural networks and effectively solving the problem of inflexible neural network mapping in current artificial intelligence chips.

[0085] In one embodiment, the instruction set includes a vector computation instruction set for implementing vector computation, an artificial neural network computation instruction set for implementing operations corresponding to various artificial neural networks, and a cross-module scheduling dedicated instruction set for other modules within the scalar engine scheduling chip to perform target operation processing.

[0086] The vector computation instruction set includes basic instructions and extended instructions designed in this embodiment. Basic instructions include, for example, vector addition, vector subtraction, vector multiplication, and vector size comparison, which can be developed in the RISC-CV architecture. The extended instructions are all vector instructions, and optionally, may include nine extended instructions. Descriptions of each extended instruction are shown in Table 2. In this embodiment, the vector computation instruction set may include multiple function instructions and multiple operation instructions. For example, the extended instructions in the vector computation instruction set may include two types of operation instructions as shown in Table 2: vector addition and vector multiplication, as well as three function instructions.

[0087] (Table 2)

[0088]

[0089]

[0090] In this context, "-" indicates that the space is empty.

[0091] The three function instructions mentioned above are the vset instruction for setting the vector length register, the vld instruction for loading a vector into the vector register set, and the vst instruction for extracting a vector from the vector register set, as shown in Table 2.

[0092] Vector addition instructions by default perform addition operations on a set of vectors already loaded into the vector register set (also known as the original vectors). The `vaddv` instruction fetches another set of vectors and adds it to the corresponding components of the original vectors. The `vadd` instruction fetches a scalar and adds it to each component of the original vectors, while the `vaddi` instruction adds an immediate value to each component of the original vectors.

[0093] Vector multiplication commands are similar to vector addition commands. The `vmulv` command retrieves another set of vectors and multiplies them correspondingly with the original vector. `vmul` retrieves a scalar and multiplies it with each component of the original vector. The `vmuli` command multiplies an immediate value with each component of the original vector.

[0094] The artificial neural network computation instruction set can implement some related operations to drive artificial neural networks, such as compiling artificial neural networks, mapping artificial neural networks, adjusting single or multiple weights of artificial neural networks, and selecting and remapping multiple artificial neural networks. Optionally, the descriptions of each instruction in the artificial neural network computation instruction set can be illustrated as shown in Table 3.

[0095] (Table 3)

[0096]

[0097]

[0098] The artificial neural network computation instructions sent by the upper-layer module are sent to the scalar engine, which then performs the corresponding data processing and schedules the internal computation processing modules to work.

[0099] Design a dedicated instruction set for cross-module scheduling, defining instructions and coordination instructions for cross-module scheduling, to achieve integrated computing and integrated scheduling capabilities. This allows the scalar engine to perform cross-module scheduling of other modules in the chip (such as the intelligent engine and the vector engine). For example, the scalar engine's scheduling of channels in the vector engine and the scheduling of logical judgment functions in the intelligent engine both require cross-module scheduling instructions and coordination instructions. Optionally, the descriptions of each instruction in the dedicated instruction set for cross-module scheduling can be illustrated in Table 4.

[0100] (Table 4)

[0101]

[0102]

[0103] The cross-module scheduling instructions sent by the upper-layer module are sent to the scalar engine, which then performs the corresponding data processing and schedules the computational processing module to work.

[0104] This application defines a new instruction set for artificial intelligence computing. Based on the developed instruction sets, it realizes on-chip instruction operations and algorithm compilation, supports scheduling instructions for intelligent engines and vector engines within the system, and compiles on-chip programs for different artificial neural networks, thereby optimizing and improving performance and flexibility, and enhancing the flexibility of using artificial intelligence chips.

[0105] Furthermore, to reduce resource overhead for irrelevant operations during chip computation, this application proposes a reconfigurable logic unit simplification mechanism. That is, by customizing reconfigurable logic units within the scalar engine, the scalar engine can switch from a normal computation flow to a reconfigurable computation flow under certain conditions, reducing resource overhead for irrelevant operations. Moreover, given the open-source nature of RISCCV, unnecessary resource overhead in the framework is eliminated to optimize energy efficiency during scalar engine computation. The reconfigurable logic unit simplification mechanism is explained below.

[0106] In one embodiment, such as Figure 2 As shown, it illustrates a flowchart of a refactoring process provided in an embodiment of this application. The on-chip compilation method for this model further includes:

[0107] Step 201: Determine the target type of the operation processing corresponding to the target instruction currently being executed by the scalar engine.

[0108] Step 202: If the target type is different from the type of operation currently corresponding to the reconfigurable array in the scalar engine, then the reconfigurable array is reconfigured.

[0109] Step 203: Use the reconfigurable array after reconstruction to process the currently executed target instruction.

[0110] The types of operations that can be processed by the reconfigurable array include at least addition and multiplication operations.

[0111] The scalar engine in the chip can determine the type of operation processing corresponding to the target instruction it is currently executing, and use it as the target type. For example, the type of operation processing corresponding to the target instruction currently being executed by the scalar engine can be an addition operation or a multiplication operation.

[0112] For reconfigurable arrays, the corresponding operation types must include at least addition and multiplication operations. Thus, the reconfigurable array can be reconfigured into an addition array when the scalar engine processes an addition operation, for the purpose of performing addition calculations. Similarly, when the reconfigurable array is processed by the scalar engine for multiplication operations, it can be reconfigured into a multiplication array, for the purpose of performing multiplication calculations.

[0113] Optionally, the reconfigurable array can be implemented based on hardware components or a combination of hardware and software components and integrated into the scalar engine.

[0114] Based on this, the scalar engine is normally in a normal computational flow, and its internal stater can be identified as such. When the target type of the operation corresponding to the currently processed target instruction is an addition or multiplication operation, the scalar engine switches to a reconfigurable computational flow, and its internal stater can be identified as such. At this time, if the type of operation that the reconfigurable array in the scalar engine can currently process is consistent with the target type, it can be directly used to process operations of that target type. For example, if both the target type and the type of operation that the reconfigurable array can currently process are addition operations, then the operation type of the reconfigurable array is reconfigured to the target type. In this way, it can be directly used to process operations corresponding to that target type. For example, if the target type corresponds to a multiplication operation, and the type of operation that the reconfigurable array currently processes is an addition operation, then it is reconfigured to process multiplication operations.

[0115] In this way, by introducing reconfigurable technology into the scalar engine, some of its logic units can be reconfigured. When performing addition operations, they can be reconfigured into addition arrays, and when performing multiplication operations, they can be reconfigured into multiplication arrays. This minimizes the number of logic units used to complete the necessary operations, ensuring chip functionality while reducing chip size and speeding up the scalar engine's processing speed.

[0116] In one embodiment, the scalar engine is designed based on a RISC-CV architecture instruction set, and it pre-defines and removes relevant useless logic, such as primitive logic unrelated to essential operations, vector computations, artificial intelligence operations, and optimization operations. This reduces the resource overhead of the scalar engine on useless computations, improving processing efficiency.

[0117] In this embodiment of the application, to further accelerate the processing speed of the scalar engine, the scalar engine is configured to reduce the pipeline processing steps of the target instruction under certain conditions. The specific details are as follows.

[0118] In one embodiment, the method further includes: if the operation processing corresponding to the target instruction currently being executed by the scalar engine meets the preset adjustment conditions, then the pipeline number of the target instruction being executed by the scalar engine is changed from the first pipeline number to the second pipeline number; wherein the second pipeline number is less than the first pipeline number.

[0119] In typical computational processing, the scalar engine executes target instructions through a six-stage pipeline. However, in specific computational processing scenarios, such as those involving artificial neural network computations or specific optimization operations, the execution process can be reduced from the conventional six-stage pipeline to a smaller number of stages, such as a three-stage or two-stage pipeline.

[0120] Optionally, the preset adjustment conditions may include, for example, cases where repeated data reading is performed, cases where the configuration does not need to be changed, and cases where a cross-module scheduling scheme corresponding to a cross-module scheduling dedicated instruction set is used.

[0121] Optionally, when the operation processing corresponding to the target instruction currently being executed by the scalar engine meets the preset adjustment conditions, it can be in a cross-pipeline call computation process, and its internal stater can be identified as a cross-pipeline call process.

[0122] Optionally, when the scalar engine completes the reconfigurable process and the cross-pipeline call process, the scalar engine triggers a computation termination instruction and sends the computation result to the interface for other modules to call the computation result.

[0123] In this embodiment of the application, when the preset adjustment conditions are met, the scalar engine speeds up the processing flow by skipping the pipeline stage of executing the target instruction, thereby reducing the resource overhead caused by the computation pipeline.

[0124] To facilitate understanding of the method of this application, a complete embodiment is provided below to fully illustrate a chip architecture scheme compatible with flexible mapping of multiple artificial neural networks. The flowchart of this scheme is shown below. Figure 3 As shown. Specifically includes:

[0125] Step 301: Deploy the vector computing instruction set, artificial neural network instruction set, and cross-module scheduling instruction set based on the RISCV architecture in the scalar engine of the chip.

[0126] Step 302: Remove useless logic from the scalar engine in the chip.

[0127] For example, logic unrelated to essential operations, vector computation, artificial intelligence operations, and optimization operations.

[0128] Step 303: Integrate a reconfigurable array into the scalar engine in the chip.

[0129] This reconfigurable array is used to reconstruct an addition array when performing an addition operation and a multiplication array when performing a multiplication operation.

[0130] Step 304: After the chip is powered on, the scalar engine enters standby mode.

[0131] In step 305, the scalar engine receives the target instruction sent from the upper layer, and its internal stater indicates a normal computation process. The target instruction is related to the artificial neural network model currently being compiled by the chip.

[0132] Step 306: If the operation processing type corresponding to the target instruction is the same as the operation processing type corresponding to the reconfigurable array, the reconfigurable array is used to complete the operation processing corresponding to the target instruction.

[0133] If the operation processing type corresponding to the target instruction is different from the operation processing type corresponding to the reconfigurable array, then the reconfigurable array is reconfigured, and the operation processing corresponding to the target instruction is completed using the reconfigurable array after reconfiguration.

[0134] Step 307: Identify whether the operation and processing status corresponding to the target instruction meets the preset adjustment conditions, and if so, adjust and reduce the pipeline number of the target instruction.

[0135] The preset adjustment conditions include, for example, cases where repeated data reading and configuration do not need to be changed, or cases involving the cross-module optimized scheduling scheme unique to this application. Furthermore, if the preset adjustment conditions are not met, the target instruction is executed using a conventional six-level pipeline.

[0136] Step 308: Execute the target instruction based on the pipeline number corresponding to the target instruction.

[0137] The chip architecture solution based on a scalar engine provided in this application, which is compatible with flexible mapping of various artificial neural networks, supports multiple artificial neural network mappings and on-chip compilation, effectively solving the problem of inflexible neural network mapping in current artificial intelligence chips. Developing a dedicated vector instruction set for artificial intelligence can expand support for vector computing for artificial intelligence applications and the optimized operations of this project. The reconfigurable logic unit simplification mechanism can reduce resource overhead for irrelevant operations and accelerate the processing speed of the scalar engine.

[0138] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0139] Based on the same inventive concept, this application also provides a model-on-chip compilation apparatus for implementing the model-on-chip compilation method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more model-on-chip compilation apparatus embodiments provided below can be found in the limitations of the model-on-chip compilation method described above, and will not be repeated here.

[0140] In one embodiment, such as Figure 4 As shown, an on-chip compilation device for a model is provided, which is applied in a chip. The on-chip compilation device 400 includes: an acquisition module 401, a conversion module 402, and an execution module 403, wherein:

[0141] The acquisition module 401 is used by the upper-layer module in the chip to acquire the artificial neural network model to be deployed in the chip;

[0142] The conversion module 402 is used by the upper-layer module to perform conversion processing on the artificial neural network model based on the instruction set built into the scalar engine in the chip, to obtain multiple target instructions corresponding to the artificial neural network model, and to send the multiple target instructions to the scalar engine;

[0143] The execution module 403 is used by the scalar engine to execute the plurality of target instructions to implement the compilation process corresponding to the artificial neural network model within the chip.

[0144] In one embodiment, the instruction set includes a vector computation instruction set for implementing vector computation, an artificial neural network computation instruction set for implementing operations corresponding to various artificial neural networks, and a cross-module scheduling dedicated instruction set for other modules within the scalar engine scheduling chip to perform target operation processing.

[0145] In one embodiment, the vector computation instruction set includes multiple function instructions and multiple operation instructions.

[0146] In one embodiment, the instruction set built into the scalar engine is developed based on the RISCV architecture, and each instruction set is identified by a different field.

[0147] In one embodiment, the first bit range of the target instruction is used to characterize the instruction set to which the target instruction belongs; the second bit range of the target instruction is used to characterize the target register address; the third bit range of the target instruction is used to characterize whether it is necessary to write to the target register and whether it is necessary to read from the source register; the fourth bit range of the target instruction is used to characterize the first source register address; the fifth bit range of the target instruction is used to characterize the second source register address; and the sixth bit range of the target instruction is used to characterize the opcode of the target instruction.

[0148] In one embodiment, such as Figure 5 As shown, another model on-chip compilation device 500 is illustrated, which further includes a refactoring module 404, wherein:

[0149] The refactoring module 404 is used to determine the target type of the operation processing corresponding to the target instruction currently being executed by the scalar engine; if the target type is different from the type of operation processing currently corresponding to the refactorable array in the scalar engine, the refactorable array is refactored; the refactored refactorable array is used to process the currently executed target instruction; wherein, the type of operation processing corresponding to the refactorable array includes at least addition and multiplication operations.

[0150] In one embodiment, the device 500 further includes a modification module 405, wherein:

[0151] Modification module 405 is used to change the pipeline number of the target instruction executed by the scalar engine from the first level to the second level if the operation processing corresponding to the target instruction currently being executed by the scalar engine meets the preset adjustment conditions; wherein the second level is less than the first level.

[0152] Each module in the aforementioned on-chip compilation device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of a computer device, so that the processor can call and execute the operations corresponding to each module.

[0153] In one embodiment, a chip is provided, the internal structure of which can be shown as follows: Figure 6 As shown, the chip includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores on-chip compilation data for the model. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements an on-chip compilation method for the model.

[0154] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the solution of this application and does not constitute a limitation on the chip to which the solution of this application is applied. The specific chip may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0155] In one embodiment, a chip is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0156] The upper-layer module in the chip acquires the artificial neural network model to be deployed in the chip;

[0157] The upper-layer module uses the instruction set built into the scalar engine in the chip to transform the artificial neural network model, obtain multiple target instructions corresponding to the artificial neural network model, and send the multiple target instructions to the scalar engine.

[0158] The scalar engine executes multiple target instructions to perform the compilation and processing of artificial neural network models within the chip.

[0159] In one embodiment, the instruction set includes a vector computation instruction set for implementing vector computation, an artificial neural network computation instruction set for implementing operations corresponding to various artificial neural networks, and a cross-module scheduling dedicated instruction set for other modules within the scalar engine scheduling chip to perform target operation processing.

[0160] In one embodiment, the vector computation instruction set includes multiple function instructions and multiple operation instructions.

[0161] In one embodiment, the instruction set built into the scalar engine is developed based on the RISCV architecture, and each instruction set is identified by a different field.

[0162] In one embodiment, the first bit range of the target instruction is used to characterize the instruction set to which the target instruction belongs; the second bit range of the target instruction is used to characterize the target register address; the third bit range of the target instruction is used to characterize whether it is necessary to write to the target register and whether it is necessary to read from the source register; the fourth bit range of the target instruction is used to characterize the first source register address; the fifth bit range of the target instruction is used to characterize the second source register address; and the sixth bit range of the target instruction is used to characterize the opcode of the target instruction.

[0163] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0164] Determine the target type of the operation processing corresponding to the target instruction currently being executed by the scalar engine; if the target type is different from the type of operation processing currently corresponding to the reconfigurable array in the scalar engine, then reconfigure the reconfigurable array; use the reconfigurable array after reconfiguration to process the currently executed target instruction; wherein, the type of operation processing corresponding to the reconfigurable array includes at least addition and multiplication operations.

[0165] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0166] If the operation processing corresponding to the target instruction currently being executed by the scalar engine meets the preset adjustment conditions, then the pipeline number of the target instruction executed by the scalar engine will be changed from the first level to the second level; wherein the second level is less than the first level.

[0167] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0168] The upper-layer module in the chip acquires the artificial neural network model to be deployed in the chip;

[0169] The upper-layer module uses the instruction set built into the scalar engine in the chip to transform the artificial neural network model, obtain multiple target instructions corresponding to the artificial neural network model, and send the multiple target instructions to the scalar engine.

[0170] The scalar engine executes multiple target instructions to perform the compilation and processing of artificial neural network models within the chip.

[0171] In one embodiment, the instruction set includes a vector computation instruction set for implementing vector computation, an artificial neural network computation instruction set for implementing operations corresponding to various artificial neural networks, and a cross-module scheduling dedicated instruction set for other modules within the scalar engine scheduling chip to perform target operation processing.

[0172] In one embodiment, the vector computation instruction set includes multiple function instructions and multiple operation instructions.

[0173] In one embodiment, the instruction set built into the scalar engine is developed based on the RISCV architecture, and each instruction set is identified by a different field.

[0174] In one embodiment, the first bit range of the target instruction is used to characterize the instruction set to which the target instruction belongs; the second bit range of the target instruction is used to characterize the target register address; the third bit range of the target instruction is used to characterize whether it is necessary to write to the target register and whether it is necessary to read from the source register; the fourth bit range of the target instruction is used to characterize the first source register address; the fifth bit range of the target instruction is used to characterize the second source register address; and the sixth bit range of the target instruction is used to characterize the opcode of the target instruction.

[0175] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0176] Determine the target type of the operation processing corresponding to the target instruction currently being executed by the scalar engine; if the target type is different from the type of operation processing currently corresponding to the reconfigurable array in the scalar engine, then reconfigure the reconfigurable array; use the reconfigurable array after reconfiguration to process the currently executed target instruction; wherein, the type of operation processing corresponding to the reconfigurable array includes at least addition and multiplication operations.

[0177] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0178] If the operation processing corresponding to the target instruction currently being executed by the scalar engine meets the preset adjustment conditions, then the pipeline number of the target instruction executed by the scalar engine will be changed from the first level to the second level; wherein the second level is less than the first level.

[0179] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0180] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0181] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0182] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for on-chip compilation of a model, characterized in that, When applied to a chip, the method includes: The upper-layer module in the chip acquires the artificial neural network model to be deployed in the chip; The upper-layer module performs transformation processing on the artificial neural network model based on the instruction set built into the scalar engine in the chip, obtains multiple target instructions corresponding to the artificial neural network model, and sends the multiple target instructions to the scalar engine; the instruction set includes a vector calculation instruction set for implementing vector calculation, an artificial neural network calculation instruction set for implementing operation operations corresponding to various artificial neural networks, and a cross-module scheduling dedicated instruction set for the scalar engine to schedule other modules in the chip to perform target operation processing; The scalar engine executes the plurality of target instructions to implement the compilation process corresponding to the artificial neural network model within the chip; Determine the target type of the operation processing corresponding to the target instruction currently being executed by the scalar engine; If the target type is different from the type of operation currently corresponding to the reconfigurable array in the scalar engine, then the reconfigurable array is reconfigured. The reconfigurable array after reconstruction processing is used to operate on the currently executing target instruction; The types of operations processed by the reconfigurable array include at least addition and multiplication operations.

2. The method according to claim 1, characterized in that, The vector calculation instruction set includes multiple function instructions and multiple operation instructions.

3. The method according to claim 1 or 2, characterized in that, The instruction set built into the scalar engine is developed based on the RISCV architecture, and each instruction set is identified by a different field.

4. The method according to claim 3, characterized in that, The first bit range of the target instruction is used to characterize the instruction set to which the target instruction belongs; The second bit range of the target instruction is used to characterize the target register address; The third bit range of the target instruction is used to characterize whether it is necessary to write to the target register and whether it is necessary to read from the source register; The fourth bit range of the target instruction is used to characterize the address of the first source register; The fifth bit range of the target instruction is used to characterize the address of the second source register; The sixth bit range of the target instruction is used to represent the opcode of the target instruction.

5. The method according to claim 1, characterized in that, The method further includes: If the operation processing corresponding to the target instruction currently being executed by the scalar engine meets the preset adjustment conditions, then the pipeline number of the scalar engine executing the target instruction is changed from the first pipeline number to the second pipeline number; wherein the second pipeline number is less than the first pipeline number.

6. The method according to claim 1, characterized in that, The reconfigurable array is reconfigured into an addition operation when the scalar engine processes the addition operation, and is used to perform the calculation of the addition operation; The reconfigurable array is reconfigured into a multiplication operation when the scalar engine processes the multiplication operation, and is used to perform the multiplication operation calculation.

7. The method according to claim 1, characterized in that, The instructions in each instruction set are in 32-bit encoded format.

8. A model on-chip compilation device, characterized in that, The device, used in a chip, includes: An acquisition module is used by the upper-layer module in the chip to acquire the artificial neural network model to be deployed in the chip; The conversion module is used by the upper-layer module to convert the artificial neural network model based on the instruction set built into the scalar engine in the chip, to obtain multiple target instructions corresponding to the artificial neural network model, and to send the multiple target instructions to the scalar engine; the instruction set includes a vector calculation instruction set for implementing vector calculation, an artificial neural network calculation instruction set for implementing operation operations corresponding to various artificial neural networks, and a cross-module scheduling dedicated instruction set for the scalar engine to schedule other modules in the chip to perform target operation processing; An execution module is used by the scalar engine to execute the plurality of target instructions to implement the compilation process corresponding to the artificial neural network model within the chip; The reconfiguration module is used to determine the target type of the operation processing corresponding to the target instruction currently being executed by the scalar engine; if the target type is different from the type of operation processing currently corresponding to the reconfigurable array in the scalar engine, the reconfigurable array is reconfigured; the reconfigurable array after reconfiguration is used to process the currently executed target instruction; wherein the type of operation processing corresponding to the reconfigurable array includes at least addition and multiplication operations.

9. A chip comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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