Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a device surface and a back surface; an isolation groove formed on the back surface of the substrate and extending from the back surface of the substrate to the device surface; and a high dielectric layer covering at least the isolation groove. The high dielectric layer comprises at least two dielectric sub-layers, the material of each dielectric sub-layer is different from that of the adjacent dielectric sub-layer to form an interface between each two adjacent dielectric sub-layers, and at least part of the dielectric sub-layers are high dielectric sub-layers. The technical scheme provided by the application can better isolate electrons and reduce the electron crosstalk on both sides of the high dielectric layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor device and its manufacturing process. Background Technology

[0002] With the development of semiconductor technology, the combination of deep trench isolation (DTI) and high-k dielectric (HIK) deposition technologies can improve the optical performance of image sensors to a certain extent. However, in these technologies, the high-k dielectric layer (HIK layer) at the trench is usually a single-layer structure made of high-k dielectric material, which cannot effectively prevent electronic crosstalk between its two sides. Summary of the Invention

[0003] This application provides a semiconductor device, comprising: a substrate including opposing device surfaces and a back surface; an isolation trench formed on the back surface of the substrate and extending from the back surface of the substrate toward the device surface; and a high-dielectric layer at least covering the isolation trench, wherein the high-dielectric layer includes at least two dielectric sublayers, each dielectric sublayer being made of a different material than the adjacent dielectric sublayers to form an interface between every two adjacent dielectric sublayers, and at least a portion of the dielectric sublayers being high-dielectric sublayers.

[0004] Furthermore, the high-dielectric sublayer is a material with a relative permittivity higher than that of silicon dioxide.

[0005] Furthermore, the high-dielectric layer comprises three or four dielectric sublayers.

[0006] Furthermore, the high-dielectric layer includes at least two high-dielectric sublayers, wherein the at least two high-dielectric sublayers are stacked sequentially, and each high-dielectric sublayer is made of a different material from its adjacent high-dielectric sublayers to form an interface between them; and / or the high-dielectric layer includes at least two high-dielectric sublayers and at least one ordinary dielectric sublayer, wherein the at least two high-dielectric sublayers and at least one ordinary dielectric sublayer are stacked sequentially, and an ordinary dielectric sublayer is disposed between two adjacent high-dielectric sublayers of the same material to form multiple interfaces between them, wherein the ordinary dielectric sublayer is a material with a relative permittivity not higher than that of silicon dioxide.

[0007] Furthermore, the dielectric sublayer furthest from the substrate is the tantalum oxide dielectric sublayer.

[0008] Furthermore, the high-dielectric layer includes a first alumina dielectric sublayer, a silicon oxide dielectric sublayer, a second alumina dielectric sublayer, and a tantalum oxide dielectric sublayer, which sequentially cover the back side of the substrate and the isolation trench.

[0009] Furthermore, the thickness of the tantalum oxide dielectric sublayer is between 400-600 Å; the sum of the thicknesses of the first alumina dielectric sublayer, the silicon oxide dielectric sublayer, and the second alumina dielectric sublayer is between 60-120 Å.

[0010] Furthermore, the thickness of the tantalum oxide dielectric sublayer is 520 Å; the thickness of each dielectric sublayer in the first alumina dielectric sublayer, silicon oxide dielectric sublayer, and second alumina dielectric sublayer is 30 Å.

[0011] Furthermore, the semiconductor device further includes: an isolation layer disposed between isolation trenches of a high-dielectric layer; and / or a dielectric sublayer closest to the substrate is a high-dielectric sublayer.

[0012] Furthermore, the semiconductor device further includes: a planarization layer covering the high-dielectric layer.

[0013] Furthermore, the substrate is a CMOS image sensor wafer or chip, and isolation trenches are set between two adjacent photosensitive pixels in the substrate to avoid crosstalk between two adjacent photosensitive pixels.

[0014] Another aspect of this application provides a semiconductor device fabrication method, comprising: providing a substrate, wherein the substrate includes opposing device surfaces and back surfaces; forming an isolation trench on the back surface of the substrate, wherein the isolation trench extends in a direction from the back surface of the substrate toward the device surface; covering at least the isolation trench with a high-dielectric layer, wherein the high-dielectric layer includes at least two dielectric sublayers, each dielectric sublayer being made of a different material than adjacent dielectric sublayers to form an interface between every two adjacent dielectric sublayers, and at least a portion of the dielectric sublayers being high-dielectric sublayers.

[0015] Furthermore, the high-dielectric layer includes at least two high-dielectric sublayers, wherein the at least two high-dielectric sublayers are stacked sequentially, and each high-dielectric sublayer is made of a different material from the adjacent high-dielectric sublayer to form an interface between them; and / or the high-dielectric layer includes at least two high-dielectric sublayers and at least one ordinary dielectric sublayer, wherein the at least two high-dielectric sublayers and at least one ordinary dielectric sublayer are stacked sequentially, and an ordinary dielectric sublayer is disposed between two adjacent high-dielectric sublayers to form multiple interfaces between them.

[0016] Furthermore, before at least covering the isolation trench with a high-dielectric layer, the method further includes: forming an isolation layer on the isolation trench, wherein the isolation layer is located between the high-dielectric layer and the isolation trench.

[0017] Furthermore, forming an isolation layer on the isolation trench includes: treating the inner wall surface of the isolation trench with ozone gas, and growing a silicon oxide layer in situ on the inner wall surface of the isolation trench through a wet oxidation process.

[0018] Furthermore, the formation of the isolation layer and the formation of the dielectric sublayer closest to the substrate are achieved within the same machine.

[0019] In the scheme of this application, the high dielectric layer includes at least two dielectric sublayers, at least some of which are high dielectric sublayers. The material of each dielectric sublayer is different from that of the adjacent dielectric sublayers, so as to form an interface between every two adjacent dielectric sublayers, thereby better isolating electrons and reducing electron crosstalk on both sides of the high dielectric layer. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0021] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application;

[0022] Figure 2 yes Figure 1 A magnified schematic diagram of local structure A in the middle;

[0023] Figure 3 This is a schematic diagram of another embodiment of the semiconductor device of this application;

[0024] Figure 4 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method of this application;

[0025] Figure 5 This is a schematic diagram of a structure in which isolation trenches are formed on the back side of the substrate;

[0026] Figure 6 This is a schematic diagram of a structure in which an isolation layer is formed on the back side of the substrate and on the isolation trench;

[0027] Figure 7 This is a schematic diagram of the structure in which the first alumina dielectric layer is formed on the isolation layer;

[0028] Figure 8 This is a schematic diagram of a structure in which a silicon oxide dielectric sublayer is formed on a first alumina dielectric layer;

[0029] Figure 9 This is a schematic diagram of the structure in which a second alumina dielectric sublayer is formed on a silicon oxide dielectric sublayer;

[0030] Figure 10 This is a schematic diagram of the structure in which a tantalum oxide dielectric sublayer is formed on the second alumina dielectric sublayer. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0032] This application provides a semiconductor device 100. For example... Figure 1 As shown, Figure 1 This is a schematic diagram of a semiconductor device 100 according to an embodiment of this application. The semiconductor device 100 may include a substrate 10, an isolation trench 20, and a high-dielectric layer 30. The substrate 10 includes a device surface 10a and a back surface 10b. The isolation trench 20 is formed on the back surface 10b of the substrate 10 and extends from the back surface 10b of the substrate 10 towards the device surface 10a. The high-dielectric layer 30 at least covers the isolation trench 20, and the high-dielectric layer 30 includes at least two dielectric sublayers 31 (labeled as shown in the diagram). Figure 2 In this embodiment, each dielectric sublayer 31 is made of a different material than its adjacent counterparts to form an interface between any two adjacent dielectric sublayers 31, and at least a portion of the dielectric sublayers 31 are high-dielectric dielectric sublayers. In some embodiments, the high-dielectric dielectric layer 30 covers the back surface 10b of the substrate 10 and the isolation trench 20. In some embodiments, the high-dielectric dielectric layer 30 may only cover the isolation trench 20. This application does not limit this, and those skilled in the art can choose according to actual needs. The following embodiments of this application illustrate the use of a high-dielectric dielectric layer 30 covering the back surface 10b of the substrate 10 and the isolation trench 20. The substrate 10 may be a silicon substrate or a germanium substrate. This application does not limit this, and those skilled in the art can choose according to actual needs. The substrate 10 may be a chip or a wafer.

[0033] The high-dielectric sublayer is a material with a relative permittivity higher than that of silicon dioxide. For example, the material of the high-dielectric sublayer may include at least one of Al2O3, Ta2O5, ZrO2, LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Si3N4, TiO2, and oxynitrides. This application does not limit the choice of materials, and those skilled in the art can select materials according to actual needs.

[0034] In the scheme of this application, the high dielectric layer 30 includes at least two dielectric sublayers 31, at least some of the dielectric sublayers 31 are high dielectric sublayers, and the material of each dielectric sublayer 31 is different from that of the adjacent dielectric sublayers 31, so as to form an interface between every two adjacent dielectric sublayers 31, thereby better isolating electrons and reducing electron crosstalk on both sides of the high dielectric layer 30.

[0035] Specifically, the substrate 10 can be a CMOS image sensor wafer or chip. For example... Figure 2 As shown, Figure 2 yes Figure 1 The enlarged structural diagram of local structure A shows that the substrate 10 may include multiple photosensitive pixels 11, which can be arranged in an array. Isolation trenches 20 are disposed between every two adjacent photosensitive pixels 11 to avoid electronic crosstalk between adjacent photosensitive pixels 11, prevent the generation of dark current, and thus reduce the possibility of forming white pixels.

[0036] Specifically, the isolation trench 20 can extend from the back surface 10b of the substrate 10 toward the device surface 10a and extend between two adjacent photosensitive pixels 11 to form an isolation between the two adjacent photosensitive pixels 11. The high-dielectric layer 30 can cover the back surface 10b of the substrate 10 and the inner wall surface of the isolation trench 20.

[0037] like Figure 2 As shown, the semiconductor device 100 may further include an isolation layer 32, which is disposed between the high-dielectric layer 30 and the back surface 10b of the substrate 10 and the isolation trench 20 (i.e., the isolation layer 32 is disposed between the high-dielectric layer 30 and the back surface 10b of the substrate 10 and between the high-dielectric layer 30 and the inner wall surface of the isolation trench 20). Specifically, the isolation layer 32 may be a silicon oxide layer (Steam OX) formed by a wet oxidation process, mainly serving an adhesion function, so that the high-dielectric layer 30 can be reliably attached to the back surface 10b of the substrate 10 and the inner wall surface of the isolation trench 20.

[0038] In some embodiments, in the high dielectric layer 30, the dielectric sublayer 31 closest to the substrate 10 can be a high dielectric sublayer. The high dielectric sublayer can form an interface with the isolation layer 32, thereby further increasing the number of interfaces, which is beneficial for better isolation of electrons, reducing electron crosstalk on both sides of the high dielectric layer 30, avoiding the generation of dark current, and reducing the possibility of forming white pixels.

[0039] In some embodiments, the dielectric sublayer 31 furthest from the substrate 10 in the high-dielectric dielectric layer 30 may be a tantalum oxide dielectric sublayer (TaO). The tantalum oxide dielectric sublayer may include any one or more oxides of tantalum, which is not limited in this application, and those skilled in the art can choose according to actual needs.

[0040] When the tantalum oxide dielectric sublayer is used as the dielectric sublayer 31 furthest from the substrate 10, the tantalum oxide dielectric sublayer is furthest from the photosensitive pixel 11, which is beneficial to improve the flat band voltage. Furthermore, due to the increase in the number of interfaces, the electronic crosstalk on both sides of the high dielectric layer 30 can be effectively reduced, the generation of dark current can be avoided, and the possibility of forming white pixels can be reduced.

[0041] In some embodiments, the high-dielectric layer 30 may include two dielectric sublayers 31. Specifically, the high-dielectric layer 30 may include an alumina dielectric sublayer (AlO) and a tantalum oxide dielectric sublayer (TaO) sequentially covering the back surface 10b of the substrate 10 and the isolation trench 20. The alumina dielectric sublayer is the dielectric sublayer 31 closest to the substrate 10, and the tantalum oxide dielectric sublayer is the dielectric sublayer 31 furthest from the substrate 10. In this case, an interface is formed between the isolation layer 32 and the alumina dielectric sublayer, and another interface is formed between the alumina dielectric sublayer and the tantalum oxide dielectric sublayer. Compared to existing technologies, this approach can, to some extent, prevent the generation of dark current.

[0042] In some embodiments, the high-dielectric layer 30 may include three or four dielectric sublayers 31, each of which is made of a different material than its adjacent counterparts, thereby increasing the number of interfaces and achieving better isolation. It should be noted that, through long-term research, those skilled in the art have found that further increasing the number of dielectric sublayers 31 in the high-dielectric layer 30 is actually detrimental to improving the isolation effect. This is because, when the number of dielectric sublayers 31 in the high-dielectric layer 30 increases further, the thickness of each dielectric sublayer 31 will relatively decrease to control the overall device size, leading not only to increased processing difficulty but also to reduced device reliability.

[0043] In some embodiments, the high-dielectric layer 30 includes at least two high-dielectric sublayers and at least one ordinary dielectric sublayer 31, wherein the at least two high-dielectric sublayers and at least one ordinary dielectric sublayer 31 are stacked sequentially, and an ordinary dielectric sublayer 31 is disposed between two adjacent high-dielectric sublayers of the same material to form multiple interfaces between them. The ordinary dielectric sublayer 31 is a material with a relative permittivity not higher than that of silicon dioxide. For example, the material of the ordinary dielectric sublayer 31 can be silicon dioxide; this application does not limit this, and those skilled in the art can choose according to actual needs.

[0044] Specifically, such as Figure 2 As shown, the high-dielectric layer 30 may include a first alumina dielectric sublayer 311 (AlO), a silicon oxide dielectric sublayer 312 (OX), a second alumina dielectric sublayer 313 (AlO), and a tantalum oxide dielectric sublayer 314 (TaO) sequentially covering the back surface 10b of the substrate 10 and the isolation trench 20. The first alumina dielectric sublayer 311 is the dielectric sublayer 31 closest to the substrate 10, and the tantalum oxide dielectric sublayer 314 is the dielectric sublayer 31 furthest from the substrate 10.

[0045] Regarding thickness, both excessively large and small thicknesses of the dielectric sublayers 31 may adversely affect device performance. Furthermore, excessively large thicknesses of the dielectric sublayers 31 can also lead to an increase in device size. For example, the thickness of the tantalum oxide dielectric sublayer 314 can be between 400-600 Å, and the combined thickness of the first alumina dielectric sublayer 311, the silicon oxide dielectric sublayer 312, and the second alumina dielectric sublayer 313 can be between 60-120 Å, in order to minimize device size while ensuring device performance.

[0046] Furthermore, the thickness of the tantalum oxide dielectric sublayer 314 can be 520 Å, and the thickness of each dielectric sublayer 31 in the first alumina dielectric sublayer 311, silicon oxide dielectric sublayer 312, and second alumina dielectric sublayer 313 is 30 Å, so as to achieve relatively better device performance and make the overall size of the semiconductor device 100 relatively small.

[0047] In terms of materials, the first alumina dielectric sublayer 311 and the second alumina dielectric sublayer 313 can be made of the same material, which may include any one or more of aluminum oxides. The silicon oxide dielectric sublayer 312 may include any one or more of silicon oxides. The tantalum oxide dielectric sublayer 314 may include any one or more of tantalum oxides. This application does not limit this, and those skilled in the art can choose according to actual needs.

[0048] like Figure 2 As shown, at this time, a first interface is formed between the isolation layer 32 and the first alumina dielectric sublayer 311, a second interface is formed between the first alumina dielectric sublayer 311 and the silicon oxide dielectric sublayer 312, a third interface is formed between the silicon oxide dielectric sublayer 312 and the second alumina dielectric sublayer 313, and a fourth interface is formed between the second alumina dielectric sublayer 313 and the tantalum oxide dielectric sublayer 314. Multiple interfaces are beneficial for better isolation of electrons, reducing electron crosstalk on both sides of the high dielectric layer 30, avoiding the generation of dark current, and reducing the possibility of forming white pixels.

[0049] Figure 2In the illustrated embodiment, the structure composed of the isolation layer 32 and the high-dielectric layer 30 meets the requirements of a conventional backlight layer structure, and its defect density also meets the requirements of a conventional backlight layer. Compared to solutions in related technologies, Figure 2 The illustrated embodiment can reduce white pixels by 9.3% and increase flat band voltage by 11.1%, significantly improving device performance.

[0050] In some embodiments, the high-dielectric layer 30 includes at least two high-dielectric sublayers, wherein the at least two high-dielectric sublayers are stacked together in sequence, and each high-dielectric sublayer is made of a different material from the adjacent high-dielectric sublayer to form an interface between them.

[0051] For example, the high-dielectric layer 30 may include a first alumina dielectric sublayer (AlO), a first tantalum oxide dielectric sublayer (TaO), a second alumina dielectric sublayer (AlO), and a second tantalum oxide dielectric sublayer (TaO) sequentially covering the back surface 10b of the substrate 10 and the isolation trench 20. The first alumina dielectric sublayer is the dielectric sublayer 31 closest to the substrate 10, and the second tantalum oxide dielectric sublayer is the dielectric sublayer 31 furthest from the substrate 10.

[0052] Regarding thickness, both excessively large and small thicknesses of the dielectric sublayers 31 may adversely affect device performance. Furthermore, excessively large thicknesses of the dielectric sublayers 31 can also lead to an increase in device size. The thickness of the second tantalum oxide dielectric sublayer can be between 400-600 Å, and the sum of the thicknesses of the first alumina dielectric sublayer, the first tantalum oxide dielectric sublayer, and the second alumina dielectric sublayer can be between 60-120 Å, in order to minimize device size while ensuring device performance.

[0053] Furthermore, the thickness of the second tantalum oxide dielectric sublayer can be 520 Å, and the thickness of each dielectric sublayer 31 in the first alumina dielectric sublayer, the first tantalum oxide dielectric sublayer, and the second alumina dielectric sublayer is 30 Å, in order to achieve relatively better device performance and make the overall size of the semiconductor device 100 relatively small.

[0054] Regarding the materials, the first alumina dielectric sublayer and the second alumina dielectric sublayer can be made of the same material, which can include any one or more of aluminum oxides. The first tantalum oxide dielectric sublayer and the second tantalum oxide dielectric sublayer can also be made of the same material, which can include any one or more of tantalum oxides. This application does not impose any restrictions on this, and those skilled in the art can choose according to actual needs.

[0055] For example, the high-dielectric layer 30 may include a lanthanum oxide dielectric sublayer (LaO), an aluminum oxide dielectric sublayer (AlO), and a tantalum oxide dielectric sublayer (TaO) sequentially covering the back surface 10b of the substrate 10 and the isolation trench 20. The lanthanum oxide dielectric sublayer is the dielectric sublayer 31 closest to the substrate 10, and the tantalum oxide dielectric sublayer is the dielectric sublayer 31 furthest from the substrate 10. The lanthanum oxide dielectric sublayer may include any one or more oxides of lanthanum; details are omitted here as they are readily understood by those skilled in the art.

[0056] like Figure 2 As shown, the semiconductor device 100 may further include a planarization layer 33 covering the high-dielectric layer 30. Specifically, the planarization layer 33 may be a silicon oxide layer (ALD OX) formed by atomic layer deposition (ALD) to protect the back surface 10b of the substrate 10.

[0057] like Figure 3 As shown, Figure 3 This is a schematic diagram of another embodiment of the semiconductor device 100 of this application. In some embodiments, the substrate 10 may be a CMOS image sensor wafer or chip, and specifically includes a pixel region 110 and a peripheral circuit region 120. An array of multiple photosensitive pixels 11 is disposed in the pixel region 110, and the peripheral circuit region 120 is disposed around the pixel region 110 for housing logic circuits and other circuit elements of the substrate 10. An isolation trench 20 may also be disposed between the pixel region 110 and the peripheral circuit region 120 to avoid the generation of dark current between the pixel region 110 and the peripheral circuit region 120, thereby reducing the possibility of forming white pixels.

[0058] This application also provides a process method for manufacturing a semiconductor device 100. For example... Figure 4 As shown, Figure 4 This is a schematic flowchart of an embodiment of the manufacturing process of the semiconductor device 100 of this application. Specifically, the manufacturing process may include the following steps:

[0059] S100: A substrate 10 is provided, wherein the substrate 10 includes opposing device surfaces 10a and back surfaces 10b.

[0060] For example, the substrate 10 may be a CMOS image sensor wafer or chip, which may include a plurality of photosensitive pixels 11. Figure 5 (Not shown in the image), multiple photosensitive pixels 11 can be arranged in an array. This application does not limit this, and those skilled in the art can choose according to actual needs.

[0061] S200: An isolation trench 20 is formed on the back surface 10b of the substrate 10, wherein the isolation trench 20 extends in a direction from the back surface 10b of the substrate 10 toward the device surface 10a.

[0062] like Figure 5 As shown, Figure 5 This is a schematic diagram of an isolation trench 20 formed on the back surface 10b of the substrate 10. The isolation trench 20 can be formed by etching. The specific etching process is readily understood by those skilled in the art and will not be described in detail here.

[0063] S300: A high-dielectric dielectric layer 30 is at least covered on the isolation trench 20, wherein the high-dielectric dielectric layer 30 includes at least two dielectric sublayers 31, each dielectric sublayer 31 having a different material from the adjacent dielectric sublayers 31 to form an interface between every two adjacent dielectric sublayers 31, and at least a portion of the dielectric sublayers 31 are high-dielectric dielectric sublayers. Specifically, prior to S300, the process method further includes:

[0064] S210: An isolation layer 32 is formed on the back surface 10b of the substrate 10 and the isolation trench 20, wherein the isolation layer 32 is located between the high dielectric layer 30 and the back surface 10b of the substrate 10 and the isolation trench 20.

[0065] like Figure 6 As shown, Figure 6 This is a schematic diagram of the structure in which an isolation layer 32 is formed on the back surface 10b of the substrate 10 and the isolation trench 20. In some embodiments, S210 can be specifically implemented by the following steps: depositing a silicon oxide layer on the back surface 10b of the substrate 10 and the inner wall surface of the isolation trench 20 by a decoupled plasma oxidation process (DPO).

[0066] In some embodiments, S210 can be implemented by the following steps: treating the back surface 10b of the substrate 10 and the inner wall surface of the isolation trench 20 with ozone gas, and growing a silicon oxide layer in situ on the back surface 10b of the substrate 10 and the inner wall surface of the isolation trench 20 by a wet oxidation process. Compared to the isolation layer 32 formed by DPO deposition, the isolation layer 32 grown in situ by the wet oxidation process can avoid the introduction of plasma, thereby avoiding damage to the substrate 10 by plasma.

[0067] In some embodiments, in S300, a high dielectric layer 30 may be covered on the back surface 10b of the substrate 10 and the isolation trench 20, or the high dielectric layer 30 may be covered only on the isolation trench 20. Correspondingly, in S210, an isolation layer may be formed only on the isolation trench 20. Within the scope readily understood by those skilled in the art, it will not be elaborated here.

[0068] In some embodiments, the high-dielectric layer 30 includes at least two high-dielectric sublayers and at least one ordinary dielectric sublayer 31, wherein the at least two high-dielectric sublayers and at least one ordinary dielectric sublayer 31 are stacked sequentially, and an ordinary dielectric sublayer 31 is disposed between two adjacent high-dielectric sublayers of the same material to form multiple interfaces between them. Specifically, the high-dielectric layer 30 may include a first alumina dielectric sublayer 311 (AlO), a silicon oxide dielectric sublayer 312 (OX), a second alumina dielectric sublayer 313 (AlO), and a tantalum oxide dielectric sublayer 314 (TaO) sequentially covering the back surface 10b of the substrate 10 and the isolation trench 20. The first alumina dielectric sublayer 311 is the dielectric sublayer 31 closest to the substrate 10, and the tantalum oxide dielectric sublayer 314 is the dielectric sublayer 31 furthest from the substrate 10.

[0069] At this point, S300 can achieve this through the following steps:

[0070] S310: A first alumina dielectric layer is formed on the isolation layer 32.

[0071] like Figure 7 As shown, Figure 7 This is a schematic diagram of the structure in which the first alumina dielectric layer is formed on the isolation layer 32. Specifically, the first alumina dielectric layer can be formed by chemical vapor deposition (CVD). As mentioned earlier, the isolation layer 32 can be formed in situ by wet oxidation. In this scheme, the formation of the isolation layer 32 and the first alumina dielectric sublayer 311 can be achieved in the same machine, which helps to reduce cycle time and increase production capacity.

[0072] S320: A silicon oxide dielectric sublayer 312 is formed on the first alumina dielectric layer.

[0073] like Figure 8 As shown, Figure 8 This is a schematic diagram of a silicon oxide dielectric sublayer 312 formed on a first alumina dielectric layer. Specifically, the silicon oxide dielectric sublayer 312 can be formed by atomic layer deposition (ALD), and this application does not limit this; those skilled in the art can choose according to actual needs.

[0074] S330: A second alumina dielectric sublayer 313 is formed on the silicon oxide dielectric sublayer 312.

[0075] like Figure 9 As shown, Figure 9This is a schematic diagram of the structure in which a second alumina dielectric sublayer 313 is formed on a silicon oxide dielectric sublayer 312. Specifically, the second alumina dielectric sublayer 313 can be formed by chemical vapor deposition (CVD) process. This application does not limit this, and those skilled in the art can choose according to actual needs.

[0076] S340: A tantalum oxide dielectric sublayer 314 is formed on the second alumina dielectric sublayer 313.

[0077] like Figure 10 As shown, Figure 10 This is a schematic diagram showing the formation of a tantalum oxide dielectric sublayer 314 on the second alumina dielectric sublayer 313. This application does not limit the specific formation process of the tantalum oxide dielectric sublayer 314; those skilled in the art can choose according to actual needs.

[0078] In some embodiments, the high-dielectric layer 30 includes at least two high-dielectric sublayers, wherein the at least two high-dielectric sublayers are stacked together in sequence, and each high-dielectric sublayer is made of a different material from the adjacent high-dielectric sublayer to form an interface between them.

[0079] For example, the high-dielectric layer 30 may include a first alumina dielectric sublayer (AlO), a first tantalum oxide dielectric sublayer (TaO), a second alumina dielectric sublayer (AlO), and a second tantalum oxide dielectric sublayer (TaO) sequentially covering the back surface 10b of the substrate 10 and the isolation trench 20. The first alumina dielectric sublayer is the dielectric sublayer 31 closest to the substrate 10, and the second tantalum oxide dielectric sublayer is the dielectric sublayer 31 furthest from the substrate 10.

[0080] For example, the high-dielectric layer 30 may include a lanthanum oxide dielectric sublayer (LaO), an aluminum oxide dielectric sublayer (AlO), and a tantalum oxide dielectric sublayer (TaO) sequentially covering the back surface 10b of the substrate 10 and the isolation trench 20. The lanthanum oxide dielectric sublayer is the dielectric sublayer 31 closest to the substrate 10, and the tantalum oxide dielectric sublayer is the dielectric sublayer 31 furthest from the substrate 10. The lanthanum oxide dielectric sublayer may include any one or more oxides of lanthanum; details are omitted here as they are readily understood by those skilled in the art.

[0081] In the foregoing description of this specification, unless otherwise expressly specified and limited, the terms "fixed," "installed," "connected," or "linked" should be interpreted broadly. For example, the term "linked" can refer to a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; or it can refer to the internal communication of two components or the interaction between two components. Therefore, unless otherwise expressly limited in this specification, those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0082] Based on the above description in this specification, those skilled in the art will also understand that the following terms used, such as "upper," "lower," "front," "rear," "left," "right," "length," "width," "thickness," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," "circumferential," "center," "longitudinal," "transverse," "clockwise," or "counterclockwise," are terms indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings of this specification. They are only for the purpose of facilitating the explanation of the present application and simplifying the description, and do not explicitly or implicitly suggest that the device or element involved must have the specific orientation, or be constructed and operated in a specific orientation. Therefore, the above-mentioned orientation or positional relationship terms should not be understood or interpreted as limitations on the present application.

[0083] Furthermore, the terms "first" or "second," etc., used in this specification to refer to numbers or ordinal numbers are for descriptive purposes only and should not be construed as indicating, explicitly or implicitly, relative importance or specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this specification, "a plurality of" means at least two, such as two, three, or more, unless otherwise explicitly specified.

[0084] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes the opposing device surface and back side; An isolation trench is formed on the back side of the substrate and extends from the back side of the substrate toward the surface of the device. A high-dielectric layer, at least covering the isolation trench, wherein the high-dielectric layer comprises at least two dielectric sublayers, each of which is made of a different material than its adjacent counterparts to form an interface between any two adjacent dielectric sublayers, and at least a portion of the dielectric sublayers are high-dielectric sublayers; the high-dielectric layer comprises at least two high-dielectric sublayers and at least one ordinary dielectric sublayer, wherein the at least two high-dielectric sublayers and the at least one ordinary dielectric sublayer are stacked sequentially, and an ordinary dielectric sublayer is disposed between any two adjacent high-dielectric sublayers of the same material to form multiple interfaces between them, wherein the ordinary dielectric sublayer is a material with a relative permittivity not higher than that of silicon dioxide; and the high-dielectric sublayer is a material with a relative permittivity higher than that of silicon dioxide.

2. The semiconductor device according to claim 1, characterized in that, The high-dielectric layer comprises three or four dielectric sublayers.

3. The semiconductor device according to claim 1, characterized in that, The high-dielectric layer includes at least two high-dielectric sublayers, wherein the at least two high-dielectric sublayers are stacked together in sequence, and each high-dielectric sublayer is made of a different material from the adjacent high-dielectric sublayer to form the interface between them.

4. The semiconductor device according to claim 1, characterized in that, The dielectric sublayer furthest from the substrate is a tantalum oxide dielectric sublayer.

5. The semiconductor device according to claim 1, characterized in that, The high dielectric layer includes a first alumina dielectric sublayer, a silicon oxide dielectric sublayer, a second alumina dielectric sublayer, and a tantalum oxide dielectric sublayer, which sequentially cover the back side of the substrate and the isolation trench.

6. The semiconductor device according to claim 5, characterized in that, The thickness of the tantalum oxide dielectric sublayer is between 400-600 Å; The sum of the thicknesses of the first alumina dielectric sublayer, the silicon oxide dielectric sublayer, and the second alumina dielectric sublayer is between 60 and 120 Å.

7. The semiconductor device according to claim 6, characterized in that, The thickness of the tantalum oxide dielectric sublayer is 520 Å; In the first alumina dielectric sublayer, the silicon oxide dielectric sublayer, and the second alumina dielectric sublayer, the thickness of each dielectric sublayer is 30 Å.

8. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: an isolation layer disposed between the high-dielectric layer and the isolation trench; and / or The dielectric sublayer closest to the substrate is a high-dielectric-density dielectric sublayer.

9. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a planarization layer covering the high-dielectric layer.

10. The semiconductor device according to claim 1, characterized in that, The substrate is a CMOS image sensor wafer or chip, and the isolation trench is disposed between two adjacent photosensitive pixels in the substrate to avoid crosstalk between two adjacent photosensitive pixels.

11. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, wherein the substrate includes opposing device surfaces and back surfaces; An isolation trench is formed on the back side of the substrate, wherein the isolation trench extends in a direction from the back side of the substrate toward the surface of the device; A high-dielectric layer is covered at least on the isolation trench, wherein the high-dielectric layer comprises at least two dielectric sublayers, each of which is made of a different material than the adjacent dielectric sublayers to form an interface between any two adjacent dielectric sublayers, and at least a portion of the dielectric sublayers are high-dielectric sublayers; the high-dielectric layer comprises at least two high-dielectric sublayers and at least one ordinary dielectric sublayer, wherein the at least two high-dielectric sublayers and at least one ordinary dielectric sublayer are stacked sequentially, and an ordinary dielectric sublayer is disposed between any two adjacent high-dielectric sublayers of the same material to form multiple interfaces between them, wherein the ordinary dielectric sublayer is a material with a relative permittivity not higher than that of silicon dioxide; and the high-dielectric sublayer is a material with a relative permittivity higher than that of silicon dioxide.

12. The method according to claim 11, characterized in that, The high-dielectric layer includes at least two high-dielectric sublayers, wherein the at least two high-dielectric sublayers are stacked together in sequence, and each high-dielectric sublayer is made of a different material from the adjacent high-dielectric sublayer to form the interface between them.

13. The method according to claim 11, characterized in that, Before at least covering the isolation trench with a high-dielectric layer, the method further includes: forming an isolation layer on the isolation trench, wherein the isolation layer is located between the high-dielectric layer and the isolation trench.

14. The method according to claim 13, characterized in that, The process of forming an isolation layer on the isolation trench includes: treating the inner wall surface of the isolation trench with ozone gas and growing a silicon oxide layer in situ on the inner wall surface of the isolation trench through a wet oxidation process.

15. The method according to claim 14, characterized in that, The formation of the isolation layer and the formation of the dielectric sublayer closest to the substrate are performed in the same machine.

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