A tunnel acceleration system for low-latency communication in a network-on-chip

Abstract

The present invention relates to a tunnel acceleration system for low-latency communication in a network-on-chip, belonging to the technical field of low-latency design research of the network-on-chip communication architecture in a multi-core system-on-chip. Based on the five-stage pipelined router architecture of the network-on-chip, the present invention designs a tunnel entrance router architecture, a tunnel transit router architecture, and a tunnel exit router architecture. Using these three types of router architectures, a tunnel path can be built in the network-on-chip. In addition to the usual pipelined data packet forwarding function, for data packets whose routing information meets the tunnel conditions, their micro-pieces can be forwarded in a tunnel acceleration manner, passing through multi-hop routing nodes with lower latency, helping to reduce the jitter of data packet communication and optimizing the communication latency of the critical path in the network-on-chip.

Description

Technical Field

[0001] The present invention belongs to the technical field of low-latency design research of on-chip network communication architectures for multi-core systems on a chip. Specifically, it relates to a tunneling acceleration system for low-latency communication in on-chip networks. Background Art

[0002] The rapid development of semiconductor technology has driven the continuous exponential growth of chip integration. Currently, the number of transistors integrated on a single chip has reached billions, or even tens of billions. The multi-processor system on a chip (MPSoC) architecture has become the mainstream architecture of processors. According to existing data, at the 100nm process node, the communication power consumption ratio between IP cores in the system on a chip exceeds 30% of the total power consumption. Research shows that with the progress of the process node and the improvement of chip integration, the communication power consumption ratio between IP cores will be higher and higher, which brings huge communication challenges. Due to low communication efficiency, poor scalability, high power consumption, etc., the design based on the traditional bus structure is difficult to meet the growing communication needs of the MPSoC system and has gradually become one of the important reasons restricting the development of the system-on-chip architecture. Compared with the traditional bus architecture, the communication architecture of the Network-on-Chip (NoC) has advantages such as high bandwidth, easy expansion, and globally asynchronous locally synchronous. After more than 20 years of development, NoC has become the main solution for the interconnection technology of multi-core systems on a chip.

[0003] As the number of cores in MPSoC develops from a few cores to dozens or hundreds of cores, the scale of the on-chip network is also increasing rapidly. For the packet communication between cores that are far apart in the network, more hops are required, resulting in greater latency. Taking the on-chip network with a 2D Mesh topology as an example, from 9 cores to 100 cores, the number of hops required for packet communication between the diagonal cores in the network increases from 4 hops to 18 hops, while only one hop is still required for packet communication between adjacent cores, and the communication latency of the network is extremely unbalanced. However, nowadays, on-chip network applications such as multimedia have relatively high requirements for packet jitter (i.e., the uniformity of latency). Coupled with the need for some critical paths in the network to have lower latency in some applications, it is particularly important to find a mechanism to reduce the jitter value of packet communication and the communication latency of critical paths in the on-chip network. Summary of the Invention

[0004] The object of the present invention is to provide a tunnel acceleration system for low-latency communication in a network-on-chip. Based on the five-stage pipelined router architecture of the network-on-chip, a tunnel entrance router architecture, a tunnel transit router architecture, and a tunnel exit router architecture are designed. Using these three types of router architectures, a tunnel path can be established in the network-on-chip. In addition to the normal pipelined data packet forwarding function, for the data packets on the tunnel path whose routing information meets the tunnel conditions, their micro-pieces can be forwarded in a tunnel acceleration manner, passing through multiple-hop routing nodes with lower latency, helping to reduce the jitter of data packet communication, optimizing the communication latency of the critical path in the network-on-chip, and solving the problems of high jitter value of data packet communication and serious communication latency of the critical path in the network-on-chip existing in the prior art.

[0005] The object of the present invention can be achieved by the following technical solutions:

[0006] A tunnel acceleration system for low-latency communication in a network-on-chip, including a network-on-chip tunnel path, a tunnel entrance router architecture, a tunnel transit router architecture, and a tunnel exit router architecture;

[0007] The network-on-chip tunnel path includes the data packets entering the tunnel entrance router. The tunnel transit router includes a multiplexer. The data packets entering the tunnel entrance router include the data packets on the tunnel path and the data packets whose subsequent paths do not include a complete tunnel path; the data packets are composed of several micro-pieces, and the micro-piece is the smallest unit of flow control in the network-on-chip. In the present invention, it is assumed that the communication bit width in the network-on-chip is the same as the size of the micro-piece, that is, the router can transmit one micro-piece to the next-level router in each cycle, and each pipeline stage of the router can process one micro-piece in each cycle;

[0008] After the data packets on the tunnel path enter the tunnel entrance router, the router performs routing calculation according to the information such as the source address and destination address contained in the header micro-piece of the data packet. If the subsequent path of the data packet includes a complete tunnel path, it is accelerated through the tunnel acceleration mechanism, otherwise it is sent to the next-level router through the normal pipeline;

[0009] The network-on-chip tunnel path is used to transmit the micro-pieces of the data packets on the tunnel path with low latency;

[0010] The tunnel entrance router architecture is used to calculate whether the subsequent path of the data packet entering the tunnel entrance router includes a complete tunnel path according to the routing information of the data packet. For the data packets whose on-chip communication paths include a complete tunnel path, it is determined whether to allow the micro-pieces of the data packets on the tunnel path to be transmitted through the tunnel path according to the remaining capacity of the tunnel exit buffer and the channel resource allocation strategy, and a tunnel establishment signal is sent to the next-level router;

[0011] The tunnel transit router architecture is used to determine whether to allow the packet micro - slices arriving at the router in the next cycle to be transmitted through the tunnel according to the tunnel establishment signal sent by the upper - level, and forward the tunnel establishment signal to the lower - level router; for the packet micro - slices on the tunnel path, they are directly forwarded to the output port after one clock cycle without occupying the buffer of the tunnel transit router.

[0012] The tunnel egress router architecture is used to determine whether to store the packet micro - slices arriving at the router in the next cycle into a dedicated tunnel egress buffer according to the tunnel establishment signal sent by the upper - level, and perform the normal pipeline forwarding process on the micro - slices; judge whether to send a tunnel egress buffer capacity warning signal to the tunnel ingress router according to the capacity of the tunnel egress buffer.

[0013] For the on - chip network tunnel path, when the packet passing through the tunnel path entrance has the remaining on - chip communication path including the whole tunnel path, it can use the tunnel mechanism to quickly transmit the micro - slices to the tunnel egress with a delay far lower than that required by the normal pipeline router forwarding mechanism.

[0014] As a further solution of the present invention, the tunnel ingress router architecture includes an input unit, a switch, a routing calculation module, a virtual channel allocation module, and a switch allocation module.

[0015] As a further solution of the present invention, when the routing calculation module performs routing calculation based on the routing information of the packet entering the tunnel ingress router, it will judge whether the subsequent path of the packet will include the complete tunnel path. For the qualified packets, that is, the packets on the tunnel path, it will decide whether to allow the packet micro - slices to be transmitted through the tunnel path according to the remaining capacity of the tunnel egress buffer and the channel resource allocation strategy, and send a tunnel establishment signal to the lower - level router.

[0016] As a further solution of the present invention, after receiving the tunnel establishment signal sent by the upper - level router, the tunnel transit router architecture will directly send the packet micro - slices of the tunnel path arriving in the next cycle to the cross - switch entrance through a multiplexer, and send them to the output port through the cross - switch within one cycle for transmission to the lower - level.

[0017] As a further solution of the present invention, after receiving the tunnel establishment signal sent by the upper - level router, the tunnel egress router architecture will store the packet micro - slices of the tunnel path arriving in the next cycle into a dedicated tunnel egress buffer, perform the normal pipeline forwarding process on the micro - slices, and judge whether to send a tunnel egress buffer capacity warning signal to the tunnel ingress router according to the capacity of the tunnel egress buffer.

[0018] Advantages of the present invention:

[0019] (1) The low-latency tunnel acceleration mechanism of the on-chip network communication architecture of the multi-core system-on-chip of the present invention includes an on-chip network tunnel path. The on-chip network tunnel path forwards the packet micro-slice whose routing information meets the conditions from the tunnel entrance to the tunnel exit through a lower-latency tunnel acceleration method across multiple-hop tunnel router nodes; the tunnel entrance router that constitutes the tunnel path judges whether it can be forwarded by the tunnel acceleration method according to the routing information of the data packet header micro-slice entering the tunnel entrance router in the routing calculation module; the tunnel transit router is used to send the packet micro-slice of the tunnel path forwarded by the tunnel acceleration method to the router output port within one cycle; the tunnel exit router is used to receive the packet micro-slice of the tunnel path and store it in a dedicated tunnel exit buffer, and judge whether it is necessary to send a warning signal to the tunnel entrance router to suspend the tunnel acceleration forwarding according to the remaining capacity of the tunnel exit buffer. This tunnel acceleration mechanism significantly reduces the latency of the packet of the tunnel path from the tunnel entrance routing node to the tunnel exit routing node.

[0020] (2) This tunnel acceleration mechanism effectively reduces the communication latency of high-hop packets between long-distance nodes by reasonably arranging the position of the tunnel path in the on-chip network, and further improves the jitter value of packet communication in a relatively large-scale on-chip network to meet the application requirements of low jitter such as multimedia communication. In addition, a tunnel path can also be set on the critical path of the on-chip network to reduce the communication latency of the critical path. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1 It is a schematic diagram of the on-chip network low-latency tunnel structure of the present invention;

[0023] Figure 2 It is a schematic diagram of the tunnel entrance router architecture of the present invention;

[0024] Figure 3 It is a schematic diagram of the tunnel transit router architecture of the present invention;

[0025] Figure 4 It is a schematic diagram of the tunnel exit router architecture of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] Next, in combination with the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0027] The following will, with reference to the accompanying drawings, elaborate on a tunnel acceleration system for low-latency communication in a network-on-chip and the router architecture constituting the tunnel, including:

[0028] Step 1: Establish a low-latency tunnel path in the network-on-chip and perform tunnel acceleration on the data packet micro-slices of the tunnel path;

[0029] Please refer to Figure 1 As shown, for the convenience of explaining the implementation manner, it is assumed that each pipeline stage of the five-stage pipelined router occupies one system clock cycle of the network-on-chip.

[0030] Arbitrarily select a continuous routing path in the network-on-chip, and replace the routers on the continuous routing path with tunnel routers to form a low-latency tunnel structure of the network-on-chip as shown in Figure 1 The tunnel consists of 1 tunnel entrance router, several tunnel transit routers, and 1 tunnel exit router;

[0031] When a data packet enters the tunnel entrance router, if the routing algorithm selected according to the specific design results in the data packet path completely containing a certain tunnel path, it is called meeting the tunnel acceleration condition, and the data packet meeting the tunnel acceleration condition is called the data packet of the tunnel path. Such data packets can skip some pipeline stages of the router nodes on the tunnel path and quickly pass through multiple router nodes in a tunnel acceleration manner, thereby significantly reducing the data packet latency. By reasonably arranging the tunnel path in the network-on-chip, the transmission latency of the data packets on the critical path or with a large number of hops in the network-on-chip can be effectively reduced.

[0032] In Figure 1 , routing node 1 is the tunnel entrance router. In addition to performing the functions of the usual five-stage pipelined router, it will also determine whether the data packet entering the tunnel entrance router is a data packet of the tunnel path; among them, routing node is the tunnel transit router. In addition to performing the functions of the usual five-stage pipelined router, it will also forward the micro-slice forwarded by the tunnel acceleration method from the input port to the output port within one cycle; routing node n is the tunnel exit router. In addition to performing the functions of the usual five-stage pipelined router, it will also store the micro-slice forwarded by the tunnel acceleration method into a dedicated tunnel exit buffer and perform the normal five-stage pipeline forwarding process on the micro-slice.

[0033] Step 2: Tunnel entrance router architecture, determining whether forwarding can be performed through tunnel acceleration;

[0034] Please refer to Figure 2 As shown, in Figure 2 the tunnel entrance router architecture shown, it still includes components related to a conventional five-stage pipelined router, including an input unit, a switch, a routing calculation module, a virtual channel allocation module, a switch allocation module, etc. Compared with a conventional on-chip network pipelined router, its routing calculation module determines whether the data packet to be forwarded is a data packet on the tunnel path;

[0035] The data packet on the tunnel path then applies for a virtual channel from the virtual channel allocator, and the virtual channel allocator will allocate a virtual channel dedicated to tunnel acceleration to the data packet; then, in accordance with micro-slots, it applies for switch time slots from the switch allocator, and the switch allocator will decide whether to allocate switch time slots to the micro-slots of the data packet on the tunnel path according to the traffic priority policy designed specifically and the tunnel exit buffer capacity warning signal bf of the tunnel exit router; while the switch allocator authorizes the switch time slot to the micro-slot of the data packet on the tunnel path, it will set the ts signal to be valid and transmit it to the next-level routing node. Since in the switch crossing cycle of this micro-slot, that is, the cycle of reading the micro-slot from the input buffer of the tunnel entrance router and crossing the switch, the ts signal has already started the link crossing stage of the on-chip network, so this signal will reach the next-level router one cycle earlier than the head micro-slot.

[0036] Step 3: Tunnel transit router, sending the micro-slots forwarded in the tunnel acceleration mode to the router output port within one cycle;

[0037] Please refer to Figure 3 As shown, in Figure 3 the tunnel transit router shown, after receiving the ts signal sent by the previous-level router, the switch allocator will establish the input-output path required for the tunnel in the next cycle and suspend the micro-slot application of other data packets to this output port; at the same time, the ts signal delayed by one clock cycle through a trigger will control the two-way multiplexer when the tunnel crossing micro-slot reaches this router in the next cycle, enabling the tunnel acceleration micro-slot to directly enter the switch crossing stage and only consuming one switch crossing cycle in this level of router. For the tunnel exit buffer warning signal bf sent by the next-level router, it is stored in a trigger for one cycle and then sent to the previous-level router to maintain the integrity of the signal and is conducive to estimating the tunnel exit buffer size design and the tunnel exit buffer remaining capacity warning threshold.

[0038] Step 4: Tunnel exit router, receiving the tunnel acceleration micro-slots and storing them in a dedicated tunnel exit buffer, and determining whether to suspend tunnel acceleration forwarding;

[0039] Please refer to Figure 4 as shown in Figure 4 the tunnel egress router shown. After receiving the ts signal sent by the upper-level router, in the next cycle, the input unit stores the arriving tunnel acceleration micro-slice into a dedicated tunnel egress buffer. This buffer is specifically used to store the micro-slices transmitted through tunnel acceleration, and when the remaining capacity is lower than a certain threshold, it sends a warning through the signal line bf to the tunnel ingress router to pause the transmission of packet micro-slices on the tunnel path. After storing the tunnel acceleration micro-slice into the tunnel egress buffer of the input unit, in the tunnel egress router, the micro-slice participates in the five-stage pipeline forwarding process of the on-chip network router again.

[0040] Step Five: Determination of the warning threshold of the tunnel egress router buffer;

[0041] The capacity warning threshold of the tunnel egress buffer is:

[0042]

[0043] where (n - 1) represents the total number of hops of the tunnel path; represents the number of cycles required for data to perform link transmission in the on-chip network.

[0044] And as Figure 1 shown, there are a total of router nodes in the tunnel path. When the buffer capacity is less than , it sends a bf warning signal. Before the buffer capacity is exhausted, the warning signal is forwarded to the switch allocation module of the tunnel ingress router to pause the forwarding of micro-slices in the tunnel acceleration mode.

[0045] In the description of the specification, the descriptions referring to terms such as "one embodiment", "example", "specific example", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0046] The above content is only an example and illustration of the concept of the present invention. Those skilled in the art of the present technology can make various modifications or supplements to the described specific embodiments or use similar methods for substitution, as long as they do not deviate from the concept of the invention or exceed the scope defined by the claims of the present invention, they should all fall within the protection scope of the present invention.

Claims

1. A tunnel acceleration system for low-latency communication in a network-on-chip, characterized in that The tunnel acceleration system includes an on-chip network tunnel path, a tunnel entrance router architecture, a tunnel transit router architecture, and a tunnel exit router architecture; The on-chip network tunnel path includes packets entering the tunnel entrance router. The tunnel transit router includes a multiplexer. The packets entering the tunnel entrance router include packets of the tunnel path and packets whose subsequent paths do not include a complete tunnel path; The on-chip network tunnel path is used to transmit packet micro-pieces of the tunnel path with low latency; The tunnel entrance router architecture is used to calculate whether the subsequent path of a packet entering the tunnel entrance router includes a complete tunnel path according to the routing information of the packet; The tunnel transit router architecture is used to determine whether to allow the packet micro-pieces arriving at the router in the next cycle to pass through the tunnel for transmission according to the tunnel establishment signal sent by the upper level, and forward the tunnel establishment signal to the lower-level router; For the packet micro-pieces of the tunnel path, they are directly forwarded to the output port after one clock cycle and do not occupy the buffer of the tunnel transit router; The tunnel exit router architecture is used to determine whether to store the packet micro-pieces arriving at the router in the next cycle in a dedicated tunnel exit buffer according to the tunnel establishment signal sent by the upper level, and perform a normal pipeline forwarding process on the micro-pieces; Judge whether it is necessary to send a tunnel exit buffer capacity warning signal to the tunnel entrance router according to the tunnel exit buffer capacity; The packets of the tunnel path are packets whose subsequent paths include a complete tunnel path. The packets whose subsequent paths do not include a complete tunnel path are non-tunnel path packets, and they cannot utilize the tunnel acceleration mechanism through the normal forwarding of the pipeline stage of the router; The packets of the tunnel path are used to determine whether to allow the packet micro-pieces of the tunnel path to pass through the tunnel path according to the remaining capacity of the tunnel exit buffer and the channel resource allocation strategy, and send a tunnel establishment signal to the lower-level router.

2. The tunnel acceleration system for low-latency communication in a network-on-chip according to claim 1, wherein For the on-chip network tunnel path, when the subsequent path of the packet entering the tunnel entrance router includes the entire tunnel path, it can pass through the tunnel mechanism.

3. The tunnel acceleration system for low-latency communication in a network-on-chip according to claim 1, wherein The tunnel entrance router architecture includes an input unit, a switch, a routing calculation module, a virtual channel allocation module, and a switch allocation module.

4. A tunneling acceleration system for low-latency communication in a network-on-chip according to claim 3, wherein, When the routing calculation module performs routing calculation based on the routing information of the packet entering the tunnel entrance router, it will judge whether the subsequent path of the packet includes a complete tunnel path. For the eligible packets, that is, the packets of the tunnel path, it will determine whether to allow the packet micro-pieces to pass through the tunnel path according to the remaining capacity of the tunnel exit buffer and the channel resource allocation strategy, and send a tunnel establishment signal to the lower-level router.

5. The tunnel acceleration system for on-chip network low-latency communication according to claim 1, characterized in that After receiving the tunnel establishment signal sent by the upper-level router, the tunnel transit router architecture will directly send the packet micro-pieces of the tunnel path arriving in the next cycle to the crossbar switch entrance through the multiplexer, and send them to the output port through the crossbar switch within one cycle for transmission to the lower level.

6. The tunnel acceleration system for low-latency communication in a network-on-chip according to claim 1, wherein Upon receiving the tunnel establishment signal sent by the upper-level router, the tunnel egress router architecture stores the data packet micro-slices of the tunnel path arriving in the next cycle in a dedicated tunnel egress buffer, and performs the normal pipeline forwarding process on the micro-slices. According to the capacity of the tunnel egress buffer, it determines whether to send a tunnel egress buffer capacity warning signal to the tunnel ingress router.

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