Parallel Conversion Interface for High-Speed Scalable Interconnect Dies and PCIe Master Devices

Abstract

The present invention discloses a parallel conversion interface for a high-speed scalable interconnect bare die and a PCIe master device, belonging to the field of integrated circuit communication. The present invention connects the Network-on-Chip (NoC) of the high-speed scalable interconnect bare die to the EP end of the PCIe master device, realizes the conversion between the AXI protocol of the PCIe master device and the transmission protocol of the Network-on-Chip (NoC), receives data packets of various request types from the PCIe master device and converts them into data packets of the Network-on-Chip (NoC) protocol, and returns data packets of various response types to the PCIe master device, and supports the transmission of multiple different request data packets in the Network-on-Chip (NoC) of the bare die, so as to realize the communication between the PCIe master device and each slave device on the high-speed scalable interconnect bare die. The present invention can realize the conversion and communication between the transmission protocol of the Network-on-Chip (NoC) of the dielet and the AXI protocol of the PCIe master device, and greatly shortens the development cycle and reduces the development cost.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit communication technology, and in particular to a parallel conversion interface for high-speed scalable interconnection bare cores and PCIe master devices. Background Art

[0002] Integrated circuit technology has been developing rapidly in line with Moore's Law. However, as the size of integrated circuits has continued to decrease in recent years, Moore's Law has approached its physical limits, and the cost and cycle of developing application-specific integrated circuits have gradually increased.

[0003] However, market demands for semiconductor performance continue to increase. Therefore, combining circuit functions at the chip level will significantly enhance chip performance. The design of a conversion interface and data exchange method for high-speed, scalable interconnect bare die and PCIe host devices will play a crucial role in the rapid integration and expansion of PCIe host devices. Summary of the invention

[0004] The purpose of the present invention is to provide a parallel conversion interface for high-speed scalable interconnection of bare cores and PCIe master devices, so as to realize the conversion and communication between the transmission protocol of the chip-on-chip network NOD and the AXI protocol of the PCIe master device.

[0005] To solve the above technical problems, the present invention provides a parallel conversion interface for a high-speed scalable interconnect bare core and a PCIe master device. The interface connects the on-chip network (NOD) of the high-speed scalable interconnect bare core and the EP end of the PCIe master device, realizes the conversion between the AXI protocol of the PCIe master device and the on-chip network (NOD) transmission protocol, receives data packets of various request types from the PCIe master device and converts them into data packets of the on-chip network (NOD) protocol, returns data packets of various response types to the PCIe master device, and supports the transmission of multiple different request data packets in the on-chip network (NOD) of the bare core, thereby realizing communication between the PCIe master device and various slave devices on the high-speed scalable interconnect bare core.

[0006] The parallel conversion interface includes a Shell module, a Kernel module and an asynchronous FIFO module;

[0007] The Shell module receives read and write requests from the PCIe master device, converts multiple different request data packets of the AXI signal into a specific format and stores them in a specific unit of the asynchronous FIFO module. It also initiates an MSI interrupt signal to the PCIe master device to notify the arrival of the response data packet. It also has address testing and ID configuration functions.

[0008] The Kernel module converts the data stored in the Shell module in the asynchronous FIFO module into data packets of the NOD on-chip network protocol, receives the returned response data packets, unpacks them and stores them in the asynchronous FIFO module. In addition, it has the functions of error retransmission and timeout retransmission for response data packets.

[0009] The asynchronous FIFO module across clock domains is connected to the Shell module and the Kernel module, and contains multiple asynchronous FIFO units, which are responsible for different read and write channels respectively.

[0010] In one implementation, one end of the PCIe network conversion interface NI on the high-speed scalable interconnected die is connected to the EP end of the PCIe master device, and the other end is connected to the on-chip network NOD. The function of the on-chip network NOD is to route and transmit the on-chip network transmission protocol, including the request event data packets of the PCIe master device to each slave device on the die and the corresponding response event data packets of the slave devices. The interaction between the PCIe network conversion interface NI and the PCIe master device is based on two groups of AXI4 buses. One group is used as a Slave interface to communicate with the EP end, and the other group is used as a Master interface to send MSI interrupt signals to the EP end.

[0011] In one implementation, the functions of the PCIe network conversion interface NI include the PCIe master device configuring NODID and SRID information for the PCIe network conversion interface NI, as well as configuring the address and data of the returned MSI interrupt.

[0012] The PCIe network conversion interface NI provides the function of address testing. The PCIe network conversion interface NI is designed with a partial decoding strategy, that is, only the lower eight bits of the address are decoded. Before the formal work starts, the PCIe master device needs to test the available address space by means of address polling. The PCIe network conversion interface NI needs to receive and convert different event data packets during the formal work. After receiving the response event sent by the slave, the PCIe network conversion interface NI must initiate an MSI interrupt signal to the PCIe master device, and the PCIe master device will then read the interrupt information of the response event and the data payload in the response event.

[0013] In one implementation, the PCIe network conversion interface NI supports the check error retransmission mechanism and the timeout retransmission mechanism. Under normal circumstances, after the PCIe network conversion interface NI receives the read response packet, it notifies the PCIe master device through an interrupt. After the PCIe master device reads the interrupt information, it sends a new request command.

[0014] The situation of the error retransmission mechanism is as follows: after the PCIe network conversion interface NI receives a read response packet and detects a checksum error, it will not interrupt the PCIe master device. Instead, it will retransmit the request packet of the NOD on-chip transport protocol. After the new NOD on-chip transport protocol response packet is returned, an interrupt will be generated to notify the PCIe master device.

[0015] The timeout retransmission mechanism is specifically as follows: if the PCIe network conversion interface NI has not received a read response packet all the time, it will trigger the retransmission of the request packet of the NOD on-chip transport protocol, and generate an interrupt to notify the PCIe master device according to the actual response situation of the retransmitted request packet of the NOD on-chip transport protocol.

[0016] In one implementation, the PCIe network conversion interface NI supports concurrent requests; for the PCIe master device, it can issue multiple request commands; the PCIe network conversion interface NI supports both the checksum error retransmission mechanism and the timeout retransmission mechanism for all issued request data packets; however, the PCIe master device should pay attention to the dependency relationships between different request events, maintain the correct read / write order for the same address of the same slave device, and can initiate read / write requests in a disorderly manner for the addresses of different slave devices or different addresses of the same slave device.

[0017] In one implementation, for the process of the PCIe master device's request, the Shell module parses the read / write request commands from AXI_S and writes the parsing results into the REQ_FIFO sub-module in the asynchronous FIFO module in accordance with the specified format; the Kernel module reads the information in the REQ_FIFO sub-module and packs the read / write request commands into on-chip network request data packets in accordance with the format of the NOD on-chip transport protocol bus.

[0018] For the response process, the Kernel module reads the response data packet from the on-chip network NOD and parses it, and writes the parsing results into the RESP_FIFO sub-module in the asynchronous FIFO module in accordance with the specified format; the Shell module reads the information in the RESP_FIFO sub-module, and when all responses are received, it sends an interrupt notification to the PCIe master device through AXI_M. The PCIe master device further reads the response information cached in the Shell module through AXI_S.

[0019] The REQ_FIFO sub-module includes FIFO_0, ..., FIFO_(n - 1), and FIFO_n, where FIFO_0 to FIFO_(n - 1) are channels for write request events and shared write request events with data payloads, and FIFO_n is a channel for read request events, erase request events, and DMA read request events without data payloads; the data payload remains in the REQ_FIFO sub-module, and the remaining request information enters the (m + 1) groups of request units in the Kernel module through the REQ_FIFO sub-module for storage, and m > n, for the PCIe network conversion interface NI to resend these different requests.

[0020] In one implementation, the write request processing module in the Shell module includes an AXI write controller, a first address test unit, a first configuration unit, a command unit, and a first FIFO write controller; for write commands from AXI_S, there are three scenarios, namely configuration, address test, and command, which are distinguished by the write address of AXI_S. The AXI write controller decodes the lower eight bits of the AXI_S write address. The write address 64’hxx10 is for configuration, the write address 64’hxx20 is for command, and the write address 64’hxx30 is for address test.

[0021] The first FIFO write controller is used to determine whether both the read channel and the write channel FIFOs are occupied, and which FIFO channels are not occupied, so as to be able to store subsequent PCIe request data packets; the request event capacity of the PCIe network conversion interface NI is to store n write request events / shared write request events and (m + 1 - n) read request events / erase request events / DMA read request events.

[0022] In one implementation, the read request processing module in the Shell module includes an AXI read controller, a second address test unit, an interrupt controller, a data unit, and a first FIFO read controller; for read commands from AXI_S, there are three scenarios, namely reading interrupt information, address test, and reading data, which are distinguished by the read address of AXI_S. The AXI read controller decodes the lower eight bits of the AXI_S write address. The read address 64’hxx10 is for the interrupt information of the response packet, the read address 64’hxx20 is for the payload data of the response packet, the read address 64’hxx30 is for address test, and the read address 64’hxx40 is for the address information of the response packet.

[0023] In one embodiment, the NOD request processing module in the Kernel module includes a second FIFO read controller, a second configuration unit, and a NOD request unit; the NOD request unit includes request unit 0, ..., request unit m; under the control of the second configuration unit and the NOD request unit, (m + 1) internal request units read data from the REQ_FIFO sub-module; the second configuration unit is used to configure registers before the formal startup of the PCIe network conversion interface NI, and the NOD request unit packs the data read from the REQ_FIFO sub-module into NOD on-chip network data packets and sends them.

[0024] In one embodiment, the NOD response processing module in the Kernel module includes a second FIFO write controller and a NOD response unit; the NOD response unit receives a NOD response, parses it, and writes the parsing result into the RESP_FIFO sub-module in cooperation with the second FIFO write controller. In the data format written into the RESP_FIFO sub-module, the high two bits are used as flag bits, and 2'b10 is used to flag exception information; there are two types of exception situations for the NOD response. One situation is a response error, that is, the response information is not received within the specified time, which is identified by the status signal resp_confirm_err, and it will cause the state machine of the NOD response processing module to enter the STUS state. If this exception occurs during the retransmission stage, the exception information will be written into the RESP_FIFO sub-module; the other situation is a read data verification error, which is identified by resp_check_err, and this exception information will be written into the RESP_FIFO sub-module when the tail microchip is received.

[0025] In a parallel conversion interface for a high-speed scalable interconnected die and a PCIe master device provided by the present invention, it can receive data packets of various request types from the PCIe master device and convert them into data packets of the die NOD on-chip network protocol, and return data packets of various response types to the PCIe master device, and support multiple different request data packets to be transmitted simultaneously in the die NOD, so as to realize the parallel read and write access of the PCIe master device to each slave device on the high-speed scalable interconnected die. The present invention realizes the conversion and communication between the transmission protocol of the on-chip network NOD of the chiplet and the AXI protocol of the PCIe master device, and greatly shortens the development cycle and reduces the development cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic structural diagram of a parallel conversion interface for a high-speed scalable interconnected die and a PCIe master device proposed by the present invention;

[0027] Figure 2 is the overall architecture block diagram of the parallel conversion interface application system;

[0028] Figure 3 It is the write FIFO data format diagram of the Shell module;

[0029] Figure 4 It is the control state transition diagram of the command processing unit in the Shell module;

[0030] Figure 5 It is the state transition diagram of the interrupt controller in the Shell module;

[0031] Figure 6 It is the state transition diagram of the NOD request unit in the Kernel module;

[0032] Figure 7 It is the write FIFO data format diagram of the Kernel module;

[0033] Figure 8 It is the state transition diagram of the NOD response unit in the Kernel module. Specific embodiments

[0034] The following further describes in detail a parallel conversion interface for a high-speed scalable interconnected bare die and a PCIe master device proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention.

[0035] The present invention provides a parallel conversion interface for a high-speed scalable interconnected bare die and a PCIe master device, and its structure is as Figure 1As shown in the figure, it includes a Shell module, a Kernel module, and an asynchronous FIFO module. Among them, the Shell module is composed of a write request processing module and a read request processing module, the Kernel module is composed of a NOD request processing module and a NOD response processing module, and the asynchronous FIFO module is composed of a REQ_FIFO sub-module and a RESP_FIFO sub-module, where the REQ_FIFO sub-module includes multiple independent asynchronous FIFO units (i.e., FIFO_0, ..., FIFO_n). The Shell module is responsible for receiving read and write requests from the PCIe master device, converting multiple different request data packets of AXI signals into a specific format and storing them in the REQ_FIFO sub-module, and can also initiate an MSI interrupt signal to the PCIe master device to notify that the response data packet has arrived. In addition, it has an address test function and an ID configuration function. The Kernel module is mainly responsible for converting the data in the REQ_FIFO sub-module into data packets of the NOD on-chip network protocol, and receiving the returned response data packets and unpacking them into the RESP_FIFO sub-module. In addition, it has an error retransmission function and a timeout retransmission function for the response data packets. The asynchronous FIFO module across clock domains connects the Shell module and the Kernel module, and there are multiple asynchronous FIFO units inside, which are responsible for different read and write channels.

[0036] The overall architecture of the parallel conversion interface application system of the present invention is as Figure 2 shown. The PCIe network conversion interface NI on the high-speed scalable interconnected die is connected to the EP end of the PCIe master device at one end and the on-chip network NOD on the die at the other end. The function of NOD is to route and transmit the on-chip network transmission protocol, including request event data packets of the PCIe master device to each slave device on the die and response event data packets of the corresponding slave devices. The interaction between the PCIe network conversion interface NI and the PCIe master device is based on two groups of AXI4 buses. One group is used as a Slave interface to communicate with the EP end, and the other group is used as a Master interface to send an MSI interrupt signal to the EP end.

[0037] In the present invention, the functions of the PCIe network conversion interface NI mainly include that the PCIe master device configures the NODID and SRID information for the PCIe network conversion interface NI, and configures the address and data of the returned MSI interrupt. The PCIe network conversion interface NI provides the function of address testing. This is because due to the uncertainty of the IP, the mapping relationship between the PCIe host address and the AXI address at the EP end cannot be determined. Therefore, the PCIe network conversion interface NI design adopts a partial decoding strategy, that is, only the lower eight bits of the address are decoded. Before the formal work starts, the PCIe master device needs to test the available address space by means of address polling. During the formal work, the PCIe network conversion interface NI needs to receive and convert different event data packets, such as write request / shared write request events, read request / erase request / DMA read request events, etc. After receiving the response event sent by the slave, the PCIe network conversion interface NI must initiate an MSI interrupt signal to the PCIe master device, and the PCIe master device will then read the interrupt information of the response event and the data payload in the response event.

[0038] The configuration operation of the PCIe network conversion interface NI in the present invention is as follows:

[0039] The PCIe master device initiates a write request with a length of 1 through the AXI_S write channel to configure information such as NoDID and SRID.

[0040] Write address: The lower eight bits of s_axi_awaddr are 8’h10;

[0041] Write data: s_axi_wdata[3:0] is NoDID, s_axi_wdata[7:6] is SRXID (X coordinate ID of the source node), s_axi_wdata[5:4] is SRYID (Y coordinate ID of the source node);

[0042] Write length: s_axi_awlen is 0;

[0043] Write address: The eighth bit of s_axi_awaddr is 8’h60;

[0044] Write data: s_axi_wdata[31:0] is the address of the returned MSI interrupt;

[0045] Write length: s_axi_awlen is 0;

[0046] Write address: The lower eight bits of s_axi_awaddr are 8’h70;

[0047] Write data: s_axi_wdata[127:96] is the returned MSI interrupt data, and these 32 bits represent which of the 32 MSI interrupts are triggered;

[0048] Write length: s_axi_awlen is 0.

[0049] The address test operation of the PCIe network conversion interface NI in the present invention is as follows:

[0050] Due to the uncertainty of the IP, the mapping relationship between the PCIe master device address and the AXI address at the EP end cannot be determined. Therefore, the interface design adopts a partial decoding strategy, that is, only the lower eight bits of the address are decoded. Before the formal work starts, the PCIe master device needs to test the available address space by means of address polling.

[0051] The PCIe master device first performs a write operation with a length of 1 on the test register in the interface.

[0052] Write address: The lower eight bits of s_axi_awaddr are 8’h30;

[0053] Write data: m_axi_wdata is an arbitrary value DATA;

[0054] Write length: s_axi_awlen is 0.

[0055] After the write operation is completed, the PCIe master device performs a read operation with a length of 1 on the test register in the interface.

[0056] Read address: The lower eight bits of s_axi_araddr are 8’h30;

[0057] Read length: s_axi_arlen is 0;

[0058] Read data: If the read data s_axi_rdata is the written value DATA, it means that the PCIe host address and the AXI address at the EP end are successfully mapped, and subsequent read and write operations are carried out on the basis of this address space range; if the read data s_axi_rdata is the default value 128’

[0059] h0123_4567_89ab_cdef_fedc_ba98_7654_3210, it means that the read address of the PCIe host address and the AXI at the EP end is successfully mapped, but the write address fails to be successfully mapped, and further testing is still required; if s_axi_rdata is not one of the above two cases, it means that the PCIe host address and the AXI address at the EP end fail to be successfully mapped, and the PCIe master device needs to continue to test the available address space.

[0060] The write / share write request operation of the PCIe network conversion interface NI in the present invention is as follows:

[0061] For a write request with a length of P words (e.g., P = 12), the PCIe master device achieves it by continuously initiating (P / 4 + 2) write requests through the AXI_S write channel. Since this IP supports a burst transfer with a maximum length of 8 at most, these (P / 4 + 2) write requests can be scattered in multiple burst transfers or split into multiple independent write requests.

[0062] Write address: The lower 8 bits of s_axi_awaddr are 8’h20;

[0063] Write data:

[0064] · The first write data: s_axi_wdata is {111'h0, LEN(9bit), TID(4bit), TTP(4bit)}, where LEN = P - 1 (11 in this example);

[0065] · The second write data: s_axi_wdata is {BNODID(4bit), BRXID(2bit), BRYID(2bit), BADDR(56bit), DNODID(4bit), DRXID(2bit), DRYID(2bit), DADDR(56bit)};

[0066] · The subsequent consecutive P / 4 write data, i.e., P / 4 data payloads;

[0067] Write length: s_axi_awlen is set according to the actual situation of the burst.

[0068] The read / erase / DMA read requests of the PCIe network conversion interface NI in the present invention are as follows:

[0069] For a read request with a length of P words (e.g., P = 12), the PCIe master device achieves it by continuously initiating 2 write requests through the AXI_S write channel. These two write requests can be achieved through a burst transfer with a burst length of 2 or through 2 independent write requests.

[0070] Write address: The lower 8 bits of s_axi_awaddr are 8’h20;

[0071] Write data:

[0072] · The first write data: s_axi_wdata is {111'h0, LEN(9bit), TID(4bit), TTP(4bit)}, where LEN = P - 1 (11 in this example);

[0073] · Second write data: s_axi_wdata is {BNODID (4 bits), BRXID (2 bits), BRYID (2 bits), BADDR (56 bits), DNODID (4 bits), DRXID (2 bits), DRYID (2 bits), DADDR (56 bits)};

[0074] Write length: s_axi_awlen is set according to the actual situation of the burst.

[0075] The interrupt signal operation of the PCIe network conversion interface NI in the present invention is as follows:

[0076] For interrupts, the PCIe network conversion interface NI initiates a write request with a length of 1 through the AXI_M write channel to generate an interrupt to the PCIe master device.

[0077] Write address: m_axi_awaddr is 64'h0000_0000_FFFF_FFFC;

[0078] Write data:

[0079] m_axi_wdata is 128'h0000_0001_0000_0000_0000_0000_0000_0000;

[0080] Write length: m_axi_awlen is 0.

[0081] The read interrupt information operation of the PCIe network conversion interface NI in the present invention is as follows:

[0082] When the PCIe master device receives an interrupt, it initiates two read requests with a length of 1 successively through the AXI_S read channel to obtain the interrupt information.

[0083] Read address: The lower eight bits of s_axi_araddr are 8’h10;

[0084] Read length: s_axi_arlen is 0;

[0085] Read data:

[0086] · s_axi_rdata[20:17] is the interrupt type, 1 represents READ_PASS, 2 represents READ_ERROR, 3 represents WRITE_PASS, 4 represents ACK, 5 represents NACK, 6 represents DMA_READ_PASS, 7 represents INT;

[0087] · s_axi_rdata[16:13] is TTP. Since there is no response packet returned for the NACK interrupt, its TTP corresponds to the TTP of the request event, while the TTPs corresponding to other types of interrupts are the TTPs of the response events;

[0088] · s_axi_rdata[12:9] is TID;

[0089] · s_axi_rdata[8:0] is LEN (if it is 11, it means the length is 12 words).

[0090] Read address: The lower eight bits of s_axi_araddr are 8’h40;

[0091] Read length: s_axi_arlen is 0;

[0092] Read data:

[0093] · s_axi_rdata is the 128-bit address in the response packet.

[0094] The response information operation of the PCIe network conversion interface NI in the present invention is as follows:

[0095] When the PCIe master device reads the interrupt information and queries that the response information is a correct read response with a length of LEN (for example, LEN = 11), it initiates (LEN + 1) / 4 read requests continuously through the AXI_S read channel to read the read response data. Since this IP supports a burst transfer with a maximum length of 8 at most, these (LEN + 1) / 4 read requests can be scattered in multiple burst transfers or split into multiple independent read requests.

[0096] Read address: The lower eight bits of s_axi_araddr are 8’h20;

[0097] Read length: s_axi_arlen is set according to the actual situation of the burst;

[0098] Read data: s_axi_rdata is the continuous read data.

[0099] In the present invention, the PCIe network conversion interface NI supports a check error retransmission mechanism and a timeout retransmission mechanism. Under normal circumstances, after the PCIe network conversion interface NI receives a read response packet, it notifies the PCIe master device through an interrupt. After the PCIe master device reads the interrupt information, it can send a new request command. The situation of the check error retransmission mechanism is as follows: after the PCIe network conversion interface NI receives a read response packet and finds a check error, it will not interrupt the PCIe master device, but instead retransmit the request packet of the NOD on-chip transmission protocol. After a new NOD on-chip transmission protocol response packet returns, it generates an interrupt to notify the PCIe master device. The timeout retransmission mechanism is specifically as follows: if the PCIe network conversion interface NI has not received a read response packet all the time, it will trigger the retransmission of the request packet of the NOD on-chip transmission protocol, and generate an interrupt to notify the PCIe master device according to the actual response situation of the retransmitted request packet of the NOD on-chip transmission protocol.

[0100] In the present invention, the PCIe network conversion interface NI supports concurrent requests. For the PCIe master device, multiple request commands can be issued. The PCIe network conversion interface NI supports both the check error retransmission mechanism and the timeout retransmission mechanism for all the issued request data packets. However, the PCIe master device should pay attention to the dependency relationship between different request events, maintain the correct read / write order for the same address of the same slave device, and can initiate read / write requests in a disorderly manner for the addresses of different slave devices or different addresses of the same slave device.

[0101] For the process of the PCIe master device's request, the Shell module in the present invention parses commands such as read / write requests from AXI_S, and writes the parsing results into the REQ_FIFO sub-module in the asynchronous FIFO module according to the specified format; the Kernel module reads the information in the REQ_FIFO sub-module and packs commands such as read / write requests into on-chip network request data packets according to the format of the NOD on-chip transmission protocol bus. For the response process, the Kernel module reads the response data packet from the on-chip network and parses it, and writes the parsing results into the RESP_FIFO sub-module in the asynchronous FIFO module according to the specified format; the Shell module reads the information in the RESP_FIFO sub-module, and when all the responses are received, it sends an interrupt notification to the PCIe master device through AXI_M, and the PCIe master device further reads the response information cached in the Shell module through AXI_S.

[0102] The REQ_FIFO sub-module consists of (n + 1) FIFOs. Among them, FIFO_0 to FIFO_(n - 1) are channels for write request events and shared write request events with data payloads, while FIFO_n is a channel for read request events, erase request events, and DMA read request events without data payloads. Specifically, the data payload remains in the REQ_FIFO sub-module, and the request information enters the (m + 1) groups of registers in the Kernel module through the REQ_FIFO sub-module for the PCIe network conversion interface NI to resend these different requests, where m > n.

[0103] The entire network interface of the present invention is divided into two clock domains, AXI and NOD. The cross-clock domain processing is implemented through the asynchronous FIFO module.

[0104] The write request processing module in the Shell module of the present invention is as Figure 1 shown. For the write commands from AXI_S, there may be three scenarios, namely configuration, address test, and command. These three scenarios are distinguished by the write address of AXI_S. The AXI write controller decodes the lower eight bits of the AXI_S write address. The write address 64’hxx10 is for configuration, 64’hxx20 is for command, and 64’hxx30 is for address test.

[0105] The first FIFO write controller in the Shell module is used to determine whether both the read channel and the write channel FIFOs are occupied, and which FIFO channels are not occupied, so that subsequent PCIe request data packets can be stored. The request event capacity of the PCIe network conversion interface NI is to store n write request events / shared write request events and (m + 1 - n) read request events / erase request events / DMA read request events.

[0106] For the address test scenario, the first address test unit writes the write data of AXI_S into the address test register, which has a special reset initial value. If the write address mapping between the RC end and the EP end is successful, the value of this register is the write data of AXI_S; otherwise, it is the reset initial value.

[0107] For the configuration scenario, the write data of AXI_S includes configuration information such as SRID and NODID. The Kernel module needs this information. Therefore, the first configuration unit in the Shell module writes it into the REQ_FIFO sub-module. The data format written into the REQ_FIFO sub-module is as Figure 3 shown, indicating its configuration information attribute through the flag bit 2’b01, and the data payload is the configuration information.

[0108] For the command scenario, the command processing unit is internally controlled by a finite state machine. As Figure 4 shown, in the W_LEN state, the first command information received includes LEN, TTP, TID, etc. Therefore, when the command information is received and the AXI_S_W channel handshake is successful, the information such as LEN, TTP, TID, etc. is saved, and the W_ADDR state is entered. In the W_ADDR state, the second command information received includes the main address, auxiliary address, etc. Since one of the conditions for s_axi_wready to be valid is that the REQ_FIFO sub-module is not full, when the AXI_S_W channel handshake is successful, the information of the first REQ_FIFO sub-module (i.e., FIFO_0) is written; after that, waiting for the condition that the REQ_FIFO sub-module is not empty, the information of the second REQ_FIFO sub-module (i.e., FIFO_1) is written, and other states are entered according to the event type. If the command information is related to the write event, the W_DATA state is entered, otherwise the W_LEN state is returned. In the W_DATA state, the condition for s_axi_wready to be valid is that the REQ_FIFO sub-module is not full. Then, when the AXI_S_W channel handshake is successful, the subsequent data information is written into the REQ_FIFO sub-module. The command processing unit judges the number of data according to the length information. When all data writing is completed, the state machine returns to the W_LEN state. The flag bit of the last data written into the REQ_FIFO sub-module is 2’b11, and the rest is 2’b00.

[0109] The logic for s_axi_awready to be valid: It is always valid in the W_LEN and W_DATA states; in the W_ADDR state, the REQ_FIFO sub-module is not empty and the first write to the REQ_FIFO sub-module is completed.

[0110] The logic for s_axi_wready to be valid: In the W_LEN state, confirm that the wait state confirm_wait_flag is low, and it is in the command stage, or the address test stage, or the configuration stage and the REQ_FIFO sub-module is not empty. The confirm_wait_flag signal is pulled high after each command reception and pulled low until the response information, or the write success information, or the response failure information is valid. Therefore, the PCIe network conversion interface NI cannot respond to new command requests when the response information has not been returned; in the W_ADDR state, the REQ_FIFO sub-module is not full and the AXI_S address information has not been written; in the W_DATA state, the REQ_FIFO sub-module is not full.

[0111] The read request processing module in the Shell module of the present invention is as Figure 1As shown in the figure. For the read commands from AXI_S, there may be three scenarios, namely reading interrupt information, address test, and reading data. These three scenarios are distinguished by the read address of AXI_S. The AXI read controller decodes the lower eight bits of the AXI_S write address. The read address 64’hxx10 is the interrupt information of the response packet, the read address 64’hxx20 is the payload data of the response packet, the read address 64’hxx30 is the address test, and the read address 64’hxx40 is the address information of the response packet.

[0112] For the address test scenario, the second address test unit will return the data in the address test register as the read response. The PCIe master device can determine whether the address mapping is successful based on the result of the read data. For the read data scenario, the first FIFO read controller will read the corresponding length of data from the RESP_FIFO sub-module as the read response. The first FIFO read controller will generate two flag signals for the interrupt controller to use. Among them, s_axi_rd_int_fin indicates the end of a read interrupt information, and s_axi_rd_data_fin indicates the end of a read data. For the read interrupt information scenario, the interrupt controller will return the value in the interrupt information register as the read response.

[0113] The logic for s_axi_rvalid to be valid: After the AR channel handshake of the Slave interface is successful, s_axi_rvalid is pulled high, that is, the data is ready, and it is pulled low again after the last data handshake of the R channel of the Slave interface is completed. The logic for s_axi_arready to be valid: After the AR channel handshake is successful, s_axi_arready is pulled low until the end of a complete read transfer, that is, it is pulled high again after the last data handshake of the R channel is completed.

[0114] The interrupt controller in the Shell module of the present invention is as Figure 1 shown. The interrupt controller reads the response data from the RESP_FIFO sub-module, parses the data of the RESP_FIFO sub-module, stores the response information according to the parsing situation, and triggers the PCIe master device through an interrupt. The state transition diagram of the state machine in the interrupt controller is as Figure 5As shown, with R_LEN as the initial state, if the RESP_FIFO sub-module is not empty, the data in the RESP_FIFO sub-module is normal data, and the interrupt controller is idle, then read the RESP_FIFO sub-module and transfer the state to the R_ADDR state; if the RESP_FIFO sub-module is not empty, the data in the RESP_FIFO sub-module is normal data, the response type is an acknowledgment, and the interrupt controller is idle, then read the RESP_FIFO sub-module and transfer the state to the ACK state; if the RESP_FIFO sub-module is not empty, the data in the RESP_FIFO sub-module is abnormal data, and the interrupt controller is idle, then read the RESP_FIFO sub-module and transfer the state to the NO_ACK state. In the R_ADDR state, if the RESP_FIFO sub-module is not empty and the response type is a read response, then read the RESP_FIFO sub-module and transfer the state to the R_DATA state; if the RESP_FIFO sub-module is not empty and the response type is not a read response, then read the RESP_FIFO sub-module and transfer the state to the R_LEN state. In the R_DATA state, if the RESP_FIFO sub-module is not empty, then read the RESP_FIFO sub-module, and while reading the RESP_FIFO sub-module, write the read response data into the read data Buffer until the length of the read data meets the LEN requirement, then transfer the state to the R_LEN state.

[0115] When all the events received in the read response end and it is in states such as ACK and NO_ACK, an interrupt is triggered by writing data to a specific address space through the M_AXI interface, and the interrupt information is written into the interrupt information register. rresp_busy is the status signal of the interrupt controller, which is pulled high after the interrupt is triggered. It is only pulled low after reading the interrupt information register or reading the read response data. During the period when rresp_busy is high, the interrupt controller cannot process new response data in the RESP_FIFO sub-module.

[0116] The NOD request processing module in the Kernel module of the present invention is as Figure 1 shown. Under the control of the second configuration unit and the NOD request unit (including request unit 0,..., request unit m), (m + 1) internal request units read data from the REQ_FIFO sub-module. The second configuration unit is used to configure the register before the PCIe network conversion interface NI officially starts working. The NOD request unit packs the data read from the REQ_FIFO sub-module into NOD on-chip network data packets and sends them.

[0117] The NOD request unit is controlled by (m + 1) identical finite state machines, and the state transition is as Figure 6As shown in the figure. In the HEAD state, if the REQ_FIFO sub-module is not empty and the data in the REQ_FIFO sub-module is not configuration information, or in the retransmission state, then initiate the on-chip data transmission of NOD, that is, raise NOD_req_valid. When the NOD request corresponding to the head micro-slice is successfully sent, the state machine enters the BODY state. In the BODY state, if the REQ_FIFO sub-module is not empty and the data in the REQ_FIFO sub-module is not configuration information, or in the retransmission state, then initiate the on-chip data transmission of NOD, that is, raise NOD_req_valid. The NOD request sending in the non-retransmission stage will trigger the read operation of the REQ_FIFO sub-module of the request. Otherwise, read data from the retransmission Buffer. When the NOD request corresponding to the last body micro-slice is successfully sent, the state machine enters the TAIL state. In the TAIL state, initiate the NOD data transmission, that is, raise NOD_req_valid. When the NOD request corresponding to the tail micro-slice is successfully sent, the state machine enters the CONFIRM state. In the CONFIRM state, wait for the read response verification to succeed, or the write response, or the DMA read reply, or the exception flag signal. The state machine returns to the HEAD state. Otherwise, it always remains in the confirmation state.

[0118] To implement data retransmission, it is necessary to store the NOD data packet in n retransmission Buffers during the sending process of the NOD data packet for use during retransmission. The body micro-slices related to the data are stored in the retransmission Buffer, while other length, address micro-slices, head micro-slices, tail micro-slices, etc. are stored in (m + 1) groups of dedicated retransmission micro-slice registers. req_repeat_flag is used as the flag bit for data packet retransmission. When there are situations such as verification errors, the response packet not being returned in time, etc., then it is necessary to raise req_repeat_flag to start the retransmission process. The condition buffer_we for writing to the retransmission Buffer is raised when sending the data payload in the BODY state, while other data packets are stored in the form of registers. When the read response data packet verification is successful, or the write response is returned, or the retransmission is completed, the retransmission Buffer will be reset. During the data sending process, when the req_repeat_flag is valid, read the retransmission micro-slice from the retransmission Buffer or the dedicated retransmission micro-slice register. Otherwise, pack the data read from the REQ_FIFO sub-module.

[0119] In addition to the command information, the configuration information in the REQ_FIFO sub-module will also trigger the read operation of the REQ_FIFO sub-module of the request, and parse the read data of the REQ_FIFO sub-module to configure registers such as SRID and SNODID.

[0120] The NOD response processing module in the Kernel module of the present invention is as Figure 1As shown. The NOD response unit receives the NOD response, parses it, and writes the parsing result into the RESP_FIFO sub-module in cooperation with the second FIFO write controller. The data format written into the RESP_FIFO sub-module is as Figure 7 shown. The high two bits are used as flag bits, and 2’b10 is used to flag exception information.

[0121] There are two possible abnormal situations for the NOD response. One situation is the response error, that is, the response information is not received within the specified time, which is identified by the status signal resp_confirm_err. This will cause the state machine of the NOD response processing module to enter the STUS state. If this exception occurs during the retransmission stage, the exception information will be written into the RESP_FIFO sub-module. The other situation is the read data verification error, which is identified by resp_check_err. This exception information will be written into the RESP_FIFO sub-module while the tail microchip is received.

[0122] The state transition of the NOD response unit is as Figure 8 shown. The default state of the state machine is RESP. When the response error flag resp_confirm_err is received and the FIFO is not full, the state machine will enter the STUS state and write the exception information into the FIFO. This state only lasts for one cycle.

[0123] The NOD response unit will feedback the response status to the NOD request unit, such as information on successful read response verification, write completion, DMA read completion, abnormal status, etc. The NOD request unit in the CONFIRM state will return to the HEAD state after receiving the response status.

[0124] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the scope of protection of the claims.

Claims

1. A parallel conversion interface for high-speed scalable interconnection bare die and PCIe master device, characterized in that, Connect the NOD (Network-on-Die) of the high-speed scalable interconnect die to the EP end of the PCIe master device, implement the conversion between the AXI protocol of the PCIe master device and the transmission protocol of the NOD network-on-die, receive data packets of various request types from the PCIe master device and convert them into data packets of the NOD network-on-die protocol, and return data packets of various response types to the PCIe master device, and support the transmission of multiple different request data packets in the NOD network-on-die of the die, so as to realize the communication between the PCIe master device and each slave device on the high-speed scalable interconnect die; The parallel conversion interface includes a Shell module, a Kernel module, and an asynchronous FIFO module; The Shell module receives read and write requests from the PCIe master device, converts multiple different request data packets of AXI signals into a specific format and stores them in specific units of the asynchronous FIFO module, and also sends an MSI interrupt signal to the PCIe master device to notify that the response data packet has arrived. In addition, it has an address test function and an ID configuration function; The Kernel module converts the data stored in the asynchronous FIFO module by the Shell module into data packets of the NOD network-on-die protocol, and receives the returned response data packets and unpacks them and stores them in the asynchronous FIFO module. In addition, it has an error retransmission function and a timeout retransmission function for response data packets; The asynchronous FIFO module across clock domains is connected to the Shell module and the Kernel module, and there are multiple asynchronous FIFO units inside, which are responsible for different read and write channels respectively; One end of the PCIe network conversion interface NI on the high-speed scalable interconnect die is connected to the EP end of the PCIe master device, and the other end is connected to the network-on-die NOD; the function of the network-on-die NOD is to route and transmit the network-on-die transmission protocol, including request event data packets from the PCIe master device to each slave device on the die and corresponding response event data packets of the slave devices; the interaction between the PCIe network conversion interface NI and the PCIe master device is based on two groups of AXI4 buses, one of which is used as a Slave interface to communicate with the EP end, and the other is used as a Master interface to send an MSI interrupt signal to the EP end; The PCIe network conversion interface NI supports a check error retransmission mechanism and a timeout retransmission mechanism; under normal circumstances, after the PCIe network conversion interface NI receives a read response packet, it notifies the PCIe master device through an interrupt, and the PCIe master device sends a new request command after reading the interrupt information; The situation of the error retransmission mechanism is as follows: after the PCIe network conversion interface NI receives a read response packet and finds a check error, it will not interrupt the PCIe master device, but instead retransmit the request packet of the NOD network-on-die protocol. After the new NOD network-on-die protocol response packet returns, it will generate an interrupt to notify the PCIe master device; The specific timeout retransmission mechanism is as follows: If the PCIe network conversion interface NI has not received a read response packet, it will trigger the retransmission of the request packet of the NOD on-chip transmission protocol, and generate an interrupt according to the actual response of the retransmitted request packet of the NOD on-chip transmission protocol to notify the PCIe master device; For the process of the PCIe master device's request, the Shell module parses the read and write request commands from AXI_S, and writes the parsing results into the REQ_FIFO sub-module in the asynchronous FIFO module according to the specified format; the Kernel module reads the information in the REQ_FIFO sub-module, and packs the read and write request commands into on-chip network request data packets according to the format of the NOD on-chip transmission protocol bus; For the response process, the Kernel module reads the response data packet from the on-chip network NOD and parses it, and writes the parsing results into the RESP_FIFO sub-module in the asynchronous FIFO module according to the specified format; the Shell module reads the information in the RESP_FIFO sub-module, and when all responses are received, it sends an interrupt notification to the PCIe master device through AXI_M, and the PCIe master device further reads the response information cached in the Shell module through AXI_S; Among them, the REQ_FIFO sub-module includes FIFO_0,..., FIFO_(n-1), FIFO_n, where FIFO_0 to FIFO_(n-1) are channels for write request events with data payloads and shared write request events, and FIFO_n is a channel for read request events without data payloads, erase request events, and DMA read request events; the data payload will be retained in the REQ_FIFO sub-module, and the remaining request information will enter the (m+1) groups of request units in the Kernel module through the REQ_FIFO sub-module for storage, and m>n, for the PCIe network conversion interface NI to retransmit these different requests.

2. The parallel conversion interface for high-speed scalable interconnection die and PCIe master device according to claim 1, characterized in that, The functions of the PCIe network conversion interface NI include the PCIe master device configuring NODID and SRID information for the PCIe network conversion interface NI, as well as configuring the address and data of the returned MSI interrupt; The PCIe network conversion interface NI provides the function of address testing. The PCIe network conversion interface NI design adopts a partial decoding strategy, that is, only the lower eight bits of the address are decoded; before the formal work starts, the PCIe master device needs to test the available address space through address polling; the PCIe network conversion interface NI needs to receive and convert different event data packets during formal work; After the PCIe network conversion interface NI receives the response event sent by the slave, it must initiate an MSI interrupt signal to the PCIe master device, and the PCIe master device will then read the interrupt information of the response event and the data payload in the response event.

3. The parallel conversion interface for high-speed scalable interconnection die and PCIe master device according to claim 2, wherein The PCIe network conversion interface NI supports concurrent requests; for the PCIe master device, it can issue multiple request commands; The PCIe network conversion interface NI supports both the check error retransmission mechanism and the timeout retransmission mechanism for all the request data packets sent out. However, the PCIe master device should pay attention to the dependency relationships between different request events, maintain the correct read / write order for the same address of the same slave device, and can initiate read / write requests out of order for the addresses of different slave devices or different addresses of the same slave device.

4. The parallel conversion interface for high-speed scalable interconnection die and PCIe master device according to claim 3, characterized in that The write request processing module in the Shell module includes an AXI write controller, a first address test unit, a first configuration unit, a command unit, and a first FIFO write controller. For the write commands from AXI_S, there are three scenarios, namely configuration, address test, and command. These three scenarios are distinguished by the write address of AXI_S. The AXI write controller decodes the lower eight bits of the AXI_S write address. The write address 64’hxx10 is for configuration, the write address 64’hxx20 is for command, and the write address 64’hxx30 is for address test. The first FIFO write controller is used to determine whether both the read channel and the write channel FIFOs are occupied and which FIFO channels are not occupied, so as to store subsequent PCIe request data packets. The request event capacity of the PCIe network conversion interface NI is to store n write request events / shared write request events and (m + 1 - n) read request events / erase request events / DMA read request events.

5. The parallel conversion interface for high-speed scalable interconnection die and PCIe master device according to claim 4, characterized in that The read request processing module in the Shell module includes an AXI read controller, a second address test unit, an interrupt controller, a data unit, and a first FIFO read controller. For the read commands from AXI_S, there are three scenarios, namely reading interrupt information, address test, and reading data. These three scenarios are distinguished by the read address of AXI_S. The AXI read controller decodes the lower eight bits of the AXI_S write address. The read address 64’hxx10 is the interrupt information of the response packet, the read address 64’hxx20 is the payload data of the response packet, the read address 64’hxx30 is for address test, and the read address 64’hxx40 is the address information of the response packet.

6. The parallel conversion interface for high-speed scalable interconnection die and PCIe master device according to claim 5, wherein The NOD request processing module in the Kernel module includes a second FIFO read controller, a second configuration unit, and a NOD request unit. The NOD request unit includes request unit 0,..., request unit m. Under the control of the second configuration unit and the NOD request unit, (m + 1) internal request units read data from the REQ_FIFO sub-module. The second configuration unit is used to configure registers before the PCIe network conversion interface NI officially starts working. The NOD request unit packs the data read from the REQ_FIFO sub-module into NOD on-chip network data packets and sends them.

7. The parallel conversion interface for high-speed scalable interconnect dies and PCIe master devices according to claim 6, characterized in that, The NOD response processing module in the Kernel module includes a second FIFO write controller and a NOD response unit; the NOD response unit receives the NOD response, parses it, and writes the parsing result into the RESP_FIFO sub-module with the cooperation of the second FIFO write controller. In the data format written into the RESP_FIFO sub-module, the high two bits are used as flag bits, and 2'b10 is used to flag exception information; there are two types of exception conditions for the NOD response. One situation is the response error, that is, the response information is not received within the specified time, which is identified by the status signal resp_confirm_err, and it will cause the state machine of the NOD response processing module to enter the STUS state. If this exception occurs during the retransmission stage, the exception information will be written into the RESP_FIFO sub-module; the other situation is the read data verification error, which is identified by resp_check_err, and this exception information will be written into the RESP_FIFO sub-module while the tail microchip is received.

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